tsc.c revision 50823
1/*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz and Don Ahn. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 37 * $FreeBSD: head/sys/i386/i386/tsc.c 50823 1999-09-03 02:04:28Z mdodd $ 38 */ 39 40/* 41 * Routines to handle clock hardware. 42 */ 43 44/* 45 * inittodr, settodr and support routines written 46 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 47 * 48 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 49 */ 50 51#include "opt_clock.h" 52#include "apm.h" 53 54#include <sys/param.h> 55#include <sys/systm.h> 56#include <sys/time.h> 57#include <sys/kernel.h> 58#ifndef SMP 59#include <sys/lock.h> 60#endif 61#include <sys/sysctl.h> 62#include <sys/cons.h> 63 64#include <machine/clock.h> 65#ifdef CLK_CALIBRATION_LOOP 66#endif 67#include <machine/cputypes.h> 68#include <machine/frame.h> 69#include <machine/ipl.h> 70#include <machine/limits.h> 71#include <machine/md_var.h> 72#include <machine/psl.h> 73#ifdef APIC_IO 74#include <machine/segments.h> 75#endif 76#if defined(SMP) || defined(APIC_IO) 77#include <machine/smp.h> 78#endif /* SMP || APIC_IO */ 79#include <machine/specialreg.h> 80 81#include <i386/isa/icu.h> 82#include <i386/isa/isa.h> 83#include <isa/rtc.h> 84#include <i386/isa/timerreg.h> 85 86#include <i386/isa/intr_machdep.h> 87 88#include "mca.h" 89#if NMCA > 0 90#include <i386/isa/mca_machdep.h> 91#endif 92 93#ifdef SMP 94#define disable_intr() CLOCK_DISABLE_INTR() 95#define enable_intr() CLOCK_ENABLE_INTR() 96 97#ifdef APIC_IO 98#include <i386/isa/intr_machdep.h> 99/* The interrupt triggered by the 8254 (timer) chip */ 100int apic_8254_intr; 101static u_long read_intr_count __P((int vec)); 102static void setup_8254_mixed_mode __P((void)); 103#endif 104#endif /* SMP */ 105 106/* 107 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 108 * can use a simple formula for leap years. 109 */ 110#define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 111#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 112 113#define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x)) 114 115/* 116 * Time in timer cycles that it takes for microtime() to disable interrupts 117 * and latch the count. microtime() currently uses "cli; outb ..." so it 118 * normally takes less than 2 timer cycles. Add a few for cache misses. 119 * Add a few more to allow for latency in bogus calls to microtime() with 120 * interrupts already disabled. 121 */ 122#define TIMER0_LATCH_COUNT 20 123 124/* 125 * Maximum frequency that we are willing to allow for timer0. Must be 126 * low enough to guarantee that the timer interrupt handler returns 127 * before the next timer interrupt. 128 */ 129#define TIMER0_MAX_FREQ 20000 130 131int adjkerntz; /* local offset from GMT in seconds */ 132int clkintr_pending; 133int disable_rtc_set; /* disable resettodr() if != 0 */ 134volatile u_int idelayed; 135int statclock_disable; 136u_int stat_imask = SWI_CLOCK_MASK; 137#ifndef TIMER_FREQ 138#define TIMER_FREQ 1193182 139#endif 140u_int timer_freq = TIMER_FREQ; 141int timer0_max_count; 142u_int tsc_freq; 143int tsc_is_broken; 144int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 145 146static int beeping = 0; 147static u_int clk_imask = HWI_MASK | SWI_MASK; 148static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 149static u_int hardclock_max_count; 150static u_int32_t i8254_lastcount; 151static u_int32_t i8254_offset; 152static int i8254_ticked; 153/* 154 * XXX new_function and timer_func should not handle clockframes, but 155 * timer_func currently needs to hold hardclock to handle the 156 * timer0_state == 0 case. We should use register_intr()/unregister_intr() 157 * to switch between clkintr() and a slightly different timerintr(). 158 */ 159static void (*new_function) __P((struct clockframe *frame)); 160static u_int new_rate; 161static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 162static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 163static u_int timer0_prescaler_count; 164 165/* Values for timerX_state: */ 166#define RELEASED 0 167#define RELEASE_PENDING 1 168#define ACQUIRED 2 169#define ACQUIRE_PENDING 3 170 171static u_char timer0_state; 172static u_char timer2_state; 173static void (*timer_func) __P((struct clockframe *frame)) = hardclock; 174static u_int tsc_present; 175 176static unsigned i8254_get_timecount __P((struct timecounter *tc)); 177static unsigned tsc_get_timecount __P((struct timecounter *tc)); 178static void set_timer_freq(u_int freq, int intr_freq); 179 180static struct timecounter tsc_timecounter = { 181 tsc_get_timecount, /* get_timecount */ 182 0, /* no poll_pps */ 183 ~0u, /* counter_mask */ 184 0, /* frequency */ 185 "TSC" /* name */ 186}; 187 188SYSCTL_OPAQUE(_debug, OID_AUTO, tsc_timecounter, CTLFLAG_RD, 189 &tsc_timecounter, sizeof(tsc_timecounter), "S,timecounter", ""); 190 191static struct timecounter i8254_timecounter = { 192 i8254_get_timecount, /* get_timecount */ 193 0, /* no poll_pps */ 194 ~0u, /* counter_mask */ 195 0, /* frequency */ 196 "i8254" /* name */ 197}; 198 199SYSCTL_OPAQUE(_debug, OID_AUTO, i8254_timecounter, CTLFLAG_RD, 200 &i8254_timecounter, sizeof(i8254_timecounter), "S,timecounter", ""); 201 202static void 203clkintr(struct clockframe frame) 204{ 205 if (timecounter->tc_get_timecount == i8254_get_timecount) { 206 disable_intr(); 207 if (i8254_ticked) 208 i8254_ticked = 0; 209 else { 210 i8254_offset += timer0_max_count; 211 i8254_lastcount = 0; 212 } 213 clkintr_pending = 0; 214 enable_intr(); 215 } 216 timer_func(&frame); 217 switch (timer0_state) { 218 219 case RELEASED: 220 setdelayed(); 221 break; 222 223 case ACQUIRED: 224 if ((timer0_prescaler_count += timer0_max_count) 225 >= hardclock_max_count) { 226 timer0_prescaler_count -= hardclock_max_count; 227 hardclock(&frame); 228 setdelayed(); 229 } 230 break; 231 232 case ACQUIRE_PENDING: 233 disable_intr(); 234 i8254_offset = i8254_get_timecount(NULL); 235 i8254_lastcount = 0; 236 timer0_max_count = TIMER_DIV(new_rate); 237 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 238 outb(TIMER_CNTR0, timer0_max_count & 0xff); 239 outb(TIMER_CNTR0, timer0_max_count >> 8); 240 enable_intr(); 241 timer_func = new_function; 242 timer0_state = ACQUIRED; 243 setdelayed(); 244 break; 245 246 case RELEASE_PENDING: 247 if ((timer0_prescaler_count += timer0_max_count) 248 >= hardclock_max_count) { 249 disable_intr(); 250 i8254_offset = i8254_get_timecount(NULL); 251 i8254_lastcount = 0; 252 timer0_max_count = hardclock_max_count; 253 outb(TIMER_MODE, 254 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 255 outb(TIMER_CNTR0, timer0_max_count & 0xff); 256 outb(TIMER_CNTR0, timer0_max_count >> 8); 257 enable_intr(); 258 timer0_prescaler_count = 0; 259 timer_func = hardclock; 260 timer0_state = RELEASED; 261 hardclock(&frame); 262 setdelayed(); 263 } 264 break; 265 } 266#if NMCA > 0 267 /* Reset clock interrupt by asserting bit 7 of port 0x61 */ 268 if (MCA_system) 269 outb(0x61, inb(0x61) | 0x80); 270#endif 271} 272 273/* 274 * The acquire and release functions must be called at ipl >= splclock(). 275 */ 276int 277acquire_timer0(int rate, void (*function) __P((struct clockframe *frame))) 278{ 279 static int old_rate; 280 281 if (rate <= 0 || rate > TIMER0_MAX_FREQ) 282 return (-1); 283 switch (timer0_state) { 284 285 case RELEASED: 286 timer0_state = ACQUIRE_PENDING; 287 break; 288 289 case RELEASE_PENDING: 290 if (rate != old_rate) 291 return (-1); 292 /* 293 * The timer has been released recently, but is being 294 * re-acquired before the release completed. In this 295 * case, we simply reclaim it as if it had not been 296 * released at all. 297 */ 298 timer0_state = ACQUIRED; 299 break; 300 301 default: 302 return (-1); /* busy */ 303 } 304 new_function = function; 305 old_rate = new_rate = rate; 306 return (0); 307} 308 309int 310acquire_timer2(int mode) 311{ 312 313 if (timer2_state != RELEASED) 314 return (-1); 315 timer2_state = ACQUIRED; 316 317 /* 318 * This access to the timer registers is as atomic as possible 319 * because it is a single instruction. We could do better if we 320 * knew the rate. Use of splclock() limits glitches to 10-100us, 321 * and this is probably good enough for timer2, so we aren't as 322 * careful with it as with timer0. 323 */ 324 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 325 326 return (0); 327} 328 329int 330release_timer0() 331{ 332 switch (timer0_state) { 333 334 case ACQUIRED: 335 timer0_state = RELEASE_PENDING; 336 break; 337 338 case ACQUIRE_PENDING: 339 /* Nothing happened yet, release quickly. */ 340 timer0_state = RELEASED; 341 break; 342 343 default: 344 return (-1); 345 } 346 return (0); 347} 348 349int 350release_timer2() 351{ 352 353 if (timer2_state != ACQUIRED) 354 return (-1); 355 timer2_state = RELEASED; 356 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 357 return (0); 358} 359 360/* 361 * This routine receives statistical clock interrupts from the RTC. 362 * As explained above, these occur at 128 interrupts per second. 363 * When profiling, we receive interrupts at a rate of 1024 Hz. 364 * 365 * This does not actually add as much overhead as it sounds, because 366 * when the statistical clock is active, the hardclock driver no longer 367 * needs to keep (inaccurate) statistics on its own. This decouples 368 * statistics gathering from scheduling interrupts. 369 * 370 * The RTC chip requires that we read status register C (RTC_INTR) 371 * to acknowledge an interrupt, before it will generate the next one. 372 * Under high interrupt load, rtcintr() can be indefinitely delayed and 373 * the clock can tick immediately after the read from RTC_INTR. In this 374 * case, the mc146818A interrupt signal will not drop for long enough 375 * to register with the 8259 PIC. If an interrupt is missed, the stat 376 * clock will halt, considerably degrading system performance. This is 377 * why we use 'while' rather than a more straightforward 'if' below. 378 * Stat clock ticks can still be lost, causing minor loss of accuracy 379 * in the statistics, but the stat clock will no longer stop. 380 */ 381static void 382rtcintr(struct clockframe frame) 383{ 384 while (rtcin(RTC_INTR) & RTCIR_PERIOD) 385 statclock(&frame); 386} 387 388#include "opt_ddb.h" 389#ifdef DDB 390#include <ddb/ddb.h> 391 392DB_SHOW_COMMAND(rtc, rtc) 393{ 394 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 395 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 396 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 397 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 398} 399#endif /* DDB */ 400 401static int 402getit(void) 403{ 404 u_long ef; 405 int high, low; 406 407 ef = read_eflags(); 408 disable_intr(); 409 410 /* Select timer0 and latch counter value. */ 411 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 412 413 low = inb(TIMER_CNTR0); 414 high = inb(TIMER_CNTR0); 415 416 CLOCK_UNLOCK(); 417 write_eflags(ef); 418 return ((high << 8) | low); 419} 420 421/* 422 * Wait "n" microseconds. 423 * Relies on timer 1 counting down from (timer_freq / hz) 424 * Note: timer had better have been programmed before this is first used! 425 */ 426void 427DELAY(int n) 428{ 429 int delta, prev_tick, tick, ticks_left; 430 431#ifdef DELAYDEBUG 432 int getit_calls = 1; 433 int n1; 434 static int state = 0; 435 436 if (state == 0) { 437 state = 1; 438 for (n1 = 1; n1 <= 10000000; n1 *= 10) 439 DELAY(n1); 440 state = 2; 441 } 442 if (state == 1) 443 printf("DELAY(%d)...", n); 444#endif 445 /* 446 * Guard against the timer being uninitialized if we are called 447 * early for console i/o. 448 */ 449 if (timer0_max_count == 0) 450 set_timer_freq(timer_freq, hz); 451 452 /* 453 * Read the counter first, so that the rest of the setup overhead is 454 * counted. Guess the initial overhead is 20 usec (on most systems it 455 * takes about 1.5 usec for each of the i/o's in getit(). The loop 456 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The 457 * multiplications and divisions to scale the count take a while). 458 */ 459 prev_tick = getit(); 460 n -= 0; /* XXX actually guess no initial overhead */ 461 /* 462 * Calculate (n * (timer_freq / 1e6)) without using floating point 463 * and without any avoidable overflows. 464 */ 465 if (n <= 0) 466 ticks_left = 0; 467 else if (n < 256) 468 /* 469 * Use fixed point to avoid a slow division by 1000000. 470 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest. 471 * 2^15 is the first power of 2 that gives exact results 472 * for n between 0 and 256. 473 */ 474 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15; 475 else 476 /* 477 * Don't bother using fixed point, although gcc-2.7.2 478 * generates particularly poor code for the long long 479 * division, since even the slow way will complete long 480 * before the delay is up (unless we're interrupted). 481 */ 482 ticks_left = ((u_int)n * (long long)timer_freq + 999999) 483 / 1000000; 484 485 while (ticks_left > 0) { 486 tick = getit(); 487#ifdef DELAYDEBUG 488 ++getit_calls; 489#endif 490 delta = prev_tick - tick; 491 prev_tick = tick; 492 if (delta < 0) { 493 delta += timer0_max_count; 494 /* 495 * Guard against timer0_max_count being wrong. 496 * This shouldn't happen in normal operation, 497 * but it may happen if set_timer_freq() is 498 * traced. 499 */ 500 if (delta < 0) 501 delta = 0; 502 } 503 ticks_left -= delta; 504 } 505#ifdef DELAYDEBUG 506 if (state == 1) 507 printf(" %d calls to getit() at %d usec each\n", 508 getit_calls, (n + 5) / getit_calls); 509#endif 510} 511 512static void 513sysbeepstop(void *chan) 514{ 515 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 516 release_timer2(); 517 beeping = 0; 518} 519 520int 521sysbeep(int pitch, int period) 522{ 523 int x = splclock(); 524 525 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 526 if (!beeping) { 527 /* Something else owns it. */ 528 splx(x); 529 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 530 } 531 disable_intr(); 532 outb(TIMER_CNTR2, pitch); 533 outb(TIMER_CNTR2, (pitch>>8)); 534 enable_intr(); 535 if (!beeping) { 536 /* enable counter2 output to speaker */ 537 outb(IO_PPI, inb(IO_PPI) | 3); 538 beeping = period; 539 timeout(sysbeepstop, (void *)NULL, period); 540 } 541 splx(x); 542 return (0); 543} 544 545/* 546 * RTC support routines 547 */ 548 549int 550rtcin(reg) 551 int reg; 552{ 553 u_char val; 554 555 outb(IO_RTC, reg); 556 inb(0x84); 557 val = inb(IO_RTC + 1); 558 inb(0x84); 559 return (val); 560} 561 562static __inline void 563writertc(u_char reg, u_char val) 564{ 565 inb(0x84); 566 outb(IO_RTC, reg); 567 inb(0x84); 568 outb(IO_RTC + 1, val); 569 inb(0x84); /* XXX work around wrong order in rtcin() */ 570} 571 572static __inline int 573readrtc(int port) 574{ 575 return(bcd2bin(rtcin(port))); 576} 577 578static u_int 579calibrate_clocks(void) 580{ 581 u_int64_t old_tsc; 582 u_int count, prev_count, tot_count; 583 int sec, start_sec, timeout; 584 585 if (bootverbose) 586 printf("Calibrating clock(s) ... "); 587 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 588 goto fail; 589 timeout = 100000000; 590 591 /* Read the mc146818A seconds counter. */ 592 for (;;) { 593 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 594 sec = rtcin(RTC_SEC); 595 break; 596 } 597 if (--timeout == 0) 598 goto fail; 599 } 600 601 /* Wait for the mC146818A seconds counter to change. */ 602 start_sec = sec; 603 for (;;) { 604 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 605 sec = rtcin(RTC_SEC); 606 if (sec != start_sec) 607 break; 608 } 609 if (--timeout == 0) 610 goto fail; 611 } 612 613 /* Start keeping track of the i8254 counter. */ 614 prev_count = getit(); 615 if (prev_count == 0 || prev_count > timer0_max_count) 616 goto fail; 617 tot_count = 0; 618 619 if (tsc_present) 620 old_tsc = rdtsc(); 621 else 622 old_tsc = 0; /* shut up gcc */ 623 624 /* 625 * Wait for the mc146818A seconds counter to change. Read the i8254 626 * counter for each iteration since this is convenient and only 627 * costs a few usec of inaccuracy. The timing of the final reads 628 * of the counters almost matches the timing of the initial reads, 629 * so the main cause of inaccuracy is the varying latency from 630 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 631 * rtcin(RTC_SEC) that returns a changed seconds count. The 632 * maximum inaccuracy from this cause is < 10 usec on 486's. 633 */ 634 start_sec = sec; 635 for (;;) { 636 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 637 sec = rtcin(RTC_SEC); 638 count = getit(); 639 if (count == 0 || count > timer0_max_count) 640 goto fail; 641 if (count > prev_count) 642 tot_count += prev_count - (count - timer0_max_count); 643 else 644 tot_count += prev_count - count; 645 prev_count = count; 646 if (sec != start_sec) 647 break; 648 if (--timeout == 0) 649 goto fail; 650 } 651 652 /* 653 * Read the cpu cycle counter. The timing considerations are 654 * similar to those for the i8254 clock. 655 */ 656 if (tsc_present) 657 tsc_freq = rdtsc() - old_tsc; 658 659 if (bootverbose) { 660 if (tsc_present) 661 printf("TSC clock: %u Hz, ", tsc_freq); 662 printf("i8254 clock: %u Hz\n", tot_count); 663 } 664 return (tot_count); 665 666fail: 667 if (bootverbose) 668 printf("failed, using default i8254 clock of %u Hz\n", 669 timer_freq); 670 return (timer_freq); 671} 672 673static void 674set_timer_freq(u_int freq, int intr_freq) 675{ 676 u_long ef; 677 int new_timer0_max_count; 678 679 ef = read_eflags(); 680 disable_intr(); 681 timer_freq = freq; 682 new_timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq); 683 if (new_timer0_max_count != timer0_max_count) { 684 timer0_max_count = new_timer0_max_count; 685 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 686 outb(TIMER_CNTR0, timer0_max_count & 0xff); 687 outb(TIMER_CNTR0, timer0_max_count >> 8); 688 } 689 CLOCK_UNLOCK(); 690 write_eflags(ef); 691} 692 693/* 694 * Initialize 8254 timer 0 early so that it can be used in DELAY(). 695 * XXX initialization of other timers is unintentionally left blank. 696 */ 697void 698startrtclock() 699{ 700 u_int delta, freq; 701 702 if (cpu_feature & CPUID_TSC) 703 tsc_present = 1; 704 else 705 tsc_present = 0; 706 707 writertc(RTC_STATUSA, rtc_statusa); 708 writertc(RTC_STATUSB, RTCSB_24HR); 709 710 set_timer_freq(timer_freq, hz); 711 freq = calibrate_clocks(); 712#ifdef CLK_CALIBRATION_LOOP 713 if (bootverbose) { 714 printf( 715 "Press a key on the console to abort clock calibration\n"); 716 while (cncheckc() == -1) 717 calibrate_clocks(); 718 } 719#endif 720 721 /* 722 * Use the calibrated i8254 frequency if it seems reasonable. 723 * Otherwise use the default, and don't use the calibrated i586 724 * frequency. 725 */ 726 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq; 727 if (delta < timer_freq / 100) { 728#ifndef CLK_USE_I8254_CALIBRATION 729 if (bootverbose) 730 printf( 731"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 732 freq = timer_freq; 733#endif 734 timer_freq = freq; 735 } else { 736 if (bootverbose) 737 printf( 738 "%d Hz differs from default of %d Hz by more than 1%%\n", 739 freq, timer_freq); 740 tsc_freq = 0; 741 } 742 743 set_timer_freq(timer_freq, hz); 744 i8254_timecounter.tc_frequency = timer_freq; 745 init_timecounter(&i8254_timecounter); 746 747#ifndef CLK_USE_TSC_CALIBRATION 748 if (tsc_freq != 0) { 749 if (bootverbose) 750 printf( 751"CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n"); 752 tsc_freq = 0; 753 } 754#endif 755 if (tsc_present && tsc_freq == 0) { 756 /* 757 * Calibration of the i586 clock relative to the mc146818A 758 * clock failed. Do a less accurate calibration relative 759 * to the i8254 clock. 760 */ 761 u_int64_t old_tsc = rdtsc(); 762 763 DELAY(1000000); 764 tsc_freq = rdtsc() - old_tsc; 765#ifdef CLK_USE_TSC_CALIBRATION 766 if (bootverbose) 767 printf("TSC clock: %u Hz (Method B)\n", tsc_freq); 768#endif 769 } 770 771#if !defined(SMP) 772 /* 773 * We can not use the TSC in SMP mode, until we figure out a 774 * cheap (impossible), reliable and precise (yeah right!) way 775 * to synchronize the TSCs of all the CPUs. 776 * Curse Intel for leaving the counter out of the I/O APIC. 777 */ 778 779#if NAPM > 0 780 /* 781 * We can not use the TSC if we support APM. Precise timekeeping 782 * on an APM'ed machine is at best a fools pursuit, since 783 * any and all of the time spent in various SMM code can't 784 * be reliably accounted for. Reading the RTC is your only 785 * source of reliable time info. The i8254 looses too of course 786 * but we need to have some kind of time... 787 * We don't know at this point whether APM is going to be used 788 * or not, nor when it might be activated. Play it safe. 789 */ 790 return; 791#endif /* NAPM > 0 */ 792 793 if (tsc_present && tsc_freq != 0 && !tsc_is_broken) { 794 tsc_timecounter.tc_frequency = tsc_freq; 795 init_timecounter(&tsc_timecounter); 796 } 797 798#endif /* !defined(SMP) */ 799} 800 801/* 802 * Initialize the time of day register, based on the time base which is, e.g. 803 * from a filesystem. 804 */ 805void 806inittodr(time_t base) 807{ 808 unsigned long sec, days; 809 int yd; 810 int year, month; 811 int y, m, s; 812 struct timespec ts; 813 814 if (base) { 815 s = splclock(); 816 ts.tv_sec = base; 817 ts.tv_nsec = 0; 818 set_timecounter(&ts); 819 splx(s); 820 } 821 822 /* Look if we have a RTC present and the time is valid */ 823 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 824 goto wrong_time; 825 826 /* wait for time update to complete */ 827 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 828 while (rtcin(RTC_STATUSA) & RTCSA_TUP); 829 830 days = 0; 831#ifdef USE_RTC_CENTURY 832 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 833#else 834 year = readrtc(RTC_YEAR) + 1900; 835 if (year < 1970) 836 year += 100; 837#endif 838 if (year < 1970) 839 goto wrong_time; 840 month = readrtc(RTC_MONTH); 841 for (m = 1; m < month; m++) 842 days += daysinmonth[m-1]; 843 if ((month > 2) && LEAPYEAR(year)) 844 days ++; 845 days += readrtc(RTC_DAY) - 1; 846 yd = days; 847 for (y = 1970; y < year; y++) 848 days += DAYSPERYEAR + LEAPYEAR(y); 849 sec = ((( days * 24 + 850 readrtc(RTC_HRS)) * 60 + 851 readrtc(RTC_MIN)) * 60 + 852 readrtc(RTC_SEC)); 853 /* sec now contains the number of seconds, since Jan 1 1970, 854 in the local time zone */ 855 856 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 857 858 y = time_second - sec; 859 if (y <= -2 || y >= 2) { 860 /* badly off, adjust it */ 861 s = splclock(); 862 ts.tv_sec = sec; 863 ts.tv_nsec = 0; 864 set_timecounter(&ts); 865 splx(s); 866 } 867 return; 868 869wrong_time: 870 printf("Invalid time in real time clock.\n"); 871 printf("Check and reset the date immediately!\n"); 872} 873 874/* 875 * Write system time back to RTC 876 */ 877void 878resettodr() 879{ 880 unsigned long tm; 881 int y, m, s; 882 883 if (disable_rtc_set) 884 return; 885 886 s = splclock(); 887 tm = time_second; 888 splx(s); 889 890 /* Disable RTC updates and interrupts. */ 891 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 892 893 /* Calculate local time to put in RTC */ 894 895 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 896 897 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 898 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 899 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 900 901 /* We have now the days since 01-01-1970 in tm */ 902 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 903 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 904 tm >= m; 905 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 906 tm -= m; 907 908 /* Now we have the years in y and the day-of-the-year in tm */ 909 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 910#ifdef USE_RTC_CENTURY 911 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 912#endif 913 for (m = 0; ; m++) { 914 int ml; 915 916 ml = daysinmonth[m]; 917 if (m == 1 && LEAPYEAR(y)) 918 ml++; 919 if (tm < ml) 920 break; 921 tm -= ml; 922 } 923 924 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 925 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 926 927 /* Reenable RTC updates and interrupts. */ 928 writertc(RTC_STATUSB, rtc_statusb); 929} 930 931 932/* 933 * Start both clocks running. 934 */ 935void 936cpu_initclocks() 937{ 938 int diag; 939#ifdef APIC_IO 940 int apic_8254_trial; 941 struct intrec *clkdesc; 942#endif /* APIC_IO */ 943 944 if (statclock_disable) { 945 /* 946 * The stat interrupt mask is different without the 947 * statistics clock. Also, don't set the interrupt 948 * flag which would normally cause the RTC to generate 949 * interrupts. 950 */ 951 stat_imask = HWI_MASK | SWI_MASK; 952 rtc_statusb = RTCSB_24HR; 953 } else { 954 /* Setting stathz to nonzero early helps avoid races. */ 955 stathz = RTC_NOPROFRATE; 956 profhz = RTC_PROFRATE; 957 } 958 959 /* Finish initializing 8253 timer 0. */ 960#ifdef APIC_IO 961 962 apic_8254_intr = isa_apic_irq(0); 963 apic_8254_trial = 0; 964 if (apic_8254_intr >= 0 ) { 965 if (apic_int_type(0, 0) == 3) 966 apic_8254_trial = 1; 967 } else { 968 /* look for ExtInt on pin 0 */ 969 if (apic_int_type(0, 0) == 3) { 970 apic_8254_intr = 0; 971 setup_8254_mixed_mode(); 972 } else 973 panic("APIC_IO: Cannot route 8254 interrupt to CPU"); 974 } 975 976 clkdesc = inthand_add("clk", apic_8254_intr, (inthand2_t *)clkintr, 977 NULL, &clk_imask, INTR_EXCL); 978 INTREN(1 << apic_8254_intr); 979 980#else /* APIC_IO */ 981 982 inthand_add("clk", 0, (inthand2_t *)clkintr, NULL, &clk_imask, 983 INTR_EXCL); 984 INTREN(IRQ0); 985 986#endif /* APIC_IO */ 987 988 /* Initialize RTC. */ 989 writertc(RTC_STATUSA, rtc_statusa); 990 writertc(RTC_STATUSB, RTCSB_24HR); 991 992 /* Don't bother enabling the statistics clock. */ 993 if (statclock_disable) 994 return; 995 diag = rtcin(RTC_DIAG); 996 if (diag != 0) 997 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS); 998 999#ifdef APIC_IO 1000 if (isa_apic_irq(8) != 8) 1001 panic("APIC RTC != 8"); 1002#endif /* APIC_IO */ 1003 1004 inthand_add("rtc", 8, (inthand2_t *)rtcintr, NULL, &stat_imask, 1005 INTR_EXCL); 1006 1007#ifdef APIC_IO 1008 INTREN(APIC_IRQ8); 1009#else 1010 INTREN(IRQ8); 1011#endif /* APIC_IO */ 1012 1013 writertc(RTC_STATUSB, rtc_statusb); 1014 1015#ifdef APIC_IO 1016 if (apic_8254_trial) { 1017 1018 printf("APIC_IO: Testing 8254 interrupt delivery\n"); 1019 while (read_intr_count(8) < 6) 1020 ; /* nothing */ 1021 if (read_intr_count(apic_8254_intr) < 3) { 1022 /* 1023 * The MP table is broken. 1024 * The 8254 was not connected to the specified pin 1025 * on the IO APIC. 1026 * Workaround: Limited variant of mixed mode. 1027 */ 1028 INTRDIS(1 << apic_8254_intr); 1029 inthand_remove(clkdesc); 1030 printf("APIC_IO: Broken MP table detected: " 1031 "8254 is not connected to IO APIC int pin %d\n", 1032 apic_8254_intr); 1033 1034 apic_8254_intr = 0; 1035 setup_8254_mixed_mode(); 1036 inthand_add("clk", apic_8254_intr,(inthand2_t *)clkintr, 1037 NULL, &clk_imask, INTR_EXCL); 1038 INTREN(1 << apic_8254_intr); 1039 } 1040 1041 } 1042 if (apic_8254_intr) 1043 printf("APIC_IO: routing 8254 via pin %d\n",apic_8254_intr); 1044 else 1045 printf("APIC_IO: routing 8254 via 8259 on pin 0\n"); 1046#endif 1047 1048} 1049 1050#ifdef APIC_IO 1051static u_long 1052read_intr_count(int vec) 1053{ 1054 u_long *up; 1055 up = intr_countp[vec]; 1056 if (up) 1057 return *up; 1058 return 0UL; 1059} 1060 1061static void 1062setup_8254_mixed_mode() 1063{ 1064 /* 1065 * Allow 8254 timer to INTerrupt 8259: 1066 * re-initialize master 8259: 1067 * reset; prog 4 bytes, single ICU, edge triggered 1068 */ 1069 outb(IO_ICU1, 0x13); 1070 outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */ 1071 outb(IO_ICU1 + 1, 0x00); /* ignore slave */ 1072 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */ 1073 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */ 1074 1075 /* program IO APIC for type 3 INT on INT0 */ 1076 if (ext_int_setup(0, 0) < 0) 1077 panic("8254 redirect via APIC pin0 impossible!"); 1078} 1079#endif 1080 1081void 1082setstatclockrate(int newhz) 1083{ 1084 if (newhz == RTC_PROFRATE) 1085 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1086 else 1087 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1088 writertc(RTC_STATUSA, rtc_statusa); 1089} 1090 1091static int 1092sysctl_machdep_i8254_freq SYSCTL_HANDLER_ARGS 1093{ 1094 int error; 1095 u_int freq; 1096 1097 /* 1098 * Use `i8254' instead of `timer' in external names because `timer' 1099 * is is too generic. Should use it everywhere. 1100 */ 1101 freq = timer_freq; 1102 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req); 1103 if (error == 0 && req->newptr != NULL) { 1104 if (timer0_state != RELEASED) 1105 return (EBUSY); /* too much trouble to handle */ 1106 set_timer_freq(freq, hz); 1107 i8254_timecounter.tc_frequency = freq; 1108 update_timecounter(&i8254_timecounter); 1109 } 1110 return (error); 1111} 1112 1113SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW, 1114 0, sizeof(u_int), sysctl_machdep_i8254_freq, "I", ""); 1115 1116static int 1117sysctl_machdep_tsc_freq SYSCTL_HANDLER_ARGS 1118{ 1119 int error; 1120 u_int freq; 1121 1122 if (tsc_timecounter.tc_frequency == 0) 1123 return (EOPNOTSUPP); 1124 freq = tsc_freq; 1125 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req); 1126 if (error == 0 && req->newptr != NULL) { 1127 tsc_freq = freq; 1128 tsc_timecounter.tc_frequency = tsc_freq; 1129 update_timecounter(&tsc_timecounter); 1130 } 1131 return (error); 1132} 1133 1134SYSCTL_PROC(_machdep, OID_AUTO, tsc_freq, CTLTYPE_INT | CTLFLAG_RW, 1135 0, sizeof(u_int), sysctl_machdep_tsc_freq, "I", ""); 1136 1137static unsigned 1138i8254_get_timecount(struct timecounter *tc) 1139{ 1140 u_int count; 1141 u_long ef; 1142 u_int high, low; 1143 1144 ef = read_eflags(); 1145 disable_intr(); 1146 1147 /* Select timer0 and latch counter value. */ 1148 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 1149 1150 low = inb(TIMER_CNTR0); 1151 high = inb(TIMER_CNTR0); 1152 count = timer0_max_count - ((high << 8) | low); 1153 if (count < i8254_lastcount || 1154 (!i8254_ticked && (clkintr_pending || 1155 ((count < 20 || (!(ef & PSL_I) && count < timer0_max_count / 2u)) && 1156#ifdef APIC_IO 1157#define lapic_irr1 ((volatile u_int *)&lapic)[0x210 / 4] /* XXX XXX */ 1158 /* XXX this assumes that apic_8254_intr is < 24. */ 1159 (lapic_irr1 & (1 << apic_8254_intr)))) 1160#else 1161 (inb(IO_ICU1) & 1))) 1162#endif 1163 )) { 1164 i8254_ticked = 1; 1165 i8254_offset += timer0_max_count; 1166 } 1167 i8254_lastcount = count; 1168 count += i8254_offset; 1169 CLOCK_UNLOCK(); 1170 write_eflags(ef); 1171 return (count); 1172} 1173 1174static unsigned 1175tsc_get_timecount(struct timecounter *tc) 1176{ 1177 return (rdtsc()); 1178} 1179