tsc.c revision 27490
1/*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz and Don Ahn. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 37 * $Id: clock.c,v 1.89 1997/07/13 01:18:47 fsmp Exp $ 38 */ 39 40/* 41 * Routines to handle clock hardware. 42 */ 43 44/* 45 * inittodr, settodr and support routines written 46 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 47 * 48 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 49 */ 50 51#include "opt_clock.h" 52#include "opt_cpu.h" 53 54#include <sys/param.h> 55#include <sys/systm.h> 56#include <sys/time.h> 57#include <sys/kernel.h> 58#include <sys/sysctl.h> 59 60#include <machine/clock.h> 61#ifdef CLK_CALIBRATION_LOOP 62#include <machine/cons.h> 63#endif 64#include <machine/cpu.h> 65#include <machine/frame.h> 66#include <machine/ipl.h> 67#ifdef APIC_IO 68#include <machine/smp.h> 69#include <machine/smptests.h> /** TEST_ALTTIMER */ 70#endif /* APIC_IO */ 71 72#include <i386/isa/icu.h> 73#include <i386/isa/isa.h> 74#include <i386/isa/intr_machdep.h> 75#include <i386/isa/rtc.h> 76#include <i386/isa/timerreg.h> 77 78/* 79 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 80 * can use a simple formula for leap years. 81 */ 82#define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 83#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 84 85#define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x)) 86 87/* 88 * Time in timer cycles that it takes for microtime() to disable interrupts 89 * and latch the count. microtime() currently uses "cli; outb ..." so it 90 * normally takes less than 2 timer cycles. Add a few for cache misses. 91 * Add a few more to allow for latency in bogus calls to microtime() with 92 * interrupts already disabled. 93 */ 94#define TIMER0_LATCH_COUNT 20 95 96/* 97 * Maximum frequency that we are willing to allow for timer0. Must be 98 * low enough to guarantee that the timer interrupt handler returns 99 * before the next timer interrupt. Must result in a lower TIMER_DIV 100 * value than TIMER0_LATCH_COUNT so that we don't have to worry about 101 * underflow in the calculation of timer0_overflow_threshold. 102 */ 103#define TIMER0_MAX_FREQ 20000 104 105int adjkerntz; /* local offset from GMT in seconds */ 106int disable_rtc_set; /* disable resettodr() if != 0 */ 107u_int idelayed; 108#if defined(I586_CPU) || defined(I686_CPU) 109#ifndef SMP 110u_int i586_ctr_bias; 111u_int i586_ctr_comultiplier; 112#endif 113u_int i586_ctr_freq; 114#ifndef SMP 115u_int i586_ctr_multiplier; 116#endif 117#endif 118int statclock_disable; 119u_int stat_imask = SWI_CLOCK_MASK; 120#ifdef TIMER_FREQ 121u_int timer_freq = TIMER_FREQ; 122#else 123u_int timer_freq = 1193182; 124#endif 125int timer0_max_count; 126u_int timer0_overflow_threshold; 127u_int timer0_prescaler_count; 128int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 129 130static int beeping = 0; 131static u_int clk_imask = HWI_MASK | SWI_MASK; 132static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 133static u_int hardclock_max_count; 134/* 135 * XXX new_function and timer_func should not handle clockframes, but 136 * timer_func currently needs to hold hardclock to handle the 137 * timer0_state == 0 case. We should use register_intr()/unregister_intr() 138 * to switch between clkintr() and a slightly different timerintr(). 139 */ 140static void (*new_function) __P((struct clockframe *frame)); 141static u_int new_rate; 142static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 143static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 144 145/* Values for timerX_state: */ 146#define RELEASED 0 147#define RELEASE_PENDING 1 148#define ACQUIRED 2 149#define ACQUIRE_PENDING 3 150 151static u_char timer0_state; 152static u_char timer2_state; 153static void (*timer_func) __P((struct clockframe *frame)) = hardclock; 154 155#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 156static void set_i586_ctr_freq(u_int i586_freq, u_int i8254_freq); 157#endif 158static void set_timer_freq(u_int freq, int intr_freq); 159 160static void 161clkintr(struct clockframe frame) 162{ 163 timer_func(&frame); 164 switch (timer0_state) { 165 166 case RELEASED: 167 setdelayed(); 168 break; 169 170 case ACQUIRED: 171 if ((timer0_prescaler_count += timer0_max_count) 172 >= hardclock_max_count) { 173 hardclock(&frame); 174 setdelayed(); 175 timer0_prescaler_count -= hardclock_max_count; 176 } 177 break; 178 179 case ACQUIRE_PENDING: 180 setdelayed(); 181 timer0_max_count = TIMER_DIV(new_rate); 182 timer0_overflow_threshold = 183 timer0_max_count - TIMER0_LATCH_COUNT; 184 disable_intr(); 185 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 186 outb(TIMER_CNTR0, timer0_max_count & 0xff); 187 outb(TIMER_CNTR0, timer0_max_count >> 8); 188 enable_intr(); 189 timer0_prescaler_count = 0; 190 timer_func = new_function; 191 timer0_state = ACQUIRED; 192 break; 193 194 case RELEASE_PENDING: 195 if ((timer0_prescaler_count += timer0_max_count) 196 >= hardclock_max_count) { 197 hardclock(&frame); 198 setdelayed(); 199 timer0_max_count = hardclock_max_count; 200 timer0_overflow_threshold = 201 timer0_max_count - TIMER0_LATCH_COUNT; 202 disable_intr(); 203 outb(TIMER_MODE, 204 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 205 outb(TIMER_CNTR0, timer0_max_count & 0xff); 206 outb(TIMER_CNTR0, timer0_max_count >> 8); 207 enable_intr(); 208 /* 209 * See microtime.s for this magic. 210 */ 211 time.tv_usec += (27465 * 212 (timer0_prescaler_count - hardclock_max_count)) 213 >> 15; 214 if (time.tv_usec >= 1000000) 215 time.tv_usec -= 1000000; 216 timer0_prescaler_count = 0; 217 timer_func = hardclock; 218 timer0_state = RELEASED; 219 } 220 break; 221 } 222} 223 224/* 225 * The acquire and release functions must be called at ipl >= splclock(). 226 */ 227int 228acquire_timer0(int rate, void (*function) __P((struct clockframe *frame))) 229{ 230 static int old_rate; 231 232 if (rate <= 0 || rate > TIMER0_MAX_FREQ) 233 return (-1); 234 switch (timer0_state) { 235 236 case RELEASED: 237 timer0_state = ACQUIRE_PENDING; 238 break; 239 240 case RELEASE_PENDING: 241 if (rate != old_rate) 242 return (-1); 243 /* 244 * The timer has been released recently, but is being 245 * re-acquired before the release completed. In this 246 * case, we simply reclaim it as if it had not been 247 * released at all. 248 */ 249 timer0_state = ACQUIRED; 250 break; 251 252 default: 253 return (-1); /* busy */ 254 } 255 new_function = function; 256 old_rate = new_rate = rate; 257 return (0); 258} 259 260int 261acquire_timer2(int mode) 262{ 263 264 if (timer2_state != RELEASED) 265 return (-1); 266 timer2_state = ACQUIRED; 267 268 /* 269 * This access to the timer registers is as atomic as possible 270 * because it is a single instruction. We could do better if we 271 * knew the rate. Use of splclock() limits glitches to 10-100us, 272 * and this is probably good enough for timer2, so we aren't as 273 * careful with it as with timer0. 274 */ 275 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 276 277 return (0); 278} 279 280int 281release_timer0() 282{ 283 switch (timer0_state) { 284 285 case ACQUIRED: 286 timer0_state = RELEASE_PENDING; 287 break; 288 289 case ACQUIRE_PENDING: 290 /* Nothing happened yet, release quickly. */ 291 timer0_state = RELEASED; 292 break; 293 294 default: 295 return (-1); 296 } 297 return (0); 298} 299 300int 301release_timer2() 302{ 303 304 if (timer2_state != ACQUIRED) 305 return (-1); 306 timer2_state = RELEASED; 307 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 308 return (0); 309} 310 311/* 312 * This routine receives statistical clock interrupts from the RTC. 313 * As explained above, these occur at 128 interrupts per second. 314 * When profiling, we receive interrupts at a rate of 1024 Hz. 315 * 316 * This does not actually add as much overhead as it sounds, because 317 * when the statistical clock is active, the hardclock driver no longer 318 * needs to keep (inaccurate) statistics on its own. This decouples 319 * statistics gathering from scheduling interrupts. 320 * 321 * The RTC chip requires that we read status register C (RTC_INTR) 322 * to acknowledge an interrupt, before it will generate the next one. 323 * Under high interrupt load, rtcintr() can be indefinitely delayed and 324 * the clock can tick immediately after the read from RTC_INTR. In this 325 * case, the mc146818A interrupt signal will not drop for long enough 326 * to register with the 8259 PIC. If an interrupt is missed, the stat 327 * clock will halt, considerably degrading system performance. This is 328 * why we use 'while' rather than a more straightforward 'if' below. 329 * Stat clock ticks can still be lost, causing minor loss of accuracy 330 * in the statistics, but the stat clock will no longer stop. 331 */ 332static void 333rtcintr(struct clockframe frame) 334{ 335 while (rtcin(RTC_INTR) & RTCIR_PERIOD) 336 statclock(&frame); 337} 338 339#include "opt_ddb.h" 340#ifdef DDB 341#include <ddb/ddb.h> 342 343DB_SHOW_COMMAND(rtc, rtc) 344{ 345 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 346 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 347 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 348 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 349} 350#endif /* DDB */ 351 352static int 353getit(void) 354{ 355 u_long ef; 356 int high, low; 357 358 ef = read_eflags(); 359 disable_intr(); 360 361 /* Select timer0 and latch counter value. */ 362 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 363 364 low = inb(TIMER_CNTR0); 365 high = inb(TIMER_CNTR0); 366 367 write_eflags(ef); 368 return ((high << 8) | low); 369} 370 371/* 372 * Wait "n" microseconds. 373 * Relies on timer 1 counting down from (timer_freq / hz) 374 * Note: timer had better have been programmed before this is first used! 375 */ 376void 377DELAY(int n) 378{ 379 int delta, prev_tick, tick, ticks_left; 380 381#ifdef DELAYDEBUG 382 int getit_calls = 1; 383 int n1; 384 static int state = 0; 385 386 if (state == 0) { 387 state = 1; 388 for (n1 = 1; n1 <= 10000000; n1 *= 10) 389 DELAY(n1); 390 state = 2; 391 } 392 if (state == 1) 393 printf("DELAY(%d)...", n); 394#endif 395 /* 396 * Guard against the timer being uninitialized if we are called 397 * early for console i/o. 398 */ 399 if (timer0_max_count == 0) 400 set_timer_freq(timer_freq, hz); 401 402 /* 403 * Read the counter first, so that the rest of the setup overhead is 404 * counted. Guess the initial overhead is 20 usec (on most systems it 405 * takes about 1.5 usec for each of the i/o's in getit(). The loop 406 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The 407 * multiplications and divisions to scale the count take a while). 408 */ 409 prev_tick = getit(); 410 n -= 0; /* XXX actually guess no initial overhead */ 411 /* 412 * Calculate (n * (timer_freq / 1e6)) without using floating point 413 * and without any avoidable overflows. 414 */ 415 if (n <= 0) 416 ticks_left = 0; 417 else if (n < 256) 418 /* 419 * Use fixed point to avoid a slow division by 1000000. 420 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest. 421 * 2^15 is the first power of 2 that gives exact results 422 * for n between 0 and 256. 423 */ 424 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15; 425 else 426 /* 427 * Don't bother using fixed point, although gcc-2.7.2 428 * generates particularly poor code for the long long 429 * division, since even the slow way will complete long 430 * before the delay is up (unless we're interrupted). 431 */ 432 ticks_left = ((u_int)n * (long long)timer_freq + 999999) 433 / 1000000; 434 435 while (ticks_left > 0) { 436 tick = getit(); 437#ifdef DELAYDEBUG 438 ++getit_calls; 439#endif 440 delta = prev_tick - tick; 441 prev_tick = tick; 442 if (delta < 0) { 443 delta += timer0_max_count; 444 /* 445 * Guard against timer0_max_count being wrong. 446 * This shouldn't happen in normal operation, 447 * but it may happen if set_timer_freq() is 448 * traced. 449 */ 450 if (delta < 0) 451 delta = 0; 452 } 453 ticks_left -= delta; 454 } 455#ifdef DELAYDEBUG 456 if (state == 1) 457 printf(" %d calls to getit() at %d usec each\n", 458 getit_calls, (n + 5) / getit_calls); 459#endif 460} 461 462static void 463sysbeepstop(void *chan) 464{ 465 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 466 release_timer2(); 467 beeping = 0; 468} 469 470int 471sysbeep(int pitch, int period) 472{ 473 int x = splclock(); 474 475 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 476 if (!beeping) { 477 /* Something else owns it. */ 478 splx(x); 479 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 480 } 481 disable_intr(); 482 outb(TIMER_CNTR2, pitch); 483 outb(TIMER_CNTR2, (pitch>>8)); 484 enable_intr(); 485 if (!beeping) { 486 /* enable counter2 output to speaker */ 487 outb(IO_PPI, inb(IO_PPI) | 3); 488 beeping = period; 489 timeout(sysbeepstop, (void *)NULL, period); 490 } 491 splx(x); 492 return (0); 493} 494 495/* 496 * RTC support routines 497 */ 498 499int 500rtcin(reg) 501 int reg; 502{ 503 u_char val; 504 505 outb(IO_RTC, reg); 506 inb(0x84); 507 val = inb(IO_RTC + 1); 508 inb(0x84); 509 return (val); 510} 511 512static __inline void 513writertc(u_char reg, u_char val) 514{ 515 outb(IO_RTC, reg); 516 outb(IO_RTC + 1, val); 517} 518 519static __inline int 520readrtc(int port) 521{ 522 return(bcd2bin(rtcin(port))); 523} 524 525static u_int 526calibrate_clocks(void) 527{ 528 u_int count, prev_count, tot_count; 529 int sec, start_sec, timeout; 530 531 if (bootverbose) 532 printf("Calibrating clock(s) ... "); 533 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 534 goto fail; 535 timeout = 100000000; 536 537 /* Read the mc146818A seconds counter. */ 538 for (;;) { 539 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 540 sec = rtcin(RTC_SEC); 541 break; 542 } 543 if (--timeout == 0) 544 goto fail; 545 } 546 547 /* Wait for the mC146818A seconds counter to change. */ 548 start_sec = sec; 549 for (;;) { 550 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 551 sec = rtcin(RTC_SEC); 552 if (sec != start_sec) 553 break; 554 } 555 if (--timeout == 0) 556 goto fail; 557 } 558 559 /* Start keeping track of the i8254 counter. */ 560 prev_count = getit(); 561 if (prev_count == 0 || prev_count > timer0_max_count) 562 goto fail; 563 tot_count = 0; 564 565#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 566 if (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686) 567 wrmsr(0x10, 0LL); /* XXX 0x10 is the MSR for the TSC */ 568#endif 569 570 /* 571 * Wait for the mc146818A seconds counter to change. Read the i8254 572 * counter for each iteration since this is convenient and only 573 * costs a few usec of inaccuracy. The timing of the final reads 574 * of the counters almost matches the timing of the initial reads, 575 * so the main cause of inaccuracy is the varying latency from 576 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 577 * rtcin(RTC_SEC) that returns a changed seconds count. The 578 * maximum inaccuracy from this cause is < 10 usec on 486's. 579 */ 580 start_sec = sec; 581 for (;;) { 582 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 583 sec = rtcin(RTC_SEC); 584 count = getit(); 585 if (count == 0 || count > timer0_max_count) 586 goto fail; 587 if (count > prev_count) 588 tot_count += prev_count - (count - timer0_max_count); 589 else 590 tot_count += prev_count - count; 591 prev_count = count; 592 if (sec != start_sec) 593 break; 594 if (--timeout == 0) 595 goto fail; 596 } 597 598#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 599 /* 600 * Read the cpu cycle counter. The timing considerations are 601 * similar to those for the i8254 clock. 602 */ 603 if (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686) { 604 set_i586_ctr_freq((u_int)rdtsc(), tot_count); 605 if (bootverbose) 606 printf("i586 clock: %u Hz, ", i586_ctr_freq); 607 } 608#endif 609 610 if (bootverbose) 611 printf("i8254 clock: %u Hz\n", tot_count); 612 return (tot_count); 613 614fail: 615 if (bootverbose) 616 printf("failed, using default i8254 clock of %u Hz\n", 617 timer_freq); 618 return (timer_freq); 619} 620 621static void 622set_timer_freq(u_int freq, int intr_freq) 623{ 624 u_long ef; 625 626 ef = read_eflags(); 627 disable_intr(); 628 timer_freq = freq; 629 timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq); 630 timer0_overflow_threshold = timer0_max_count - TIMER0_LATCH_COUNT; 631 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 632 outb(TIMER_CNTR0, timer0_max_count & 0xff); 633 outb(TIMER_CNTR0, timer0_max_count >> 8); 634 write_eflags(ef); 635} 636 637/* 638 * Initialize 8253 timer 0 early so that it can be used in DELAY(). 639 * XXX initialization of other timers is unintentionally left blank. 640 */ 641void 642startrtclock() 643{ 644 u_int delta, freq; 645 646 writertc(RTC_STATUSA, rtc_statusa); 647 writertc(RTC_STATUSB, RTCSB_24HR); 648 649 set_timer_freq(timer_freq, hz); 650 freq = calibrate_clocks(); 651#ifdef CLK_CALIBRATION_LOOP 652 if (bootverbose) { 653 printf( 654 "Press a key on the console to abort clock calibration\n"); 655 while (cncheckc() == -1) 656 calibrate_clocks(); 657 } 658#endif 659 660 /* 661 * Use the calibrated i8254 frequency if it seems reasonable. 662 * Otherwise use the default, and don't use the calibrated i586 663 * frequency. 664 */ 665 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq; 666 if (delta < timer_freq / 100) { 667#ifndef CLK_USE_I8254_CALIBRATION 668 if (bootverbose) 669 printf( 670"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 671 freq = timer_freq; 672#endif 673 timer_freq = freq; 674 } else { 675 if (bootverbose) 676 printf( 677 "%d Hz differs from default of %d Hz by more than 1%%\n", 678 freq, timer_freq); 679#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 680 i586_ctr_freq = 0; 681#endif 682 } 683 684 set_timer_freq(timer_freq, hz); 685 686#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 687#ifndef CLK_USE_I586_CALIBRATION 688 if (i586_ctr_freq != 0) { 689 if (bootverbose) 690 printf( 691"CLK_USE_I586_CALIBRATION not specified - using old calibration method\n"); 692 i586_ctr_freq = 0; 693 } 694#endif 695 if (i586_ctr_freq == 0 && 696 (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686)) { 697 /* 698 * Calibration of the i586 clock relative to the mc146818A 699 * clock failed. Do a less accurate calibration relative 700 * to the i8254 clock. 701 */ 702 wrmsr(0x10, 0LL); /* XXX */ 703 DELAY(1000000); 704 set_i586_ctr_freq((u_int)rdtsc(), timer_freq); 705#ifdef CLK_USE_I586_CALIBRATION 706 if (bootverbose) 707 printf("i586 clock: %u Hz\n", i586_ctr_freq); 708#endif 709 } 710#endif 711} 712 713/* 714 * Initialize the time of day register, based on the time base which is, e.g. 715 * from a filesystem. 716 */ 717void 718inittodr(time_t base) 719{ 720 unsigned long sec, days; 721 int yd; 722 int year, month; 723 int y, m, s; 724 725 s = splclock(); 726 time.tv_sec = base; 727 time.tv_usec = 0; 728 splx(s); 729 730 /* Look if we have a RTC present and the time is valid */ 731 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 732 goto wrong_time; 733 734 /* wait for time update to complete */ 735 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 736 while (rtcin(RTC_STATUSA) & RTCSA_TUP); 737 738 days = 0; 739#ifdef USE_RTC_CENTURY 740 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 741#else 742 year = readrtc(RTC_YEAR) + 1900; 743 if (year < 1970) 744 year += 100; 745#endif 746 if (year < 1970) 747 goto wrong_time; 748 month = readrtc(RTC_MONTH); 749 for (m = 1; m < month; m++) 750 days += daysinmonth[m-1]; 751 if ((month > 2) && LEAPYEAR(year)) 752 days ++; 753 days += readrtc(RTC_DAY) - 1; 754 yd = days; 755 for (y = 1970; y < year; y++) 756 days += DAYSPERYEAR + LEAPYEAR(y); 757 sec = ((( days * 24 + 758 readrtc(RTC_HRS)) * 60 + 759 readrtc(RTC_MIN)) * 60 + 760 readrtc(RTC_SEC)); 761 /* sec now contains the number of seconds, since Jan 1 1970, 762 in the local time zone */ 763 764 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 765 766 s = splclock(); 767 time.tv_sec = sec; 768 splx(s); 769 return; 770 771wrong_time: 772 printf("Invalid time in real time clock.\n"); 773 printf("Check and reset the date immediately!\n"); 774} 775 776/* 777 * Write system time back to RTC 778 */ 779void 780resettodr() 781{ 782 unsigned long tm; 783 int y, m, s; 784 785 if (disable_rtc_set) 786 return; 787 788 s = splclock(); 789 tm = time.tv_sec; 790 splx(s); 791 792 /* Disable RTC updates and interrupts. */ 793 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 794 795 /* Calculate local time to put in RTC */ 796 797 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 798 799 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 800 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 801 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 802 803 /* We have now the days since 01-01-1970 in tm */ 804 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 805 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 806 tm >= m; 807 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 808 tm -= m; 809 810 /* Now we have the years in y and the day-of-the-year in tm */ 811 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 812#ifdef USE_RTC_CENTURY 813 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 814#endif 815 for (m = 0; ; m++) { 816 int ml; 817 818 ml = daysinmonth[m]; 819 if (m == 1 && LEAPYEAR(y)) 820 ml++; 821 if (tm < ml) 822 break; 823 tm -= ml; 824 } 825 826 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 827 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 828 829 /* Reenable RTC updates and interrupts. */ 830 writertc(RTC_STATUSB, rtc_statusb); 831} 832 833#ifdef APIC_IO 834 835/* XXX FIXME: from icu.s: */ 836extern u_int vec[]; 837extern void vec8254 __P((void)); 838extern void vecRTC __P((void)); 839extern u_int ivectors[]; 840extern u_int Xintr8254; 841extern u_int XintrRTC; 842extern u_int mask8254; 843extern u_int maskRTC; 844 845#endif /* APIC_IO */ 846 847/* 848 * Start both clocks running. 849 */ 850void 851cpu_initclocks() 852{ 853 int diag; 854#ifdef APIC_IO 855 int x; 856#endif /* APIC_IO */ 857 858 if (statclock_disable) { 859 /* 860 * The stat interrupt mask is different without the 861 * statistics clock. Also, don't set the interrupt 862 * flag which would normally cause the RTC to generate 863 * interrupts. 864 */ 865 stat_imask = HWI_MASK | SWI_MASK; 866 rtc_statusb = RTCSB_24HR; 867 } else { 868 /* Setting stathz to nonzero early helps avoid races. */ 869 stathz = RTC_NOPROFRATE; 870 profhz = RTC_PROFRATE; 871 } 872 873 /* Finish initializing 8253 timer 0. */ 874#ifdef APIC_IO 875#if 0 876#ifndef IO_ICU1 877#define IO_ICU1 0x20 878#endif /* IO_ICU1 */ 879#endif /** 0 */ 880 881 /* 8254 is traditionally on ISA IRQ0 */ 882 if ((x = isa_apic_pin(0)) < 0) { 883 /* bummer, attempt to redirect thru the 8259 */ 884 if (bootverbose) 885 printf("APIC missing 8254 connection\n"); 886 887 /* allow 8254 timer to INTerrupt 8259 */ 888#ifdef TEST_ALTTIMER 889 /* 890 * re-initialize master 8259: 891 * reset; prog 4 bytes, single ICU, edge triggered 892 */ 893 outb(IO_ICU1, 0x13); 894 outb(IO_ICU1 + 1, NRSVIDT); /* start vector */ 895 outb(IO_ICU1 + 1, 0x00); /* ignore slave */ 896 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */ 897 898 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */ 899#else 900 x = inb(IO_ICU1 + 1); /* current mask in 8259 */ 901 x &= ~1; /* clear 8254 timer mask */ 902 outb(IO_ICU1 + 1, x); /* write new mask */ 903#endif /* TEST_ALTTIMER */ 904 905 /* program IO APIC for type 3 INT on INT0 */ 906 if (ext_int_setup(0, 0) < 0) 907 panic("8254 redirect impossible!"); 908 x = 0; /* 8259 is on 0 */ 909 } 910 911 vec[x] = (u_int)vec8254; 912 Xintr8254 = (u_int)ivectors[x]; /* XXX might need Xfastintr# */ 913 mask8254 = (1 << x); 914 register_intr(/* irq */ x, /* XXX id */ 0, /* flags */ 0, 915 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 916 /* unit */ 0); 917 INTREN(mask8254); 918#else 919 register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0, 920 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 921 /* unit */ 0); 922 INTREN(IRQ0); 923#endif /* APIC_IO */ 924 925#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 926 /* 927 * Finish setting up anti-jitter measures. 928 */ 929 if (i586_ctr_freq != 0) 930 i586_ctr_bias = rdtsc(); 931#endif 932 933 /* Initialize RTC. */ 934 writertc(RTC_STATUSA, rtc_statusa); 935 writertc(RTC_STATUSB, RTCSB_24HR); 936 937 /* Don't bother enabling the statistics clock. */ 938 if (statclock_disable) 939 return; 940 diag = rtcin(RTC_DIAG); 941 if (diag != 0) 942 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS); 943#ifdef APIC_IO 944 /* RTC is traditionally on ISA IRQ8 */ 945 if ((x = isa_apic_pin(8)) < 0) 946 panic("APIC missing RTC connection"); 947 948 vec[x] = (u_int)vecRTC; 949 XintrRTC = (u_int)ivectors[x]; /* XXX might need Xfastintr# */ 950 maskRTC = (1 << x); 951 register_intr(/* irq */ x, /* XXX id */ 1, /* flags */ 0, 952 /* XXX */ (inthand2_t *)rtcintr, &stat_imask, 953 /* unit */ 0); 954 INTREN(maskRTC); 955#else 956 register_intr(/* irq */ 8, /* XXX id */ 1, /* flags */ 0, 957 /* XXX */ (inthand2_t *)rtcintr, &stat_imask, 958 /* unit */ 0); 959 INTREN(IRQ8); 960#endif /* APIC_IO */ 961 writertc(RTC_STATUSB, rtc_statusb); 962 963#ifdef APIC_IO 964 if (bootverbose) { 965 printf("SMP: enabled INTs: "); 966 for (x = 0; x < 24; ++x) 967 if ((imen & (1 << x)) == 0) 968 printf("%d, ", x); 969 printf("imen: 0x%08x\n", imen); 970 } 971#endif /* APIC_IO */ 972} 973 974void 975setstatclockrate(int newhz) 976{ 977 if (newhz == RTC_PROFRATE) 978 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 979 else 980 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 981 writertc(RTC_STATUSA, rtc_statusa); 982} 983 984static int 985sysctl_machdep_i8254_freq SYSCTL_HANDLER_ARGS 986{ 987 int error; 988 u_int freq; 989 990 /* 991 * Use `i8254' instead of `timer' in external names because `timer' 992 * is is too generic. Should use it everywhere. 993 */ 994 freq = timer_freq; 995 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 996 if (error == 0 && req->newptr != NULL) { 997 if (timer0_state != 0) 998 return (EBUSY); /* too much trouble to handle */ 999 set_timer_freq(freq, hz); 1000#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 1001 set_i586_ctr_freq(i586_ctr_freq, timer_freq); 1002#endif 1003 } 1004 return (error); 1005} 1006 1007SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW, 1008 0, sizeof(u_int), sysctl_machdep_i8254_freq, "I", ""); 1009 1010#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 1011static void 1012set_i586_ctr_freq(u_int i586_freq, u_int i8254_freq) 1013{ 1014 u_int comultiplier, multiplier; 1015 u_long ef; 1016 1017 if (i586_freq == 0) { 1018 i586_ctr_freq = i586_freq; 1019 return; 1020 } 1021 comultiplier = ((unsigned long long)i586_freq 1022 << I586_CTR_COMULTIPLIER_SHIFT) / i8254_freq; 1023 multiplier = (1000000LL << I586_CTR_MULTIPLIER_SHIFT) / i586_freq; 1024 ef = read_eflags(); 1025 disable_intr(); 1026 i586_ctr_freq = i586_freq; 1027 i586_ctr_comultiplier = comultiplier; 1028 i586_ctr_multiplier = multiplier; 1029 write_eflags(ef); 1030} 1031 1032static int 1033sysctl_machdep_i586_freq SYSCTL_HANDLER_ARGS 1034{ 1035 int error; 1036 u_int freq; 1037 1038 if (cpu_class != CPUCLASS_586 && cpu_class != CPUCLASS_686) 1039 return (EOPNOTSUPP); 1040 freq = i586_ctr_freq; 1041 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 1042 if (error == 0 && req->newptr != NULL) 1043 set_i586_ctr_freq(freq, timer_freq); 1044 return (error); 1045} 1046 1047SYSCTL_PROC(_machdep, OID_AUTO, i586_freq, CTLTYPE_INT | CTLFLAG_RW, 1048 0, sizeof(u_int), sysctl_machdep_i586_freq, "I", ""); 1049#endif /* (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) */ 1050