tsc.c revision 17395
1/*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz and Don Ahn. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 37 * $Id: clock.c,v 1.66 1996/07/30 19:26:47 bde Exp $ 38 */ 39 40/* 41 * inittodr, settodr and support routines written 42 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 43 * 44 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 45 */ 46 47/* 48 * Primitive clock interrupt routines. 49 */ 50#include "opt_ddb.h" 51#include "opt_clock.h" 52 53#include <sys/param.h> 54#include <sys/systm.h> 55#include <sys/time.h> 56#include <sys/kernel.h> 57#include <sys/sysctl.h> 58 59#include <machine/clock.h> 60#ifdef CLK_CALIBRATION_LOOP 61#include <machine/cons.h> 62#endif 63#include <machine/cpu.h> 64#include <machine/frame.h> 65 66#include <i386/isa/icu.h> 67#include <i386/isa/isa.h> 68#include <i386/isa/isa_device.h> 69#include <i386/isa/rtc.h> 70#include <i386/isa/timerreg.h> 71 72/* 73 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 74 * can use a simple formula for leap years. 75 */ 76#define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 77#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 78 79#define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x)) 80 81/* 82 * Time in timer cycles that it takes for microtime() to disable interrupts 83 * and latch the count. microtime() currently uses "cli; outb ..." so it 84 * normally takes less than 2 timer cycles. Add a few for cache misses. 85 * Add a few more to allow for latency in bogus calls to microtime() with 86 * interrupts already disabled. 87 */ 88#define TIMER0_LATCH_COUNT 20 89 90/* 91 * Maximum frequency that we are willing to allow for timer0. Must be 92 * low enough to guarantee that the timer interrupt handler returns 93 * before the next timer interrupt. Must result in a lower TIMER_DIV 94 * value than TIMER0_LATCH_COUNT so that we don't have to worry about 95 * underflow in the calculation of timer0_overflow_threshold. 96 */ 97#define TIMER0_MAX_FREQ 20000 98 99int adjkerntz; /* local offset from GMT in seconds */ 100int disable_rtc_set; /* disable resettodr() if != 0 */ 101int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 102 103u_int idelayed; 104#if defined(I586_CPU) || defined(I686_CPU) 105u_int i586_ctr_bias; 106u_int i586_ctr_comultiplier; 107u_int i586_ctr_freq; 108u_int i586_ctr_multiplier; 109long long i586_last_tick; 110unsigned long i586_avg_tick; 111#endif 112int statclock_disable; 113u_int stat_imask = SWI_CLOCK_MASK; 114#ifdef TIMER_FREQ 115u_int timer_freq = TIMER_FREQ; 116#else 117u_int timer_freq = 1193182; 118#endif 119int timer0_max_count; 120u_int timer0_overflow_threshold; 121u_int timer0_prescaler_count; 122 123static int beeping = 0; 124static u_int clk_imask = HWI_MASK | SWI_MASK; 125static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 126static u_int hardclock_max_count; 127/* 128 * XXX new_function and timer_func should not handle clockframes, but 129 * timer_func currently needs to hold hardclock to handle the 130 * timer0_state == 0 case. We should use register_intr()/unregister_intr() 131 * to switch between clkintr() and a slightly different timerintr(). 132 */ 133static void (*new_function) __P((struct clockframe *frame)); 134static u_int new_rate; 135static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 136static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 137 138/* Values for timerX_state: */ 139#define RELEASED 0 140#define RELEASE_PENDING 1 141#define ACQUIRED 2 142#define ACQUIRE_PENDING 3 143 144static u_char timer0_state; 145static u_char timer2_state; 146static void (*timer_func) __P((struct clockframe *frame)) = hardclock; 147 148#if defined(I586_CPU) || defined(I686_CPU) 149static void set_i586_ctr_freq(u_int i586_freq, u_int i8254_freq); 150#endif 151 152static void 153clkintr(struct clockframe frame) 154{ 155 timer_func(&frame); 156 switch (timer0_state) { 157 158 case RELEASED: 159 setdelayed(); 160 break; 161 162 case ACQUIRED: 163 if ((timer0_prescaler_count += timer0_max_count) 164 >= hardclock_max_count) { 165 hardclock(&frame); 166 setdelayed(); 167 timer0_prescaler_count -= hardclock_max_count; 168 } 169 break; 170 171 case ACQUIRE_PENDING: 172 setdelayed(); 173 timer0_max_count = TIMER_DIV(new_rate); 174 timer0_overflow_threshold = 175 timer0_max_count - TIMER0_LATCH_COUNT; 176 disable_intr(); 177 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 178 outb(TIMER_CNTR0, timer0_max_count & 0xff); 179 outb(TIMER_CNTR0, timer0_max_count >> 8); 180 enable_intr(); 181 timer0_prescaler_count = 0; 182 timer_func = new_function; 183 timer0_state = ACQUIRED; 184 break; 185 186 case RELEASE_PENDING: 187 if ((timer0_prescaler_count += timer0_max_count) 188 >= hardclock_max_count) { 189 hardclock(&frame); 190 setdelayed(); 191 timer0_max_count = hardclock_max_count; 192 timer0_overflow_threshold = 193 timer0_max_count - TIMER0_LATCH_COUNT; 194 disable_intr(); 195 outb(TIMER_MODE, 196 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 197 outb(TIMER_CNTR0, timer0_max_count & 0xff); 198 outb(TIMER_CNTR0, timer0_max_count >> 8); 199 enable_intr(); 200 /* 201 * See microtime.s for this magic. 202 */ 203 time.tv_usec += (27465 * 204 (timer0_prescaler_count - hardclock_max_count)) 205 >> 15; 206 if (time.tv_usec >= 1000000) 207 time.tv_usec -= 1000000; 208 timer0_prescaler_count = 0; 209 timer_func = hardclock; 210 timer0_state = RELEASED; 211 } 212 break; 213 } 214} 215 216/* 217 * The acquire and release functions must be called at ipl >= splclock(). 218 */ 219int 220acquire_timer0(int rate, void (*function) __P((struct clockframe *frame))) 221{ 222 static int old_rate; 223 224 if (rate <= 0 || rate > TIMER0_MAX_FREQ) 225 return (-1); 226 switch (timer0_state) { 227 228 case RELEASED: 229 timer0_state = ACQUIRE_PENDING; 230 break; 231 232 case RELEASE_PENDING: 233 if (rate != old_rate) 234 return (-1); 235 /* 236 * The timer has been released recently, but is being 237 * re-acquired before the release completed. In this 238 * case, we simply reclaim it as if it had not been 239 * released at all. 240 */ 241 timer0_state = ACQUIRED; 242 break; 243 244 default: 245 return (-1); /* busy */ 246 } 247 new_function = function; 248 old_rate = new_rate = rate; 249 return (0); 250} 251 252int 253acquire_timer2(int mode) 254{ 255 256 if (timer2_state != RELEASED) 257 return (-1); 258 timer2_state = ACQUIRED; 259 260 /* 261 * This access to the timer registers is as atomic as possible 262 * because it is a single instruction. We could do better if we 263 * knew the rate. Use of splclock() limits glitches to 10-100us, 264 * and this is probably good enough for timer2, so we aren't as 265 * careful with it as with timer0. 266 */ 267 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 268 269 return (0); 270} 271 272int 273release_timer0() 274{ 275 switch (timer0_state) { 276 277 case ACQUIRED: 278 timer0_state = RELEASE_PENDING; 279 break; 280 281 case ACQUIRE_PENDING: 282 /* Nothing happened yet, release quickly. */ 283 timer0_state = RELEASED; 284 break; 285 286 default: 287 return (-1); 288 } 289 return (0); 290} 291 292int 293release_timer2() 294{ 295 296 if (timer2_state != ACQUIRED) 297 return (-1); 298 timer2_state = RELEASED; 299 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 300 return (0); 301} 302 303/* 304 * This routine receives statistical clock interrupts from the RTC. 305 * As explained above, these occur at 128 interrupts per second. 306 * When profiling, we receive interrupts at a rate of 1024 Hz. 307 * 308 * This does not actually add as much overhead as it sounds, because 309 * when the statistical clock is active, the hardclock driver no longer 310 * needs to keep (inaccurate) statistics on its own. This decouples 311 * statistics gathering from scheduling interrupts. 312 * 313 * The RTC chip requires that we read status register C (RTC_INTR) 314 * to acknowledge an interrupt, before it will generate the next one. 315 */ 316static void 317rtcintr(struct clockframe frame) 318{ 319 u_char stat; 320 stat = rtcin(RTC_INTR); 321 if(stat & RTCIR_PERIOD) { 322 statclock(&frame); 323 } 324} 325 326#ifdef DDB 327static void 328DDB_printrtc(void) 329{ 330 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 331 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 332 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 333 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 334} 335#endif 336 337static int 338getit(void) 339{ 340 u_long ef; 341 int high, low; 342 343 ef = read_eflags(); 344 disable_intr(); 345 346 /* Select timer0 and latch counter value. */ 347 outb(TIMER_MODE, TIMER_SEL0); 348 349 low = inb(TIMER_CNTR0); 350 high = inb(TIMER_CNTR0); 351 352 write_eflags(ef); 353 return ((high << 8) | low); 354} 355 356/* 357 * Wait "n" microseconds. 358 * Relies on timer 1 counting down from (timer_freq / hz) 359 * Note: timer had better have been programmed before this is first used! 360 */ 361void 362DELAY(int n) 363{ 364 int prev_tick, tick, ticks_left, sec, usec; 365 366#ifdef DELAYDEBUG 367 int getit_calls = 1; 368 int n1; 369 static int state = 0; 370 371 if (state == 0) { 372 state = 1; 373 for (n1 = 1; n1 <= 10000000; n1 *= 10) 374 DELAY(n1); 375 state = 2; 376 } 377 if (state == 1) 378 printf("DELAY(%d)...", n); 379#endif 380 /* 381 * Read the counter first, so that the rest of the setup overhead is 382 * counted. Guess the initial overhead is 20 usec (on most systems it 383 * takes about 1.5 usec for each of the i/o's in getit(). The loop 384 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The 385 * multiplications and divisions to scale the count take a while). 386 */ 387 prev_tick = getit(); 388 n -= 20; 389 /* 390 * Calculate (n * (timer_freq / 1e6)) without using floating point 391 * and without any avoidable overflows. 392 */ 393 sec = n / 1000000; 394 usec = n - sec * 1000000; 395 ticks_left = sec * timer_freq 396 + usec * (timer_freq / 1000000) 397 + usec * ((timer_freq % 1000000) / 1000) / 1000 398 + usec * (timer_freq % 1000) / 1000000; 399 if (n < 0) 400 ticks_left = 0; /* XXX timer_freq is unsigned */ 401 402 while (ticks_left > 0) { 403 tick = getit(); 404#ifdef DELAYDEBUG 405 ++getit_calls; 406#endif 407 if (tick > prev_tick) 408 ticks_left -= prev_tick - (tick - timer0_max_count); 409 else 410 ticks_left -= prev_tick - tick; 411 prev_tick = tick; 412 } 413#ifdef DELAYDEBUG 414 if (state == 1) 415 printf(" %d calls to getit() at %d usec each\n", 416 getit_calls, (n + 5) / getit_calls); 417#endif 418} 419 420static void 421sysbeepstop(void *chan) 422{ 423 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 424 release_timer2(); 425 beeping = 0; 426} 427 428int 429sysbeep(int pitch, int period) 430{ 431 int x = splclock(); 432 433 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 434 if (!beeping) { 435 /* Something else owns it. */ 436 splx(x); 437 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 438 } 439 disable_intr(); 440 outb(TIMER_CNTR2, pitch); 441 outb(TIMER_CNTR2, (pitch>>8)); 442 enable_intr(); 443 if (!beeping) { 444 /* enable counter2 output to speaker */ 445 outb(IO_PPI, inb(IO_PPI) | 3); 446 beeping = period; 447 timeout(sysbeepstop, (void *)NULL, period); 448 } 449 splx(x); 450 return (0); 451} 452 453/* 454 * RTC support routines 455 */ 456 457int 458rtcin(reg) 459 int reg; 460{ 461 u_char val; 462 463 outb(IO_RTC, reg); 464 inb(0x84); 465 val = inb(IO_RTC + 1); 466 inb(0x84); 467 return (val); 468} 469 470static __inline void 471writertc(u_char reg, u_char val) 472{ 473 outb(IO_RTC, reg); 474 outb(IO_RTC + 1, val); 475} 476 477static __inline int 478readrtc(int port) 479{ 480 return(bcd2bin(rtcin(port))); 481} 482 483static u_int 484calibrate_clocks(void) 485{ 486 u_int count, prev_count, tot_count; 487 int sec, start_sec, timeout; 488 489 printf("Calibrating clock(s) relative to mc146818A clock...\n"); 490 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 491 goto fail; 492 timeout = 100000000; 493 494 /* Read the mc146818A seconds counter. */ 495 for (;;) { 496 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 497 sec = rtcin(RTC_SEC); 498 break; 499 } 500 if (--timeout == 0) 501 goto fail; 502 } 503 504 /* Wait for the mC146818A seconds counter to change. */ 505 start_sec = sec; 506 for (;;) { 507 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 508 sec = rtcin(RTC_SEC); 509 if (sec != start_sec) 510 break; 511 } 512 if (--timeout == 0) 513 goto fail; 514 } 515 516 /* Start keeping track of the i8254 counter. */ 517 prev_count = getit(); 518 if (prev_count == 0 || prev_count > timer0_max_count) 519 goto fail; 520 tot_count = 0; 521 522#if defined(I586_CPU) || defined(I686_CPU) 523 if (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686) 524 wrmsr(0x10, 0LL); /* XXX 0x10 is the MSR for the TSC */ 525#endif 526 527 /* 528 * Wait for the mc146818A seconds counter to change. Read the i8254 529 * counter for each iteration since this is convenient and only 530 * costs a few usec of inaccuracy. The timing of the final reads 531 * of the counters almost matches the timing of the initial reads, 532 * so the main cause of inaccuracy is the varying latency from 533 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 534 * rtcin(RTC_SEC) that returns a changed seconds count. The 535 * maximum inaccuracy from this cause is < 10 usec on 486's. 536 */ 537 start_sec = sec; 538 for (;;) { 539 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 540 sec = rtcin(RTC_SEC); 541 count = getit(); 542 if (count == 0 || count > timer0_max_count) 543 goto fail; 544 if (count > prev_count) 545 tot_count += prev_count - (count - timer0_max_count); 546 else 547 tot_count += prev_count - count; 548 prev_count = count; 549 if (sec != start_sec) 550 break; 551 if (--timeout == 0) 552 goto fail; 553 } 554 555#if defined(I586_CPU) || defined(I686_CPU) 556 /* 557 * Read the cpu cycle counter. The timing considerations are 558 * similar to those for the i8254 clock. 559 */ 560 if (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686) { 561 set_i586_ctr_freq((u_int)rdtsc(), tot_count); 562 printf("i586 clock: %u Hz, ", i586_ctr_freq); 563 } 564#endif 565 566 printf("i8254 clock: %u Hz\n", tot_count); 567 return (tot_count); 568 569fail: 570 printf("failed, using default i8254 clock of %u Hz\n", timer_freq); 571 return (timer_freq); 572} 573 574static void 575set_timer_freq(u_int freq, int intr_freq) 576{ 577 u_long ef; 578 579 ef = read_eflags(); 580 disable_intr(); 581 timer_freq = freq; 582 timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq); 583 timer0_overflow_threshold = timer0_max_count - TIMER0_LATCH_COUNT; 584 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 585 outb(TIMER_CNTR0, timer0_max_count & 0xff); 586 outb(TIMER_CNTR0, timer0_max_count >> 8); 587 write_eflags(ef); 588} 589 590/* 591 * Initialize 8253 timer 0 early so that it can be used in DELAY(). 592 * XXX initialization of other timers is unintentionally left blank. 593 */ 594void 595startrtclock() 596{ 597 u_int delta, freq; 598 599 writertc(RTC_STATUSA, rtc_statusa); 600 writertc(RTC_STATUSB, RTCSB_24HR); 601 602 set_timer_freq(timer_freq, hz); 603 freq = calibrate_clocks(); 604#ifdef CLK_CALIBRATION_LOOP 605 if (bootverbose) { 606 printf( 607 "Press a key on the console to abort clock calibration\n"); 608 while (!cncheckc()) 609 calibrate_clocks(); 610 } 611#endif 612 613 /* 614 * Use the calibrated i8254 frequency if it seems reasonable. 615 * Otherwise use the default, and don't use the calibrated i586 616 * frequency. 617 */ 618 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq; 619 if (delta < timer_freq / 100) { 620#ifndef CLK_USE_I8254_CALIBRATION 621 if (bootverbose) 622 printf( 623"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 624 freq = timer_freq; 625#endif 626 timer_freq = freq; 627 } else { 628 printf("%d Hz differs from default of %d Hz by more than 1%%\n", 629 freq, timer_freq); 630#if defined(I586_CPU) || defined(I686_CPU) 631 i586_ctr_freq = 0; 632#endif 633 } 634 635 set_timer_freq(timer_freq, hz); 636 637#if defined(I586_CPU) || defined(I686_CPU) 638#ifndef CLK_USE_I586_CALIBRATION 639 if (i586_ctr_freq != 0) { 640 if (bootverbose) 641 printf( 642"CLK_USE_I586_CALIBRATION not specified - using old calibration method\n"); 643 i586_ctr_freq = 0; 644 } 645#endif 646 if (i586_ctr_freq == 0 && 647 (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686)) { 648 /* 649 * Calibration of the i586 clock relative to the mc146818A 650 * clock failed. Do a less accurate calibration relative 651 * to the i8254 clock. 652 */ 653 wrmsr(0x10, 0LL); /* XXX */ 654 DELAY(1000000); 655 set_i586_ctr_freq((u_int)rdtsc(), timer_freq); 656#ifdef CLK_USE_I586_CALIBRATION 657 printf("i586 clock: %u Hz\n", i586_ctr_freq); 658#endif 659 } 660#endif 661} 662 663/* 664 * Initialize the time of day register, based on the time base which is, e.g. 665 * from a filesystem. 666 */ 667void 668inittodr(time_t base) 669{ 670 unsigned long sec, days; 671 int yd; 672 int year, month; 673 int y, m, s; 674 675 s = splclock(); 676 time.tv_sec = base; 677 time.tv_usec = 0; 678 splx(s); 679 680 /* Look if we have a RTC present and the time is valid */ 681 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 682 goto wrong_time; 683 684 /* wait for time update to complete */ 685 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 686 while (rtcin(RTC_STATUSA) & RTCSA_TUP); 687 688 days = 0; 689#ifdef USE_RTC_CENTURY 690 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 691#else 692 year = readrtc(RTC_YEAR) + 1900; 693 if (year < 1970) 694 year += 100; 695#endif 696 if (year < 1970) 697 goto wrong_time; 698 month = readrtc(RTC_MONTH); 699 for (m = 1; m < month; m++) 700 days += daysinmonth[m-1]; 701 if ((month > 2) && LEAPYEAR(year)) 702 days ++; 703 days += readrtc(RTC_DAY) - 1; 704 yd = days; 705 for (y = 1970; y < year; y++) 706 days += DAYSPERYEAR + LEAPYEAR(y); 707 sec = ((( days * 24 + 708 readrtc(RTC_HRS)) * 60 + 709 readrtc(RTC_MIN)) * 60 + 710 readrtc(RTC_SEC)); 711 /* sec now contains the number of seconds, since Jan 1 1970, 712 in the local time zone */ 713 714 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 715 716 s = splclock(); 717 time.tv_sec = sec; 718 splx(s); 719 return; 720 721wrong_time: 722 printf("Invalid time in real time clock.\n"); 723 printf("Check and reset the date immediately!\n"); 724} 725 726/* 727 * Write system time back to RTC 728 */ 729void 730resettodr() 731{ 732 unsigned long tm; 733 int y, m, s; 734 735 if (disable_rtc_set) 736 return; 737 738 s = splclock(); 739 tm = time.tv_sec; 740 splx(s); 741 742 /* Disable RTC updates and interrupts. */ 743 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 744 745 /* Calculate local time to put in RTC */ 746 747 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 748 749 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 750 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 751 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 752 753 /* We have now the days since 01-01-1970 in tm */ 754 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 755 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 756 tm >= m; 757 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 758 tm -= m; 759 760 /* Now we have the years in y and the day-of-the-year in tm */ 761 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 762#ifdef USE_RTC_CENTURY 763 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 764#endif 765 for (m = 0; ; m++) { 766 int ml; 767 768 ml = daysinmonth[m]; 769 if (m == 1 && LEAPYEAR(y)) 770 ml++; 771 if (tm < ml) 772 break; 773 tm -= ml; 774 } 775 776 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 777 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 778 779 /* Reenable RTC updates and interrupts. */ 780 writertc(RTC_STATUSB, rtc_statusb); 781} 782 783/* 784 * Start both clocks running. 785 */ 786void 787cpu_initclocks() 788{ 789 int diag; 790 791 if (statclock_disable) { 792 /* 793 * The stat interrupt mask is different without the 794 * statistics clock. Also, don't set the interrupt 795 * flag which would normally cause the RTC to generate 796 * interrupts. 797 */ 798 stat_imask = HWI_MASK | SWI_MASK; 799 rtc_statusb = RTCSB_24HR; 800 } else { 801 /* Setting stathz to nonzero early helps avoid races. */ 802 stathz = RTC_NOPROFRATE; 803 profhz = RTC_PROFRATE; 804 } 805 806 /* Finish initializing 8253 timer 0. */ 807 register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0, 808 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 809 /* unit */ 0); 810 INTREN(IRQ0); 811#if defined(I586_CPU) || defined(I686_CPU) 812 /* 813 * Finish setting up anti-jitter measures. 814 */ 815 if (i586_ctr_freq != 0) { 816 i586_last_tick = rdtsc(); 817 i586_ctr_bias = i586_last_tick; 818 } 819#endif 820 821 /* Initialize RTC. */ 822 writertc(RTC_STATUSA, rtc_statusa); 823 writertc(RTC_STATUSB, RTCSB_24HR); 824 825 /* Don't bother enabling the statistics clock. */ 826 if (statclock_disable) 827 return; 828 diag = rtcin(RTC_DIAG); 829 if (diag != 0) 830 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS); 831 register_intr(/* irq */ 8, /* XXX id */ 1, /* flags */ 0, 832 /* XXX */ (inthand2_t *)rtcintr, &stat_imask, 833 /* unit */ 0); 834 INTREN(IRQ8); 835 writertc(RTC_STATUSB, rtc_statusb); 836} 837 838void 839setstatclockrate(int newhz) 840{ 841 if (newhz == RTC_PROFRATE) 842 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 843 else 844 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 845 writertc(RTC_STATUSA, rtc_statusa); 846} 847 848static int 849sysctl_machdep_i8254_freq SYSCTL_HANDLER_ARGS 850{ 851 int error; 852 u_int freq; 853 854 /* 855 * Use `i8254' instead of `timer' in external names because `timer' 856 * is is too generic. Should use it everywhere. 857 */ 858 freq = timer_freq; 859 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 860 if (error == 0 && req->newptr != NULL) { 861 if (timer0_state != 0) 862 return (EBUSY); /* too much trouble to handle */ 863 set_timer_freq(freq, hz); 864#if defined(I586_CPU) || defined(I686_CPU) 865 set_i586_ctr_freq(i586_ctr_freq, timer_freq); 866#endif 867 } 868 return (error); 869} 870 871SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW, 872 0, sizeof(u_int), sysctl_machdep_i8254_freq, "I", ""); 873 874#if defined(I586_CPU) || defined(I686_CPU) 875static void 876set_i586_ctr_freq(u_int i586_freq, u_int i8254_freq) 877{ 878 u_int comultiplier, multiplier; 879 u_long ef; 880 881 if (i586_freq == 0) { 882 i586_ctr_freq = i586_freq; 883 return; 884 } 885 comultiplier = ((unsigned long long)i586_freq 886 << I586_CTR_COMULTIPLIER_SHIFT) / i8254_freq; 887 multiplier = (1000000LL << I586_CTR_MULTIPLIER_SHIFT) / i586_freq; 888 ef = read_eflags(); 889 disable_intr(); 890 i586_ctr_freq = i586_freq; 891 i586_ctr_comultiplier = comultiplier; 892 i586_ctr_multiplier = multiplier; 893 write_eflags(ef); 894} 895 896static int 897sysctl_machdep_i586_freq SYSCTL_HANDLER_ARGS 898{ 899 int error; 900 u_int freq; 901 902 if (cpu_class != CPUCLASS_586 && cpu_class != CPUCLASS_686) 903 return (EOPNOTSUPP); 904 freq = i586_ctr_freq; 905 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 906 if (error == 0 && req->newptr != NULL) 907 set_i586_ctr_freq(freq, timer_freq); 908 return (error); 909} 910 911SYSCTL_PROC(_machdep, OID_AUTO, i586_freq, CTLTYPE_INT | CTLFLAG_RW, 912 0, sizeof(u_int), sysctl_machdep_i586_freq, "I", ""); 913#endif /* defined(I586_CPU) || defined(I686_CPU) */ 914