mptable.c revision 79609
1/* 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: head/sys/i386/i386/mptable.c 79609 2001-07-12 06:32:51Z peter $ 26 */ 27 28#include "opt_cpu.h" 29 30#ifdef SMP 31#include <machine/smptests.h> 32#else 33#error 34#endif 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/bus.h> 39#include <sys/cons.h> /* cngetc() */ 40#include <sys/dkstat.h> 41#ifdef GPROF 42#include <sys/gmon.h> 43#endif 44#include <sys/kernel.h> 45#include <sys/lock.h> 46#include <sys/malloc.h> 47#include <sys/memrange.h> 48#include <sys/mutex.h> 49#include <sys/pcpu.h> 50#include <sys/proc.h> 51#include <sys/smp.h> 52#include <sys/sysctl.h> 53#include <sys/user.h> 54 55#include <vm/vm.h> 56#include <vm/vm_param.h> 57#include <vm/pmap.h> 58#include <vm/vm_kern.h> 59#include <vm/vm_extern.h> 60#include <vm/vm_map.h> 61 62#include <machine/apic.h> 63#include <machine/atomic.h> 64#include <machine/cpu.h> 65#include <machine/cpufunc.h> 66#include <machine/mpapic.h> 67#include <machine/psl.h> 68#include <machine/segments.h> 69#include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */ 70#include <machine/tss.h> 71#include <machine/specialreg.h> 72#include <machine/globaldata.h> 73 74#if defined(APIC_IO) 75#include <machine/md_var.h> /* setidt() */ 76#include <i386/isa/icu.h> /* IPIs */ 77#include <i386/isa/intr_machdep.h> /* IPIs */ 78#endif /* APIC_IO */ 79 80#if defined(TEST_DEFAULT_CONFIG) 81#define MPFPS_MPFB1 TEST_DEFAULT_CONFIG 82#else 83#define MPFPS_MPFB1 mpfps->mpfb1 84#endif /* TEST_DEFAULT_CONFIG */ 85 86#define WARMBOOT_TARGET 0 87#define WARMBOOT_OFF (KERNBASE + 0x0467) 88#define WARMBOOT_SEG (KERNBASE + 0x0469) 89 90#ifdef PC98 91#define BIOS_BASE (0xe8000) 92#define BIOS_SIZE (0x18000) 93#else 94#define BIOS_BASE (0xf0000) 95#define BIOS_SIZE (0x10000) 96#endif 97#define BIOS_COUNT (BIOS_SIZE/4) 98 99#define CMOS_REG (0x70) 100#define CMOS_DATA (0x71) 101#define BIOS_RESET (0x0f) 102#define BIOS_WARM (0x0a) 103 104#define PROCENTRY_FLAG_EN 0x01 105#define PROCENTRY_FLAG_BP 0x02 106#define IOAPICENTRY_FLAG_EN 0x01 107 108 109/* MP Floating Pointer Structure */ 110typedef struct MPFPS { 111 char signature[4]; 112 void *pap; 113 u_char length; 114 u_char spec_rev; 115 u_char checksum; 116 u_char mpfb1; 117 u_char mpfb2; 118 u_char mpfb3; 119 u_char mpfb4; 120 u_char mpfb5; 121} *mpfps_t; 122 123/* MP Configuration Table Header */ 124typedef struct MPCTH { 125 char signature[4]; 126 u_short base_table_length; 127 u_char spec_rev; 128 u_char checksum; 129 u_char oem_id[8]; 130 u_char product_id[12]; 131 void *oem_table_pointer; 132 u_short oem_table_size; 133 u_short entry_count; 134 void *apic_address; 135 u_short extended_table_length; 136 u_char extended_table_checksum; 137 u_char reserved; 138} *mpcth_t; 139 140 141typedef struct PROCENTRY { 142 u_char type; 143 u_char apic_id; 144 u_char apic_version; 145 u_char cpu_flags; 146 u_long cpu_signature; 147 u_long feature_flags; 148 u_long reserved1; 149 u_long reserved2; 150} *proc_entry_ptr; 151 152typedef struct BUSENTRY { 153 u_char type; 154 u_char bus_id; 155 char bus_type[6]; 156} *bus_entry_ptr; 157 158typedef struct IOAPICENTRY { 159 u_char type; 160 u_char apic_id; 161 u_char apic_version; 162 u_char apic_flags; 163 void *apic_address; 164} *io_apic_entry_ptr; 165 166typedef struct INTENTRY { 167 u_char type; 168 u_char int_type; 169 u_short int_flags; 170 u_char src_bus_id; 171 u_char src_bus_irq; 172 u_char dst_apic_id; 173 u_char dst_apic_int; 174} *int_entry_ptr; 175 176/* descriptions of MP basetable entries */ 177typedef struct BASETABLE_ENTRY { 178 u_char type; 179 u_char length; 180 char name[16]; 181} basetable_entry; 182 183/* 184 * this code MUST be enabled here and in mpboot.s. 185 * it follows the very early stages of AP boot by placing values in CMOS ram. 186 * it NORMALLY will never be needed and thus the primitive method for enabling. 187 * 188#define CHECK_POINTS 189 */ 190 191#if defined(CHECK_POINTS) && !defined(PC98) 192#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 193#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 194 195#define CHECK_INIT(D); \ 196 CHECK_WRITE(0x34, (D)); \ 197 CHECK_WRITE(0x35, (D)); \ 198 CHECK_WRITE(0x36, (D)); \ 199 CHECK_WRITE(0x37, (D)); \ 200 CHECK_WRITE(0x38, (D)); \ 201 CHECK_WRITE(0x39, (D)); 202 203#define CHECK_PRINT(S); \ 204 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 205 (S), \ 206 CHECK_READ(0x34), \ 207 CHECK_READ(0x35), \ 208 CHECK_READ(0x36), \ 209 CHECK_READ(0x37), \ 210 CHECK_READ(0x38), \ 211 CHECK_READ(0x39)); 212 213#else /* CHECK_POINTS */ 214 215#define CHECK_INIT(D) 216#define CHECK_PRINT(S) 217 218#endif /* CHECK_POINTS */ 219 220/* 221 * Values to send to the POST hardware. 222 */ 223#define MP_BOOTADDRESS_POST 0x10 224#define MP_PROBE_POST 0x11 225#define MPTABLE_PASS1_POST 0x12 226 227#define MP_START_POST 0x13 228#define MP_ENABLE_POST 0x14 229#define MPTABLE_PASS2_POST 0x15 230 231#define START_ALL_APS_POST 0x16 232#define INSTALL_AP_TRAMP_POST 0x17 233#define START_AP_POST 0x18 234 235#define MP_ANNOUNCE_POST 0x19 236 237/* used to hold the AP's until we are ready to release them */ 238static struct mtx ap_boot_mtx; 239 240/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ 241int current_postcode; 242 243/** XXX FIXME: what system files declare these??? */ 244extern struct region_descriptor r_gdt, r_idt; 245 246int bsp_apic_ready = 0; /* flags useability of BSP apic */ 247int mp_naps; /* # of Applications processors */ 248int mp_nbusses; /* # of busses */ 249int mp_napics; /* # of IO APICs */ 250int boot_cpu_id; /* designated BSP */ 251vm_offset_t cpu_apic_address; 252vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */ 253extern int nkpt; 254 255u_int32_t cpu_apic_versions[MAXCPU]; 256u_int32_t *io_apic_versions; 257 258#ifdef APIC_INTR_REORDER 259struct { 260 volatile int *location; 261 int bit; 262} apic_isrbit_location[32]; 263#endif 264 265struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE]; 266 267/* 268 * APIC ID logical/physical mapping structures. 269 * We oversize these to simplify boot-time config. 270 */ 271int cpu_num_to_apic_id[NAPICID]; 272int io_num_to_apic_id[NAPICID]; 273int apic_id_to_logical[NAPICID]; 274 275 276/* AP uses this during bootstrap. Do not staticize. */ 277char *bootSTK; 278static int bootAP; 279 280/* Hotwire a 0->4MB V==P mapping */ 281extern pt_entry_t *KPTphys; 282 283/* SMP page table page */ 284extern pt_entry_t *SMPpt; 285 286struct pcb stoppcbs[MAXCPU]; 287 288int invltlb_ok = 0; /* throttle smp_invltlb() till safe */ 289SYSCTL_INT(_machdep, OID_AUTO, invltlb_ok, CTLFLAG_RW, &invltlb_ok, 0, ""); 290 291/* 292 * Local data and functions. 293 */ 294 295/* Set to 1 once we're ready to let the APs out of the pen. */ 296static volatile int aps_ready = 0; 297 298static int mp_capable; 299static u_int boot_address; 300static u_int base_memory; 301 302static int picmode; /* 0: virtual wire mode, 1: PIC mode */ 303static mpfps_t mpfps; 304static int search_for_sig(u_int32_t target, int count); 305static void mp_enable(u_int boot_addr); 306 307static void mptable_pass1(void); 308static int mptable_pass2(void); 309static void default_mp_table(int type); 310static void fix_mp_table(void); 311static void setup_apic_irq_mapping(void); 312static void init_locks(void); 313static int start_all_aps(u_int boot_addr); 314static void install_ap_tramp(u_int boot_addr); 315static int start_ap(int logicalCpu, u_int boot_addr); 316void ap_init(void); 317static int apic_int_is_bus_type(int intr, int bus_type); 318static void release_aps(void *dummy); 319 320/* 321 * initialize all the SMP locks 322 */ 323 324/* critical region around IO APIC, apic_imen */ 325struct mtx imen_mtx; 326 327/* lock region used by kernel profiling */ 328int mcount_lock; 329 330#ifdef USE_COMLOCK 331/* locks com (tty) data/hardware accesses: a FASTINTR() */ 332struct mtx com_mtx; 333#endif /* USE_COMLOCK */ 334 335static void 336init_locks(void) 337{ 338 339#ifdef USE_COMLOCK 340 mtx_init(&com_mtx, "com", MTX_SPIN); 341#endif /* USE_COMLOCK */ 342} 343 344/* 345 * Calculate usable address in base memory for AP trampoline code. 346 */ 347u_int 348mp_bootaddress(u_int basemem) 349{ 350 POSTCODE(MP_BOOTADDRESS_POST); 351 352 base_memory = basemem * 1024; /* convert to bytes */ 353 354 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ 355 if ((base_memory - boot_address) < bootMP_size) 356 boot_address -= 4096; /* not enough, lower by 4k */ 357 358 return boot_address; 359} 360 361 362/* 363 * Look for an Intel MP spec table (ie, SMP capable hardware). 364 */ 365void 366i386_mp_probe(void) 367{ 368 int x; 369 u_long segment; 370 u_int32_t target; 371 372 POSTCODE(MP_PROBE_POST); 373 374 /* see if EBDA exists */ 375 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) { 376 /* search first 1K of EBDA */ 377 target = (u_int32_t) (segment << 4); 378 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 379 goto found; 380 } else { 381 /* last 1K of base memory, effective 'top of base' passed in */ 382 target = (u_int32_t) (base_memory - 0x400); 383 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 384 goto found; 385 } 386 387 /* search the BIOS */ 388 target = (u_int32_t) BIOS_BASE; 389 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) 390 goto found; 391 392 /* nothing found */ 393 mpfps = (mpfps_t)0; 394 mp_capable = 0; 395 return; 396 397found: 398 /* calculate needed resources */ 399 mpfps = (mpfps_t)x; 400 mptable_pass1(); 401 402 /* flag fact that we are running multiple processors */ 403 mp_capable = 1; 404} 405 406int 407cpu_mp_probe(void) 408{ 409 return (mp_capable); 410} 411 412/* 413 * Initialize the SMP hardware and the APIC and start up the AP's. 414 */ 415void 416cpu_mp_start(void) 417{ 418 POSTCODE(MP_START_POST); 419 420 /* look for MP capable motherboard */ 421 if (mp_capable) 422 mp_enable(boot_address); 423 else 424 panic("MP hardware not found!"); 425 426 cpu_setregs(); 427} 428 429 430/* 431 * Print various information about the SMP system hardware and setup. 432 */ 433void 434cpu_mp_announce(void) 435{ 436 int x; 437 438 POSTCODE(MP_ANNOUNCE_POST); 439 440 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0)); 441 printf(", version: 0x%08x", cpu_apic_versions[0]); 442 printf(", at 0x%08x\n", cpu_apic_address); 443 for (x = 1; x <= mp_naps; ++x) { 444 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x)); 445 printf(", version: 0x%08x", cpu_apic_versions[x]); 446 printf(", at 0x%08x\n", cpu_apic_address); 447 } 448 449#if defined(APIC_IO) 450 for (x = 0; x < mp_napics; ++x) { 451 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x)); 452 printf(", version: 0x%08x", io_apic_versions[x]); 453 printf(", at 0x%08x\n", io_apic_address[x]); 454 } 455#else 456 printf(" Warning: APIC I/O disabled\n"); 457#endif /* APIC_IO */ 458} 459 460/* 461 * AP cpu's call this to sync up protected mode. 462 */ 463void 464init_secondary(void) 465{ 466 int gsel_tss; 467 int x, myid = bootAP; 468 469 gdt_segs[GPRIV_SEL].ssd_base = (int) &SMP_prvspace[myid]; 470 gdt_segs[GPROC0_SEL].ssd_base = 471 (int) &SMP_prvspace[myid].globaldata.gd_common_tss; 472 SMP_prvspace[myid].globaldata.gd_prvspace = 473 &SMP_prvspace[myid].globaldata; 474 475 for (x = 0; x < NGDT; x++) { 476 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd); 477 } 478 479 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 480 r_gdt.rd_base = (int) &gdt[myid * NGDT]; 481 lgdt(&r_gdt); /* does magic intra-segment return */ 482 483 lidt(&r_idt); 484 485 lldt(_default_ldt); 486 PCPU_SET(currentldt, _default_ldt); 487 488 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 489 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS; 490 PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */ 491 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL)); 492 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16); 493 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd); 494 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt)); 495 ltr(gsel_tss); 496 497 pmap_set_opt(); 498} 499 500 501#if defined(APIC_IO) 502/* 503 * Final configuration of the BSP's local APIC: 504 * - disable 'pic mode'. 505 * - disable 'virtual wire mode'. 506 * - enable NMI. 507 */ 508void 509bsp_apic_configure(void) 510{ 511 u_char byte; 512 u_int32_t temp; 513 514 /* leave 'pic mode' if necessary */ 515 if (picmode) { 516 outb(0x22, 0x70); /* select IMCR */ 517 byte = inb(0x23); /* current contents */ 518 byte |= 0x01; /* mask external INTR */ 519 outb(0x23, byte); /* disconnect 8259s/NMI */ 520 } 521 522 /* mask lint0 (the 8259 'virtual wire' connection) */ 523 temp = lapic.lvt_lint0; 524 temp |= APIC_LVT_M; /* set the mask */ 525 lapic.lvt_lint0 = temp; 526 527 /* setup lint1 to handle NMI */ 528 temp = lapic.lvt_lint1; 529 temp &= ~APIC_LVT_M; /* clear the mask */ 530 lapic.lvt_lint1 = temp; 531 532 if (bootverbose) 533 apic_dump("bsp_apic_configure()"); 534} 535#endif /* APIC_IO */ 536 537 538/******************************************************************* 539 * local functions and data 540 */ 541 542/* 543 * start the SMP system 544 */ 545static void 546mp_enable(u_int boot_addr) 547{ 548 int x; 549#if defined(APIC_IO) 550 int apic; 551 u_int ux; 552#endif /* APIC_IO */ 553 554 POSTCODE(MP_ENABLE_POST); 555 556 /* turn on 4MB of V == P addressing so we can get to MP table */ 557 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME); 558 invltlb(); 559 560 /* examine the MP table for needed info, uses physical addresses */ 561 x = mptable_pass2(); 562 563 *(int *)PTD = 0; 564 invltlb(); 565 566 /* can't process default configs till the CPU APIC is pmapped */ 567 if (x) 568 default_mp_table(x); 569 570 /* post scan cleanup */ 571 fix_mp_table(); 572 setup_apic_irq_mapping(); 573 574#if defined(APIC_IO) 575 576 /* fill the LOGICAL io_apic_versions table */ 577 for (apic = 0; apic < mp_napics; ++apic) { 578 ux = io_apic_read(apic, IOAPIC_VER); 579 io_apic_versions[apic] = ux; 580 io_apic_set_id(apic, IO_TO_ID(apic)); 581 } 582 583 /* program each IO APIC in the system */ 584 for (apic = 0; apic < mp_napics; ++apic) 585 if (io_apic_setup(apic) < 0) 586 panic("IO APIC setup failure"); 587 588 /* install a 'Spurious INTerrupt' vector */ 589 setidt(XSPURIOUSINT_OFFSET, Xspuriousint, 590 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 591 592 /* install an inter-CPU IPI for TLB invalidation */ 593 setidt(XINVLTLB_OFFSET, Xinvltlb, 594 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 595 596 /* install an inter-CPU IPI for forwarding hardclock() */ 597 setidt(XHARDCLOCK_OFFSET, Xhardclock, 598 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 599 600 /* install an inter-CPU IPI for forwarding statclock() */ 601 setidt(XSTATCLOCK_OFFSET, Xstatclock, 602 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 603 604 /* install an inter-CPU IPI for all-CPU rendezvous */ 605 setidt(XRENDEZVOUS_OFFSET, Xrendezvous, 606 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 607 608 /* install an inter-CPU IPI for forcing an additional software trap */ 609 setidt(XCPUAST_OFFSET, Xcpuast, 610 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 611 612 /* install an inter-CPU IPI for CPU stop/restart */ 613 setidt(XCPUSTOP_OFFSET, Xcpustop, 614 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 615 616#if defined(TEST_TEST1) 617 /* install a "fake hardware INTerrupt" vector */ 618 setidt(XTEST1_OFFSET, Xtest1, 619 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 620#endif /** TEST_TEST1 */ 621 622#endif /* APIC_IO */ 623 624 /* initialize all SMP locks */ 625 init_locks(); 626 627 /* start each Application Processor */ 628 start_all_aps(boot_addr); 629} 630 631 632/* 633 * look for the MP spec signature 634 */ 635 636/* string defined by the Intel MP Spec as identifying the MP table */ 637#define MP_SIG 0x5f504d5f /* _MP_ */ 638#define NEXT(X) ((X) += 4) 639static int 640search_for_sig(u_int32_t target, int count) 641{ 642 int x; 643 u_int32_t *addr = (u_int32_t *) (KERNBASE + target); 644 645 for (x = 0; x < count; NEXT(x)) 646 if (addr[x] == MP_SIG) 647 /* make array index a byte index */ 648 return (target + (x * sizeof(u_int32_t))); 649 650 return -1; 651} 652 653 654static basetable_entry basetable_entry_types[] = 655{ 656 {0, 20, "Processor"}, 657 {1, 8, "Bus"}, 658 {2, 8, "I/O APIC"}, 659 {3, 8, "I/O INT"}, 660 {4, 8, "Local INT"} 661}; 662 663typedef struct BUSDATA { 664 u_char bus_id; 665 enum busTypes bus_type; 666} bus_datum; 667 668typedef struct INTDATA { 669 u_char int_type; 670 u_short int_flags; 671 u_char src_bus_id; 672 u_char src_bus_irq; 673 u_char dst_apic_id; 674 u_char dst_apic_int; 675 u_char int_vector; 676} io_int, local_int; 677 678typedef struct BUSTYPENAME { 679 u_char type; 680 char name[7]; 681} bus_type_name; 682 683static bus_type_name bus_type_table[] = 684{ 685 {CBUS, "CBUS"}, 686 {CBUSII, "CBUSII"}, 687 {EISA, "EISA"}, 688 {MCA, "MCA"}, 689 {UNKNOWN_BUSTYPE, "---"}, 690 {ISA, "ISA"}, 691 {MCA, "MCA"}, 692 {UNKNOWN_BUSTYPE, "---"}, 693 {UNKNOWN_BUSTYPE, "---"}, 694 {UNKNOWN_BUSTYPE, "---"}, 695 {UNKNOWN_BUSTYPE, "---"}, 696 {UNKNOWN_BUSTYPE, "---"}, 697 {PCI, "PCI"}, 698 {UNKNOWN_BUSTYPE, "---"}, 699 {UNKNOWN_BUSTYPE, "---"}, 700 {UNKNOWN_BUSTYPE, "---"}, 701 {UNKNOWN_BUSTYPE, "---"}, 702 {XPRESS, "XPRESS"}, 703 {UNKNOWN_BUSTYPE, "---"} 704}; 705/* from MP spec v1.4, table 5-1 */ 706static int default_data[7][5] = 707{ 708/* nbus, id0, type0, id1, type1 */ 709 {1, 0, ISA, 255, 255}, 710 {1, 0, EISA, 255, 255}, 711 {1, 0, EISA, 255, 255}, 712 {1, 0, MCA, 255, 255}, 713 {2, 0, ISA, 1, PCI}, 714 {2, 0, EISA, 1, PCI}, 715 {2, 0, MCA, 1, PCI} 716}; 717 718 719/* the bus data */ 720static bus_datum *bus_data; 721 722/* the IO INT data, one entry per possible APIC INTerrupt */ 723static io_int *io_apic_ints; 724 725static int nintrs; 726 727static int processor_entry __P((proc_entry_ptr entry, int cpu)); 728static int bus_entry __P((bus_entry_ptr entry, int bus)); 729static int io_apic_entry __P((io_apic_entry_ptr entry, int apic)); 730static int int_entry __P((int_entry_ptr entry, int intr)); 731static int lookup_bus_type __P((char *name)); 732 733 734/* 735 * 1st pass on motherboard's Intel MP specification table. 736 * 737 * initializes: 738 * mp_ncpus = 1 739 * 740 * determines: 741 * cpu_apic_address (common to all CPUs) 742 * io_apic_address[N] 743 * mp_naps 744 * mp_nbusses 745 * mp_napics 746 * nintrs 747 */ 748static void 749mptable_pass1(void) 750{ 751 int x; 752 mpcth_t cth; 753 int totalSize; 754 void* position; 755 int count; 756 int type; 757 758 POSTCODE(MPTABLE_PASS1_POST); 759 760 /* clear various tables */ 761 for (x = 0; x < NAPICID; ++x) { 762 io_apic_address[x] = ~0; /* IO APIC address table */ 763 } 764 765 /* init everything to empty */ 766 mp_naps = 0; 767 mp_nbusses = 0; 768 mp_napics = 0; 769 nintrs = 0; 770 771 /* check for use of 'default' configuration */ 772 if (MPFPS_MPFB1 != 0) { 773 /* use default addresses */ 774 cpu_apic_address = DEFAULT_APIC_BASE; 775 io_apic_address[0] = DEFAULT_IO_APIC_BASE; 776 777 /* fill in with defaults */ 778 mp_naps = 2; /* includes BSP */ 779 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0]; 780#if defined(APIC_IO) 781 mp_napics = 1; 782 nintrs = 16; 783#endif /* APIC_IO */ 784 } 785 else { 786 if ((cth = mpfps->pap) == 0) 787 panic("MP Configuration Table Header MISSING!"); 788 789 cpu_apic_address = (vm_offset_t) cth->apic_address; 790 791 /* walk the table, recording info of interest */ 792 totalSize = cth->base_table_length - sizeof(struct MPCTH); 793 position = (u_char *) cth + sizeof(struct MPCTH); 794 count = cth->entry_count; 795 796 while (count--) { 797 switch (type = *(u_char *) position) { 798 case 0: /* processor_entry */ 799 if (((proc_entry_ptr)position)->cpu_flags 800 & PROCENTRY_FLAG_EN) 801 ++mp_naps; 802 break; 803 case 1: /* bus_entry */ 804 ++mp_nbusses; 805 break; 806 case 2: /* io_apic_entry */ 807 if (((io_apic_entry_ptr)position)->apic_flags 808 & IOAPICENTRY_FLAG_EN) 809 io_apic_address[mp_napics++] = 810 (vm_offset_t)((io_apic_entry_ptr) 811 position)->apic_address; 812 break; 813 case 3: /* int_entry */ 814 ++nintrs; 815 break; 816 case 4: /* int_entry */ 817 break; 818 default: 819 panic("mpfps Base Table HOSED!"); 820 /* NOTREACHED */ 821 } 822 823 totalSize -= basetable_entry_types[type].length; 824 (u_char*)position += basetable_entry_types[type].length; 825 } 826 } 827 828 /* qualify the numbers */ 829 if (mp_naps > MAXCPU) { 830 printf("Warning: only using %d of %d available CPUs!\n", 831 MAXCPU, mp_naps); 832 mp_naps = MAXCPU; 833 } 834 835 /* 836 * Count the BSP. 837 * This is also used as a counter while starting the APs. 838 */ 839 mp_ncpus = 1; 840 841 --mp_naps; /* subtract the BSP */ 842} 843 844 845/* 846 * 2nd pass on motherboard's Intel MP specification table. 847 * 848 * sets: 849 * boot_cpu_id 850 * ID_TO_IO(N), phy APIC ID to log CPU/IO table 851 * CPU_TO_ID(N), logical CPU to APIC ID table 852 * IO_TO_ID(N), logical IO to APIC ID table 853 * bus_data[N] 854 * io_apic_ints[N] 855 */ 856static int 857mptable_pass2(void) 858{ 859 int x; 860 mpcth_t cth; 861 int totalSize; 862 void* position; 863 int count; 864 int type; 865 int apic, bus, cpu, intr; 866 int i, j; 867 int pgeflag; 868 869 POSTCODE(MPTABLE_PASS2_POST); 870 871 pgeflag = 0; /* XXX - Not used under SMP yet. */ 872 873 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics, 874 M_DEVBUF, M_WAITOK); 875 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics, 876 M_DEVBUF, M_WAITOK); 877 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + 1), 878 M_DEVBUF, M_WAITOK); 879 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses, 880 M_DEVBUF, M_WAITOK); 881 882 bzero(ioapic, sizeof(ioapic_t *) * mp_napics); 883 884 for (i = 0; i < mp_napics; i++) { 885 for (j = 0; j < mp_napics; j++) { 886 /* same page frame as a previous IO apic? */ 887 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) == 888 (io_apic_address[i] & PG_FRAME)) { 889 ioapic[i] = (ioapic_t *)((u_int)SMP_prvspace 890 + (NPTEPG-2-j) * PAGE_SIZE 891 + (io_apic_address[i] & PAGE_MASK)); 892 break; 893 } 894 /* use this slot if available */ 895 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) == 0) { 896 SMPpt[NPTEPG-2-j] = (pt_entry_t)(PG_V | PG_RW | 897 pgeflag | (io_apic_address[i] & PG_FRAME)); 898 ioapic[i] = (ioapic_t *)((u_int)SMP_prvspace 899 + (NPTEPG-2-j) * PAGE_SIZE 900 + (io_apic_address[i] & PAGE_MASK)); 901 break; 902 } 903 } 904 } 905 906 /* clear various tables */ 907 for (x = 0; x < NAPICID; ++x) { 908 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */ 909 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */ 910 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */ 911 } 912 913 /* clear bus data table */ 914 for (x = 0; x < mp_nbusses; ++x) 915 bus_data[x].bus_id = 0xff; 916 917 /* clear IO APIC INT table */ 918 for (x = 0; x < (nintrs + 1); ++x) { 919 io_apic_ints[x].int_type = 0xff; 920 io_apic_ints[x].int_vector = 0xff; 921 } 922 923 /* setup the cpu/apic mapping arrays */ 924 boot_cpu_id = -1; 925 926 /* record whether PIC or virtual-wire mode */ 927 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0; 928 929 /* check for use of 'default' configuration */ 930 if (MPFPS_MPFB1 != 0) 931 return MPFPS_MPFB1; /* return default configuration type */ 932 933 if ((cth = mpfps->pap) == 0) 934 panic("MP Configuration Table Header MISSING!"); 935 936 /* walk the table, recording info of interest */ 937 totalSize = cth->base_table_length - sizeof(struct MPCTH); 938 position = (u_char *) cth + sizeof(struct MPCTH); 939 count = cth->entry_count; 940 apic = bus = intr = 0; 941 cpu = 1; /* pre-count the BSP */ 942 943 while (count--) { 944 switch (type = *(u_char *) position) { 945 case 0: 946 if (processor_entry(position, cpu)) 947 ++cpu; 948 break; 949 case 1: 950 if (bus_entry(position, bus)) 951 ++bus; 952 break; 953 case 2: 954 if (io_apic_entry(position, apic)) 955 ++apic; 956 break; 957 case 3: 958 if (int_entry(position, intr)) 959 ++intr; 960 break; 961 case 4: 962 /* int_entry(position); */ 963 break; 964 default: 965 panic("mpfps Base Table HOSED!"); 966 /* NOTREACHED */ 967 } 968 969 totalSize -= basetable_entry_types[type].length; 970 (u_char *) position += basetable_entry_types[type].length; 971 } 972 973 if (boot_cpu_id == -1) 974 panic("NO BSP found!"); 975 976 /* report fact that its NOT a default configuration */ 977 return 0; 978} 979 980 981void 982assign_apic_irq(int apic, int intpin, int irq) 983{ 984 int x; 985 986 if (int_to_apicintpin[irq].ioapic != -1) 987 panic("assign_apic_irq: inconsistent table"); 988 989 int_to_apicintpin[irq].ioapic = apic; 990 int_to_apicintpin[irq].int_pin = intpin; 991 int_to_apicintpin[irq].apic_address = ioapic[apic]; 992 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin; 993 994 for (x = 0; x < nintrs; x++) { 995 if ((io_apic_ints[x].int_type == 0 || 996 io_apic_ints[x].int_type == 3) && 997 io_apic_ints[x].int_vector == 0xff && 998 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) && 999 io_apic_ints[x].dst_apic_int == intpin) 1000 io_apic_ints[x].int_vector = irq; 1001 } 1002} 1003 1004void 1005revoke_apic_irq(int irq) 1006{ 1007 int x; 1008 int oldapic; 1009 int oldintpin; 1010 1011 if (int_to_apicintpin[irq].ioapic == -1) 1012 panic("assign_apic_irq: inconsistent table"); 1013 1014 oldapic = int_to_apicintpin[irq].ioapic; 1015 oldintpin = int_to_apicintpin[irq].int_pin; 1016 1017 int_to_apicintpin[irq].ioapic = -1; 1018 int_to_apicintpin[irq].int_pin = 0; 1019 int_to_apicintpin[irq].apic_address = NULL; 1020 int_to_apicintpin[irq].redirindex = 0; 1021 1022 for (x = 0; x < nintrs; x++) { 1023 if ((io_apic_ints[x].int_type == 0 || 1024 io_apic_ints[x].int_type == 3) && 1025 io_apic_ints[x].int_vector == 0xff && 1026 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) && 1027 io_apic_ints[x].dst_apic_int == oldintpin) 1028 io_apic_ints[x].int_vector = 0xff; 1029 } 1030} 1031 1032 1033static void 1034allocate_apic_irq(int intr) 1035{ 1036 int apic; 1037 int intpin; 1038 int irq; 1039 1040 if (io_apic_ints[intr].int_vector != 0xff) 1041 return; /* Interrupt handler already assigned */ 1042 1043 if (io_apic_ints[intr].int_type != 0 && 1044 (io_apic_ints[intr].int_type != 3 || 1045 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) && 1046 io_apic_ints[intr].dst_apic_int == 0))) 1047 return; /* Not INT or ExtInt on != (0, 0) */ 1048 1049 irq = 0; 1050 while (irq < APIC_INTMAPSIZE && 1051 int_to_apicintpin[irq].ioapic != -1) 1052 irq++; 1053 1054 if (irq >= APIC_INTMAPSIZE) 1055 return; /* No free interrupt handlers */ 1056 1057 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id); 1058 intpin = io_apic_ints[intr].dst_apic_int; 1059 1060 assign_apic_irq(apic, intpin, irq); 1061 io_apic_setup_intpin(apic, intpin); 1062} 1063 1064 1065static void 1066swap_apic_id(int apic, int oldid, int newid) 1067{ 1068 int x; 1069 int oapic; 1070 1071 1072 if (oldid == newid) 1073 return; /* Nothing to do */ 1074 1075 printf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n", 1076 apic, oldid, newid); 1077 1078 /* Swap physical APIC IDs in interrupt entries */ 1079 for (x = 0; x < nintrs; x++) { 1080 if (io_apic_ints[x].dst_apic_id == oldid) 1081 io_apic_ints[x].dst_apic_id = newid; 1082 else if (io_apic_ints[x].dst_apic_id == newid) 1083 io_apic_ints[x].dst_apic_id = oldid; 1084 } 1085 1086 /* Swap physical APIC IDs in IO_TO_ID mappings */ 1087 for (oapic = 0; oapic < mp_napics; oapic++) 1088 if (IO_TO_ID(oapic) == newid) 1089 break; 1090 1091 if (oapic < mp_napics) { 1092 printf("Changing APIC ID for IO APIC #%d from " 1093 "%d to %d in MP table\n", 1094 oapic, newid, oldid); 1095 IO_TO_ID(oapic) = oldid; 1096 } 1097 IO_TO_ID(apic) = newid; 1098} 1099 1100 1101static void 1102fix_id_to_io_mapping(void) 1103{ 1104 int x; 1105 1106 for (x = 0; x < NAPICID; x++) 1107 ID_TO_IO(x) = -1; 1108 1109 for (x = 0; x <= mp_naps; x++) 1110 if (CPU_TO_ID(x) < NAPICID) 1111 ID_TO_IO(CPU_TO_ID(x)) = x; 1112 1113 for (x = 0; x < mp_napics; x++) 1114 if (IO_TO_ID(x) < NAPICID) 1115 ID_TO_IO(IO_TO_ID(x)) = x; 1116} 1117 1118 1119static int 1120first_free_apic_id(void) 1121{ 1122 int freeid, x; 1123 1124 for (freeid = 0; freeid < NAPICID; freeid++) { 1125 for (x = 0; x <= mp_naps; x++) 1126 if (CPU_TO_ID(x) == freeid) 1127 break; 1128 if (x <= mp_naps) 1129 continue; 1130 for (x = 0; x < mp_napics; x++) 1131 if (IO_TO_ID(x) == freeid) 1132 break; 1133 if (x < mp_napics) 1134 continue; 1135 return freeid; 1136 } 1137 return freeid; 1138} 1139 1140 1141static int 1142io_apic_id_acceptable(int apic, int id) 1143{ 1144 int cpu; /* Logical CPU number */ 1145 int oapic; /* Logical IO APIC number for other IO APIC */ 1146 1147 if (id >= NAPICID) 1148 return 0; /* Out of range */ 1149 1150 for (cpu = 0; cpu <= mp_naps; cpu++) 1151 if (CPU_TO_ID(cpu) == id) 1152 return 0; /* Conflict with CPU */ 1153 1154 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++) 1155 if (IO_TO_ID(oapic) == id) 1156 return 0; /* Conflict with other APIC */ 1157 1158 return 1; /* ID is acceptable for IO APIC */ 1159} 1160 1161 1162/* 1163 * parse an Intel MP specification table 1164 */ 1165static void 1166fix_mp_table(void) 1167{ 1168 int x; 1169 int id; 1170 int bus_0 = 0; /* Stop GCC warning */ 1171 int bus_pci = 0; /* Stop GCC warning */ 1172 int num_pci_bus; 1173 int apic; /* IO APIC unit number */ 1174 int freeid; /* Free physical APIC ID */ 1175 int physid; /* Current physical IO APIC ID */ 1176 1177 /* 1178 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS 1179 * did it wrong. The MP spec says that when more than 1 PCI bus 1180 * exists the BIOS must begin with bus entries for the PCI bus and use 1181 * actual PCI bus numbering. This implies that when only 1 PCI bus 1182 * exists the BIOS can choose to ignore this ordering, and indeed many 1183 * MP motherboards do ignore it. This causes a problem when the PCI 1184 * sub-system makes requests of the MP sub-system based on PCI bus 1185 * numbers. So here we look for the situation and renumber the 1186 * busses and associated INTs in an effort to "make it right". 1187 */ 1188 1189 /* find bus 0, PCI bus, count the number of PCI busses */ 1190 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { 1191 if (bus_data[x].bus_id == 0) { 1192 bus_0 = x; 1193 } 1194 if (bus_data[x].bus_type == PCI) { 1195 ++num_pci_bus; 1196 bus_pci = x; 1197 } 1198 } 1199 /* 1200 * bus_0 == slot of bus with ID of 0 1201 * bus_pci == slot of last PCI bus encountered 1202 */ 1203 1204 /* check the 1 PCI bus case for sanity */ 1205 /* if it is number 0 all is well */ 1206 if (num_pci_bus == 1 && 1207 bus_data[bus_pci].bus_id != 0) { 1208 1209 /* mis-numbered, swap with whichever bus uses slot 0 */ 1210 1211 /* swap the bus entry types */ 1212 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type; 1213 bus_data[bus_0].bus_type = PCI; 1214 1215 /* swap each relavant INTerrupt entry */ 1216 id = bus_data[bus_pci].bus_id; 1217 for (x = 0; x < nintrs; ++x) { 1218 if (io_apic_ints[x].src_bus_id == id) { 1219 io_apic_ints[x].src_bus_id = 0; 1220 } 1221 else if (io_apic_ints[x].src_bus_id == 0) { 1222 io_apic_ints[x].src_bus_id = id; 1223 } 1224 } 1225 } 1226 1227 /* Assign IO APIC IDs. 1228 * 1229 * First try the existing ID. If a conflict is detected, try 1230 * the ID in the MP table. If a conflict is still detected, find 1231 * a free id. 1232 * 1233 * We cannot use the ID_TO_IO table before all conflicts has been 1234 * resolved and the table has been corrected. 1235 */ 1236 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */ 1237 1238 /* First try to use the value set by the BIOS */ 1239 physid = io_apic_get_id(apic); 1240 if (io_apic_id_acceptable(apic, physid)) { 1241 if (IO_TO_ID(apic) != physid) 1242 swap_apic_id(apic, IO_TO_ID(apic), physid); 1243 continue; 1244 } 1245 1246 /* Then check if the value in the MP table is acceptable */ 1247 if (io_apic_id_acceptable(apic, IO_TO_ID(apic))) 1248 continue; 1249 1250 /* Last resort, find a free APIC ID and use it */ 1251 freeid = first_free_apic_id(); 1252 if (freeid >= NAPICID) 1253 panic("No free physical APIC IDs found"); 1254 1255 if (io_apic_id_acceptable(apic, freeid)) { 1256 swap_apic_id(apic, IO_TO_ID(apic), freeid); 1257 continue; 1258 } 1259 panic("Free physical APIC ID not usable"); 1260 } 1261 fix_id_to_io_mapping(); 1262 1263 /* detect and fix broken Compaq MP table */ 1264 if (apic_int_type(0, 0) == -1) { 1265 printf("APIC_IO: MP table broken: 8259->APIC entry missing!\n"); 1266 io_apic_ints[nintrs].int_type = 3; /* ExtInt */ 1267 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */ 1268 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */ 1269 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0); 1270 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */ 1271 nintrs++; 1272 } 1273} 1274 1275 1276/* Assign low level interrupt handlers */ 1277static void 1278setup_apic_irq_mapping(void) 1279{ 1280 int x; 1281 int int_vector; 1282 1283 /* Clear array */ 1284 for (x = 0; x < APIC_INTMAPSIZE; x++) { 1285 int_to_apicintpin[x].ioapic = -1; 1286 int_to_apicintpin[x].int_pin = 0; 1287 int_to_apicintpin[x].apic_address = NULL; 1288 int_to_apicintpin[x].redirindex = 0; 1289 } 1290 1291 /* First assign ISA/EISA interrupts */ 1292 for (x = 0; x < nintrs; x++) { 1293 int_vector = io_apic_ints[x].src_bus_irq; 1294 if (int_vector < APIC_INTMAPSIZE && 1295 io_apic_ints[x].int_vector == 0xff && 1296 int_to_apicintpin[int_vector].ioapic == -1 && 1297 (apic_int_is_bus_type(x, ISA) || 1298 apic_int_is_bus_type(x, EISA)) && 1299 io_apic_ints[x].int_type == 0) { 1300 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id), 1301 io_apic_ints[x].dst_apic_int, 1302 int_vector); 1303 } 1304 } 1305 1306 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */ 1307 for (x = 0; x < nintrs; x++) { 1308 if (io_apic_ints[x].dst_apic_int == 0 && 1309 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) && 1310 io_apic_ints[x].int_vector == 0xff && 1311 int_to_apicintpin[0].ioapic == -1 && 1312 io_apic_ints[x].int_type == 3) { 1313 assign_apic_irq(0, 0, 0); 1314 break; 1315 } 1316 } 1317 /* PCI interrupt assignment is deferred */ 1318} 1319 1320 1321static int 1322processor_entry(proc_entry_ptr entry, int cpu) 1323{ 1324 /* check for usability */ 1325 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN)) 1326 return 0; 1327 1328 if(entry->apic_id >= NAPICID) 1329 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1); 1330 /* check for BSP flag */ 1331 if (entry->cpu_flags & PROCENTRY_FLAG_BP) { 1332 boot_cpu_id = entry->apic_id; 1333 CPU_TO_ID(0) = entry->apic_id; 1334 ID_TO_CPU(entry->apic_id) = 0; 1335 return 0; /* its already been counted */ 1336 } 1337 1338 /* add another AP to list, if less than max number of CPUs */ 1339 else if (cpu < MAXCPU) { 1340 CPU_TO_ID(cpu) = entry->apic_id; 1341 ID_TO_CPU(entry->apic_id) = cpu; 1342 return 1; 1343 } 1344 1345 return 0; 1346} 1347 1348 1349static int 1350bus_entry(bus_entry_ptr entry, int bus) 1351{ 1352 int x; 1353 char c, name[8]; 1354 1355 /* encode the name into an index */ 1356 for (x = 0; x < 6; ++x) { 1357 if ((c = entry->bus_type[x]) == ' ') 1358 break; 1359 name[x] = c; 1360 } 1361 name[x] = '\0'; 1362 1363 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) 1364 panic("unknown bus type: '%s'", name); 1365 1366 bus_data[bus].bus_id = entry->bus_id; 1367 bus_data[bus].bus_type = x; 1368 1369 return 1; 1370} 1371 1372 1373static int 1374io_apic_entry(io_apic_entry_ptr entry, int apic) 1375{ 1376 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) 1377 return 0; 1378 1379 IO_TO_ID(apic) = entry->apic_id; 1380 if (entry->apic_id < NAPICID) 1381 ID_TO_IO(entry->apic_id) = apic; 1382 1383 return 1; 1384} 1385 1386 1387static int 1388lookup_bus_type(char *name) 1389{ 1390 int x; 1391 1392 for (x = 0; x < MAX_BUSTYPE; ++x) 1393 if (strcmp(bus_type_table[x].name, name) == 0) 1394 return bus_type_table[x].type; 1395 1396 return UNKNOWN_BUSTYPE; 1397} 1398 1399 1400static int 1401int_entry(int_entry_ptr entry, int intr) 1402{ 1403 int apic; 1404 1405 io_apic_ints[intr].int_type = entry->int_type; 1406 io_apic_ints[intr].int_flags = entry->int_flags; 1407 io_apic_ints[intr].src_bus_id = entry->src_bus_id; 1408 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq; 1409 if (entry->dst_apic_id == 255) { 1410 /* This signal goes to all IO APICS. Select an IO APIC 1411 with sufficient number of interrupt pins */ 1412 for (apic = 0; apic < mp_napics; apic++) 1413 if (((io_apic_read(apic, IOAPIC_VER) & 1414 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >= 1415 entry->dst_apic_int) 1416 break; 1417 if (apic < mp_napics) 1418 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic); 1419 else 1420 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; 1421 } else 1422 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; 1423 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int; 1424 1425 return 1; 1426} 1427 1428 1429static int 1430apic_int_is_bus_type(int intr, int bus_type) 1431{ 1432 int bus; 1433 1434 for (bus = 0; bus < mp_nbusses; ++bus) 1435 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) 1436 && ((int) bus_data[bus].bus_type == bus_type)) 1437 return 1; 1438 1439 return 0; 1440} 1441 1442 1443/* 1444 * Given a traditional ISA INT mask, return an APIC mask. 1445 */ 1446u_int 1447isa_apic_mask(u_int isa_mask) 1448{ 1449 int isa_irq; 1450 int apic_pin; 1451 1452#if defined(SKIP_IRQ15_REDIRECT) 1453 if (isa_mask == (1 << 15)) { 1454 printf("skipping ISA IRQ15 redirect\n"); 1455 return isa_mask; 1456 } 1457#endif /* SKIP_IRQ15_REDIRECT */ 1458 1459 isa_irq = ffs(isa_mask); /* find its bit position */ 1460 if (isa_irq == 0) /* doesn't exist */ 1461 return 0; 1462 --isa_irq; /* make it zero based */ 1463 1464 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */ 1465 if (apic_pin == -1) 1466 return 0; 1467 1468 return (1 << apic_pin); /* convert pin# to a mask */ 1469} 1470 1471 1472/* 1473 * Determine which APIC pin an ISA/EISA INT is attached to. 1474 */ 1475#define INTTYPE(I) (io_apic_ints[(I)].int_type) 1476#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) 1477#define INTIRQ(I) (io_apic_ints[(I)].int_vector) 1478#define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id)) 1479 1480#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) 1481int 1482isa_apic_irq(int isa_irq) 1483{ 1484 int intr; 1485 1486 for (intr = 0; intr < nintrs; ++intr) { /* check each record */ 1487 if (INTTYPE(intr) == 0) { /* standard INT */ 1488 if (SRCBUSIRQ(intr) == isa_irq) { 1489 if (apic_int_is_bus_type(intr, ISA) || 1490 apic_int_is_bus_type(intr, EISA)) { 1491 if (INTIRQ(intr) == 0xff) 1492 return -1; /* unassigned */ 1493 return INTIRQ(intr); /* found */ 1494 } 1495 } 1496 } 1497 } 1498 return -1; /* NOT found */ 1499} 1500 1501 1502/* 1503 * Determine which APIC pin a PCI INT is attached to. 1504 */ 1505#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) 1506#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) 1507#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) 1508int 1509pci_apic_irq(int pciBus, int pciDevice, int pciInt) 1510{ 1511 int intr; 1512 1513 --pciInt; /* zero based */ 1514 1515 for (intr = 0; intr < nintrs; ++intr) /* check each record */ 1516 if ((INTTYPE(intr) == 0) /* standard INT */ 1517 && (SRCBUSID(intr) == pciBus) 1518 && (SRCBUSDEVICE(intr) == pciDevice) 1519 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ 1520 if (apic_int_is_bus_type(intr, PCI)) { 1521 if (INTIRQ(intr) == 0xff) 1522 allocate_apic_irq(intr); 1523 if (INTIRQ(intr) == 0xff) 1524 return -1; /* unassigned */ 1525 return INTIRQ(intr); /* exact match */ 1526 } 1527 1528 return -1; /* NOT found */ 1529} 1530 1531int 1532next_apic_irq(int irq) 1533{ 1534 int intr, ointr; 1535 int bus, bustype; 1536 1537 bus = 0; 1538 bustype = 0; 1539 for (intr = 0; intr < nintrs; intr++) { 1540 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0) 1541 continue; 1542 bus = SRCBUSID(intr); 1543 bustype = apic_bus_type(bus); 1544 if (bustype != ISA && 1545 bustype != EISA && 1546 bustype != PCI) 1547 continue; 1548 break; 1549 } 1550 if (intr >= nintrs) { 1551 return -1; 1552 } 1553 for (ointr = intr + 1; ointr < nintrs; ointr++) { 1554 if (INTTYPE(ointr) != 0) 1555 continue; 1556 if (bus != SRCBUSID(ointr)) 1557 continue; 1558 if (bustype == PCI) { 1559 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr)) 1560 continue; 1561 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr)) 1562 continue; 1563 } 1564 if (bustype == ISA || bustype == EISA) { 1565 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr)) 1566 continue; 1567 } 1568 if (INTPIN(intr) == INTPIN(ointr)) 1569 continue; 1570 break; 1571 } 1572 if (ointr >= nintrs) { 1573 return -1; 1574 } 1575 return INTIRQ(ointr); 1576} 1577#undef SRCBUSLINE 1578#undef SRCBUSDEVICE 1579#undef SRCBUSID 1580#undef SRCBUSIRQ 1581 1582#undef INTPIN 1583#undef INTIRQ 1584#undef INTAPIC 1585#undef INTTYPE 1586 1587 1588/* 1589 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt. 1590 * 1591 * XXX FIXME: 1592 * Exactly what this means is unclear at this point. It is a solution 1593 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard 1594 * could route any of the ISA INTs to upper (>15) IRQ values. But most would 1595 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an 1596 * option. 1597 */ 1598int 1599undirect_isa_irq(int rirq) 1600{ 1601#if defined(READY) 1602 if (bootverbose) 1603 printf("Freeing redirected ISA irq %d.\n", rirq); 1604 /** FIXME: tickle the MB redirector chip */ 1605 return -1; 1606#else 1607 if (bootverbose) 1608 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq); 1609 return 0; 1610#endif /* READY */ 1611} 1612 1613 1614/* 1615 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt 1616 */ 1617int 1618undirect_pci_irq(int rirq) 1619{ 1620#if defined(READY) 1621 if (bootverbose) 1622 printf("Freeing redirected PCI irq %d.\n", rirq); 1623 1624 /** FIXME: tickle the MB redirector chip */ 1625 return -1; 1626#else 1627 if (bootverbose) 1628 printf("Freeing (NOT implemented) redirected PCI irq %d.\n", 1629 rirq); 1630 return 0; 1631#endif /* READY */ 1632} 1633 1634 1635/* 1636 * given a bus ID, return: 1637 * the bus type if found 1638 * -1 if NOT found 1639 */ 1640int 1641apic_bus_type(int id) 1642{ 1643 int x; 1644 1645 for (x = 0; x < mp_nbusses; ++x) 1646 if (bus_data[x].bus_id == id) 1647 return bus_data[x].bus_type; 1648 1649 return -1; 1650} 1651 1652 1653/* 1654 * given a LOGICAL APIC# and pin#, return: 1655 * the associated src bus ID if found 1656 * -1 if NOT found 1657 */ 1658int 1659apic_src_bus_id(int apic, int pin) 1660{ 1661 int x; 1662 1663 /* search each of the possible INTerrupt sources */ 1664 for (x = 0; x < nintrs; ++x) 1665 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1666 (pin == io_apic_ints[x].dst_apic_int)) 1667 return (io_apic_ints[x].src_bus_id); 1668 1669 return -1; /* NOT found */ 1670} 1671 1672 1673/* 1674 * given a LOGICAL APIC# and pin#, return: 1675 * the associated src bus IRQ if found 1676 * -1 if NOT found 1677 */ 1678int 1679apic_src_bus_irq(int apic, int pin) 1680{ 1681 int x; 1682 1683 for (x = 0; x < nintrs; x++) 1684 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1685 (pin == io_apic_ints[x].dst_apic_int)) 1686 return (io_apic_ints[x].src_bus_irq); 1687 1688 return -1; /* NOT found */ 1689} 1690 1691 1692/* 1693 * given a LOGICAL APIC# and pin#, return: 1694 * the associated INTerrupt type if found 1695 * -1 if NOT found 1696 */ 1697int 1698apic_int_type(int apic, int pin) 1699{ 1700 int x; 1701 1702 /* search each of the possible INTerrupt sources */ 1703 for (x = 0; x < nintrs; ++x) 1704 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1705 (pin == io_apic_ints[x].dst_apic_int)) 1706 return (io_apic_ints[x].int_type); 1707 1708 return -1; /* NOT found */ 1709} 1710 1711int 1712apic_irq(int apic, int pin) 1713{ 1714 int x; 1715 int res; 1716 1717 for (x = 0; x < nintrs; ++x) 1718 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1719 (pin == io_apic_ints[x].dst_apic_int)) { 1720 res = io_apic_ints[x].int_vector; 1721 if (res == 0xff) 1722 return -1; 1723 if (apic != int_to_apicintpin[res].ioapic) 1724 panic("apic_irq: inconsistent table"); 1725 if (pin != int_to_apicintpin[res].int_pin) 1726 panic("apic_irq inconsistent table (2)"); 1727 return res; 1728 } 1729 return -1; 1730} 1731 1732 1733/* 1734 * given a LOGICAL APIC# and pin#, return: 1735 * the associated trigger mode if found 1736 * -1 if NOT found 1737 */ 1738int 1739apic_trigger(int apic, int pin) 1740{ 1741 int x; 1742 1743 /* search each of the possible INTerrupt sources */ 1744 for (x = 0; x < nintrs; ++x) 1745 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1746 (pin == io_apic_ints[x].dst_apic_int)) 1747 return ((io_apic_ints[x].int_flags >> 2) & 0x03); 1748 1749 return -1; /* NOT found */ 1750} 1751 1752 1753/* 1754 * given a LOGICAL APIC# and pin#, return: 1755 * the associated 'active' level if found 1756 * -1 if NOT found 1757 */ 1758int 1759apic_polarity(int apic, int pin) 1760{ 1761 int x; 1762 1763 /* search each of the possible INTerrupt sources */ 1764 for (x = 0; x < nintrs; ++x) 1765 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1766 (pin == io_apic_ints[x].dst_apic_int)) 1767 return (io_apic_ints[x].int_flags & 0x03); 1768 1769 return -1; /* NOT found */ 1770} 1771 1772 1773/* 1774 * set data according to MP defaults 1775 * FIXME: probably not complete yet... 1776 */ 1777static void 1778default_mp_table(int type) 1779{ 1780 int ap_cpu_id; 1781#if defined(APIC_IO) 1782 int io_apic_id; 1783 int pin; 1784#endif /* APIC_IO */ 1785 1786#if 0 1787 printf(" MP default config type: %d\n", type); 1788 switch (type) { 1789 case 1: 1790 printf(" bus: ISA, APIC: 82489DX\n"); 1791 break; 1792 case 2: 1793 printf(" bus: EISA, APIC: 82489DX\n"); 1794 break; 1795 case 3: 1796 printf(" bus: EISA, APIC: 82489DX\n"); 1797 break; 1798 case 4: 1799 printf(" bus: MCA, APIC: 82489DX\n"); 1800 break; 1801 case 5: 1802 printf(" bus: ISA+PCI, APIC: Integrated\n"); 1803 break; 1804 case 6: 1805 printf(" bus: EISA+PCI, APIC: Integrated\n"); 1806 break; 1807 case 7: 1808 printf(" bus: MCA+PCI, APIC: Integrated\n"); 1809 break; 1810 default: 1811 printf(" future type\n"); 1812 break; 1813 /* NOTREACHED */ 1814 } 1815#endif /* 0 */ 1816 1817 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24; 1818 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; 1819 1820 /* BSP */ 1821 CPU_TO_ID(0) = boot_cpu_id; 1822 ID_TO_CPU(boot_cpu_id) = 0; 1823 1824 /* one and only AP */ 1825 CPU_TO_ID(1) = ap_cpu_id; 1826 ID_TO_CPU(ap_cpu_id) = 1; 1827 1828#if defined(APIC_IO) 1829 /* one and only IO APIC */ 1830 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; 1831 1832 /* 1833 * sanity check, refer to MP spec section 3.6.6, last paragraph 1834 * necessary as some hardware isn't properly setting up the IO APIC 1835 */ 1836#if defined(REALLY_ANAL_IOAPICID_VALUE) 1837 if (io_apic_id != 2) { 1838#else 1839 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { 1840#endif /* REALLY_ANAL_IOAPICID_VALUE */ 1841 io_apic_set_id(0, 2); 1842 io_apic_id = 2; 1843 } 1844 IO_TO_ID(0) = io_apic_id; 1845 ID_TO_IO(io_apic_id) = 0; 1846#endif /* APIC_IO */ 1847 1848 /* fill out bus entries */ 1849 switch (type) { 1850 case 1: 1851 case 2: 1852 case 3: 1853 case 4: 1854 case 5: 1855 case 6: 1856 case 7: 1857 bus_data[0].bus_id = default_data[type - 1][1]; 1858 bus_data[0].bus_type = default_data[type - 1][2]; 1859 bus_data[1].bus_id = default_data[type - 1][3]; 1860 bus_data[1].bus_type = default_data[type - 1][4]; 1861 break; 1862 1863 /* case 4: case 7: MCA NOT supported */ 1864 default: /* illegal/reserved */ 1865 panic("BAD default MP config: %d", type); 1866 /* NOTREACHED */ 1867 } 1868 1869#if defined(APIC_IO) 1870 /* general cases from MP v1.4, table 5-2 */ 1871 for (pin = 0; pin < 16; ++pin) { 1872 io_apic_ints[pin].int_type = 0; 1873 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */ 1874 io_apic_ints[pin].src_bus_id = 0; 1875 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */ 1876 io_apic_ints[pin].dst_apic_id = io_apic_id; 1877 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */ 1878 } 1879 1880 /* special cases from MP v1.4, table 5-2 */ 1881 if (type == 2) { 1882 io_apic_ints[2].int_type = 0xff; /* N/C */ 1883 io_apic_ints[13].int_type = 0xff; /* N/C */ 1884#if !defined(APIC_MIXED_MODE) 1885 /** FIXME: ??? */ 1886 panic("sorry, can't support type 2 default yet"); 1887#endif /* APIC_MIXED_MODE */ 1888 } 1889 else 1890 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ 1891 1892 if (type == 7) 1893 io_apic_ints[0].int_type = 0xff; /* N/C */ 1894 else 1895 io_apic_ints[0].int_type = 3; /* vectored 8259 */ 1896#endif /* APIC_IO */ 1897} 1898 1899 1900/* 1901 * start each AP in our list 1902 */ 1903static int 1904start_all_aps(u_int boot_addr) 1905{ 1906 int x, i, pg; 1907 u_char mpbiosreason; 1908 u_long mpbioswarmvec; 1909 struct globaldata *gd; 1910 char *stack; 1911 uintptr_t kptbase; 1912 1913 POSTCODE(START_ALL_APS_POST); 1914 1915 mtx_init(&ap_boot_mtx, "ap boot", MTX_SPIN); 1916 1917 /* initialize BSP's local APIC */ 1918 apic_initialize(); 1919 bsp_apic_ready = 1; 1920 1921 /* install the AP 1st level boot code */ 1922 install_ap_tramp(boot_addr); 1923 1924 1925 /* save the current value of the warm-start vector */ 1926 mpbioswarmvec = *((u_long *) WARMBOOT_OFF); 1927#ifndef PC98 1928 outb(CMOS_REG, BIOS_RESET); 1929 mpbiosreason = inb(CMOS_DATA); 1930#endif 1931 1932 /* record BSP in CPU map */ 1933 all_cpus = 1; 1934 1935 /* set up temporary P==V mapping for AP boot */ 1936 /* XXX this is a hack, we should boot the AP on its own stack/PTD */ 1937 kptbase = (uintptr_t)(void *)KPTphys; 1938 for (x = 0; x < NKPT; x++) 1939 PTD[x] = (pd_entry_t)(PG_V | PG_RW | 1940 ((kptbase + x * PAGE_SIZE) & PG_FRAME)); 1941 invltlb(); 1942 1943 /* start each AP */ 1944 for (x = 1; x <= mp_naps; ++x) { 1945 1946 /* This is a bit verbose, it will go away soon. */ 1947 1948 /* first page of AP's private space */ 1949 pg = x * i386_btop(sizeof(struct privatespace)); 1950 1951 /* allocate a new private data page */ 1952 gd = (struct globaldata *)kmem_alloc(kernel_map, PAGE_SIZE); 1953 1954 /* wire it into the private page table page */ 1955 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys(gd)); 1956 1957 /* allocate and set up an idle stack data page */ 1958 stack = (char *)kmem_alloc(kernel_map, UPAGES*PAGE_SIZE); 1959 for (i = 0; i < UPAGES; i++) 1960 SMPpt[pg + 1 + i] = (pt_entry_t) 1961 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 1962 1963 /* prime data page for it to use */ 1964 gd->gd_cpuid = x; 1965 globaldata_register(gd); 1966 1967 /* setup a vector to our boot code */ 1968 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 1969 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); 1970#ifndef PC98 1971 outb(CMOS_REG, BIOS_RESET); 1972 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 1973#endif 1974 1975 bootSTK = &SMP_prvspace[x].idlestack[UPAGES*PAGE_SIZE]; 1976 bootAP = x; 1977 1978 /* attempt to start the Application Processor */ 1979 CHECK_INIT(99); /* setup checkpoints */ 1980 if (!start_ap(x, boot_addr)) { 1981 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); 1982 CHECK_PRINT("trace"); /* show checkpoints */ 1983 /* better panic as the AP may be running loose */ 1984 printf("panic y/n? [y] "); 1985 if (cngetc() != 'n') 1986 panic("bye-bye"); 1987 } 1988 CHECK_PRINT("trace"); /* show checkpoints */ 1989 1990 /* record its version info */ 1991 cpu_apic_versions[x] = cpu_apic_versions[0]; 1992 1993 all_cpus |= (1 << x); /* record AP in CPU map */ 1994 } 1995 1996 /* build our map of 'other' CPUs */ 1997 PCPU_SET(other_cpus, all_cpus & ~(1 << PCPU_GET(cpuid))); 1998 1999 /* fill in our (BSP) APIC version */ 2000 cpu_apic_versions[0] = lapic.version; 2001 2002 /* restore the warmstart vector */ 2003 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 2004#ifndef PC98 2005 outb(CMOS_REG, BIOS_RESET); 2006 outb(CMOS_DATA, mpbiosreason); 2007#endif 2008 2009 /* 2010 * Set up the idle context for the BSP. Similar to above except 2011 * that some was done by locore, some by pmap.c and some is implicit 2012 * because the BSP is cpu#0 and the page is initially zero, and also 2013 * because we can refer to variables by name on the BSP.. 2014 */ 2015 2016 /* Allocate and setup BSP idle stack */ 2017 stack = (char *)kmem_alloc(kernel_map, UPAGES * PAGE_SIZE); 2018 for (i = 0; i < UPAGES; i++) 2019 SMPpt[1 + i] = (pt_entry_t) 2020 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 2021 2022 for (x = 0; x < NKPT; x++) 2023 PTD[x] = 0; 2024 pmap_set_opt(); 2025 2026 /* number of APs actually started */ 2027 return mp_ncpus - 1; 2028} 2029 2030 2031/* 2032 * load the 1st level AP boot code into base memory. 2033 */ 2034 2035/* targets for relocation */ 2036extern void bigJump(void); 2037extern void bootCodeSeg(void); 2038extern void bootDataSeg(void); 2039extern void MPentry(void); 2040extern u_int MP_GDT; 2041extern u_int mp_gdtbase; 2042 2043static void 2044install_ap_tramp(u_int boot_addr) 2045{ 2046 int x; 2047 int size = *(int *) ((u_long) & bootMP_size); 2048 u_char *src = (u_char *) ((u_long) bootMP); 2049 u_char *dst = (u_char *) boot_addr + KERNBASE; 2050 u_int boot_base = (u_int) bootMP; 2051 u_int8_t *dst8; 2052 u_int16_t *dst16; 2053 u_int32_t *dst32; 2054 2055 POSTCODE(INSTALL_AP_TRAMP_POST); 2056 2057 for (x = 0; x < size; ++x) 2058 *dst++ = *src++; 2059 2060 /* 2061 * modify addresses in code we just moved to basemem. unfortunately we 2062 * need fairly detailed info about mpboot.s for this to work. changes 2063 * to mpboot.s might require changes here. 2064 */ 2065 2066 /* boot code is located in KERNEL space */ 2067 dst = (u_char *) boot_addr + KERNBASE; 2068 2069 /* modify the lgdt arg */ 2070 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 2071 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); 2072 2073 /* modify the ljmp target for MPentry() */ 2074 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 2075 *dst32 = ((u_int) MPentry - KERNBASE); 2076 2077 /* modify the target for boot code segment */ 2078 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 2079 dst8 = (u_int8_t *) (dst16 + 1); 2080 *dst16 = (u_int) boot_addr & 0xffff; 2081 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 2082 2083 /* modify the target for boot data segment */ 2084 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 2085 dst8 = (u_int8_t *) (dst16 + 1); 2086 *dst16 = (u_int) boot_addr & 0xffff; 2087 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 2088} 2089 2090 2091/* 2092 * this function starts the AP (application processor) identified 2093 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 2094 * to accomplish this. This is necessary because of the nuances 2095 * of the different hardware we might encounter. It ain't pretty, 2096 * but it seems to work. 2097 */ 2098static int 2099start_ap(int logical_cpu, u_int boot_addr) 2100{ 2101 int physical_cpu; 2102 int vector; 2103 int cpus; 2104 u_long icr_lo, icr_hi; 2105 2106 POSTCODE(START_AP_POST); 2107 2108 /* get the PHYSICAL APIC ID# */ 2109 physical_cpu = CPU_TO_ID(logical_cpu); 2110 2111 /* calculate the vector */ 2112 vector = (boot_addr >> 12) & 0xff; 2113 2114 /* used as a watchpoint to signal AP startup */ 2115 cpus = mp_ncpus; 2116 2117 /* 2118 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 2119 * and running the target CPU. OR this INIT IPI might be latched (P5 2120 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 2121 * ignored. 2122 */ 2123 2124 /* setup the address for the target AP */ 2125 icr_hi = lapic.icr_hi & ~APIC_ID_MASK; 2126 icr_hi |= (physical_cpu << 24); 2127 lapic.icr_hi = icr_hi; 2128 2129 /* do an INIT IPI: assert RESET */ 2130 icr_lo = lapic.icr_lo & 0xfff00000; 2131 lapic.icr_lo = icr_lo | 0x0000c500; 2132 2133 /* wait for pending status end */ 2134 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2135 /* spin */ ; 2136 2137 /* do an INIT IPI: deassert RESET */ 2138 lapic.icr_lo = icr_lo | 0x00008500; 2139 2140 /* wait for pending status end */ 2141 u_sleep(10000); /* wait ~10mS */ 2142 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2143 /* spin */ ; 2144 2145 /* 2146 * next we do a STARTUP IPI: the previous INIT IPI might still be 2147 * latched, (P5 bug) this 1st STARTUP would then terminate 2148 * immediately, and the previously started INIT IPI would continue. OR 2149 * the previous INIT IPI has already run. and this STARTUP IPI will 2150 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 2151 * will run. 2152 */ 2153 2154 /* do a STARTUP IPI */ 2155 lapic.icr_lo = icr_lo | 0x00000600 | vector; 2156 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2157 /* spin */ ; 2158 u_sleep(200); /* wait ~200uS */ 2159 2160 /* 2161 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 2162 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 2163 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 2164 * recognized after hardware RESET or INIT IPI. 2165 */ 2166 2167 lapic.icr_lo = icr_lo | 0x00000600 | vector; 2168 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2169 /* spin */ ; 2170 u_sleep(200); /* wait ~200uS */ 2171 2172 /* wait for it to start */ 2173 set_apic_timer(5000000);/* == 5 seconds */ 2174 while (read_apic_timer()) 2175 if (mp_ncpus > cpus) 2176 return 1; /* return SUCCESS */ 2177 2178 return 0; /* return FAILURE */ 2179} 2180 2181/* 2182 * Flush the TLB on all other CPU's 2183 * 2184 * XXX: Needs to handshake and wait for completion before proceding. 2185 */ 2186void 2187smp_invltlb(void) 2188{ 2189#if defined(APIC_IO) 2190 if (smp_started && invltlb_ok) 2191 ipi_all_but_self(IPI_INVLTLB); 2192#endif /* APIC_IO */ 2193} 2194 2195void 2196invlpg(u_int addr) 2197{ 2198 __asm __volatile("invlpg (%0)"::"r"(addr):"memory"); 2199 2200 /* send a message to the other CPUs */ 2201 smp_invltlb(); 2202} 2203 2204void 2205invltlb(void) 2206{ 2207 u_long temp; 2208 2209 /* 2210 * This should be implemented as load_cr3(rcr3()) when load_cr3() is 2211 * inlined. 2212 */ 2213 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory"); 2214 2215 /* send a message to the other CPUs */ 2216 smp_invltlb(); 2217} 2218 2219 2220/* 2221 * This is called once the rest of the system is up and running and we're 2222 * ready to let the AP's out of the pen. 2223 */ 2224extern void enable_sse(void); 2225 2226void 2227ap_init(void) 2228{ 2229 u_int apic_id; 2230 2231 /* spin until all the AP's are ready */ 2232 while (!aps_ready) 2233 /* spin */ ; 2234 2235 /* 2236 * Set curproc to our per-cpu idleproc so that mutexes have 2237 * something unique to lock with. 2238 */ 2239 PCPU_SET(curproc, PCPU_GET(idleproc)); 2240 PCPU_SET(spinlocks, NULL); 2241 2242 /* lock against other AP's that are waking up */ 2243 mtx_lock_spin(&ap_boot_mtx); 2244 2245 /* BSP may have changed PTD while we're waiting for the lock */ 2246 cpu_invltlb(); 2247 2248 smp_cpus++; 2249 2250#if defined(I586_CPU) && !defined(NO_F00F_HACK) 2251 lidt(&r_idt); 2252#endif 2253 2254 /* Build our map of 'other' CPUs. */ 2255 PCPU_SET(other_cpus, all_cpus & ~(1 << PCPU_GET(cpuid))); 2256 2257 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid)); 2258 2259 /* set up CPU registers and state */ 2260 cpu_setregs(); 2261 2262 /* set up FPU state on the AP */ 2263 npxinit(__INITIAL_NPXCW__); 2264 2265 /* set up SSE registers */ 2266 enable_sse(); 2267 2268 /* A quick check from sanity claus */ 2269 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]); 2270 if (PCPU_GET(cpuid) != apic_id) { 2271 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid)); 2272 printf("SMP: apic_id = %d\n", apic_id); 2273 printf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]); 2274 panic("cpuid mismatch! boom!!"); 2275 } 2276 2277 /* Init local apic for irq's */ 2278 apic_initialize(); 2279 2280 /* Set memory range attributes for this CPU to match the BSP */ 2281 mem_range_AP_init(); 2282 2283 /* 2284 * Activate smp_invltlb, although strictly speaking, this isn't 2285 * quite correct yet. We should have a bitfield for cpus willing 2286 * to accept TLB flush IPI's or something and sync them. 2287 */ 2288 if (smp_cpus == mp_ncpus) { 2289 invltlb_ok = 1; 2290 smp_started = 1; /* enable IPI's, tlb shootdown, freezes etc */ 2291 smp_active = 1; /* historic */ 2292 } 2293 2294 /* let other AP's wake up now */ 2295 mtx_unlock_spin(&ap_boot_mtx); 2296 2297 /* wait until all the AP's are up */ 2298 while (smp_started == 0) 2299 ; /* nothing */ 2300 2301 microuptime(PCPU_PTR(switchtime)); 2302 PCPU_SET(switchticks, ticks); 2303 2304 /* ok, now grab sched_lock and enter the scheduler */ 2305 enable_intr(); 2306 mtx_lock_spin(&sched_lock); 2307 cpu_throw(); /* doesn't return */ 2308 2309 panic("scheduler returned us to ap_init"); 2310} 2311 2312/* 2313 * For statclock, we send an IPI to all CPU's to have them call this 2314 * function. 2315 */ 2316void 2317forwarded_statclock(struct trapframe frame) 2318{ 2319 2320 mtx_lock_spin(&sched_lock); 2321 statclock_process(curproc, TRAPF_PC(&frame), TRAPF_USERMODE(&frame)); 2322 mtx_unlock_spin(&sched_lock); 2323} 2324 2325void 2326forward_statclock(void) 2327{ 2328 int map; 2329 2330 CTR0(KTR_SMP, "forward_statclock"); 2331 2332 if (!smp_started || !invltlb_ok || cold || panicstr) 2333 return; 2334 2335 map = PCPU_GET(other_cpus) & ~stopped_cpus ; 2336 if (map != 0) 2337 ipi_selected(map, IPI_STATCLOCK); 2338} 2339 2340/* 2341 * For each hardclock(), we send an IPI to all other CPU's to have them 2342 * execute this function. It would be nice to reduce contention on 2343 * sched_lock if we could simply peek at the CPU to determine the user/kernel 2344 * state and call hardclock_process() on the CPU receiving the clock interrupt 2345 * and then just use a simple IPI to handle any ast's if needed. 2346 */ 2347void 2348forwarded_hardclock(struct trapframe frame) 2349{ 2350 2351 mtx_lock_spin(&sched_lock); 2352 hardclock_process(curproc, TRAPF_USERMODE(&frame)); 2353 mtx_unlock_spin(&sched_lock); 2354} 2355 2356void 2357forward_hardclock(void) 2358{ 2359 u_int map; 2360 2361 CTR0(KTR_SMP, "forward_hardclock"); 2362 2363 if (!smp_started || !invltlb_ok || cold || panicstr) 2364 return; 2365 2366 map = PCPU_GET(other_cpus) & ~stopped_cpus ; 2367 if (map != 0) 2368 ipi_selected(map, IPI_HARDCLOCK); 2369} 2370 2371#ifdef APIC_INTR_REORDER 2372/* 2373 * Maintain mapping from softintr vector to isr bit in local apic. 2374 */ 2375void 2376set_lapic_isrloc(int intr, int vector) 2377{ 2378 if (intr < 0 || intr > 32) 2379 panic("set_apic_isrloc: bad intr argument: %d",intr); 2380 if (vector < ICU_OFFSET || vector > 255) 2381 panic("set_apic_isrloc: bad vector argument: %d",vector); 2382 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2); 2383 apic_isrbit_location[intr].bit = (1<<(vector & 31)); 2384} 2385#endif 2386 2387/* 2388 * send an IPI to a set of cpus. 2389 */ 2390void 2391ipi_selected(u_int32_t cpus, u_int ipi) 2392{ 2393 2394 CTR2(KTR_SMP, __func__ ": cpus: %x ipi: %x", cpus, ipi); 2395 selected_apic_ipi(cpus, ipi, APIC_DELMODE_FIXED); 2396} 2397 2398/* 2399 * send an IPI INTerrupt containing 'vector' to all CPUs, including myself 2400 */ 2401void 2402ipi_all(u_int ipi) 2403{ 2404 2405 CTR1(KTR_SMP, __func__ ": ipi: %x", ipi); 2406 apic_ipi(APIC_DEST_ALLISELF, ipi, APIC_DELMODE_FIXED); 2407} 2408 2409/* 2410 * send an IPI to all CPUs EXCEPT myself 2411 */ 2412void 2413ipi_all_but_self(u_int ipi) 2414{ 2415 2416 CTR1(KTR_SMP, __func__ ": ipi: %x", ipi); 2417 apic_ipi(APIC_DEST_ALLESELF, ipi, APIC_DELMODE_FIXED); 2418} 2419 2420/* 2421 * send an IPI to myself 2422 */ 2423void 2424ipi_self(u_int ipi) 2425{ 2426 2427 CTR1(KTR_SMP, __func__ ": ipi: %x", ipi); 2428 apic_ipi(APIC_DEST_SELF, ipi, APIC_DELMODE_FIXED); 2429} 2430 2431void 2432release_aps(void *dummy __unused) 2433{ 2434 atomic_store_rel_int(&aps_ready, 1); 2435} 2436 2437SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL); 2438