mptable.c revision 52121
1/* 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: head/sys/i386/i386/mptable.c 52121 1999-10-11 14:50:03Z peter $ 26 */ 27 28#include "opt_smp.h" 29#include "opt_cpu.h" 30#include "opt_user_ldt.h" 31 32#ifdef SMP 33#include <machine/smptests.h> 34#else 35#error 36#endif 37 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/kernel.h> 41#include <sys/proc.h> 42#include <sys/sysctl.h> 43#include <sys/malloc.h> 44#include <sys/memrange.h> 45#ifdef BETTER_CLOCK 46#include <sys/dkstat.h> 47#endif 48#include <sys/cons.h> /* cngetc() */ 49 50#include <vm/vm.h> 51#include <vm/vm_param.h> 52#include <vm/pmap.h> 53#include <vm/vm_kern.h> 54#include <vm/vm_extern.h> 55#ifdef BETTER_CLOCK 56#include <sys/lock.h> 57#include <vm/vm_map.h> 58#include <sys/user.h> 59#ifdef GPROF 60#include <sys/gmon.h> 61#endif 62#endif 63 64#include <machine/smp.h> 65#include <machine/apic.h> 66#include <machine/atomic.h> 67#include <machine/cpufunc.h> 68#include <machine/mpapic.h> 69#include <machine/psl.h> 70#include <machine/segments.h> 71#include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */ 72#include <machine/tss.h> 73#include <machine/specialreg.h> 74#include <machine/globaldata.h> 75 76#if defined(APIC_IO) 77#include <machine/md_var.h> /* setidt() */ 78#include <i386/isa/icu.h> /* IPIs */ 79#include <i386/isa/intr_machdep.h> /* IPIs */ 80#endif /* APIC_IO */ 81 82#if defined(TEST_DEFAULT_CONFIG) 83#define MPFPS_MPFB1 TEST_DEFAULT_CONFIG 84#else 85#define MPFPS_MPFB1 mpfps->mpfb1 86#endif /* TEST_DEFAULT_CONFIG */ 87 88#define WARMBOOT_TARGET 0 89#define WARMBOOT_OFF (KERNBASE + 0x0467) 90#define WARMBOOT_SEG (KERNBASE + 0x0469) 91 92#ifdef PC98 93#define BIOS_BASE (0xe8000) 94#define BIOS_SIZE (0x18000) 95#else 96#define BIOS_BASE (0xf0000) 97#define BIOS_SIZE (0x10000) 98#endif 99#define BIOS_COUNT (BIOS_SIZE/4) 100 101#define CMOS_REG (0x70) 102#define CMOS_DATA (0x71) 103#define BIOS_RESET (0x0f) 104#define BIOS_WARM (0x0a) 105 106#define PROCENTRY_FLAG_EN 0x01 107#define PROCENTRY_FLAG_BP 0x02 108#define IOAPICENTRY_FLAG_EN 0x01 109 110 111/* MP Floating Pointer Structure */ 112typedef struct MPFPS { 113 char signature[4]; 114 void *pap; 115 u_char length; 116 u_char spec_rev; 117 u_char checksum; 118 u_char mpfb1; 119 u_char mpfb2; 120 u_char mpfb3; 121 u_char mpfb4; 122 u_char mpfb5; 123} *mpfps_t; 124 125/* MP Configuration Table Header */ 126typedef struct MPCTH { 127 char signature[4]; 128 u_short base_table_length; 129 u_char spec_rev; 130 u_char checksum; 131 u_char oem_id[8]; 132 u_char product_id[12]; 133 void *oem_table_pointer; 134 u_short oem_table_size; 135 u_short entry_count; 136 void *apic_address; 137 u_short extended_table_length; 138 u_char extended_table_checksum; 139 u_char reserved; 140} *mpcth_t; 141 142 143typedef struct PROCENTRY { 144 u_char type; 145 u_char apic_id; 146 u_char apic_version; 147 u_char cpu_flags; 148 u_long cpu_signature; 149 u_long feature_flags; 150 u_long reserved1; 151 u_long reserved2; 152} *proc_entry_ptr; 153 154typedef struct BUSENTRY { 155 u_char type; 156 u_char bus_id; 157 char bus_type[6]; 158} *bus_entry_ptr; 159 160typedef struct IOAPICENTRY { 161 u_char type; 162 u_char apic_id; 163 u_char apic_version; 164 u_char apic_flags; 165 void *apic_address; 166} *io_apic_entry_ptr; 167 168typedef struct INTENTRY { 169 u_char type; 170 u_char int_type; 171 u_short int_flags; 172 u_char src_bus_id; 173 u_char src_bus_irq; 174 u_char dst_apic_id; 175 u_char dst_apic_int; 176} *int_entry_ptr; 177 178/* descriptions of MP basetable entries */ 179typedef struct BASETABLE_ENTRY { 180 u_char type; 181 u_char length; 182 char name[16]; 183} basetable_entry; 184 185/* 186 * this code MUST be enabled here and in mpboot.s. 187 * it follows the very early stages of AP boot by placing values in CMOS ram. 188 * it NORMALLY will never be needed and thus the primitive method for enabling. 189 * 190#define CHECK_POINTS 191 */ 192 193#if defined(CHECK_POINTS) && !defined(PC98) 194#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 195#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 196 197#define CHECK_INIT(D); \ 198 CHECK_WRITE(0x34, (D)); \ 199 CHECK_WRITE(0x35, (D)); \ 200 CHECK_WRITE(0x36, (D)); \ 201 CHECK_WRITE(0x37, (D)); \ 202 CHECK_WRITE(0x38, (D)); \ 203 CHECK_WRITE(0x39, (D)); 204 205#define CHECK_PRINT(S); \ 206 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 207 (S), \ 208 CHECK_READ(0x34), \ 209 CHECK_READ(0x35), \ 210 CHECK_READ(0x36), \ 211 CHECK_READ(0x37), \ 212 CHECK_READ(0x38), \ 213 CHECK_READ(0x39)); 214 215#else /* CHECK_POINTS */ 216 217#define CHECK_INIT(D) 218#define CHECK_PRINT(S) 219 220#endif /* CHECK_POINTS */ 221 222/* 223 * Values to send to the POST hardware. 224 */ 225#define MP_BOOTADDRESS_POST 0x10 226#define MP_PROBE_POST 0x11 227#define MPTABLE_PASS1_POST 0x12 228 229#define MP_START_POST 0x13 230#define MP_ENABLE_POST 0x14 231#define MPTABLE_PASS2_POST 0x15 232 233#define START_ALL_APS_POST 0x16 234#define INSTALL_AP_TRAMP_POST 0x17 235#define START_AP_POST 0x18 236 237#define MP_ANNOUNCE_POST 0x19 238 239 240/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ 241int current_postcode; 242 243/** XXX FIXME: what system files declare these??? */ 244extern struct region_descriptor r_gdt, r_idt; 245 246int bsp_apic_ready = 0; /* flags useability of BSP apic */ 247int mp_ncpus; /* # of CPUs, including BSP */ 248int mp_naps; /* # of Applications processors */ 249int mp_nbusses; /* # of busses */ 250int mp_napics; /* # of IO APICs */ 251int boot_cpu_id; /* designated BSP */ 252vm_offset_t cpu_apic_address; 253vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */ 254extern int nkpt; 255 256u_int32_t cpu_apic_versions[NCPU]; 257u_int32_t io_apic_versions[NAPIC]; 258 259#ifdef APIC_INTR_DIAGNOSTIC 260int apic_itrace_enter[32]; 261int apic_itrace_tryisrlock[32]; 262int apic_itrace_gotisrlock[32]; 263int apic_itrace_active[32]; 264int apic_itrace_masked[32]; 265int apic_itrace_noisrlock[32]; 266int apic_itrace_masked2[32]; 267int apic_itrace_unmask[32]; 268int apic_itrace_noforward[32]; 269int apic_itrace_leave[32]; 270int apic_itrace_enter2[32]; 271int apic_itrace_doreti[32]; 272int apic_itrace_splz[32]; 273int apic_itrace_eoi[32]; 274#ifdef APIC_INTR_DIAGNOSTIC_IRQ 275unsigned short apic_itrace_debugbuffer[32768]; 276int apic_itrace_debugbuffer_idx; 277struct simplelock apic_itrace_debuglock; 278#endif 279#endif 280 281#ifdef APIC_INTR_REORDER 282struct { 283 volatile int *location; 284 int bit; 285} apic_isrbit_location[32]; 286#endif 287 288struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE]; 289 290/* 291 * APIC ID logical/physical mapping structures. 292 * We oversize these to simplify boot-time config. 293 */ 294int cpu_num_to_apic_id[NAPICID]; 295int io_num_to_apic_id[NAPICID]; 296int apic_id_to_logical[NAPICID]; 297 298 299/* Bitmap of all available CPUs */ 300u_int all_cpus; 301 302/* AP uses this during bootstrap. Do not staticize. */ 303char *bootSTK; 304static int bootAP; 305 306/* Hotwire a 0->4MB V==P mapping */ 307extern pt_entry_t *KPTphys; 308 309/* SMP page table page */ 310extern pt_entry_t *SMPpt; 311 312struct pcb stoppcbs[NCPU]; 313 314int smp_started; /* has the system started? */ 315 316/* 317 * Local data and functions. 318 */ 319 320static int mp_capable; 321static u_int boot_address; 322static u_int base_memory; 323 324static int picmode; /* 0: virtual wire mode, 1: PIC mode */ 325static mpfps_t mpfps; 326static int search_for_sig(u_int32_t target, int count); 327static void mp_enable(u_int boot_addr); 328 329static int mptable_pass1(void); 330static int mptable_pass2(void); 331static void default_mp_table(int type); 332static void fix_mp_table(void); 333static void setup_apic_irq_mapping(void); 334static void init_locks(void); 335static int start_all_aps(u_int boot_addr); 336static void install_ap_tramp(u_int boot_addr); 337static int start_ap(int logicalCpu, u_int boot_addr); 338 339/* 340 * Calculate usable address in base memory for AP trampoline code. 341 */ 342u_int 343mp_bootaddress(u_int basemem) 344{ 345 POSTCODE(MP_BOOTADDRESS_POST); 346 347 base_memory = basemem * 1024; /* convert to bytes */ 348 349 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ 350 if ((base_memory - boot_address) < bootMP_size) 351 boot_address -= 4096; /* not enough, lower by 4k */ 352 353 return boot_address; 354} 355 356 357/* 358 * Look for an Intel MP spec table (ie, SMP capable hardware). 359 */ 360int 361mp_probe(void) 362{ 363 int x; 364 u_long segment; 365 u_int32_t target; 366 367 POSTCODE(MP_PROBE_POST); 368 369 /* see if EBDA exists */ 370 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) { 371 /* search first 1K of EBDA */ 372 target = (u_int32_t) (segment << 4); 373 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 374 goto found; 375 } else { 376 /* last 1K of base memory, effective 'top of base' passed in */ 377 target = (u_int32_t) (base_memory - 0x400); 378 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 379 goto found; 380 } 381 382 /* search the BIOS */ 383 target = (u_int32_t) BIOS_BASE; 384 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) 385 goto found; 386 387 /* nothing found */ 388 mpfps = (mpfps_t)0; 389 mp_capable = 0; 390 return 0; 391 392found: 393 /* calculate needed resources */ 394 mpfps = (mpfps_t)x; 395 if (mptable_pass1()) 396 panic("you must reconfigure your kernel"); 397 398 /* flag fact that we are running multiple processors */ 399 mp_capable = 1; 400 return 1; 401} 402 403 404/* 405 * Startup the SMP processors. 406 */ 407void 408mp_start(void) 409{ 410 POSTCODE(MP_START_POST); 411 412 /* look for MP capable motherboard */ 413 if (mp_capable) 414 mp_enable(boot_address); 415 else 416 panic("MP hardware not found!"); 417} 418 419 420/* 421 * Print various information about the SMP system hardware and setup. 422 */ 423void 424mp_announce(void) 425{ 426 int x; 427 428 POSTCODE(MP_ANNOUNCE_POST); 429 430 printf("FreeBSD/SMP: Multiprocessor motherboard\n"); 431 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0)); 432 printf(", version: 0x%08x", cpu_apic_versions[0]); 433 printf(", at 0x%08x\n", cpu_apic_address); 434 for (x = 1; x <= mp_naps; ++x) { 435 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x)); 436 printf(", version: 0x%08x", cpu_apic_versions[x]); 437 printf(", at 0x%08x\n", cpu_apic_address); 438 } 439 440#if defined(APIC_IO) 441 for (x = 0; x < mp_napics; ++x) { 442 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x)); 443 printf(", version: 0x%08x", io_apic_versions[x]); 444 printf(", at 0x%08x\n", io_apic_address[x]); 445 } 446#else 447 printf(" Warning: APIC I/O disabled\n"); 448#endif /* APIC_IO */ 449} 450 451/* 452 * AP cpu's call this to sync up protected mode. 453 */ 454void 455init_secondary(void) 456{ 457 int gsel_tss; 458 int x, myid = bootAP; 459 460 gdt_segs[GPRIV_SEL].ssd_base = (int) &SMP_prvspace[myid]; 461 gdt_segs[GPROC0_SEL].ssd_base = 462 (int) &SMP_prvspace[myid].globaldata.gd_common_tss; 463 SMP_prvspace[myid].globaldata.gd_prvspace = &SMP_prvspace[myid]; 464 465 for (x = 0; x < NGDT; x++) { 466 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd); 467 } 468 469 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 470 r_gdt.rd_base = (int) &gdt[myid * NGDT]; 471 lgdt(&r_gdt); /* does magic intra-segment return */ 472 473 lidt(&r_idt); 474 475 lldt(_default_ldt); 476#ifdef USER_LDT 477 currentldt = _default_ldt; 478#endif 479 480 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 481 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS; 482 common_tss.tss_esp0 = 0; /* not used until after switch */ 483 common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 484 common_tss.tss_ioopt = (sizeof common_tss) << 16; 485 tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd; 486 common_tssd = *tss_gdt; 487 ltr(gsel_tss); 488 489 load_cr0(0x8005003b); /* XXX! */ 490 491 pmap_set_opt(); 492} 493 494 495#if defined(APIC_IO) 496/* 497 * Final configuration of the BSP's local APIC: 498 * - disable 'pic mode'. 499 * - disable 'virtual wire mode'. 500 * - enable NMI. 501 */ 502void 503bsp_apic_configure(void) 504{ 505 u_char byte; 506 u_int32_t temp; 507 508 /* leave 'pic mode' if necessary */ 509 if (picmode) { 510 outb(0x22, 0x70); /* select IMCR */ 511 byte = inb(0x23); /* current contents */ 512 byte |= 0x01; /* mask external INTR */ 513 outb(0x23, byte); /* disconnect 8259s/NMI */ 514 } 515 516 /* mask lint0 (the 8259 'virtual wire' connection) */ 517 temp = lapic.lvt_lint0; 518 temp |= APIC_LVT_M; /* set the mask */ 519 lapic.lvt_lint0 = temp; 520 521 /* setup lint1 to handle NMI */ 522 temp = lapic.lvt_lint1; 523 temp &= ~APIC_LVT_M; /* clear the mask */ 524 lapic.lvt_lint1 = temp; 525 526 if (bootverbose) 527 apic_dump("bsp_apic_configure()"); 528} 529#endif /* APIC_IO */ 530 531 532/******************************************************************* 533 * local functions and data 534 */ 535 536/* 537 * start the SMP system 538 */ 539static void 540mp_enable(u_int boot_addr) 541{ 542 int x; 543#if defined(APIC_IO) 544 int apic; 545 u_int ux; 546#endif /* APIC_IO */ 547 548 POSTCODE(MP_ENABLE_POST); 549 550 /* turn on 4MB of V == P addressing so we can get to MP table */ 551 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME); 552 invltlb(); 553 554 /* examine the MP table for needed info, uses physical addresses */ 555 x = mptable_pass2(); 556 557 *(int *)PTD = 0; 558 invltlb(); 559 560 /* can't process default configs till the CPU APIC is pmapped */ 561 if (x) 562 default_mp_table(x); 563 564 /* post scan cleanup */ 565 fix_mp_table(); 566 setup_apic_irq_mapping(); 567 568#if defined(APIC_IO) 569 570 /* fill the LOGICAL io_apic_versions table */ 571 for (apic = 0; apic < mp_napics; ++apic) { 572 ux = io_apic_read(apic, IOAPIC_VER); 573 io_apic_versions[apic] = ux; 574 } 575 576 /* program each IO APIC in the system */ 577 for (apic = 0; apic < mp_napics; ++apic) 578 if (io_apic_setup(apic) < 0) 579 panic("IO APIC setup failure"); 580 581 /* install a 'Spurious INTerrupt' vector */ 582 setidt(XSPURIOUSINT_OFFSET, Xspuriousint, 583 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 584 585 /* install an inter-CPU IPI for TLB invalidation */ 586 setidt(XINVLTLB_OFFSET, Xinvltlb, 587 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 588 589#ifdef BETTER_CLOCK 590 /* install an inter-CPU IPI for reading processor state */ 591 setidt(XCPUCHECKSTATE_OFFSET, Xcpucheckstate, 592 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 593#endif 594 595 /* install an inter-CPU IPI for all-CPU rendezvous */ 596 setidt(XRENDEZVOUS_OFFSET, Xrendezvous, 597 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 598 599 /* install an inter-CPU IPI for forcing an additional software trap */ 600 setidt(XCPUAST_OFFSET, Xcpuast, 601 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 602 603 /* install an inter-CPU IPI for interrupt forwarding */ 604 setidt(XFORWARD_IRQ_OFFSET, Xforward_irq, 605 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 606 607 /* install an inter-CPU IPI for CPU stop/restart */ 608 setidt(XCPUSTOP_OFFSET, Xcpustop, 609 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 610 611#if defined(TEST_TEST1) 612 /* install a "fake hardware INTerrupt" vector */ 613 setidt(XTEST1_OFFSET, Xtest1, 614 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 615#endif /** TEST_TEST1 */ 616 617#endif /* APIC_IO */ 618 619 /* initialize all SMP locks */ 620 init_locks(); 621 622 /* start each Application Processor */ 623 start_all_aps(boot_addr); 624 625 /* 626 * The init process might be started on a different CPU now, 627 * and the boot CPU might not call prepare_usermode to get 628 * cr0 correctly configured. Thus we initialize cr0 here. 629 */ 630 load_cr0(rcr0() | CR0_WP | CR0_AM); 631} 632 633 634/* 635 * look for the MP spec signature 636 */ 637 638/* string defined by the Intel MP Spec as identifying the MP table */ 639#define MP_SIG 0x5f504d5f /* _MP_ */ 640#define NEXT(X) ((X) += 4) 641static int 642search_for_sig(u_int32_t target, int count) 643{ 644 int x; 645 u_int32_t *addr = (u_int32_t *) (KERNBASE + target); 646 647 for (x = 0; x < count; NEXT(x)) 648 if (addr[x] == MP_SIG) 649 /* make array index a byte index */ 650 return (target + (x * sizeof(u_int32_t))); 651 652 return -1; 653} 654 655 656static basetable_entry basetable_entry_types[] = 657{ 658 {0, 20, "Processor"}, 659 {1, 8, "Bus"}, 660 {2, 8, "I/O APIC"}, 661 {3, 8, "I/O INT"}, 662 {4, 8, "Local INT"} 663}; 664 665typedef struct BUSDATA { 666 u_char bus_id; 667 enum busTypes bus_type; 668} bus_datum; 669 670typedef struct INTDATA { 671 u_char int_type; 672 u_short int_flags; 673 u_char src_bus_id; 674 u_char src_bus_irq; 675 u_char dst_apic_id; 676 u_char dst_apic_int; 677 u_char int_vector; 678} io_int, local_int; 679 680typedef struct BUSTYPENAME { 681 u_char type; 682 char name[7]; 683} bus_type_name; 684 685static bus_type_name bus_type_table[] = 686{ 687 {CBUS, "CBUS"}, 688 {CBUSII, "CBUSII"}, 689 {EISA, "EISA"}, 690 {UNKNOWN_BUSTYPE, "---"}, 691 {UNKNOWN_BUSTYPE, "---"}, 692 {ISA, "ISA"}, 693 {UNKNOWN_BUSTYPE, "---"}, 694 {UNKNOWN_BUSTYPE, "---"}, 695 {UNKNOWN_BUSTYPE, "---"}, 696 {UNKNOWN_BUSTYPE, "---"}, 697 {UNKNOWN_BUSTYPE, "---"}, 698 {UNKNOWN_BUSTYPE, "---"}, 699 {PCI, "PCI"}, 700 {UNKNOWN_BUSTYPE, "---"}, 701 {UNKNOWN_BUSTYPE, "---"}, 702 {UNKNOWN_BUSTYPE, "---"}, 703 {UNKNOWN_BUSTYPE, "---"}, 704 {XPRESS, "XPRESS"}, 705 {UNKNOWN_BUSTYPE, "---"} 706}; 707/* from MP spec v1.4, table 5-1 */ 708static int default_data[7][5] = 709{ 710/* nbus, id0, type0, id1, type1 */ 711 {1, 0, ISA, 255, 255}, 712 {1, 0, EISA, 255, 255}, 713 {1, 0, EISA, 255, 255}, 714 {0, 255, 255, 255, 255},/* MCA not supported */ 715 {2, 0, ISA, 1, PCI}, 716 {2, 0, EISA, 1, PCI}, 717 {0, 255, 255, 255, 255} /* MCA not supported */ 718}; 719 720 721/* the bus data */ 722static bus_datum bus_data[NBUS]; 723 724/* the IO INT data, one entry per possible APIC INTerrupt */ 725static io_int io_apic_ints[NINTR]; 726 727static int nintrs; 728 729static int processor_entry __P((proc_entry_ptr entry, int cpu)); 730static int bus_entry __P((bus_entry_ptr entry, int bus)); 731static int io_apic_entry __P((io_apic_entry_ptr entry, int apic)); 732static int int_entry __P((int_entry_ptr entry, int intr)); 733static int lookup_bus_type __P((char *name)); 734 735 736/* 737 * 1st pass on motherboard's Intel MP specification table. 738 * 739 * initializes: 740 * mp_ncpus = 1 741 * 742 * determines: 743 * cpu_apic_address (common to all CPUs) 744 * io_apic_address[N] 745 * mp_naps 746 * mp_nbusses 747 * mp_napics 748 * nintrs 749 */ 750static int 751mptable_pass1(void) 752{ 753 int x; 754 mpcth_t cth; 755 int totalSize; 756 void* position; 757 int count; 758 int type; 759 int mustpanic; 760 761 POSTCODE(MPTABLE_PASS1_POST); 762 763 mustpanic = 0; 764 765 /* clear various tables */ 766 for (x = 0; x < NAPICID; ++x) { 767 io_apic_address[x] = ~0; /* IO APIC address table */ 768 } 769 770 /* init everything to empty */ 771 mp_naps = 0; 772 mp_nbusses = 0; 773 mp_napics = 0; 774 nintrs = 0; 775 776 /* check for use of 'default' configuration */ 777 if (MPFPS_MPFB1 != 0) { 778 /* use default addresses */ 779 cpu_apic_address = DEFAULT_APIC_BASE; 780 io_apic_address[0] = DEFAULT_IO_APIC_BASE; 781 782 /* fill in with defaults */ 783 mp_naps = 2; /* includes BSP */ 784 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0]; 785#if defined(APIC_IO) 786 mp_napics = 1; 787 nintrs = 16; 788#endif /* APIC_IO */ 789 } 790 else { 791 if ((cth = mpfps->pap) == 0) 792 panic("MP Configuration Table Header MISSING!"); 793 794 cpu_apic_address = (vm_offset_t) cth->apic_address; 795 796 /* walk the table, recording info of interest */ 797 totalSize = cth->base_table_length - sizeof(struct MPCTH); 798 position = (u_char *) cth + sizeof(struct MPCTH); 799 count = cth->entry_count; 800 801 while (count--) { 802 switch (type = *(u_char *) position) { 803 case 0: /* processor_entry */ 804 if (((proc_entry_ptr)position)->cpu_flags 805 & PROCENTRY_FLAG_EN) 806 ++mp_naps; 807 break; 808 case 1: /* bus_entry */ 809 ++mp_nbusses; 810 break; 811 case 2: /* io_apic_entry */ 812 if (((io_apic_entry_ptr)position)->apic_flags 813 & IOAPICENTRY_FLAG_EN) 814 io_apic_address[mp_napics++] = 815 (vm_offset_t)((io_apic_entry_ptr) 816 position)->apic_address; 817 break; 818 case 3: /* int_entry */ 819 ++nintrs; 820 break; 821 case 4: /* int_entry */ 822 break; 823 default: 824 panic("mpfps Base Table HOSED!"); 825 /* NOTREACHED */ 826 } 827 828 totalSize -= basetable_entry_types[type].length; 829 (u_char*)position += basetable_entry_types[type].length; 830 } 831 } 832 833 /* qualify the numbers */ 834 if (mp_naps > NCPU) { 835 printf("Warning: only using %d of %d available CPUs!\n", 836 NCPU, mp_naps); 837 mp_naps = NCPU; 838 } 839 if (mp_nbusses > NBUS) { 840 printf("found %d busses, increase NBUS\n", mp_nbusses); 841 mustpanic = 1; 842 } 843 if (mp_napics > NAPIC) { 844 printf("found %d apics, increase NAPIC\n", mp_napics); 845 mustpanic = 1; 846 } 847 if (nintrs > NINTR) { 848 printf("found %d intrs, increase NINTR\n", nintrs); 849 mustpanic = 1; 850 } 851 852 /* 853 * Count the BSP. 854 * This is also used as a counter while starting the APs. 855 */ 856 mp_ncpus = 1; 857 858 --mp_naps; /* subtract the BSP */ 859 860 return mustpanic; 861} 862 863 864/* 865 * 2nd pass on motherboard's Intel MP specification table. 866 * 867 * sets: 868 * boot_cpu_id 869 * ID_TO_IO(N), phy APIC ID to log CPU/IO table 870 * CPU_TO_ID(N), logical CPU to APIC ID table 871 * IO_TO_ID(N), logical IO to APIC ID table 872 * bus_data[N] 873 * io_apic_ints[N] 874 */ 875static int 876mptable_pass2(void) 877{ 878 int x; 879 mpcth_t cth; 880 int totalSize; 881 void* position; 882 int count; 883 int type; 884 int apic, bus, cpu, intr; 885 886 POSTCODE(MPTABLE_PASS2_POST); 887 888 /* clear various tables */ 889 for (x = 0; x < NAPICID; ++x) { 890 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */ 891 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */ 892 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */ 893 } 894 895 /* clear bus data table */ 896 for (x = 0; x < NBUS; ++x) 897 bus_data[x].bus_id = 0xff; 898 899 /* clear IO APIC INT table */ 900 for (x = 0; x < NINTR; ++x) { 901 io_apic_ints[x].int_type = 0xff; 902 io_apic_ints[x].int_vector = 0xff; 903 } 904 905 /* setup the cpu/apic mapping arrays */ 906 boot_cpu_id = -1; 907 908 /* record whether PIC or virtual-wire mode */ 909 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0; 910 911 /* check for use of 'default' configuration */ 912 if (MPFPS_MPFB1 != 0) 913 return MPFPS_MPFB1; /* return default configuration type */ 914 915 if ((cth = mpfps->pap) == 0) 916 panic("MP Configuration Table Header MISSING!"); 917 918 /* walk the table, recording info of interest */ 919 totalSize = cth->base_table_length - sizeof(struct MPCTH); 920 position = (u_char *) cth + sizeof(struct MPCTH); 921 count = cth->entry_count; 922 apic = bus = intr = 0; 923 cpu = 1; /* pre-count the BSP */ 924 925 while (count--) { 926 switch (type = *(u_char *) position) { 927 case 0: 928 if (processor_entry(position, cpu)) 929 ++cpu; 930 break; 931 case 1: 932 if (bus_entry(position, bus)) 933 ++bus; 934 break; 935 case 2: 936 if (io_apic_entry(position, apic)) 937 ++apic; 938 break; 939 case 3: 940 if (int_entry(position, intr)) 941 ++intr; 942 break; 943 case 4: 944 /* int_entry(position); */ 945 break; 946 default: 947 panic("mpfps Base Table HOSED!"); 948 /* NOTREACHED */ 949 } 950 951 totalSize -= basetable_entry_types[type].length; 952 (u_char *) position += basetable_entry_types[type].length; 953 } 954 955 if (boot_cpu_id == -1) 956 panic("NO BSP found!"); 957 958 /* report fact that its NOT a default configuration */ 959 return 0; 960} 961 962 963static void 964assign_apic_irq(int apic, int intpin, int irq) 965{ 966 int x; 967 968 if (int_to_apicintpin[irq].ioapic != -1) 969 panic("assign_apic_irq: inconsistent table"); 970 971 int_to_apicintpin[irq].ioapic = apic; 972 int_to_apicintpin[irq].int_pin = intpin; 973 int_to_apicintpin[irq].apic_address = ioapic[apic]; 974 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin; 975 976 for (x = 0; x < nintrs; x++) { 977 if ((io_apic_ints[x].int_type == 0 || 978 io_apic_ints[x].int_type == 3) && 979 io_apic_ints[x].int_vector == 0xff && 980 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) && 981 io_apic_ints[x].dst_apic_int == intpin) 982 io_apic_ints[x].int_vector = irq; 983 } 984} 985 986/* 987 * parse an Intel MP specification table 988 */ 989static void 990fix_mp_table(void) 991{ 992 int x; 993 int id; 994 int bus_0 = 0; /* Stop GCC warning */ 995 int bus_pci = 0; /* Stop GCC warning */ 996 int num_pci_bus; 997 998 /* 999 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS 1000 * did it wrong. The MP spec says that when more than 1 PCI bus 1001 * exists the BIOS must begin with bus entries for the PCI bus and use 1002 * actual PCI bus numbering. This implies that when only 1 PCI bus 1003 * exists the BIOS can choose to ignore this ordering, and indeed many 1004 * MP motherboards do ignore it. This causes a problem when the PCI 1005 * sub-system makes requests of the MP sub-system based on PCI bus 1006 * numbers. So here we look for the situation and renumber the 1007 * busses and associated INTs in an effort to "make it right". 1008 */ 1009 1010 /* find bus 0, PCI bus, count the number of PCI busses */ 1011 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { 1012 if (bus_data[x].bus_id == 0) { 1013 bus_0 = x; 1014 } 1015 if (bus_data[x].bus_type == PCI) { 1016 ++num_pci_bus; 1017 bus_pci = x; 1018 } 1019 } 1020 /* 1021 * bus_0 == slot of bus with ID of 0 1022 * bus_pci == slot of last PCI bus encountered 1023 */ 1024 1025 /* check the 1 PCI bus case for sanity */ 1026 if (num_pci_bus == 1) { 1027 1028 /* if it is number 0 all is well */ 1029 if (bus_data[bus_pci].bus_id == 0) 1030 return; 1031 1032 /* mis-numbered, swap with whichever bus uses slot 0 */ 1033 1034 /* swap the bus entry types */ 1035 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type; 1036 bus_data[bus_0].bus_type = PCI; 1037 1038 /* swap each relavant INTerrupt entry */ 1039 id = bus_data[bus_pci].bus_id; 1040 for (x = 0; x < nintrs; ++x) { 1041 if (io_apic_ints[x].src_bus_id == id) { 1042 io_apic_ints[x].src_bus_id = 0; 1043 } 1044 else if (io_apic_ints[x].src_bus_id == 0) { 1045 io_apic_ints[x].src_bus_id = id; 1046 } 1047 } 1048 } 1049 /* sanity check if more than 1 PCI bus */ 1050 else if (num_pci_bus > 1) { 1051 for (x = 0; x < mp_nbusses; ++x) { 1052 if (bus_data[x].bus_type != PCI) 1053 continue; 1054 } 1055 } 1056} 1057 1058 1059static void 1060setup_apic_irq_mapping(void) 1061{ 1062 int x; 1063 int int_vector; 1064 1065 /* Assign low level interrupt handlers */ 1066 for (x = 0; x < APIC_INTMAPSIZE; x++) { 1067 int_to_apicintpin[x].ioapic = -1; 1068 int_to_apicintpin[x].int_pin = 0; 1069 int_to_apicintpin[x].apic_address = NULL; 1070 int_to_apicintpin[x].redirindex = 0; 1071 } 1072 for (x = 0; x < nintrs; x++) { 1073 if (io_apic_ints[x].dst_apic_int < APIC_INTMAPSIZE && 1074 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) && 1075 io_apic_ints[x].int_vector == 0xff && 1076 (io_apic_ints[x].int_type == 0 || 1077 io_apic_ints[x].int_type == 3)) { 1078 assign_apic_irq(0, 1079 io_apic_ints[x].dst_apic_int, 1080 io_apic_ints[x].dst_apic_int); 1081 } 1082 } 1083 int_vector = 0; 1084 while (int_vector < APIC_INTMAPSIZE && 1085 int_to_apicintpin[int_vector].ioapic != -1) 1086 int_vector++; 1087 for (x = 0; x < nintrs && int_vector < APIC_INTMAPSIZE; x++) { 1088 if ((io_apic_ints[x].int_type == 0 || 1089 io_apic_ints[x].int_type == 3) && 1090 io_apic_ints[x].int_vector == 0xff) { 1091 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id), 1092 io_apic_ints[x].dst_apic_int, 1093 int_vector); 1094 int_vector++; 1095 while (int_vector < APIC_INTMAPSIZE && 1096 int_to_apicintpin[int_vector].ioapic != -1) 1097 int_vector++; 1098 } 1099 } 1100} 1101 1102 1103static int 1104processor_entry(proc_entry_ptr entry, int cpu) 1105{ 1106 /* check for usability */ 1107 if ((cpu >= NCPU) || !(entry->cpu_flags & PROCENTRY_FLAG_EN)) 1108 return 0; 1109 1110 /* check for BSP flag */ 1111 if (entry->cpu_flags & PROCENTRY_FLAG_BP) { 1112 boot_cpu_id = entry->apic_id; 1113 CPU_TO_ID(0) = entry->apic_id; 1114 ID_TO_CPU(entry->apic_id) = 0; 1115 return 0; /* its already been counted */ 1116 } 1117 1118 /* add another AP to list, if less than max number of CPUs */ 1119 else { 1120 CPU_TO_ID(cpu) = entry->apic_id; 1121 ID_TO_CPU(entry->apic_id) = cpu; 1122 return 1; 1123 } 1124} 1125 1126 1127static int 1128bus_entry(bus_entry_ptr entry, int bus) 1129{ 1130 int x; 1131 char c, name[8]; 1132 1133 /* encode the name into an index */ 1134 for (x = 0; x < 6; ++x) { 1135 if ((c = entry->bus_type[x]) == ' ') 1136 break; 1137 name[x] = c; 1138 } 1139 name[x] = '\0'; 1140 1141 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) 1142 panic("unknown bus type: '%s'", name); 1143 1144 bus_data[bus].bus_id = entry->bus_id; 1145 bus_data[bus].bus_type = x; 1146 1147 return 1; 1148} 1149 1150 1151static int 1152io_apic_entry(io_apic_entry_ptr entry, int apic) 1153{ 1154 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) 1155 return 0; 1156 1157 IO_TO_ID(apic) = entry->apic_id; 1158 ID_TO_IO(entry->apic_id) = apic; 1159 1160 return 1; 1161} 1162 1163 1164static int 1165lookup_bus_type(char *name) 1166{ 1167 int x; 1168 1169 for (x = 0; x < MAX_BUSTYPE; ++x) 1170 if (strcmp(bus_type_table[x].name, name) == 0) 1171 return bus_type_table[x].type; 1172 1173 return UNKNOWN_BUSTYPE; 1174} 1175 1176 1177static int 1178int_entry(int_entry_ptr entry, int intr) 1179{ 1180 int apic; 1181 1182 io_apic_ints[intr].int_type = entry->int_type; 1183 io_apic_ints[intr].int_flags = entry->int_flags; 1184 io_apic_ints[intr].src_bus_id = entry->src_bus_id; 1185 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq; 1186 if (entry->dst_apic_id == 255) { 1187 /* This signal goes to all IO APICS. Select an IO APIC 1188 with sufficient number of interrupt pins */ 1189 for (apic = 0; apic < mp_napics; apic++) 1190 if (((io_apic_read(apic, IOAPIC_VER) & 1191 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >= 1192 entry->dst_apic_int) 1193 break; 1194 if (apic < mp_napics) 1195 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic); 1196 else 1197 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; 1198 } else 1199 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; 1200 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int; 1201 1202 return 1; 1203} 1204 1205 1206static int 1207apic_int_is_bus_type(int intr, int bus_type) 1208{ 1209 int bus; 1210 1211 for (bus = 0; bus < mp_nbusses; ++bus) 1212 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) 1213 && ((int) bus_data[bus].bus_type == bus_type)) 1214 return 1; 1215 1216 return 0; 1217} 1218 1219 1220/* 1221 * Given a traditional ISA INT mask, return an APIC mask. 1222 */ 1223u_int 1224isa_apic_mask(u_int isa_mask) 1225{ 1226 int isa_irq; 1227 int apic_pin; 1228 1229#if defined(SKIP_IRQ15_REDIRECT) 1230 if (isa_mask == (1 << 15)) { 1231 printf("skipping ISA IRQ15 redirect\n"); 1232 return isa_mask; 1233 } 1234#endif /* SKIP_IRQ15_REDIRECT */ 1235 1236 isa_irq = ffs(isa_mask); /* find its bit position */ 1237 if (isa_irq == 0) /* doesn't exist */ 1238 return 0; 1239 --isa_irq; /* make it zero based */ 1240 1241 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */ 1242 if (apic_pin == -1) 1243 return 0; 1244 1245 return (1 << apic_pin); /* convert pin# to a mask */ 1246} 1247 1248 1249/* 1250 * Determine which APIC pin an ISA/EISA INT is attached to. 1251 */ 1252#define INTTYPE(I) (io_apic_ints[(I)].int_type) 1253#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) 1254#define INTIRQ(I) (io_apic_ints[(I)].int_vector) 1255#define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id)) 1256 1257#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) 1258int 1259isa_apic_irq(int isa_irq) 1260{ 1261 int intr; 1262 1263 for (intr = 0; intr < nintrs; ++intr) { /* check each record */ 1264 if (INTTYPE(intr) == 0) { /* standard INT */ 1265 if (SRCBUSIRQ(intr) == isa_irq) { 1266 if (apic_int_is_bus_type(intr, ISA) || 1267 apic_int_is_bus_type(intr, EISA)) 1268 return INTIRQ(intr); /* found */ 1269 } 1270 } 1271 } 1272 return -1; /* NOT found */ 1273} 1274 1275 1276/* 1277 * Determine which APIC pin a PCI INT is attached to. 1278 */ 1279#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) 1280#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) 1281#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) 1282int 1283pci_apic_irq(int pciBus, int pciDevice, int pciInt) 1284{ 1285 int intr; 1286 1287 --pciInt; /* zero based */ 1288 1289 for (intr = 0; intr < nintrs; ++intr) /* check each record */ 1290 if ((INTTYPE(intr) == 0) /* standard INT */ 1291 && (SRCBUSID(intr) == pciBus) 1292 && (SRCBUSDEVICE(intr) == pciDevice) 1293 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ 1294 if (apic_int_is_bus_type(intr, PCI)) 1295 return INTIRQ(intr); /* exact match */ 1296 1297 return -1; /* NOT found */ 1298} 1299 1300int 1301next_apic_irq(int irq) 1302{ 1303 int intr, ointr; 1304 int bus, bustype; 1305 1306 bus = 0; 1307 bustype = 0; 1308 for (intr = 0; intr < nintrs; intr++) { 1309 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0) 1310 continue; 1311 bus = SRCBUSID(intr); 1312 bustype = apic_bus_type(bus); 1313 if (bustype != ISA && 1314 bustype != EISA && 1315 bustype != PCI) 1316 continue; 1317 break; 1318 } 1319 if (intr >= nintrs) { 1320 return -1; 1321 } 1322 for (ointr = intr + 1; ointr < nintrs; ointr++) { 1323 if (INTTYPE(ointr) != 0) 1324 continue; 1325 if (bus != SRCBUSID(ointr)) 1326 continue; 1327 if (bustype == PCI) { 1328 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr)) 1329 continue; 1330 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr)) 1331 continue; 1332 } 1333 if (bustype == ISA || bustype == EISA) { 1334 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr)) 1335 continue; 1336 } 1337 if (INTPIN(intr) == INTPIN(ointr)) 1338 continue; 1339 break; 1340 } 1341 if (ointr >= nintrs) { 1342 return -1; 1343 } 1344 return INTIRQ(ointr); 1345} 1346#undef SRCBUSLINE 1347#undef SRCBUSDEVICE 1348#undef SRCBUSID 1349#undef SRCBUSIRQ 1350 1351#undef INTPIN 1352#undef INTIRQ 1353#undef INTAPIC 1354#undef INTTYPE 1355 1356 1357/* 1358 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt. 1359 * 1360 * XXX FIXME: 1361 * Exactly what this means is unclear at this point. It is a solution 1362 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard 1363 * could route any of the ISA INTs to upper (>15) IRQ values. But most would 1364 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an 1365 * option. 1366 */ 1367int 1368undirect_isa_irq(int rirq) 1369{ 1370#if defined(READY) 1371 if (bootverbose) 1372 printf("Freeing redirected ISA irq %d.\n", rirq); 1373 /** FIXME: tickle the MB redirector chip */ 1374 return ???; 1375#else 1376 if (bootverbose) 1377 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq); 1378 return 0; 1379#endif /* READY */ 1380} 1381 1382 1383/* 1384 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt 1385 */ 1386int 1387undirect_pci_irq(int rirq) 1388{ 1389#if defined(READY) 1390 if (bootverbose) 1391 printf("Freeing redirected PCI irq %d.\n", rirq); 1392 1393 /** FIXME: tickle the MB redirector chip */ 1394 return ???; 1395#else 1396 if (bootverbose) 1397 printf("Freeing (NOT implemented) redirected PCI irq %d.\n", 1398 rirq); 1399 return 0; 1400#endif /* READY */ 1401} 1402 1403 1404/* 1405 * given a bus ID, return: 1406 * the bus type if found 1407 * -1 if NOT found 1408 */ 1409int 1410apic_bus_type(int id) 1411{ 1412 int x; 1413 1414 for (x = 0; x < mp_nbusses; ++x) 1415 if (bus_data[x].bus_id == id) 1416 return bus_data[x].bus_type; 1417 1418 return -1; 1419} 1420 1421 1422/* 1423 * given a LOGICAL APIC# and pin#, return: 1424 * the associated src bus ID if found 1425 * -1 if NOT found 1426 */ 1427int 1428apic_src_bus_id(int apic, int pin) 1429{ 1430 int x; 1431 1432 /* search each of the possible INTerrupt sources */ 1433 for (x = 0; x < nintrs; ++x) 1434 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1435 (pin == io_apic_ints[x].dst_apic_int)) 1436 return (io_apic_ints[x].src_bus_id); 1437 1438 return -1; /* NOT found */ 1439} 1440 1441 1442/* 1443 * given a LOGICAL APIC# and pin#, return: 1444 * the associated src bus IRQ if found 1445 * -1 if NOT found 1446 */ 1447int 1448apic_src_bus_irq(int apic, int pin) 1449{ 1450 int x; 1451 1452 for (x = 0; x < nintrs; x++) 1453 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1454 (pin == io_apic_ints[x].dst_apic_int)) 1455 return (io_apic_ints[x].src_bus_irq); 1456 1457 return -1; /* NOT found */ 1458} 1459 1460 1461/* 1462 * given a LOGICAL APIC# and pin#, return: 1463 * the associated INTerrupt type if found 1464 * -1 if NOT found 1465 */ 1466int 1467apic_int_type(int apic, int pin) 1468{ 1469 int x; 1470 1471 /* search each of the possible INTerrupt sources */ 1472 for (x = 0; x < nintrs; ++x) 1473 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1474 (pin == io_apic_ints[x].dst_apic_int)) 1475 return (io_apic_ints[x].int_type); 1476 1477 return -1; /* NOT found */ 1478} 1479 1480int 1481apic_irq(int apic, int pin) 1482{ 1483 int x; 1484 int res; 1485 1486 for (x = 0; x < nintrs; ++x) 1487 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1488 (pin == io_apic_ints[x].dst_apic_int)) { 1489 res = io_apic_ints[x].int_vector; 1490 if (res == 0xff) 1491 return -1; 1492 if (apic != int_to_apicintpin[res].ioapic) 1493 panic("apic_irq: inconsistent table"); 1494 if (pin != int_to_apicintpin[res].int_pin) 1495 panic("apic_irq inconsistent table (2)"); 1496 return res; 1497 } 1498 return -1; 1499} 1500 1501 1502/* 1503 * given a LOGICAL APIC# and pin#, return: 1504 * the associated trigger mode if found 1505 * -1 if NOT found 1506 */ 1507int 1508apic_trigger(int apic, int pin) 1509{ 1510 int x; 1511 1512 /* search each of the possible INTerrupt sources */ 1513 for (x = 0; x < nintrs; ++x) 1514 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1515 (pin == io_apic_ints[x].dst_apic_int)) 1516 return ((io_apic_ints[x].int_flags >> 2) & 0x03); 1517 1518 return -1; /* NOT found */ 1519} 1520 1521 1522/* 1523 * given a LOGICAL APIC# and pin#, return: 1524 * the associated 'active' level if found 1525 * -1 if NOT found 1526 */ 1527int 1528apic_polarity(int apic, int pin) 1529{ 1530 int x; 1531 1532 /* search each of the possible INTerrupt sources */ 1533 for (x = 0; x < nintrs; ++x) 1534 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1535 (pin == io_apic_ints[x].dst_apic_int)) 1536 return (io_apic_ints[x].int_flags & 0x03); 1537 1538 return -1; /* NOT found */ 1539} 1540 1541 1542/* 1543 * set data according to MP defaults 1544 * FIXME: probably not complete yet... 1545 */ 1546static void 1547default_mp_table(int type) 1548{ 1549 int ap_cpu_id; 1550#if defined(APIC_IO) 1551 u_int32_t ux; 1552 int io_apic_id; 1553 int pin; 1554#endif /* APIC_IO */ 1555 1556#if 0 1557 printf(" MP default config type: %d\n", type); 1558 switch (type) { 1559 case 1: 1560 printf(" bus: ISA, APIC: 82489DX\n"); 1561 break; 1562 case 2: 1563 printf(" bus: EISA, APIC: 82489DX\n"); 1564 break; 1565 case 3: 1566 printf(" bus: EISA, APIC: 82489DX\n"); 1567 break; 1568 case 4: 1569 printf(" bus: MCA, APIC: 82489DX\n"); 1570 break; 1571 case 5: 1572 printf(" bus: ISA+PCI, APIC: Integrated\n"); 1573 break; 1574 case 6: 1575 printf(" bus: EISA+PCI, APIC: Integrated\n"); 1576 break; 1577 case 7: 1578 printf(" bus: MCA+PCI, APIC: Integrated\n"); 1579 break; 1580 default: 1581 printf(" future type\n"); 1582 break; 1583 /* NOTREACHED */ 1584 } 1585#endif /* 0 */ 1586 1587 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24; 1588 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; 1589 1590 /* BSP */ 1591 CPU_TO_ID(0) = boot_cpu_id; 1592 ID_TO_CPU(boot_cpu_id) = 0; 1593 1594 /* one and only AP */ 1595 CPU_TO_ID(1) = ap_cpu_id; 1596 ID_TO_CPU(ap_cpu_id) = 1; 1597 1598#if defined(APIC_IO) 1599 /* one and only IO APIC */ 1600 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; 1601 1602 /* 1603 * sanity check, refer to MP spec section 3.6.6, last paragraph 1604 * necessary as some hardware isn't properly setting up the IO APIC 1605 */ 1606#if defined(REALLY_ANAL_IOAPICID_VALUE) 1607 if (io_apic_id != 2) { 1608#else 1609 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { 1610#endif /* REALLY_ANAL_IOAPICID_VALUE */ 1611 ux = io_apic_read(0, IOAPIC_ID); /* get current contents */ 1612 ux &= ~APIC_ID_MASK; /* clear the ID field */ 1613 ux |= 0x02000000; /* set it to '2' */ 1614 io_apic_write(0, IOAPIC_ID, ux); /* write new value */ 1615 ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */ 1616 if ((ux & APIC_ID_MASK) != 0x02000000) 1617 panic("can't control IO APIC ID, reg: 0x%08x", ux); 1618 io_apic_id = 2; 1619 } 1620 IO_TO_ID(0) = io_apic_id; 1621 ID_TO_IO(io_apic_id) = 0; 1622#endif /* APIC_IO */ 1623 1624 /* fill out bus entries */ 1625 switch (type) { 1626 case 1: 1627 case 2: 1628 case 3: 1629 case 5: 1630 case 6: 1631 bus_data[0].bus_id = default_data[type - 1][1]; 1632 bus_data[0].bus_type = default_data[type - 1][2]; 1633 bus_data[1].bus_id = default_data[type - 1][3]; 1634 bus_data[1].bus_type = default_data[type - 1][4]; 1635 break; 1636 1637 /* case 4: case 7: MCA NOT supported */ 1638 default: /* illegal/reserved */ 1639 panic("BAD default MP config: %d", type); 1640 /* NOTREACHED */ 1641 } 1642 1643#if defined(APIC_IO) 1644 /* general cases from MP v1.4, table 5-2 */ 1645 for (pin = 0; pin < 16; ++pin) { 1646 io_apic_ints[pin].int_type = 0; 1647 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */ 1648 io_apic_ints[pin].src_bus_id = 0; 1649 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */ 1650 io_apic_ints[pin].dst_apic_id = io_apic_id; 1651 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */ 1652 } 1653 1654 /* special cases from MP v1.4, table 5-2 */ 1655 if (type == 2) { 1656 io_apic_ints[2].int_type = 0xff; /* N/C */ 1657 io_apic_ints[13].int_type = 0xff; /* N/C */ 1658#if !defined(APIC_MIXED_MODE) 1659 /** FIXME: ??? */ 1660 panic("sorry, can't support type 2 default yet"); 1661#endif /* APIC_MIXED_MODE */ 1662 } 1663 else 1664 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ 1665 1666 if (type == 7) 1667 io_apic_ints[0].int_type = 0xff; /* N/C */ 1668 else 1669 io_apic_ints[0].int_type = 3; /* vectored 8259 */ 1670#endif /* APIC_IO */ 1671} 1672 1673 1674/* 1675 * initialize all the SMP locks 1676 */ 1677 1678/* critical region around IO APIC, apic_imen */ 1679struct simplelock imen_lock; 1680 1681/* critical region around splxx(), cpl, cml, cil, ipending */ 1682struct simplelock cpl_lock; 1683 1684/* Make FAST_INTR() routines sequential */ 1685struct simplelock fast_intr_lock; 1686 1687/* critical region around INTR() routines */ 1688struct simplelock intr_lock; 1689 1690/* lock regions protected in UP kernel via cli/sti */ 1691struct simplelock mpintr_lock; 1692 1693/* lock region used by kernel profiling */ 1694struct simplelock mcount_lock; 1695 1696#ifdef USE_COMLOCK 1697/* locks com (tty) data/hardware accesses: a FASTINTR() */ 1698struct simplelock com_lock; 1699#endif /* USE_COMLOCK */ 1700 1701#ifdef USE_CLOCKLOCK 1702/* lock regions around the clock hardware */ 1703struct simplelock clock_lock; 1704#endif /* USE_CLOCKLOCK */ 1705 1706/* lock around the MP rendezvous */ 1707static struct simplelock smp_rv_lock; 1708 1709static void 1710init_locks(void) 1711{ 1712 /* 1713 * Get the initial mp_lock with a count of 1 for the BSP. 1714 * This uses a LOGICAL cpu ID, ie BSP == 0. 1715 */ 1716 mp_lock = 0x00000001; 1717 1718 /* ISR uses its own "giant lock" */ 1719 isr_lock = FREE_LOCK; 1720 1721#if defined(APIC_INTR_DIAGNOSTIC) && defined(APIC_INTR_DIAGNOSTIC_IRQ) 1722 s_lock_init((struct simplelock*)&apic_itrace_debuglock); 1723#endif 1724 1725 s_lock_init((struct simplelock*)&mpintr_lock); 1726 1727 s_lock_init((struct simplelock*)&mcount_lock); 1728 1729 s_lock_init((struct simplelock*)&fast_intr_lock); 1730 s_lock_init((struct simplelock*)&intr_lock); 1731 s_lock_init((struct simplelock*)&imen_lock); 1732 s_lock_init((struct simplelock*)&cpl_lock); 1733 s_lock_init(&smp_rv_lock); 1734 1735#ifdef USE_COMLOCK 1736 s_lock_init((struct simplelock*)&com_lock); 1737#endif /* USE_COMLOCK */ 1738#ifdef USE_CLOCKLOCK 1739 s_lock_init((struct simplelock*)&clock_lock); 1740#endif /* USE_CLOCKLOCK */ 1741} 1742 1743 1744/* Wait for all APs to be fully initialized */ 1745extern int wait_ap(unsigned int); 1746 1747/* 1748 * start each AP in our list 1749 */ 1750static int 1751start_all_aps(u_int boot_addr) 1752{ 1753 int x, i, pg; 1754 u_char mpbiosreason; 1755 u_long mpbioswarmvec; 1756 struct globaldata *gd; 1757 char *stack; 1758 1759 POSTCODE(START_ALL_APS_POST); 1760 1761 /* initialize BSP's local APIC */ 1762 apic_initialize(); 1763 bsp_apic_ready = 1; 1764 1765 /* install the AP 1st level boot code */ 1766 install_ap_tramp(boot_addr); 1767 1768 1769 /* save the current value of the warm-start vector */ 1770 mpbioswarmvec = *((u_long *) WARMBOOT_OFF); 1771#ifndef PC98 1772 outb(CMOS_REG, BIOS_RESET); 1773 mpbiosreason = inb(CMOS_DATA); 1774#endif 1775 1776 /* record BSP in CPU map */ 1777 all_cpus = 1; 1778 1779 /* set up 0 -> 4MB P==V mapping for AP boot */ 1780 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME); 1781 invltlb(); 1782 1783 /* start each AP */ 1784 for (x = 1; x <= mp_naps; ++x) { 1785 1786 /* This is a bit verbose, it will go away soon. */ 1787 1788 /* first page of AP's private space */ 1789 pg = x * i386_btop(sizeof(struct privatespace)); 1790 1791 /* allocate a new private data page */ 1792 gd = (struct globaldata *)kmem_alloc(kernel_map, PAGE_SIZE); 1793 1794 /* wire it into the private page table page */ 1795 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys(gd)); 1796 1797 /* allocate and set up an idle stack data page */ 1798 stack = (char *)kmem_alloc(kernel_map, UPAGES*PAGE_SIZE); 1799 for (i = 0; i < UPAGES; i++) 1800 SMPpt[pg + 5 + i] = (pt_entry_t) 1801 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 1802 1803 SMPpt[pg + 1] = 0; /* *prv_CMAP1 */ 1804 SMPpt[pg + 2] = 0; /* *prv_CMAP2 */ 1805 SMPpt[pg + 3] = 0; /* *prv_CMAP3 */ 1806 SMPpt[pg + 4] = 0; /* *prv_PMAP1 */ 1807 1808 /* prime data page for it to use */ 1809 gd->gd_cpuid = x; 1810 gd->gd_cpu_lockid = x << 24; 1811 gd->gd_prv_CMAP1 = &SMPpt[pg + 1]; 1812 gd->gd_prv_CMAP2 = &SMPpt[pg + 2]; 1813 gd->gd_prv_CMAP3 = &SMPpt[pg + 3]; 1814 gd->gd_prv_PMAP1 = &SMPpt[pg + 4]; 1815 gd->gd_prv_CADDR1 = SMP_prvspace[x].CPAGE1; 1816 gd->gd_prv_CADDR2 = SMP_prvspace[x].CPAGE2; 1817 gd->gd_prv_CADDR3 = SMP_prvspace[x].CPAGE3; 1818 gd->gd_prv_PADDR1 = (unsigned *)SMP_prvspace[x].PPAGE1; 1819 1820 /* setup a vector to our boot code */ 1821 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 1822 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); 1823#ifndef PC98 1824 outb(CMOS_REG, BIOS_RESET); 1825 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 1826#endif 1827 1828 bootSTK = &SMP_prvspace[x].idlestack[UPAGES*PAGE_SIZE]; 1829 bootAP = x; 1830 1831 /* attempt to start the Application Processor */ 1832 CHECK_INIT(99); /* setup checkpoints */ 1833 if (!start_ap(x, boot_addr)) { 1834 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); 1835 CHECK_PRINT("trace"); /* show checkpoints */ 1836 /* better panic as the AP may be running loose */ 1837 printf("panic y/n? [y] "); 1838 if (cngetc() != 'n') 1839 panic("bye-bye"); 1840 } 1841 CHECK_PRINT("trace"); /* show checkpoints */ 1842 1843 /* record its version info */ 1844 cpu_apic_versions[x] = cpu_apic_versions[0]; 1845 1846 all_cpus |= (1 << x); /* record AP in CPU map */ 1847 } 1848 1849 /* build our map of 'other' CPUs */ 1850 other_cpus = all_cpus & ~(1 << cpuid); 1851 1852 /* fill in our (BSP) APIC version */ 1853 cpu_apic_versions[0] = lapic.version; 1854 1855 /* restore the warmstart vector */ 1856 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 1857#ifndef PC98 1858 outb(CMOS_REG, BIOS_RESET); 1859 outb(CMOS_DATA, mpbiosreason); 1860#endif 1861 1862 /* 1863 * Set up the idle context for the BSP. Similar to above except 1864 * that some was done by locore, some by pmap.c and some is implicit 1865 * because the BSP is cpu#0 and the page is initially zero, and also 1866 * because we can refer to variables by name on the BSP.. 1867 */ 1868 1869 /* Allocate and setup BSP idle stack */ 1870 stack = (char *)kmem_alloc(kernel_map, UPAGES * PAGE_SIZE); 1871 for (i = 0; i < UPAGES; i++) 1872 SMPpt[5 + i] = (pt_entry_t) 1873 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 1874 1875 *(int *)PTD = 0; 1876 pmap_set_opt(); 1877 1878 /* number of APs actually started */ 1879 return mp_ncpus - 1; 1880} 1881 1882 1883/* 1884 * load the 1st level AP boot code into base memory. 1885 */ 1886 1887/* targets for relocation */ 1888extern void bigJump(void); 1889extern void bootCodeSeg(void); 1890extern void bootDataSeg(void); 1891extern void MPentry(void); 1892extern u_int MP_GDT; 1893extern u_int mp_gdtbase; 1894 1895static void 1896install_ap_tramp(u_int boot_addr) 1897{ 1898 int x; 1899 int size = *(int *) ((u_long) & bootMP_size); 1900 u_char *src = (u_char *) ((u_long) bootMP); 1901 u_char *dst = (u_char *) boot_addr + KERNBASE; 1902 u_int boot_base = (u_int) bootMP; 1903 u_int8_t *dst8; 1904 u_int16_t *dst16; 1905 u_int32_t *dst32; 1906 1907 POSTCODE(INSTALL_AP_TRAMP_POST); 1908 1909 for (x = 0; x < size; ++x) 1910 *dst++ = *src++; 1911 1912 /* 1913 * modify addresses in code we just moved to basemem. unfortunately we 1914 * need fairly detailed info about mpboot.s for this to work. changes 1915 * to mpboot.s might require changes here. 1916 */ 1917 1918 /* boot code is located in KERNEL space */ 1919 dst = (u_char *) boot_addr + KERNBASE; 1920 1921 /* modify the lgdt arg */ 1922 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 1923 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); 1924 1925 /* modify the ljmp target for MPentry() */ 1926 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 1927 *dst32 = ((u_int) MPentry - KERNBASE); 1928 1929 /* modify the target for boot code segment */ 1930 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 1931 dst8 = (u_int8_t *) (dst16 + 1); 1932 *dst16 = (u_int) boot_addr & 0xffff; 1933 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1934 1935 /* modify the target for boot data segment */ 1936 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 1937 dst8 = (u_int8_t *) (dst16 + 1); 1938 *dst16 = (u_int) boot_addr & 0xffff; 1939 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1940} 1941 1942 1943/* 1944 * this function starts the AP (application processor) identified 1945 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 1946 * to accomplish this. This is necessary because of the nuances 1947 * of the different hardware we might encounter. It ain't pretty, 1948 * but it seems to work. 1949 */ 1950static int 1951start_ap(int logical_cpu, u_int boot_addr) 1952{ 1953 int physical_cpu; 1954 int vector; 1955 int cpus; 1956 u_long icr_lo, icr_hi; 1957 1958 POSTCODE(START_AP_POST); 1959 1960 /* get the PHYSICAL APIC ID# */ 1961 physical_cpu = CPU_TO_ID(logical_cpu); 1962 1963 /* calculate the vector */ 1964 vector = (boot_addr >> 12) & 0xff; 1965 1966 /* used as a watchpoint to signal AP startup */ 1967 cpus = mp_ncpus; 1968 1969 /* 1970 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 1971 * and running the target CPU. OR this INIT IPI might be latched (P5 1972 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 1973 * ignored. 1974 */ 1975 1976 /* setup the address for the target AP */ 1977 icr_hi = lapic.icr_hi & ~APIC_ID_MASK; 1978 icr_hi |= (physical_cpu << 24); 1979 lapic.icr_hi = icr_hi; 1980 1981 /* do an INIT IPI: assert RESET */ 1982 icr_lo = lapic.icr_lo & 0xfff00000; 1983 lapic.icr_lo = icr_lo | 0x0000c500; 1984 1985 /* wait for pending status end */ 1986 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1987 /* spin */ ; 1988 1989 /* do an INIT IPI: deassert RESET */ 1990 lapic.icr_lo = icr_lo | 0x00008500; 1991 1992 /* wait for pending status end */ 1993 u_sleep(10000); /* wait ~10mS */ 1994 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1995 /* spin */ ; 1996 1997 /* 1998 * next we do a STARTUP IPI: the previous INIT IPI might still be 1999 * latched, (P5 bug) this 1st STARTUP would then terminate 2000 * immediately, and the previously started INIT IPI would continue. OR 2001 * the previous INIT IPI has already run. and this STARTUP IPI will 2002 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 2003 * will run. 2004 */ 2005 2006 /* do a STARTUP IPI */ 2007 lapic.icr_lo = icr_lo | 0x00000600 | vector; 2008 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2009 /* spin */ ; 2010 u_sleep(200); /* wait ~200uS */ 2011 2012 /* 2013 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 2014 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 2015 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 2016 * recognized after hardware RESET or INIT IPI. 2017 */ 2018 2019 lapic.icr_lo = icr_lo | 0x00000600 | vector; 2020 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2021 /* spin */ ; 2022 u_sleep(200); /* wait ~200uS */ 2023 2024 /* wait for it to start */ 2025 set_apic_timer(5000000);/* == 5 seconds */ 2026 while (read_apic_timer()) 2027 if (mp_ncpus > cpus) 2028 return 1; /* return SUCCESS */ 2029 2030 return 0; /* return FAILURE */ 2031} 2032 2033 2034/* 2035 * Flush the TLB on all other CPU's 2036 * 2037 * XXX: Needs to handshake and wait for completion before proceding. 2038 */ 2039void 2040smp_invltlb(void) 2041{ 2042#if defined(APIC_IO) 2043 if (smp_started && invltlb_ok) 2044 all_but_self_ipi(XINVLTLB_OFFSET); 2045#endif /* APIC_IO */ 2046} 2047 2048void 2049invlpg(u_int addr) 2050{ 2051 __asm __volatile("invlpg (%0)"::"r"(addr):"memory"); 2052 2053 /* send a message to the other CPUs */ 2054 smp_invltlb(); 2055} 2056 2057void 2058invltlb(void) 2059{ 2060 u_long temp; 2061 2062 /* 2063 * This should be implemented as load_cr3(rcr3()) when load_cr3() is 2064 * inlined. 2065 */ 2066 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory"); 2067 2068 /* send a message to the other CPUs */ 2069 smp_invltlb(); 2070} 2071 2072 2073/* 2074 * When called the executing CPU will send an IPI to all other CPUs 2075 * requesting that they halt execution. 2076 * 2077 * Usually (but not necessarily) called with 'other_cpus' as its arg. 2078 * 2079 * - Signals all CPUs in map to stop. 2080 * - Waits for each to stop. 2081 * 2082 * Returns: 2083 * -1: error 2084 * 0: NA 2085 * 1: ok 2086 * 2087 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs 2088 * from executing at same time. 2089 */ 2090int 2091stop_cpus(u_int map) 2092{ 2093 if (!smp_started) 2094 return 0; 2095 2096 /* send the Xcpustop IPI to all CPUs in map */ 2097 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED); 2098 2099 while ((stopped_cpus & map) != map) 2100 /* spin */ ; 2101 2102 return 1; 2103} 2104 2105 2106/* 2107 * Called by a CPU to restart stopped CPUs. 2108 * 2109 * Usually (but not necessarily) called with 'stopped_cpus' as its arg. 2110 * 2111 * - Signals all CPUs in map to restart. 2112 * - Waits for each to restart. 2113 * 2114 * Returns: 2115 * -1: error 2116 * 0: NA 2117 * 1: ok 2118 */ 2119int 2120restart_cpus(u_int map) 2121{ 2122 if (!smp_started) 2123 return 0; 2124 2125 started_cpus = map; /* signal other cpus to restart */ 2126 2127 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */ 2128 /* spin */ ; 2129 2130 return 1; 2131} 2132 2133int smp_active = 0; /* are the APs allowed to run? */ 2134SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RW, &smp_active, 0, ""); 2135 2136/* XXX maybe should be hw.ncpu */ 2137static int smp_cpus = 1; /* how many cpu's running */ 2138SYSCTL_INT(_machdep, OID_AUTO, smp_cpus, CTLFLAG_RD, &smp_cpus, 0, ""); 2139 2140int invltlb_ok = 0; /* throttle smp_invltlb() till safe */ 2141SYSCTL_INT(_machdep, OID_AUTO, invltlb_ok, CTLFLAG_RW, &invltlb_ok, 0, ""); 2142 2143/* Warning: Do not staticize. Used from swtch.s */ 2144int do_page_zero_idle = 1; /* bzero pages for fun and profit in idleloop */ 2145SYSCTL_INT(_machdep, OID_AUTO, do_page_zero_idle, CTLFLAG_RW, 2146 &do_page_zero_idle, 0, ""); 2147 2148/* Is forwarding of a interrupt to the CPU holding the ISR lock enabled ? */ 2149int forward_irq_enabled = 1; 2150SYSCTL_INT(_machdep, OID_AUTO, forward_irq_enabled, CTLFLAG_RW, 2151 &forward_irq_enabled, 0, ""); 2152 2153/* Enable forwarding of a signal to a process running on a different CPU */ 2154static int forward_signal_enabled = 1; 2155SYSCTL_INT(_machdep, OID_AUTO, forward_signal_enabled, CTLFLAG_RW, 2156 &forward_signal_enabled, 0, ""); 2157 2158/* Enable forwarding of roundrobin to all other cpus */ 2159static int forward_roundrobin_enabled = 1; 2160SYSCTL_INT(_machdep, OID_AUTO, forward_roundrobin_enabled, CTLFLAG_RW, 2161 &forward_roundrobin_enabled, 0, ""); 2162 2163/* 2164 * This is called once the rest of the system is up and running and we're 2165 * ready to let the AP's out of the pen. 2166 */ 2167void ap_init(void); 2168 2169void 2170ap_init() 2171{ 2172 u_int apic_id; 2173 2174 /* BSP may have changed PTD while we're waiting for the lock */ 2175 cpu_invltlb(); 2176 2177 smp_cpus++; 2178 2179#if defined(I586_CPU) && !defined(NO_F00F_HACK) 2180 lidt(&r_idt); 2181#endif 2182 2183 /* Build our map of 'other' CPUs. */ 2184 other_cpus = all_cpus & ~(1 << cpuid); 2185 2186 printf("SMP: AP CPU #%d Launched!\n", cpuid); 2187 2188 /* XXX FIXME: i386 specific, and redundant: Setup the FPU. */ 2189 load_cr0((rcr0() & ~CR0_EM) | CR0_MP | CR0_NE | CR0_TS); 2190 2191 /* set up FPU state on the AP */ 2192 npxinit(__INITIAL_NPXCW__); 2193 2194 /* A quick check from sanity claus */ 2195 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]); 2196 if (cpuid != apic_id) { 2197 printf("SMP: cpuid = %d\n", cpuid); 2198 printf("SMP: apic_id = %d\n", apic_id); 2199 printf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]); 2200 panic("cpuid mismatch! boom!!"); 2201 } 2202 2203 /* Init local apic for irq's */ 2204 apic_initialize(); 2205 2206 /* Set memory range attributes for this CPU to match the BSP */ 2207 mem_range_AP_init(); 2208 2209 /* 2210 * Activate smp_invltlb, although strictly speaking, this isn't 2211 * quite correct yet. We should have a bitfield for cpus willing 2212 * to accept TLB flush IPI's or something and sync them. 2213 */ 2214 if (smp_cpus == mp_ncpus) { 2215 invltlb_ok = 1; 2216 smp_started = 1; /* enable IPI's, tlb shootdown, freezes etc */ 2217 smp_active = 1; /* historic */ 2218 } 2219} 2220 2221#ifdef BETTER_CLOCK 2222 2223#define CHECKSTATE_USER 0 2224#define CHECKSTATE_SYS 1 2225#define CHECKSTATE_INTR 2 2226 2227/* Do not staticize. Used from apic_vector.s */ 2228struct proc* checkstate_curproc[NCPU]; 2229int checkstate_cpustate[NCPU]; 2230u_long checkstate_pc[NCPU]; 2231 2232extern long cp_time[CPUSTATES]; 2233 2234#define PC_TO_INDEX(pc, prof) \ 2235 ((int)(((u_quad_t)((pc) - (prof)->pr_off) * \ 2236 (u_quad_t)((prof)->pr_scale)) >> 16) & ~1) 2237 2238static void 2239addupc_intr_forwarded(struct proc *p, int id, int *astmap) 2240{ 2241 int i; 2242 struct uprof *prof; 2243 u_long pc; 2244 2245 pc = checkstate_pc[id]; 2246 prof = &p->p_stats->p_prof; 2247 if (pc >= prof->pr_off && 2248 (i = PC_TO_INDEX(pc, prof)) < prof->pr_size) { 2249 if ((p->p_flag & P_OWEUPC) == 0) { 2250 prof->pr_addr = pc; 2251 prof->pr_ticks = 1; 2252 p->p_flag |= P_OWEUPC; 2253 } 2254 *astmap |= (1 << id); 2255 } 2256} 2257 2258static void 2259forwarded_statclock(int id, int pscnt, int *astmap) 2260{ 2261 struct pstats *pstats; 2262 long rss; 2263 struct rusage *ru; 2264 struct vmspace *vm; 2265 int cpustate; 2266 struct proc *p; 2267#ifdef GPROF 2268 register struct gmonparam *g; 2269 int i; 2270#endif 2271 2272 p = checkstate_curproc[id]; 2273 cpustate = checkstate_cpustate[id]; 2274 2275 switch (cpustate) { 2276 case CHECKSTATE_USER: 2277 if (p->p_flag & P_PROFIL) 2278 addupc_intr_forwarded(p, id, astmap); 2279 if (pscnt > 1) 2280 return; 2281 p->p_uticks++; 2282 if (p->p_nice > NZERO) 2283 cp_time[CP_NICE]++; 2284 else 2285 cp_time[CP_USER]++; 2286 break; 2287 case CHECKSTATE_SYS: 2288#ifdef GPROF 2289 /* 2290 * Kernel statistics are just like addupc_intr, only easier. 2291 */ 2292 g = &_gmonparam; 2293 if (g->state == GMON_PROF_ON) { 2294 i = checkstate_pc[id] - g->lowpc; 2295 if (i < g->textsize) { 2296 i /= HISTFRACTION * sizeof(*g->kcount); 2297 g->kcount[i]++; 2298 } 2299 } 2300#endif 2301 if (pscnt > 1) 2302 return; 2303 2304 if (!p) 2305 cp_time[CP_IDLE]++; 2306 else { 2307 p->p_sticks++; 2308 cp_time[CP_SYS]++; 2309 } 2310 break; 2311 case CHECKSTATE_INTR: 2312 default: 2313#ifdef GPROF 2314 /* 2315 * Kernel statistics are just like addupc_intr, only easier. 2316 */ 2317 g = &_gmonparam; 2318 if (g->state == GMON_PROF_ON) { 2319 i = checkstate_pc[id] - g->lowpc; 2320 if (i < g->textsize) { 2321 i /= HISTFRACTION * sizeof(*g->kcount); 2322 g->kcount[i]++; 2323 } 2324 } 2325#endif 2326 if (pscnt > 1) 2327 return; 2328 if (p) 2329 p->p_iticks++; 2330 cp_time[CP_INTR]++; 2331 } 2332 if (p != NULL) { 2333 p->p_cpticks++; 2334 if (++p->p_estcpu == 0) 2335 p->p_estcpu--; 2336 if ((p->p_estcpu & 3) == 0) { 2337 resetpriority(p); 2338 if (p->p_priority >= PUSER) 2339 p->p_priority = p->p_usrpri; 2340 } 2341 2342 /* Update resource usage integrals and maximums. */ 2343 if ((pstats = p->p_stats) != NULL && 2344 (ru = &pstats->p_ru) != NULL && 2345 (vm = p->p_vmspace) != NULL) { 2346 ru->ru_ixrss += pgtok(vm->vm_tsize); 2347 ru->ru_idrss += pgtok(vm->vm_dsize); 2348 ru->ru_isrss += pgtok(vm->vm_ssize); 2349 rss = pgtok(vmspace_resident_count(vm)); 2350 if (ru->ru_maxrss < rss) 2351 ru->ru_maxrss = rss; 2352 } 2353 } 2354} 2355 2356void 2357forward_statclock(int pscnt) 2358{ 2359 int map; 2360 int id; 2361 int i; 2362 2363 /* Kludge. We don't yet have separate locks for the interrupts 2364 * and the kernel. This means that we cannot let the other processors 2365 * handle complex interrupts while inhibiting them from entering 2366 * the kernel in a non-interrupt context. 2367 * 2368 * What we can do, without changing the locking mechanisms yet, 2369 * is letting the other processors handle a very simple interrupt 2370 * (wich determines the processor states), and do the main 2371 * work ourself. 2372 */ 2373 2374 if (!smp_started || !invltlb_ok || cold || panicstr) 2375 return; 2376 2377 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle ) */ 2378 2379 map = other_cpus & ~stopped_cpus ; 2380 checkstate_probed_cpus = 0; 2381 if (map != 0) 2382 selected_apic_ipi(map, 2383 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED); 2384 2385 i = 0; 2386 while (checkstate_probed_cpus != map) { 2387 /* spin */ 2388 i++; 2389 if (i == 100000) { 2390#ifdef BETTER_CLOCK_DIAGNOSTIC 2391 printf("forward_statclock: checkstate %x\n", 2392 checkstate_probed_cpus); 2393#endif 2394 break; 2395 } 2396 } 2397 2398 /* 2399 * Step 2: walk through other processors processes, update ticks and 2400 * profiling info. 2401 */ 2402 2403 map = 0; 2404 for (id = 0; id < mp_ncpus; id++) { 2405 if (id == cpuid) 2406 continue; 2407 if (((1 << id) & checkstate_probed_cpus) == 0) 2408 continue; 2409 forwarded_statclock(id, pscnt, &map); 2410 } 2411 if (map != 0) { 2412 checkstate_need_ast |= map; 2413 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED); 2414 i = 0; 2415 while ((checkstate_need_ast & map) != 0) { 2416 /* spin */ 2417 i++; 2418 if (i > 100000) { 2419#ifdef BETTER_CLOCK_DIAGNOSTIC 2420 printf("forward_statclock: dropped ast 0x%x\n", 2421 checkstate_need_ast & map); 2422#endif 2423 break; 2424 } 2425 } 2426 } 2427} 2428 2429void 2430forward_hardclock(int pscnt) 2431{ 2432 int map; 2433 int id; 2434 struct proc *p; 2435 struct pstats *pstats; 2436 int i; 2437 2438 /* Kludge. We don't yet have separate locks for the interrupts 2439 * and the kernel. This means that we cannot let the other processors 2440 * handle complex interrupts while inhibiting them from entering 2441 * the kernel in a non-interrupt context. 2442 * 2443 * What we can do, without changing the locking mechanisms yet, 2444 * is letting the other processors handle a very simple interrupt 2445 * (wich determines the processor states), and do the main 2446 * work ourself. 2447 */ 2448 2449 if (!smp_started || !invltlb_ok || cold || panicstr) 2450 return; 2451 2452 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle) */ 2453 2454 map = other_cpus & ~stopped_cpus ; 2455 checkstate_probed_cpus = 0; 2456 if (map != 0) 2457 selected_apic_ipi(map, 2458 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED); 2459 2460 i = 0; 2461 while (checkstate_probed_cpus != map) { 2462 /* spin */ 2463 i++; 2464 if (i == 100000) { 2465#ifdef BETTER_CLOCK_DIAGNOSTIC 2466 printf("forward_hardclock: checkstate %x\n", 2467 checkstate_probed_cpus); 2468#endif 2469 break; 2470 } 2471 } 2472 2473 /* 2474 * Step 2: walk through other processors processes, update virtual 2475 * timer and profiling timer. If stathz == 0, also update ticks and 2476 * profiling info. 2477 */ 2478 2479 map = 0; 2480 for (id = 0; id < mp_ncpus; id++) { 2481 if (id == cpuid) 2482 continue; 2483 if (((1 << id) & checkstate_probed_cpus) == 0) 2484 continue; 2485 p = checkstate_curproc[id]; 2486 if (p) { 2487 pstats = p->p_stats; 2488 if (checkstate_cpustate[id] == CHECKSTATE_USER && 2489 timevalisset(&pstats->p_timer[ITIMER_VIRTUAL].it_value) && 2490 itimerdecr(&pstats->p_timer[ITIMER_VIRTUAL], tick) == 0) { 2491 psignal(p, SIGVTALRM); 2492 map |= (1 << id); 2493 } 2494 if (timevalisset(&pstats->p_timer[ITIMER_PROF].it_value) && 2495 itimerdecr(&pstats->p_timer[ITIMER_PROF], tick) == 0) { 2496 psignal(p, SIGPROF); 2497 map |= (1 << id); 2498 } 2499 } 2500 if (stathz == 0) { 2501 forwarded_statclock( id, pscnt, &map); 2502 } 2503 } 2504 if (map != 0) { 2505 checkstate_need_ast |= map; 2506 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED); 2507 i = 0; 2508 while ((checkstate_need_ast & map) != 0) { 2509 /* spin */ 2510 i++; 2511 if (i > 100000) { 2512#ifdef BETTER_CLOCK_DIAGNOSTIC 2513 printf("forward_hardclock: dropped ast 0x%x\n", 2514 checkstate_need_ast & map); 2515#endif 2516 break; 2517 } 2518 } 2519 } 2520} 2521 2522#endif /* BETTER_CLOCK */ 2523 2524void 2525forward_signal(struct proc *p) 2526{ 2527 int map; 2528 int id; 2529 int i; 2530 2531 /* Kludge. We don't yet have separate locks for the interrupts 2532 * and the kernel. This means that we cannot let the other processors 2533 * handle complex interrupts while inhibiting them from entering 2534 * the kernel in a non-interrupt context. 2535 * 2536 * What we can do, without changing the locking mechanisms yet, 2537 * is letting the other processors handle a very simple interrupt 2538 * (wich determines the processor states), and do the main 2539 * work ourself. 2540 */ 2541 2542 if (!smp_started || !invltlb_ok || cold || panicstr) 2543 return; 2544 if (!forward_signal_enabled) 2545 return; 2546 while (1) { 2547 if (p->p_stat != SRUN) 2548 return; 2549 id = p->p_oncpu; 2550 if (id == 0xff) 2551 return; 2552 map = (1<<id); 2553 checkstate_need_ast |= map; 2554 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED); 2555 i = 0; 2556 while ((checkstate_need_ast & map) != 0) { 2557 /* spin */ 2558 i++; 2559 if (i > 100000) { 2560#if 0 2561 printf("forward_signal: dropped ast 0x%x\n", 2562 checkstate_need_ast & map); 2563#endif 2564 break; 2565 } 2566 } 2567 if (id == p->p_oncpu) 2568 return; 2569 } 2570} 2571 2572void 2573forward_roundrobin(void) 2574{ 2575 u_int map; 2576 int i; 2577 2578 if (!smp_started || !invltlb_ok || cold || panicstr) 2579 return; 2580 if (!forward_roundrobin_enabled) 2581 return; 2582 resched_cpus |= other_cpus; 2583 map = other_cpus & ~stopped_cpus ; 2584#if 1 2585 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED); 2586#else 2587 (void) all_but_self_ipi(XCPUAST_OFFSET); 2588#endif 2589 i = 0; 2590 while ((checkstate_need_ast & map) != 0) { 2591 /* spin */ 2592 i++; 2593 if (i > 100000) { 2594#if 0 2595 printf("forward_roundrobin: dropped ast 0x%x\n", 2596 checkstate_need_ast & map); 2597#endif 2598 break; 2599 } 2600 } 2601} 2602 2603 2604#ifdef APIC_INTR_REORDER 2605/* 2606 * Maintain mapping from softintr vector to isr bit in local apic. 2607 */ 2608void 2609set_lapic_isrloc(int intr, int vector) 2610{ 2611 if (intr < 0 || intr > 32) 2612 panic("set_apic_isrloc: bad intr argument: %d",intr); 2613 if (vector < ICU_OFFSET || vector > 255) 2614 panic("set_apic_isrloc: bad vector argument: %d",vector); 2615 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2); 2616 apic_isrbit_location[intr].bit = (1<<(vector & 31)); 2617} 2618#endif 2619 2620/* 2621 * All-CPU rendezvous. CPUs are signalled, all execute the setup function 2622 * (if specified), rendezvous, execute the action function (if specified), 2623 * rendezvous again, execute the teardown function (if specified), and then 2624 * resume. 2625 * 2626 * Note that the supplied external functions _must_ be reentrant and aware 2627 * that they are running in parallel and in an unknown lock context. 2628 */ 2629static void (*smp_rv_setup_func)(void *arg); 2630static void (*smp_rv_action_func)(void *arg); 2631static void (*smp_rv_teardown_func)(void *arg); 2632static void *smp_rv_func_arg; 2633static volatile int smp_rv_waiters[2]; 2634 2635void 2636smp_rendezvous_action(void) 2637{ 2638 /* setup function */ 2639 if (smp_rv_setup_func != NULL) 2640 smp_rv_setup_func(smp_rv_func_arg); 2641 /* spin on entry rendezvous */ 2642 atomic_add_int(&smp_rv_waiters[0], 1); 2643 while (smp_rv_waiters[0] < mp_ncpus) 2644 ; 2645 /* action function */ 2646 if (smp_rv_action_func != NULL) 2647 smp_rv_action_func(smp_rv_func_arg); 2648 /* spin on exit rendezvous */ 2649 atomic_add_int(&smp_rv_waiters[1], 1); 2650 while (smp_rv_waiters[1] < mp_ncpus) 2651 ; 2652 /* teardown function */ 2653 if (smp_rv_teardown_func != NULL) 2654 smp_rv_teardown_func(smp_rv_func_arg); 2655} 2656 2657void 2658smp_rendezvous(void (* setup_func)(void *), 2659 void (* action_func)(void *), 2660 void (* teardown_func)(void *), 2661 void *arg) 2662{ 2663 u_int efl; 2664 2665 /* obtain rendezvous lock */ 2666 s_lock(&smp_rv_lock); /* XXX sleep here? NOWAIT flag? */ 2667 2668 /* set static function pointers */ 2669 smp_rv_setup_func = setup_func; 2670 smp_rv_action_func = action_func; 2671 smp_rv_teardown_func = teardown_func; 2672 smp_rv_func_arg = arg; 2673 smp_rv_waiters[0] = 0; 2674 smp_rv_waiters[1] = 0; 2675 2676 /* disable interrupts on this CPU, save interrupt status */ 2677 efl = read_eflags(); 2678 write_eflags(efl & ~PSL_I); 2679 2680 /* signal other processors, which will enter the IPI with interrupts off */ 2681 all_but_self_ipi(XRENDEZVOUS_OFFSET); 2682 2683 /* call executor function */ 2684 smp_rendezvous_action(); 2685 2686 /* restore interrupt flag */ 2687 write_eflags(efl); 2688 2689 /* release lock */ 2690 s_unlock(&smp_rv_lock); 2691} 2692