mptable.c revision 48145
1/* 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $Id: mp_machdep.c,v 1.104 1999/06/23 21:47:22 luoqi Exp $ 26 */ 27 28#include "opt_smp.h" 29#include "opt_cpu.h" 30#include "opt_user_ldt.h" 31 32#ifdef SMP 33#include <machine/smptests.h> 34#else 35#error 36#endif 37 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/kernel.h> 41#include <sys/proc.h> 42#include <sys/sysctl.h> 43#include <sys/malloc.h> 44#include <sys/memrange.h> 45#ifdef BETTER_CLOCK 46#include <sys/dkstat.h> 47#endif 48 49#include <vm/vm.h> 50#include <vm/vm_param.h> 51#include <vm/pmap.h> 52#include <vm/vm_kern.h> 53#include <vm/vm_extern.h> 54#ifdef BETTER_CLOCK 55#include <sys/lock.h> 56#include <vm/vm_map.h> 57#include <sys/user.h> 58#ifdef GPROF 59#include <sys/gmon.h> 60#endif 61#endif 62 63#include <machine/smp.h> 64#include <machine/apic.h> 65#include <machine/mpapic.h> 66#include <machine/segments.h> 67#include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */ 68#include <machine/tss.h> 69#include <machine/specialreg.h> 70#include <machine/cputypes.h> 71#include <machine/globaldata.h> 72 73#include <i386/i386/cons.h> /* cngetc() */ 74 75#if defined(APIC_IO) 76#include <machine/md_var.h> /* setidt() */ 77#include <i386/isa/icu.h> /* IPIs */ 78#include <i386/isa/intr_machdep.h> /* IPIs */ 79#endif /* APIC_IO */ 80 81#if defined(TEST_DEFAULT_CONFIG) 82#define MPFPS_MPFB1 TEST_DEFAULT_CONFIG 83#else 84#define MPFPS_MPFB1 mpfps->mpfb1 85#endif /* TEST_DEFAULT_CONFIG */ 86 87#define WARMBOOT_TARGET 0 88#define WARMBOOT_OFF (KERNBASE + 0x0467) 89#define WARMBOOT_SEG (KERNBASE + 0x0469) 90 91#ifdef PC98 92#define BIOS_BASE (0xe8000) 93#define BIOS_SIZE (0x18000) 94#else 95#define BIOS_BASE (0xf0000) 96#define BIOS_SIZE (0x10000) 97#endif 98#define BIOS_COUNT (BIOS_SIZE/4) 99 100#define CMOS_REG (0x70) 101#define CMOS_DATA (0x71) 102#define BIOS_RESET (0x0f) 103#define BIOS_WARM (0x0a) 104 105#define PROCENTRY_FLAG_EN 0x01 106#define PROCENTRY_FLAG_BP 0x02 107#define IOAPICENTRY_FLAG_EN 0x01 108 109 110/* MP Floating Pointer Structure */ 111typedef struct MPFPS { 112 char signature[4]; 113 void *pap; 114 u_char length; 115 u_char spec_rev; 116 u_char checksum; 117 u_char mpfb1; 118 u_char mpfb2; 119 u_char mpfb3; 120 u_char mpfb4; 121 u_char mpfb5; 122} *mpfps_t; 123 124/* MP Configuration Table Header */ 125typedef struct MPCTH { 126 char signature[4]; 127 u_short base_table_length; 128 u_char spec_rev; 129 u_char checksum; 130 u_char oem_id[8]; 131 u_char product_id[12]; 132 void *oem_table_pointer; 133 u_short oem_table_size; 134 u_short entry_count; 135 void *apic_address; 136 u_short extended_table_length; 137 u_char extended_table_checksum; 138 u_char reserved; 139} *mpcth_t; 140 141 142typedef struct PROCENTRY { 143 u_char type; 144 u_char apic_id; 145 u_char apic_version; 146 u_char cpu_flags; 147 u_long cpu_signature; 148 u_long feature_flags; 149 u_long reserved1; 150 u_long reserved2; 151} *proc_entry_ptr; 152 153typedef struct BUSENTRY { 154 u_char type; 155 u_char bus_id; 156 char bus_type[6]; 157} *bus_entry_ptr; 158 159typedef struct IOAPICENTRY { 160 u_char type; 161 u_char apic_id; 162 u_char apic_version; 163 u_char apic_flags; 164 void *apic_address; 165} *io_apic_entry_ptr; 166 167typedef struct INTENTRY { 168 u_char type; 169 u_char int_type; 170 u_short int_flags; 171 u_char src_bus_id; 172 u_char src_bus_irq; 173 u_char dst_apic_id; 174 u_char dst_apic_int; 175} *int_entry_ptr; 176 177/* descriptions of MP basetable entries */ 178typedef struct BASETABLE_ENTRY { 179 u_char type; 180 u_char length; 181 char name[16]; 182} basetable_entry; 183 184/* 185 * this code MUST be enabled here and in mpboot.s. 186 * it follows the very early stages of AP boot by placing values in CMOS ram. 187 * it NORMALLY will never be needed and thus the primitive method for enabling. 188 * 189#define CHECK_POINTS 190 */ 191 192#if defined(CHECK_POINTS) && !defined(PC98) 193#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 194#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 195 196#define CHECK_INIT(D); \ 197 CHECK_WRITE(0x34, (D)); \ 198 CHECK_WRITE(0x35, (D)); \ 199 CHECK_WRITE(0x36, (D)); \ 200 CHECK_WRITE(0x37, (D)); \ 201 CHECK_WRITE(0x38, (D)); \ 202 CHECK_WRITE(0x39, (D)); 203 204#define CHECK_PRINT(S); \ 205 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 206 (S), \ 207 CHECK_READ(0x34), \ 208 CHECK_READ(0x35), \ 209 CHECK_READ(0x36), \ 210 CHECK_READ(0x37), \ 211 CHECK_READ(0x38), \ 212 CHECK_READ(0x39)); 213 214#else /* CHECK_POINTS */ 215 216#define CHECK_INIT(D) 217#define CHECK_PRINT(S) 218 219#endif /* CHECK_POINTS */ 220 221/* 222 * Values to send to the POST hardware. 223 */ 224#define MP_BOOTADDRESS_POST 0x10 225#define MP_PROBE_POST 0x11 226#define MPTABLE_PASS1_POST 0x12 227 228#define MP_START_POST 0x13 229#define MP_ENABLE_POST 0x14 230#define MPTABLE_PASS2_POST 0x15 231 232#define START_ALL_APS_POST 0x16 233#define INSTALL_AP_TRAMP_POST 0x17 234#define START_AP_POST 0x18 235 236#define MP_ANNOUNCE_POST 0x19 237 238 239/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ 240int current_postcode; 241 242/** XXX FIXME: what system files declare these??? */ 243extern struct region_descriptor r_gdt, r_idt; 244 245int bsp_apic_ready = 0; /* flags useability of BSP apic */ 246int mp_ncpus; /* # of CPUs, including BSP */ 247int mp_naps; /* # of Applications processors */ 248int mp_nbusses; /* # of busses */ 249int mp_napics; /* # of IO APICs */ 250int boot_cpu_id; /* designated BSP */ 251vm_offset_t cpu_apic_address; 252vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */ 253extern int nkpt; 254 255u_int32_t cpu_apic_versions[NCPU]; 256u_int32_t io_apic_versions[NAPIC]; 257 258#ifdef APIC_INTR_DIAGNOSTIC 259int apic_itrace_enter[32]; 260int apic_itrace_tryisrlock[32]; 261int apic_itrace_gotisrlock[32]; 262int apic_itrace_active[32]; 263int apic_itrace_masked[32]; 264int apic_itrace_noisrlock[32]; 265int apic_itrace_masked2[32]; 266int apic_itrace_unmask[32]; 267int apic_itrace_noforward[32]; 268int apic_itrace_leave[32]; 269int apic_itrace_enter2[32]; 270int apic_itrace_doreti[32]; 271int apic_itrace_splz[32]; 272int apic_itrace_eoi[32]; 273#ifdef APIC_INTR_DIAGNOSTIC_IRQ 274unsigned short apic_itrace_debugbuffer[32768]; 275int apic_itrace_debugbuffer_idx; 276struct simplelock apic_itrace_debuglock; 277#endif 278#endif 279 280#ifdef APIC_INTR_REORDER 281struct { 282 volatile int *location; 283 int bit; 284} apic_isrbit_location[32]; 285#endif 286 287struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE]; 288 289/* 290 * APIC ID logical/physical mapping structures. 291 * We oversize these to simplify boot-time config. 292 */ 293int cpu_num_to_apic_id[NAPICID]; 294int io_num_to_apic_id[NAPICID]; 295int apic_id_to_logical[NAPICID]; 296 297 298/* Bitmap of all available CPUs */ 299u_int all_cpus; 300 301/* AP uses this during bootstrap. Do not staticize. */ 302char *bootSTK; 303static int bootAP; 304 305/* Hotwire a 0->4MB V==P mapping */ 306extern pt_entry_t *KPTphys; 307 308/* SMP page table page */ 309extern pt_entry_t *SMPpt; 310 311struct pcb stoppcbs[NCPU]; 312 313int smp_started; /* has the system started? */ 314 315/* 316 * Local data and functions. 317 */ 318 319static int mp_capable; 320static u_int boot_address; 321static u_int base_memory; 322 323static int picmode; /* 0: virtual wire mode, 1: PIC mode */ 324static mpfps_t mpfps; 325static int search_for_sig(u_int32_t target, int count); 326static void mp_enable(u_int boot_addr); 327 328static int mptable_pass1(void); 329static int mptable_pass2(void); 330static void default_mp_table(int type); 331static void fix_mp_table(void); 332static void setup_apic_irq_mapping(void); 333static void init_locks(void); 334static int start_all_aps(u_int boot_addr); 335static void install_ap_tramp(u_int boot_addr); 336static int start_ap(int logicalCpu, u_int boot_addr); 337 338/* 339 * Calculate usable address in base memory for AP trampoline code. 340 */ 341u_int 342mp_bootaddress(u_int basemem) 343{ 344 POSTCODE(MP_BOOTADDRESS_POST); 345 346 base_memory = basemem * 1024; /* convert to bytes */ 347 348 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ 349 if ((base_memory - boot_address) < bootMP_size) 350 boot_address -= 4096; /* not enough, lower by 4k */ 351 352 return boot_address; 353} 354 355 356/* 357 * Look for an Intel MP spec table (ie, SMP capable hardware). 358 */ 359int 360mp_probe(void) 361{ 362 int x; 363 u_long segment; 364 u_int32_t target; 365 366 POSTCODE(MP_PROBE_POST); 367 368 /* see if EBDA exists */ 369 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) { 370 /* search first 1K of EBDA */ 371 target = (u_int32_t) (segment << 4); 372 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 373 goto found; 374 } else { 375 /* last 1K of base memory, effective 'top of base' passed in */ 376 target = (u_int32_t) (base_memory - 0x400); 377 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 378 goto found; 379 } 380 381 /* search the BIOS */ 382 target = (u_int32_t) BIOS_BASE; 383 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) 384 goto found; 385 386 /* nothing found */ 387 mpfps = (mpfps_t)0; 388 mp_capable = 0; 389 return 0; 390 391found: 392 /* calculate needed resources */ 393 mpfps = (mpfps_t)x; 394 if (mptable_pass1()) 395 panic("you must reconfigure your kernel"); 396 397 /* flag fact that we are running multiple processors */ 398 mp_capable = 1; 399 return 1; 400} 401 402 403/* 404 * Startup the SMP processors. 405 */ 406void 407mp_start(void) 408{ 409 POSTCODE(MP_START_POST); 410 411 /* look for MP capable motherboard */ 412 if (mp_capable) 413 mp_enable(boot_address); 414 else 415 panic("MP hardware not found!"); 416} 417 418 419/* 420 * Print various information about the SMP system hardware and setup. 421 */ 422void 423mp_announce(void) 424{ 425 int x; 426 427 POSTCODE(MP_ANNOUNCE_POST); 428 429 printf("FreeBSD/SMP: Multiprocessor motherboard\n"); 430 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0)); 431 printf(", version: 0x%08x", cpu_apic_versions[0]); 432 printf(", at 0x%08x\n", cpu_apic_address); 433 for (x = 1; x <= mp_naps; ++x) { 434 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x)); 435 printf(", version: 0x%08x", cpu_apic_versions[x]); 436 printf(", at 0x%08x\n", cpu_apic_address); 437 } 438 439#if defined(APIC_IO) 440 for (x = 0; x < mp_napics; ++x) { 441 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x)); 442 printf(", version: 0x%08x", io_apic_versions[x]); 443 printf(", at 0x%08x\n", io_apic_address[x]); 444 } 445#else 446 printf(" Warning: APIC I/O disabled\n"); 447#endif /* APIC_IO */ 448} 449 450/* 451 * AP cpu's call this to sync up protected mode. 452 */ 453void 454init_secondary(void) 455{ 456 int gsel_tss; 457 int x, myid = bootAP; 458 459 gdt_segs[GPRIV_SEL].ssd_base = (int) &SMP_prvspace[myid]; 460 gdt_segs[GPROC0_SEL].ssd_base = 461 (int) &SMP_prvspace[myid].globaldata.gd_common_tss; 462 SMP_prvspace[myid].globaldata.gd_prvspace = &SMP_prvspace[myid]; 463 464 for (x = 0; x < NGDT; x++) { 465 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd); 466 } 467 468 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 469 r_gdt.rd_base = (int) &gdt[myid * NGDT]; 470 lgdt(&r_gdt); /* does magic intra-segment return */ 471 472 lidt(&r_idt); 473 474 lldt(_default_ldt); 475#ifdef USER_LDT 476 currentldt = _default_ldt; 477#endif 478 479 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 480 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS; 481 common_tss.tss_esp0 = 0; /* not used until after switch */ 482 common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 483 common_tss.tss_ioopt = (sizeof common_tss) << 16; 484 tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd; 485 common_tssd = *tss_gdt; 486 ltr(gsel_tss); 487 488 load_cr0(0x8005003b); /* XXX! */ 489 490 pmap_set_opt(); 491} 492 493 494#if defined(APIC_IO) 495/* 496 * Final configuration of the BSP's local APIC: 497 * - disable 'pic mode'. 498 * - disable 'virtual wire mode'. 499 * - enable NMI. 500 */ 501void 502bsp_apic_configure(void) 503{ 504 u_char byte; 505 u_int32_t temp; 506 507 /* leave 'pic mode' if necessary */ 508 if (picmode) { 509 outb(0x22, 0x70); /* select IMCR */ 510 byte = inb(0x23); /* current contents */ 511 byte |= 0x01; /* mask external INTR */ 512 outb(0x23, byte); /* disconnect 8259s/NMI */ 513 } 514 515 /* mask lint0 (the 8259 'virtual wire' connection) */ 516 temp = lapic.lvt_lint0; 517 temp |= APIC_LVT_M; /* set the mask */ 518 lapic.lvt_lint0 = temp; 519 520 /* setup lint1 to handle NMI */ 521 temp = lapic.lvt_lint1; 522 temp &= ~APIC_LVT_M; /* clear the mask */ 523 lapic.lvt_lint1 = temp; 524 525 if (bootverbose) 526 apic_dump("bsp_apic_configure()"); 527} 528#endif /* APIC_IO */ 529 530 531/******************************************************************* 532 * local functions and data 533 */ 534 535/* 536 * start the SMP system 537 */ 538static void 539mp_enable(u_int boot_addr) 540{ 541 int x; 542#if defined(APIC_IO) 543 int apic; 544 u_int ux; 545#endif /* APIC_IO */ 546 547 POSTCODE(MP_ENABLE_POST); 548 549 /* turn on 4MB of V == P addressing so we can get to MP table */ 550 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME); 551 invltlb(); 552 553 /* examine the MP table for needed info, uses physical addresses */ 554 x = mptable_pass2(); 555 556 *(int *)PTD = 0; 557 invltlb(); 558 559 /* can't process default configs till the CPU APIC is pmapped */ 560 if (x) 561 default_mp_table(x); 562 563 /* post scan cleanup */ 564 fix_mp_table(); 565 setup_apic_irq_mapping(); 566 567#if defined(APIC_IO) 568 569 /* fill the LOGICAL io_apic_versions table */ 570 for (apic = 0; apic < mp_napics; ++apic) { 571 ux = io_apic_read(apic, IOAPIC_VER); 572 io_apic_versions[apic] = ux; 573 } 574 575 /* program each IO APIC in the system */ 576 for (apic = 0; apic < mp_napics; ++apic) 577 if (io_apic_setup(apic) < 0) 578 panic("IO APIC setup failure"); 579 580 /* install a 'Spurious INTerrupt' vector */ 581 setidt(XSPURIOUSINT_OFFSET, Xspuriousint, 582 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 583 584 /* install an inter-CPU IPI for TLB invalidation */ 585 setidt(XINVLTLB_OFFSET, Xinvltlb, 586 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 587 588#ifdef BETTER_CLOCK 589 /* install an inter-CPU IPI for reading processor state */ 590 setidt(XCPUCHECKSTATE_OFFSET, Xcpucheckstate, 591 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 592#endif 593 594 /* install an inter-CPU IPI for forcing an additional software trap */ 595 setidt(XCPUAST_OFFSET, Xcpuast, 596 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 597 598 /* install an inter-CPU IPI for interrupt forwarding */ 599 setidt(XFORWARD_IRQ_OFFSET, Xforward_irq, 600 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 601 602 /* install an inter-CPU IPI for CPU stop/restart */ 603 setidt(XCPUSTOP_OFFSET, Xcpustop, 604 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 605 606#if defined(TEST_TEST1) 607 /* install a "fake hardware INTerrupt" vector */ 608 setidt(XTEST1_OFFSET, Xtest1, 609 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 610#endif /** TEST_TEST1 */ 611 612#endif /* APIC_IO */ 613 614 /* initialize all SMP locks */ 615 init_locks(); 616 617 /* start each Application Processor */ 618 start_all_aps(boot_addr); 619 620 /* 621 * The init process might be started on a different CPU now, 622 * and the boot CPU might not call prepare_usermode to get 623 * cr0 correctly configured. Thus we initialize cr0 here. 624 */ 625 load_cr0(rcr0() | CR0_WP | CR0_AM); 626} 627 628 629/* 630 * look for the MP spec signature 631 */ 632 633/* string defined by the Intel MP Spec as identifying the MP table */ 634#define MP_SIG 0x5f504d5f /* _MP_ */ 635#define NEXT(X) ((X) += 4) 636static int 637search_for_sig(u_int32_t target, int count) 638{ 639 int x; 640 u_int32_t *addr = (u_int32_t *) (KERNBASE + target); 641 642 for (x = 0; x < count; NEXT(x)) 643 if (addr[x] == MP_SIG) 644 /* make array index a byte index */ 645 return (target + (x * sizeof(u_int32_t))); 646 647 return -1; 648} 649 650 651static basetable_entry basetable_entry_types[] = 652{ 653 {0, 20, "Processor"}, 654 {1, 8, "Bus"}, 655 {2, 8, "I/O APIC"}, 656 {3, 8, "I/O INT"}, 657 {4, 8, "Local INT"} 658}; 659 660typedef struct BUSDATA { 661 u_char bus_id; 662 enum busTypes bus_type; 663} bus_datum; 664 665typedef struct INTDATA { 666 u_char int_type; 667 u_short int_flags; 668 u_char src_bus_id; 669 u_char src_bus_irq; 670 u_char dst_apic_id; 671 u_char dst_apic_int; 672 u_char int_vector; 673} io_int, local_int; 674 675typedef struct BUSTYPENAME { 676 u_char type; 677 char name[7]; 678} bus_type_name; 679 680static bus_type_name bus_type_table[] = 681{ 682 {CBUS, "CBUS"}, 683 {CBUSII, "CBUSII"}, 684 {EISA, "EISA"}, 685 {UNKNOWN_BUSTYPE, "---"}, 686 {UNKNOWN_BUSTYPE, "---"}, 687 {ISA, "ISA"}, 688 {UNKNOWN_BUSTYPE, "---"}, 689 {UNKNOWN_BUSTYPE, "---"}, 690 {UNKNOWN_BUSTYPE, "---"}, 691 {UNKNOWN_BUSTYPE, "---"}, 692 {UNKNOWN_BUSTYPE, "---"}, 693 {UNKNOWN_BUSTYPE, "---"}, 694 {PCI, "PCI"}, 695 {UNKNOWN_BUSTYPE, "---"}, 696 {UNKNOWN_BUSTYPE, "---"}, 697 {UNKNOWN_BUSTYPE, "---"}, 698 {UNKNOWN_BUSTYPE, "---"}, 699 {XPRESS, "XPRESS"}, 700 {UNKNOWN_BUSTYPE, "---"} 701}; 702/* from MP spec v1.4, table 5-1 */ 703static int default_data[7][5] = 704{ 705/* nbus, id0, type0, id1, type1 */ 706 {1, 0, ISA, 255, 255}, 707 {1, 0, EISA, 255, 255}, 708 {1, 0, EISA, 255, 255}, 709 {0, 255, 255, 255, 255},/* MCA not supported */ 710 {2, 0, ISA, 1, PCI}, 711 {2, 0, EISA, 1, PCI}, 712 {0, 255, 255, 255, 255} /* MCA not supported */ 713}; 714 715 716/* the bus data */ 717static bus_datum bus_data[NBUS]; 718 719/* the IO INT data, one entry per possible APIC INTerrupt */ 720static io_int io_apic_ints[NINTR]; 721 722static int nintrs; 723 724static int processor_entry __P((proc_entry_ptr entry, int cpu)); 725static int bus_entry __P((bus_entry_ptr entry, int bus)); 726static int io_apic_entry __P((io_apic_entry_ptr entry, int apic)); 727static int int_entry __P((int_entry_ptr entry, int intr)); 728static int lookup_bus_type __P((char *name)); 729 730 731/* 732 * 1st pass on motherboard's Intel MP specification table. 733 * 734 * initializes: 735 * mp_ncpus = 1 736 * 737 * determines: 738 * cpu_apic_address (common to all CPUs) 739 * io_apic_address[N] 740 * mp_naps 741 * mp_nbusses 742 * mp_napics 743 * nintrs 744 */ 745static int 746mptable_pass1(void) 747{ 748 int x; 749 mpcth_t cth; 750 int totalSize; 751 void* position; 752 int count; 753 int type; 754 int mustpanic; 755 756 POSTCODE(MPTABLE_PASS1_POST); 757 758 mustpanic = 0; 759 760 /* clear various tables */ 761 for (x = 0; x < NAPICID; ++x) { 762 io_apic_address[x] = ~0; /* IO APIC address table */ 763 } 764 765 /* init everything to empty */ 766 mp_naps = 0; 767 mp_nbusses = 0; 768 mp_napics = 0; 769 nintrs = 0; 770 771 /* check for use of 'default' configuration */ 772 if (MPFPS_MPFB1 != 0) { 773 /* use default addresses */ 774 cpu_apic_address = DEFAULT_APIC_BASE; 775 io_apic_address[0] = DEFAULT_IO_APIC_BASE; 776 777 /* fill in with defaults */ 778 mp_naps = 2; /* includes BSP */ 779 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0]; 780#if defined(APIC_IO) 781 mp_napics = 1; 782 nintrs = 16; 783#endif /* APIC_IO */ 784 } 785 else { 786 if ((cth = mpfps->pap) == 0) 787 panic("MP Configuration Table Header MISSING!"); 788 789 cpu_apic_address = (vm_offset_t) cth->apic_address; 790 791 /* walk the table, recording info of interest */ 792 totalSize = cth->base_table_length - sizeof(struct MPCTH); 793 position = (u_char *) cth + sizeof(struct MPCTH); 794 count = cth->entry_count; 795 796 while (count--) { 797 switch (type = *(u_char *) position) { 798 case 0: /* processor_entry */ 799 if (((proc_entry_ptr)position)->cpu_flags 800 & PROCENTRY_FLAG_EN) 801 ++mp_naps; 802 break; 803 case 1: /* bus_entry */ 804 ++mp_nbusses; 805 break; 806 case 2: /* io_apic_entry */ 807 if (((io_apic_entry_ptr)position)->apic_flags 808 & IOAPICENTRY_FLAG_EN) 809 io_apic_address[mp_napics++] = 810 (vm_offset_t)((io_apic_entry_ptr) 811 position)->apic_address; 812 break; 813 case 3: /* int_entry */ 814 ++nintrs; 815 break; 816 case 4: /* int_entry */ 817 break; 818 default: 819 panic("mpfps Base Table HOSED!"); 820 /* NOTREACHED */ 821 } 822 823 totalSize -= basetable_entry_types[type].length; 824 (u_char*)position += basetable_entry_types[type].length; 825 } 826 } 827 828 /* qualify the numbers */ 829 if (mp_naps > NCPU) { 830 printf("Warning: only using %d of %d available CPUs!\n", 831 NCPU, mp_naps); 832 mp_naps = NCPU; 833 } 834 if (mp_nbusses > NBUS) { 835 printf("found %d busses, increase NBUS\n", mp_nbusses); 836 mustpanic = 1; 837 } 838 if (mp_napics > NAPIC) { 839 printf("found %d apics, increase NAPIC\n", mp_napics); 840 mustpanic = 1; 841 } 842 if (nintrs > NINTR) { 843 printf("found %d intrs, increase NINTR\n", nintrs); 844 mustpanic = 1; 845 } 846 847 /* 848 * Count the BSP. 849 * This is also used as a counter while starting the APs. 850 */ 851 mp_ncpus = 1; 852 853 --mp_naps; /* subtract the BSP */ 854 855 return mustpanic; 856} 857 858 859/* 860 * 2nd pass on motherboard's Intel MP specification table. 861 * 862 * sets: 863 * boot_cpu_id 864 * ID_TO_IO(N), phy APIC ID to log CPU/IO table 865 * CPU_TO_ID(N), logical CPU to APIC ID table 866 * IO_TO_ID(N), logical IO to APIC ID table 867 * bus_data[N] 868 * io_apic_ints[N] 869 */ 870static int 871mptable_pass2(void) 872{ 873 int x; 874 mpcth_t cth; 875 int totalSize; 876 void* position; 877 int count; 878 int type; 879 int apic, bus, cpu, intr; 880 881 POSTCODE(MPTABLE_PASS2_POST); 882 883 /* clear various tables */ 884 for (x = 0; x < NAPICID; ++x) { 885 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */ 886 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */ 887 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */ 888 } 889 890 /* clear bus data table */ 891 for (x = 0; x < NBUS; ++x) 892 bus_data[x].bus_id = 0xff; 893 894 /* clear IO APIC INT table */ 895 for (x = 0; x < NINTR; ++x) { 896 io_apic_ints[x].int_type = 0xff; 897 io_apic_ints[x].int_vector = 0xff; 898 } 899 900 /* setup the cpu/apic mapping arrays */ 901 boot_cpu_id = -1; 902 903 /* record whether PIC or virtual-wire mode */ 904 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0; 905 906 /* check for use of 'default' configuration */ 907 if (MPFPS_MPFB1 != 0) 908 return MPFPS_MPFB1; /* return default configuration type */ 909 910 if ((cth = mpfps->pap) == 0) 911 panic("MP Configuration Table Header MISSING!"); 912 913 /* walk the table, recording info of interest */ 914 totalSize = cth->base_table_length - sizeof(struct MPCTH); 915 position = (u_char *) cth + sizeof(struct MPCTH); 916 count = cth->entry_count; 917 apic = bus = intr = 0; 918 cpu = 1; /* pre-count the BSP */ 919 920 while (count--) { 921 switch (type = *(u_char *) position) { 922 case 0: 923 if (processor_entry(position, cpu)) 924 ++cpu; 925 break; 926 case 1: 927 if (bus_entry(position, bus)) 928 ++bus; 929 break; 930 case 2: 931 if (io_apic_entry(position, apic)) 932 ++apic; 933 break; 934 case 3: 935 if (int_entry(position, intr)) 936 ++intr; 937 break; 938 case 4: 939 /* int_entry(position); */ 940 break; 941 default: 942 panic("mpfps Base Table HOSED!"); 943 /* NOTREACHED */ 944 } 945 946 totalSize -= basetable_entry_types[type].length; 947 (u_char *) position += basetable_entry_types[type].length; 948 } 949 950 if (boot_cpu_id == -1) 951 panic("NO BSP found!"); 952 953 /* report fact that its NOT a default configuration */ 954 return 0; 955} 956 957 958static void 959assign_apic_irq(int apic, int intpin, int irq) 960{ 961 int x; 962 963 if (int_to_apicintpin[irq].ioapic != -1) 964 panic("assign_apic_irq: inconsistent table"); 965 966 int_to_apicintpin[irq].ioapic = apic; 967 int_to_apicintpin[irq].int_pin = intpin; 968 int_to_apicintpin[irq].apic_address = ioapic[apic]; 969 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin; 970 971 for (x = 0; x < nintrs; x++) { 972 if ((io_apic_ints[x].int_type == 0 || 973 io_apic_ints[x].int_type == 3) && 974 io_apic_ints[x].int_vector == 0xff && 975 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) && 976 io_apic_ints[x].dst_apic_int == intpin) 977 io_apic_ints[x].int_vector = irq; 978 } 979} 980 981/* 982 * parse an Intel MP specification table 983 */ 984static void 985fix_mp_table(void) 986{ 987 int x; 988 int id; 989 int bus_0 = 0; /* Stop GCC warning */ 990 int bus_pci = 0; /* Stop GCC warning */ 991 int num_pci_bus; 992 993 /* 994 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS 995 * did it wrong. The MP spec says that when more than 1 PCI bus 996 * exists the BIOS must begin with bus entries for the PCI bus and use 997 * actual PCI bus numbering. This implies that when only 1 PCI bus 998 * exists the BIOS can choose to ignore this ordering, and indeed many 999 * MP motherboards do ignore it. This causes a problem when the PCI 1000 * sub-system makes requests of the MP sub-system based on PCI bus 1001 * numbers. So here we look for the situation and renumber the 1002 * busses and associated INTs in an effort to "make it right". 1003 */ 1004 1005 /* find bus 0, PCI bus, count the number of PCI busses */ 1006 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { 1007 if (bus_data[x].bus_id == 0) { 1008 bus_0 = x; 1009 } 1010 if (bus_data[x].bus_type == PCI) { 1011 ++num_pci_bus; 1012 bus_pci = x; 1013 } 1014 } 1015 /* 1016 * bus_0 == slot of bus with ID of 0 1017 * bus_pci == slot of last PCI bus encountered 1018 */ 1019 1020 /* check the 1 PCI bus case for sanity */ 1021 if (num_pci_bus == 1) { 1022 1023 /* if it is number 0 all is well */ 1024 if (bus_data[bus_pci].bus_id == 0) 1025 return; 1026 1027 /* mis-numbered, swap with whichever bus uses slot 0 */ 1028 1029 /* swap the bus entry types */ 1030 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type; 1031 bus_data[bus_0].bus_type = PCI; 1032 1033 /* swap each relavant INTerrupt entry */ 1034 id = bus_data[bus_pci].bus_id; 1035 for (x = 0; x < nintrs; ++x) { 1036 if (io_apic_ints[x].src_bus_id == id) { 1037 io_apic_ints[x].src_bus_id = 0; 1038 } 1039 else if (io_apic_ints[x].src_bus_id == 0) { 1040 io_apic_ints[x].src_bus_id = id; 1041 } 1042 } 1043 } 1044 /* sanity check if more than 1 PCI bus */ 1045 else if (num_pci_bus > 1) { 1046 for (x = 0; x < mp_nbusses; ++x) { 1047 if (bus_data[x].bus_type != PCI) 1048 continue; 1049 } 1050 } 1051} 1052 1053 1054static void 1055setup_apic_irq_mapping(void) 1056{ 1057 int x; 1058 int int_vector; 1059 1060 /* Assign low level interrupt handlers */ 1061 for (x = 0; x < APIC_INTMAPSIZE; x++) { 1062 int_to_apicintpin[x].ioapic = -1; 1063 int_to_apicintpin[x].int_pin = 0; 1064 int_to_apicintpin[x].apic_address = NULL; 1065 int_to_apicintpin[x].redirindex = 0; 1066 } 1067 for (x = 0; x < nintrs; x++) { 1068 if (io_apic_ints[x].dst_apic_int < APIC_INTMAPSIZE && 1069 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) && 1070 io_apic_ints[x].int_vector == 0xff && 1071 (io_apic_ints[x].int_type == 0 || 1072 io_apic_ints[x].int_type == 3)) { 1073 assign_apic_irq(0, 1074 io_apic_ints[x].dst_apic_int, 1075 io_apic_ints[x].dst_apic_int); 1076 } 1077 } 1078 int_vector = 0; 1079 while (int_vector < APIC_INTMAPSIZE && 1080 int_to_apicintpin[int_vector].ioapic != -1) 1081 int_vector++; 1082 for (x = 0; x < nintrs && int_vector < APIC_INTMAPSIZE; x++) { 1083 if ((io_apic_ints[x].int_type == 0 || 1084 io_apic_ints[x].int_type == 3) && 1085 io_apic_ints[x].int_vector == 0xff) { 1086 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id), 1087 io_apic_ints[x].dst_apic_int, 1088 int_vector); 1089 int_vector++; 1090 while (int_vector < APIC_INTMAPSIZE && 1091 int_to_apicintpin[int_vector].ioapic != -1) 1092 int_vector++; 1093 } 1094 } 1095} 1096 1097 1098static int 1099processor_entry(proc_entry_ptr entry, int cpu) 1100{ 1101 /* check for usability */ 1102 if ((cpu >= NCPU) || !(entry->cpu_flags & PROCENTRY_FLAG_EN)) 1103 return 0; 1104 1105 /* check for BSP flag */ 1106 if (entry->cpu_flags & PROCENTRY_FLAG_BP) { 1107 boot_cpu_id = entry->apic_id; 1108 CPU_TO_ID(0) = entry->apic_id; 1109 ID_TO_CPU(entry->apic_id) = 0; 1110 return 0; /* its already been counted */ 1111 } 1112 1113 /* add another AP to list, if less than max number of CPUs */ 1114 else { 1115 CPU_TO_ID(cpu) = entry->apic_id; 1116 ID_TO_CPU(entry->apic_id) = cpu; 1117 return 1; 1118 } 1119} 1120 1121 1122static int 1123bus_entry(bus_entry_ptr entry, int bus) 1124{ 1125 int x; 1126 char c, name[8]; 1127 1128 /* encode the name into an index */ 1129 for (x = 0; x < 6; ++x) { 1130 if ((c = entry->bus_type[x]) == ' ') 1131 break; 1132 name[x] = c; 1133 } 1134 name[x] = '\0'; 1135 1136 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) 1137 panic("unknown bus type: '%s'", name); 1138 1139 bus_data[bus].bus_id = entry->bus_id; 1140 bus_data[bus].bus_type = x; 1141 1142 return 1; 1143} 1144 1145 1146static int 1147io_apic_entry(io_apic_entry_ptr entry, int apic) 1148{ 1149 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) 1150 return 0; 1151 1152 IO_TO_ID(apic) = entry->apic_id; 1153 ID_TO_IO(entry->apic_id) = apic; 1154 1155 return 1; 1156} 1157 1158 1159static int 1160lookup_bus_type(char *name) 1161{ 1162 int x; 1163 1164 for (x = 0; x < MAX_BUSTYPE; ++x) 1165 if (strcmp(bus_type_table[x].name, name) == 0) 1166 return bus_type_table[x].type; 1167 1168 return UNKNOWN_BUSTYPE; 1169} 1170 1171 1172static int 1173int_entry(int_entry_ptr entry, int intr) 1174{ 1175 int apic; 1176 1177 io_apic_ints[intr].int_type = entry->int_type; 1178 io_apic_ints[intr].int_flags = entry->int_flags; 1179 io_apic_ints[intr].src_bus_id = entry->src_bus_id; 1180 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq; 1181 if (entry->dst_apic_id == 255) { 1182 /* This signal goes to all IO APICS. Select an IO APIC 1183 with sufficient number of interrupt pins */ 1184 for (apic = 0; apic < mp_napics; apic++) 1185 if (((io_apic_read(apic, IOAPIC_VER) & 1186 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >= 1187 entry->dst_apic_int) 1188 break; 1189 if (apic < mp_napics) 1190 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic); 1191 else 1192 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; 1193 } else 1194 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; 1195 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int; 1196 1197 return 1; 1198} 1199 1200 1201static int 1202apic_int_is_bus_type(int intr, int bus_type) 1203{ 1204 int bus; 1205 1206 for (bus = 0; bus < mp_nbusses; ++bus) 1207 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) 1208 && ((int) bus_data[bus].bus_type == bus_type)) 1209 return 1; 1210 1211 return 0; 1212} 1213 1214 1215/* 1216 * Given a traditional ISA INT mask, return an APIC mask. 1217 */ 1218u_int 1219isa_apic_mask(u_int isa_mask) 1220{ 1221 int isa_irq; 1222 int apic_pin; 1223 1224#if defined(SKIP_IRQ15_REDIRECT) 1225 if (isa_mask == (1 << 15)) { 1226 printf("skipping ISA IRQ15 redirect\n"); 1227 return isa_mask; 1228 } 1229#endif /* SKIP_IRQ15_REDIRECT */ 1230 1231 isa_irq = ffs(isa_mask); /* find its bit position */ 1232 if (isa_irq == 0) /* doesn't exist */ 1233 return 0; 1234 --isa_irq; /* make it zero based */ 1235 1236 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */ 1237 if (apic_pin == -1) 1238 return 0; 1239 1240 return (1 << apic_pin); /* convert pin# to a mask */ 1241} 1242 1243 1244/* 1245 * Determine which APIC pin an ISA/EISA INT is attached to. 1246 */ 1247#define INTTYPE(I) (io_apic_ints[(I)].int_type) 1248#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) 1249#define INTIRQ(I) (io_apic_ints[(I)].int_vector) 1250#define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id)) 1251 1252#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) 1253int 1254isa_apic_irq(int isa_irq) 1255{ 1256 int intr; 1257 1258 for (intr = 0; intr < nintrs; ++intr) { /* check each record */ 1259 if (INTTYPE(intr) == 0) { /* standard INT */ 1260 if (SRCBUSIRQ(intr) == isa_irq) { 1261 if (apic_int_is_bus_type(intr, ISA) || 1262 apic_int_is_bus_type(intr, EISA)) 1263 return INTIRQ(intr); /* found */ 1264 } 1265 } 1266 } 1267 return -1; /* NOT found */ 1268} 1269 1270 1271/* 1272 * Determine which APIC pin a PCI INT is attached to. 1273 */ 1274#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) 1275#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) 1276#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) 1277int 1278pci_apic_irq(int pciBus, int pciDevice, int pciInt) 1279{ 1280 int intr; 1281 1282 --pciInt; /* zero based */ 1283 1284 for (intr = 0; intr < nintrs; ++intr) /* check each record */ 1285 if ((INTTYPE(intr) == 0) /* standard INT */ 1286 && (SRCBUSID(intr) == pciBus) 1287 && (SRCBUSDEVICE(intr) == pciDevice) 1288 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ 1289 if (apic_int_is_bus_type(intr, PCI)) 1290 return INTIRQ(intr); /* exact match */ 1291 1292 return -1; /* NOT found */ 1293} 1294 1295int 1296next_apic_irq(int irq) 1297{ 1298 int intr, ointr; 1299 int bus, bustype; 1300 1301 bus = 0; 1302 bustype = 0; 1303 for (intr = 0; intr < nintrs; intr++) { 1304 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0) 1305 continue; 1306 bus = SRCBUSID(intr); 1307 bustype = apic_bus_type(bus); 1308 if (bustype != ISA && 1309 bustype != EISA && 1310 bustype != PCI) 1311 continue; 1312 break; 1313 } 1314 if (intr >= nintrs) { 1315 return -1; 1316 } 1317 for (ointr = intr + 1; ointr < nintrs; ointr++) { 1318 if (INTTYPE(ointr) != 0) 1319 continue; 1320 if (bus != SRCBUSID(ointr)) 1321 continue; 1322 if (bustype == PCI) { 1323 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr)) 1324 continue; 1325 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr)) 1326 continue; 1327 } 1328 if (bustype == ISA || bustype == EISA) { 1329 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr)) 1330 continue; 1331 } 1332 if (INTPIN(intr) == INTPIN(ointr)) 1333 continue; 1334 break; 1335 } 1336 if (ointr >= nintrs) { 1337 return -1; 1338 } 1339 return INTIRQ(ointr); 1340} 1341#undef SRCBUSLINE 1342#undef SRCBUSDEVICE 1343#undef SRCBUSID 1344#undef SRCBUSIRQ 1345 1346#undef INTPIN 1347#undef INTIRQ 1348#undef INTAPIC 1349#undef INTTYPE 1350 1351 1352/* 1353 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt. 1354 * 1355 * XXX FIXME: 1356 * Exactly what this means is unclear at this point. It is a solution 1357 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard 1358 * could route any of the ISA INTs to upper (>15) IRQ values. But most would 1359 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an 1360 * option. 1361 */ 1362int 1363undirect_isa_irq(int rirq) 1364{ 1365#if defined(READY) 1366 if (bootverbose) 1367 printf("Freeing redirected ISA irq %d.\n", rirq); 1368 /** FIXME: tickle the MB redirector chip */ 1369 return ???; 1370#else 1371 if (bootverbose) 1372 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq); 1373 return 0; 1374#endif /* READY */ 1375} 1376 1377 1378/* 1379 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt 1380 */ 1381int 1382undirect_pci_irq(int rirq) 1383{ 1384#if defined(READY) 1385 if (bootverbose) 1386 printf("Freeing redirected PCI irq %d.\n", rirq); 1387 1388 /** FIXME: tickle the MB redirector chip */ 1389 return ???; 1390#else 1391 if (bootverbose) 1392 printf("Freeing (NOT implemented) redirected PCI irq %d.\n", 1393 rirq); 1394 return 0; 1395#endif /* READY */ 1396} 1397 1398 1399/* 1400 * given a bus ID, return: 1401 * the bus type if found 1402 * -1 if NOT found 1403 */ 1404int 1405apic_bus_type(int id) 1406{ 1407 int x; 1408 1409 for (x = 0; x < mp_nbusses; ++x) 1410 if (bus_data[x].bus_id == id) 1411 return bus_data[x].bus_type; 1412 1413 return -1; 1414} 1415 1416 1417/* 1418 * given a LOGICAL APIC# and pin#, return: 1419 * the associated src bus ID if found 1420 * -1 if NOT found 1421 */ 1422int 1423apic_src_bus_id(int apic, int pin) 1424{ 1425 int x; 1426 1427 /* search each of the possible INTerrupt sources */ 1428 for (x = 0; x < nintrs; ++x) 1429 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1430 (pin == io_apic_ints[x].dst_apic_int)) 1431 return (io_apic_ints[x].src_bus_id); 1432 1433 return -1; /* NOT found */ 1434} 1435 1436 1437/* 1438 * given a LOGICAL APIC# and pin#, return: 1439 * the associated src bus IRQ if found 1440 * -1 if NOT found 1441 */ 1442int 1443apic_src_bus_irq(int apic, int pin) 1444{ 1445 int x; 1446 1447 for (x = 0; x < nintrs; x++) 1448 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1449 (pin == io_apic_ints[x].dst_apic_int)) 1450 return (io_apic_ints[x].src_bus_irq); 1451 1452 return -1; /* NOT found */ 1453} 1454 1455 1456/* 1457 * given a LOGICAL APIC# and pin#, return: 1458 * the associated INTerrupt type if found 1459 * -1 if NOT found 1460 */ 1461int 1462apic_int_type(int apic, int pin) 1463{ 1464 int x; 1465 1466 /* search each of the possible INTerrupt sources */ 1467 for (x = 0; x < nintrs; ++x) 1468 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1469 (pin == io_apic_ints[x].dst_apic_int)) 1470 return (io_apic_ints[x].int_type); 1471 1472 return -1; /* NOT found */ 1473} 1474 1475int 1476apic_irq(int apic, int pin) 1477{ 1478 int x; 1479 int res; 1480 1481 for (x = 0; x < nintrs; ++x) 1482 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1483 (pin == io_apic_ints[x].dst_apic_int)) { 1484 res = io_apic_ints[x].int_vector; 1485 if (res == 0xff) 1486 return -1; 1487 if (apic != int_to_apicintpin[res].ioapic) 1488 panic("apic_irq: inconsistent table"); 1489 if (pin != int_to_apicintpin[res].int_pin) 1490 panic("apic_irq inconsistent table (2)"); 1491 return res; 1492 } 1493 return -1; 1494} 1495 1496 1497/* 1498 * given a LOGICAL APIC# and pin#, return: 1499 * the associated trigger mode if found 1500 * -1 if NOT found 1501 */ 1502int 1503apic_trigger(int apic, int pin) 1504{ 1505 int x; 1506 1507 /* search each of the possible INTerrupt sources */ 1508 for (x = 0; x < nintrs; ++x) 1509 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1510 (pin == io_apic_ints[x].dst_apic_int)) 1511 return ((io_apic_ints[x].int_flags >> 2) & 0x03); 1512 1513 return -1; /* NOT found */ 1514} 1515 1516 1517/* 1518 * given a LOGICAL APIC# and pin#, return: 1519 * the associated 'active' level if found 1520 * -1 if NOT found 1521 */ 1522int 1523apic_polarity(int apic, int pin) 1524{ 1525 int x; 1526 1527 /* search each of the possible INTerrupt sources */ 1528 for (x = 0; x < nintrs; ++x) 1529 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1530 (pin == io_apic_ints[x].dst_apic_int)) 1531 return (io_apic_ints[x].int_flags & 0x03); 1532 1533 return -1; /* NOT found */ 1534} 1535 1536 1537/* 1538 * set data according to MP defaults 1539 * FIXME: probably not complete yet... 1540 */ 1541static void 1542default_mp_table(int type) 1543{ 1544 int ap_cpu_id; 1545#if defined(APIC_IO) 1546 u_int32_t ux; 1547 int io_apic_id; 1548 int pin; 1549#endif /* APIC_IO */ 1550 1551#if 0 1552 printf(" MP default config type: %d\n", type); 1553 switch (type) { 1554 case 1: 1555 printf(" bus: ISA, APIC: 82489DX\n"); 1556 break; 1557 case 2: 1558 printf(" bus: EISA, APIC: 82489DX\n"); 1559 break; 1560 case 3: 1561 printf(" bus: EISA, APIC: 82489DX\n"); 1562 break; 1563 case 4: 1564 printf(" bus: MCA, APIC: 82489DX\n"); 1565 break; 1566 case 5: 1567 printf(" bus: ISA+PCI, APIC: Integrated\n"); 1568 break; 1569 case 6: 1570 printf(" bus: EISA+PCI, APIC: Integrated\n"); 1571 break; 1572 case 7: 1573 printf(" bus: MCA+PCI, APIC: Integrated\n"); 1574 break; 1575 default: 1576 printf(" future type\n"); 1577 break; 1578 /* NOTREACHED */ 1579 } 1580#endif /* 0 */ 1581 1582 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24; 1583 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; 1584 1585 /* BSP */ 1586 CPU_TO_ID(0) = boot_cpu_id; 1587 ID_TO_CPU(boot_cpu_id) = 0; 1588 1589 /* one and only AP */ 1590 CPU_TO_ID(1) = ap_cpu_id; 1591 ID_TO_CPU(ap_cpu_id) = 1; 1592 1593#if defined(APIC_IO) 1594 /* one and only IO APIC */ 1595 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; 1596 1597 /* 1598 * sanity check, refer to MP spec section 3.6.6, last paragraph 1599 * necessary as some hardware isn't properly setting up the IO APIC 1600 */ 1601#if defined(REALLY_ANAL_IOAPICID_VALUE) 1602 if (io_apic_id != 2) { 1603#else 1604 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { 1605#endif /* REALLY_ANAL_IOAPICID_VALUE */ 1606 ux = io_apic_read(0, IOAPIC_ID); /* get current contents */ 1607 ux &= ~APIC_ID_MASK; /* clear the ID field */ 1608 ux |= 0x02000000; /* set it to '2' */ 1609 io_apic_write(0, IOAPIC_ID, ux); /* write new value */ 1610 ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */ 1611 if ((ux & APIC_ID_MASK) != 0x02000000) 1612 panic("can't control IO APIC ID, reg: 0x%08x", ux); 1613 io_apic_id = 2; 1614 } 1615 IO_TO_ID(0) = io_apic_id; 1616 ID_TO_IO(io_apic_id) = 0; 1617#endif /* APIC_IO */ 1618 1619 /* fill out bus entries */ 1620 switch (type) { 1621 case 1: 1622 case 2: 1623 case 3: 1624 case 5: 1625 case 6: 1626 bus_data[0].bus_id = default_data[type - 1][1]; 1627 bus_data[0].bus_type = default_data[type - 1][2]; 1628 bus_data[1].bus_id = default_data[type - 1][3]; 1629 bus_data[1].bus_type = default_data[type - 1][4]; 1630 break; 1631 1632 /* case 4: case 7: MCA NOT supported */ 1633 default: /* illegal/reserved */ 1634 panic("BAD default MP config: %d", type); 1635 /* NOTREACHED */ 1636 } 1637 1638#if defined(APIC_IO) 1639 /* general cases from MP v1.4, table 5-2 */ 1640 for (pin = 0; pin < 16; ++pin) { 1641 io_apic_ints[pin].int_type = 0; 1642 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */ 1643 io_apic_ints[pin].src_bus_id = 0; 1644 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */ 1645 io_apic_ints[pin].dst_apic_id = io_apic_id; 1646 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */ 1647 } 1648 1649 /* special cases from MP v1.4, table 5-2 */ 1650 if (type == 2) { 1651 io_apic_ints[2].int_type = 0xff; /* N/C */ 1652 io_apic_ints[13].int_type = 0xff; /* N/C */ 1653#if !defined(APIC_MIXED_MODE) 1654 /** FIXME: ??? */ 1655 panic("sorry, can't support type 2 default yet"); 1656#endif /* APIC_MIXED_MODE */ 1657 } 1658 else 1659 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ 1660 1661 if (type == 7) 1662 io_apic_ints[0].int_type = 0xff; /* N/C */ 1663 else 1664 io_apic_ints[0].int_type = 3; /* vectored 8259 */ 1665#endif /* APIC_IO */ 1666} 1667 1668 1669/* 1670 * initialize all the SMP locks 1671 */ 1672 1673/* critical region around IO APIC, apic_imen */ 1674struct simplelock imen_lock; 1675 1676/* critical region around splxx(), cpl, cml, cil, ipending */ 1677struct simplelock cpl_lock; 1678 1679/* Make FAST_INTR() routines sequential */ 1680struct simplelock fast_intr_lock; 1681 1682/* critical region around INTR() routines */ 1683struct simplelock intr_lock; 1684 1685/* lock regions protected in UP kernel via cli/sti */ 1686struct simplelock mpintr_lock; 1687 1688/* lock region used by kernel profiling */ 1689struct simplelock mcount_lock; 1690 1691#ifdef USE_COMLOCK 1692/* locks com (tty) data/hardware accesses: a FASTINTR() */ 1693struct simplelock com_lock; 1694#endif /* USE_COMLOCK */ 1695 1696#ifdef USE_CLOCKLOCK 1697/* lock regions around the clock hardware */ 1698struct simplelock clock_lock; 1699#endif /* USE_CLOCKLOCK */ 1700 1701static void 1702init_locks(void) 1703{ 1704 /* 1705 * Get the initial mp_lock with a count of 1 for the BSP. 1706 * This uses a LOGICAL cpu ID, ie BSP == 0. 1707 */ 1708 mp_lock = 0x00000001; 1709 1710 /* ISR uses its own "giant lock" */ 1711 isr_lock = FREE_LOCK; 1712 1713#if defined(APIC_INTR_DIAGNOSTIC) && defined(APIC_INTR_DIAGNOSTIC_IRQ) 1714 s_lock_init((struct simplelock*)&apic_itrace_debuglock); 1715#endif 1716 1717 s_lock_init((struct simplelock*)&mpintr_lock); 1718 1719 s_lock_init((struct simplelock*)&mcount_lock); 1720 1721 s_lock_init((struct simplelock*)&fast_intr_lock); 1722 s_lock_init((struct simplelock*)&intr_lock); 1723 s_lock_init((struct simplelock*)&imen_lock); 1724 s_lock_init((struct simplelock*)&cpl_lock); 1725 1726#ifdef USE_COMLOCK 1727 s_lock_init((struct simplelock*)&com_lock); 1728#endif /* USE_COMLOCK */ 1729#ifdef USE_CLOCKLOCK 1730 s_lock_init((struct simplelock*)&clock_lock); 1731#endif /* USE_CLOCKLOCK */ 1732} 1733 1734 1735/* Wait for all APs to be fully initialized */ 1736extern int wait_ap(unsigned int); 1737 1738/* 1739 * start each AP in our list 1740 */ 1741static int 1742start_all_aps(u_int boot_addr) 1743{ 1744 int x, i, pg; 1745 u_char mpbiosreason; 1746 u_long mpbioswarmvec; 1747 struct globaldata *gd; 1748 char *stack; 1749 1750 POSTCODE(START_ALL_APS_POST); 1751 1752 /* initialize BSP's local APIC */ 1753 apic_initialize(); 1754 bsp_apic_ready = 1; 1755 1756 /* install the AP 1st level boot code */ 1757 install_ap_tramp(boot_addr); 1758 1759 1760 /* save the current value of the warm-start vector */ 1761 mpbioswarmvec = *((u_long *) WARMBOOT_OFF); 1762#ifndef PC98 1763 outb(CMOS_REG, BIOS_RESET); 1764 mpbiosreason = inb(CMOS_DATA); 1765#endif 1766 1767 /* record BSP in CPU map */ 1768 all_cpus = 1; 1769 1770 /* set up 0 -> 4MB P==V mapping for AP boot */ 1771 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME); 1772 invltlb(); 1773 1774 /* start each AP */ 1775 for (x = 1; x <= mp_naps; ++x) { 1776 1777 /* This is a bit verbose, it will go away soon. */ 1778 1779 /* first page of AP's private space */ 1780 pg = x * i386_btop(sizeof(struct privatespace)); 1781 1782 /* allocate a new private data page */ 1783 gd = (struct globaldata *)kmem_alloc(kernel_map, PAGE_SIZE); 1784 1785 /* wire it into the private page table page */ 1786 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys(gd)); 1787 1788 /* allocate and set up an idle stack data page */ 1789 stack = (char *)kmem_alloc(kernel_map, UPAGES*PAGE_SIZE); 1790 for (i = 0; i < UPAGES; i++) 1791 SMPpt[pg + 5 + i] = (pt_entry_t) 1792 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 1793 1794 SMPpt[pg + 1] = 0; /* *prv_CMAP1 */ 1795 SMPpt[pg + 2] = 0; /* *prv_CMAP2 */ 1796 SMPpt[pg + 3] = 0; /* *prv_CMAP3 */ 1797 SMPpt[pg + 4] = 0; /* *prv_PMAP1 */ 1798 1799 /* prime data page for it to use */ 1800 gd->gd_cpuid = x; 1801 gd->gd_cpu_lockid = x << 24; 1802 gd->gd_prv_CMAP1 = &SMPpt[pg + 1]; 1803 gd->gd_prv_CMAP2 = &SMPpt[pg + 2]; 1804 gd->gd_prv_CMAP3 = &SMPpt[pg + 3]; 1805 gd->gd_prv_PMAP1 = &SMPpt[pg + 4]; 1806 gd->gd_prv_CADDR1 = SMP_prvspace[x].CPAGE1; 1807 gd->gd_prv_CADDR2 = SMP_prvspace[x].CPAGE2; 1808 gd->gd_prv_CADDR3 = SMP_prvspace[x].CPAGE3; 1809 gd->gd_prv_PADDR1 = (unsigned *)SMP_prvspace[x].PPAGE1; 1810 1811 /* setup a vector to our boot code */ 1812 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 1813 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); 1814#ifndef PC98 1815 outb(CMOS_REG, BIOS_RESET); 1816 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 1817#endif 1818 1819 bootSTK = &SMP_prvspace[x].idlestack[UPAGES*PAGE_SIZE]; 1820 bootAP = x; 1821 1822 /* attempt to start the Application Processor */ 1823 CHECK_INIT(99); /* setup checkpoints */ 1824 if (!start_ap(x, boot_addr)) { 1825 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); 1826 CHECK_PRINT("trace"); /* show checkpoints */ 1827 /* better panic as the AP may be running loose */ 1828 printf("panic y/n? [y] "); 1829 if (cngetc() != 'n') 1830 panic("bye-bye"); 1831 } 1832 CHECK_PRINT("trace"); /* show checkpoints */ 1833 1834 /* record its version info */ 1835 cpu_apic_versions[x] = cpu_apic_versions[0]; 1836 1837 all_cpus |= (1 << x); /* record AP in CPU map */ 1838 } 1839 1840 /* build our map of 'other' CPUs */ 1841 other_cpus = all_cpus & ~(1 << cpuid); 1842 1843 /* fill in our (BSP) APIC version */ 1844 cpu_apic_versions[0] = lapic.version; 1845 1846 /* restore the warmstart vector */ 1847 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 1848#ifndef PC98 1849 outb(CMOS_REG, BIOS_RESET); 1850 outb(CMOS_DATA, mpbiosreason); 1851#endif 1852 1853 /* 1854 * Set up the idle context for the BSP. Similar to above except 1855 * that some was done by locore, some by pmap.c and some is implicit 1856 * because the BSP is cpu#0 and the page is initially zero, and also 1857 * because we can refer to variables by name on the BSP.. 1858 */ 1859 1860 /* Allocate and setup BSP idle stack */ 1861 stack = (char *)kmem_alloc(kernel_map, UPAGES * PAGE_SIZE); 1862 for (i = 0; i < UPAGES; i++) 1863 SMPpt[5 + i] = (pt_entry_t) 1864 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 1865 1866 *(int *)PTD = 0; 1867 pmap_set_opt(); 1868 1869 /* number of APs actually started */ 1870 return mp_ncpus - 1; 1871} 1872 1873 1874/* 1875 * load the 1st level AP boot code into base memory. 1876 */ 1877 1878/* targets for relocation */ 1879extern void bigJump(void); 1880extern void bootCodeSeg(void); 1881extern void bootDataSeg(void); 1882extern void MPentry(void); 1883extern u_int MP_GDT; 1884extern u_int mp_gdtbase; 1885 1886static void 1887install_ap_tramp(u_int boot_addr) 1888{ 1889 int x; 1890 int size = *(int *) ((u_long) & bootMP_size); 1891 u_char *src = (u_char *) ((u_long) bootMP); 1892 u_char *dst = (u_char *) boot_addr + KERNBASE; 1893 u_int boot_base = (u_int) bootMP; 1894 u_int8_t *dst8; 1895 u_int16_t *dst16; 1896 u_int32_t *dst32; 1897 1898 POSTCODE(INSTALL_AP_TRAMP_POST); 1899 1900 for (x = 0; x < size; ++x) 1901 *dst++ = *src++; 1902 1903 /* 1904 * modify addresses in code we just moved to basemem. unfortunately we 1905 * need fairly detailed info about mpboot.s for this to work. changes 1906 * to mpboot.s might require changes here. 1907 */ 1908 1909 /* boot code is located in KERNEL space */ 1910 dst = (u_char *) boot_addr + KERNBASE; 1911 1912 /* modify the lgdt arg */ 1913 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 1914 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); 1915 1916 /* modify the ljmp target for MPentry() */ 1917 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 1918 *dst32 = ((u_int) MPentry - KERNBASE); 1919 1920 /* modify the target for boot code segment */ 1921 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 1922 dst8 = (u_int8_t *) (dst16 + 1); 1923 *dst16 = (u_int) boot_addr & 0xffff; 1924 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1925 1926 /* modify the target for boot data segment */ 1927 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 1928 dst8 = (u_int8_t *) (dst16 + 1); 1929 *dst16 = (u_int) boot_addr & 0xffff; 1930 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1931} 1932 1933 1934/* 1935 * this function starts the AP (application processor) identified 1936 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 1937 * to accomplish this. This is necessary because of the nuances 1938 * of the different hardware we might encounter. It ain't pretty, 1939 * but it seems to work. 1940 */ 1941static int 1942start_ap(int logical_cpu, u_int boot_addr) 1943{ 1944 int physical_cpu; 1945 int vector; 1946 int cpus; 1947 u_long icr_lo, icr_hi; 1948 1949 POSTCODE(START_AP_POST); 1950 1951 /* get the PHYSICAL APIC ID# */ 1952 physical_cpu = CPU_TO_ID(logical_cpu); 1953 1954 /* calculate the vector */ 1955 vector = (boot_addr >> 12) & 0xff; 1956 1957 /* used as a watchpoint to signal AP startup */ 1958 cpus = mp_ncpus; 1959 1960 /* 1961 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 1962 * and running the target CPU. OR this INIT IPI might be latched (P5 1963 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 1964 * ignored. 1965 */ 1966 1967 /* setup the address for the target AP */ 1968 icr_hi = lapic.icr_hi & ~APIC_ID_MASK; 1969 icr_hi |= (physical_cpu << 24); 1970 lapic.icr_hi = icr_hi; 1971 1972 /* do an INIT IPI: assert RESET */ 1973 icr_lo = lapic.icr_lo & 0xfff00000; 1974 lapic.icr_lo = icr_lo | 0x0000c500; 1975 1976 /* wait for pending status end */ 1977 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1978 /* spin */ ; 1979 1980 /* do an INIT IPI: deassert RESET */ 1981 lapic.icr_lo = icr_lo | 0x00008500; 1982 1983 /* wait for pending status end */ 1984 u_sleep(10000); /* wait ~10mS */ 1985 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1986 /* spin */ ; 1987 1988 /* 1989 * next we do a STARTUP IPI: the previous INIT IPI might still be 1990 * latched, (P5 bug) this 1st STARTUP would then terminate 1991 * immediately, and the previously started INIT IPI would continue. OR 1992 * the previous INIT IPI has already run. and this STARTUP IPI will 1993 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 1994 * will run. 1995 */ 1996 1997 /* do a STARTUP IPI */ 1998 lapic.icr_lo = icr_lo | 0x00000600 | vector; 1999 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2000 /* spin */ ; 2001 u_sleep(200); /* wait ~200uS */ 2002 2003 /* 2004 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 2005 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 2006 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 2007 * recognized after hardware RESET or INIT IPI. 2008 */ 2009 2010 lapic.icr_lo = icr_lo | 0x00000600 | vector; 2011 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2012 /* spin */ ; 2013 u_sleep(200); /* wait ~200uS */ 2014 2015 /* wait for it to start */ 2016 set_apic_timer(5000000);/* == 5 seconds */ 2017 while (read_apic_timer()) 2018 if (mp_ncpus > cpus) 2019 return 1; /* return SUCCESS */ 2020 2021 return 0; /* return FAILURE */ 2022} 2023 2024 2025/* 2026 * Flush the TLB on all other CPU's 2027 * 2028 * XXX: Needs to handshake and wait for completion before proceding. 2029 */ 2030void 2031smp_invltlb(void) 2032{ 2033#if defined(APIC_IO) 2034 if (smp_started && invltlb_ok) 2035 all_but_self_ipi(XINVLTLB_OFFSET); 2036#endif /* APIC_IO */ 2037} 2038 2039void 2040invlpg(u_int addr) 2041{ 2042 __asm __volatile("invlpg (%0)"::"r"(addr):"memory"); 2043 2044 /* send a message to the other CPUs */ 2045 smp_invltlb(); 2046} 2047 2048void 2049invltlb(void) 2050{ 2051 u_long temp; 2052 2053 /* 2054 * This should be implemented as load_cr3(rcr3()) when load_cr3() is 2055 * inlined. 2056 */ 2057 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory"); 2058 2059 /* send a message to the other CPUs */ 2060 smp_invltlb(); 2061} 2062 2063 2064/* 2065 * When called the executing CPU will send an IPI to all other CPUs 2066 * requesting that they halt execution. 2067 * 2068 * Usually (but not necessarily) called with 'other_cpus' as its arg. 2069 * 2070 * - Signals all CPUs in map to stop. 2071 * - Waits for each to stop. 2072 * 2073 * Returns: 2074 * -1: error 2075 * 0: NA 2076 * 1: ok 2077 * 2078 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs 2079 * from executing at same time. 2080 */ 2081int 2082stop_cpus(u_int map) 2083{ 2084 if (!smp_started) 2085 return 0; 2086 2087 /* send the Xcpustop IPI to all CPUs in map */ 2088 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED); 2089 2090 while ((stopped_cpus & map) != map) 2091 /* spin */ ; 2092 2093 return 1; 2094} 2095 2096 2097/* 2098 * Called by a CPU to restart stopped CPUs. 2099 * 2100 * Usually (but not necessarily) called with 'stopped_cpus' as its arg. 2101 * 2102 * - Signals all CPUs in map to restart. 2103 * - Waits for each to restart. 2104 * 2105 * Returns: 2106 * -1: error 2107 * 0: NA 2108 * 1: ok 2109 */ 2110int 2111restart_cpus(u_int map) 2112{ 2113 if (!smp_started) 2114 return 0; 2115 2116 started_cpus = map; /* signal other cpus to restart */ 2117 2118 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */ 2119 /* spin */ ; 2120 2121 return 1; 2122} 2123 2124int smp_active = 0; /* are the APs allowed to run? */ 2125SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RW, &smp_active, 0, ""); 2126 2127/* XXX maybe should be hw.ncpu */ 2128static int smp_cpus = 1; /* how many cpu's running */ 2129SYSCTL_INT(_machdep, OID_AUTO, smp_cpus, CTLFLAG_RD, &smp_cpus, 0, ""); 2130 2131int invltlb_ok = 0; /* throttle smp_invltlb() till safe */ 2132SYSCTL_INT(_machdep, OID_AUTO, invltlb_ok, CTLFLAG_RW, &invltlb_ok, 0, ""); 2133 2134/* Warning: Do not staticize. Used from swtch.s */ 2135int do_page_zero_idle = 1; /* bzero pages for fun and profit in idleloop */ 2136SYSCTL_INT(_machdep, OID_AUTO, do_page_zero_idle, CTLFLAG_RW, 2137 &do_page_zero_idle, 0, ""); 2138 2139/* Is forwarding of a interrupt to the CPU holding the ISR lock enabled ? */ 2140int forward_irq_enabled = 1; 2141SYSCTL_INT(_machdep, OID_AUTO, forward_irq_enabled, CTLFLAG_RW, 2142 &forward_irq_enabled, 0, ""); 2143 2144/* Enable forwarding of a signal to a process running on a different CPU */ 2145static int forward_signal_enabled = 1; 2146SYSCTL_INT(_machdep, OID_AUTO, forward_signal_enabled, CTLFLAG_RW, 2147 &forward_signal_enabled, 0, ""); 2148 2149/* Enable forwarding of roundrobin to all other cpus */ 2150static int forward_roundrobin_enabled = 1; 2151SYSCTL_INT(_machdep, OID_AUTO, forward_roundrobin_enabled, CTLFLAG_RW, 2152 &forward_roundrobin_enabled, 0, ""); 2153 2154/* 2155 * This is called once the rest of the system is up and running and we're 2156 * ready to let the AP's out of the pen. 2157 */ 2158void ap_init(void); 2159 2160void 2161ap_init() 2162{ 2163 u_int apic_id; 2164 2165 /* BSP may have changed PTD while we're waiting for the lock */ 2166 cpu_invltlb(); 2167 2168 smp_cpus++; 2169 2170#if defined(I586_CPU) && !defined(NO_F00F_HACK) 2171 lidt(&r_idt); 2172#endif 2173 2174 /* Build our map of 'other' CPUs. */ 2175 other_cpus = all_cpus & ~(1 << cpuid); 2176 2177 printf("SMP: AP CPU #%d Launched!\n", cpuid); 2178 2179 /* XXX FIXME: i386 specific, and redundant: Setup the FPU. */ 2180 load_cr0((rcr0() & ~CR0_EM) | CR0_MP | CR0_NE | CR0_TS); 2181 2182 /* A quick check from sanity claus */ 2183 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]); 2184 if (cpuid != apic_id) { 2185 printf("SMP: cpuid = %d\n", cpuid); 2186 printf("SMP: apic_id = %d\n", apic_id); 2187 printf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]); 2188 panic("cpuid mismatch! boom!!"); 2189 } 2190 2191 /* Init local apic for irq's */ 2192 apic_initialize(); 2193 2194 /* Set memory range attributes for this CPU to match the BSP */ 2195 mem_range_AP_init(); 2196 2197 /* 2198 * Activate smp_invltlb, although strictly speaking, this isn't 2199 * quite correct yet. We should have a bitfield for cpus willing 2200 * to accept TLB flush IPI's or something and sync them. 2201 */ 2202 if (smp_cpus == mp_ncpus) { 2203 invltlb_ok = 1; 2204 smp_started = 1; /* enable IPI's, tlb shootdown, freezes etc */ 2205 smp_active = 1; /* historic */ 2206 } 2207} 2208 2209#ifdef BETTER_CLOCK 2210 2211#define CHECKSTATE_USER 0 2212#define CHECKSTATE_SYS 1 2213#define CHECKSTATE_INTR 2 2214 2215/* Do not staticize. Used from apic_vector.s */ 2216struct proc* checkstate_curproc[NCPU]; 2217int checkstate_cpustate[NCPU]; 2218u_long checkstate_pc[NCPU]; 2219 2220extern long cp_time[CPUSTATES]; 2221 2222#define PC_TO_INDEX(pc, prof) \ 2223 ((int)(((u_quad_t)((pc) - (prof)->pr_off) * \ 2224 (u_quad_t)((prof)->pr_scale)) >> 16) & ~1) 2225 2226static void 2227addupc_intr_forwarded(struct proc *p, int id, int *astmap) 2228{ 2229 int i; 2230 struct uprof *prof; 2231 u_long pc; 2232 2233 pc = checkstate_pc[id]; 2234 prof = &p->p_stats->p_prof; 2235 if (pc >= prof->pr_off && 2236 (i = PC_TO_INDEX(pc, prof)) < prof->pr_size) { 2237 if ((p->p_flag & P_OWEUPC) == 0) { 2238 prof->pr_addr = pc; 2239 prof->pr_ticks = 1; 2240 p->p_flag |= P_OWEUPC; 2241 } 2242 *astmap |= (1 << id); 2243 } 2244} 2245 2246static void 2247forwarded_statclock(int id, int pscnt, int *astmap) 2248{ 2249 struct pstats *pstats; 2250 long rss; 2251 struct rusage *ru; 2252 struct vmspace *vm; 2253 int cpustate; 2254 struct proc *p; 2255#ifdef GPROF 2256 register struct gmonparam *g; 2257 int i; 2258#endif 2259 2260 p = checkstate_curproc[id]; 2261 cpustate = checkstate_cpustate[id]; 2262 2263 switch (cpustate) { 2264 case CHECKSTATE_USER: 2265 if (p->p_flag & P_PROFIL) 2266 addupc_intr_forwarded(p, id, astmap); 2267 if (pscnt > 1) 2268 return; 2269 p->p_uticks++; 2270 if (p->p_nice > NZERO) 2271 cp_time[CP_NICE]++; 2272 else 2273 cp_time[CP_USER]++; 2274 break; 2275 case CHECKSTATE_SYS: 2276#ifdef GPROF 2277 /* 2278 * Kernel statistics are just like addupc_intr, only easier. 2279 */ 2280 g = &_gmonparam; 2281 if (g->state == GMON_PROF_ON) { 2282 i = checkstate_pc[id] - g->lowpc; 2283 if (i < g->textsize) { 2284 i /= HISTFRACTION * sizeof(*g->kcount); 2285 g->kcount[i]++; 2286 } 2287 } 2288#endif 2289 if (pscnt > 1) 2290 return; 2291 2292 if (!p) 2293 cp_time[CP_IDLE]++; 2294 else { 2295 p->p_sticks++; 2296 cp_time[CP_SYS]++; 2297 } 2298 break; 2299 case CHECKSTATE_INTR: 2300 default: 2301#ifdef GPROF 2302 /* 2303 * Kernel statistics are just like addupc_intr, only easier. 2304 */ 2305 g = &_gmonparam; 2306 if (g->state == GMON_PROF_ON) { 2307 i = checkstate_pc[id] - g->lowpc; 2308 if (i < g->textsize) { 2309 i /= HISTFRACTION * sizeof(*g->kcount); 2310 g->kcount[i]++; 2311 } 2312 } 2313#endif 2314 if (pscnt > 1) 2315 return; 2316 if (p) 2317 p->p_iticks++; 2318 cp_time[CP_INTR]++; 2319 } 2320 if (p != NULL) { 2321 p->p_cpticks++; 2322 if (++p->p_estcpu == 0) 2323 p->p_estcpu--; 2324 if ((p->p_estcpu & 3) == 0) { 2325 resetpriority(p); 2326 if (p->p_priority >= PUSER) 2327 p->p_priority = p->p_usrpri; 2328 } 2329 2330 /* Update resource usage integrals and maximums. */ 2331 if ((pstats = p->p_stats) != NULL && 2332 (ru = &pstats->p_ru) != NULL && 2333 (vm = p->p_vmspace) != NULL) { 2334 ru->ru_ixrss += pgtok(vm->vm_tsize); 2335 ru->ru_idrss += pgtok(vm->vm_dsize); 2336 ru->ru_isrss += pgtok(vm->vm_ssize); 2337 rss = pgtok(vmspace_resident_count(vm)); 2338 if (ru->ru_maxrss < rss) 2339 ru->ru_maxrss = rss; 2340 } 2341 } 2342} 2343 2344void 2345forward_statclock(int pscnt) 2346{ 2347 int map; 2348 int id; 2349 int i; 2350 2351 /* Kludge. We don't yet have separate locks for the interrupts 2352 * and the kernel. This means that we cannot let the other processors 2353 * handle complex interrupts while inhibiting them from entering 2354 * the kernel in a non-interrupt context. 2355 * 2356 * What we can do, without changing the locking mechanisms yet, 2357 * is letting the other processors handle a very simple interrupt 2358 * (wich determines the processor states), and do the main 2359 * work ourself. 2360 */ 2361 2362 if (!smp_started || !invltlb_ok || cold || panicstr) 2363 return; 2364 2365 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle ) */ 2366 2367 map = other_cpus & ~stopped_cpus ; 2368 checkstate_probed_cpus = 0; 2369 if (map != 0) 2370 selected_apic_ipi(map, 2371 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED); 2372 2373 i = 0; 2374 while (checkstate_probed_cpus != map) { 2375 /* spin */ 2376 i++; 2377 if (i == 100000) { 2378#ifdef BETTER_CLOCK_DIAGNOSTIC 2379 printf("forward_statclock: checkstate %x\n", 2380 checkstate_probed_cpus); 2381#endif 2382 break; 2383 } 2384 } 2385 2386 /* 2387 * Step 2: walk through other processors processes, update ticks and 2388 * profiling info. 2389 */ 2390 2391 map = 0; 2392 for (id = 0; id < mp_ncpus; id++) { 2393 if (id == cpuid) 2394 continue; 2395 if (((1 << id) & checkstate_probed_cpus) == 0) 2396 continue; 2397 forwarded_statclock(id, pscnt, &map); 2398 } 2399 if (map != 0) { 2400 checkstate_need_ast |= map; 2401 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED); 2402 i = 0; 2403 while ((checkstate_need_ast & map) != 0) { 2404 /* spin */ 2405 i++; 2406 if (i > 100000) { 2407#ifdef BETTER_CLOCK_DIAGNOSTIC 2408 printf("forward_statclock: dropped ast 0x%x\n", 2409 checkstate_need_ast & map); 2410#endif 2411 break; 2412 } 2413 } 2414 } 2415} 2416 2417void 2418forward_hardclock(int pscnt) 2419{ 2420 int map; 2421 int id; 2422 struct proc *p; 2423 struct pstats *pstats; 2424 int i; 2425 2426 /* Kludge. We don't yet have separate locks for the interrupts 2427 * and the kernel. This means that we cannot let the other processors 2428 * handle complex interrupts while inhibiting them from entering 2429 * the kernel in a non-interrupt context. 2430 * 2431 * What we can do, without changing the locking mechanisms yet, 2432 * is letting the other processors handle a very simple interrupt 2433 * (wich determines the processor states), and do the main 2434 * work ourself. 2435 */ 2436 2437 if (!smp_started || !invltlb_ok || cold || panicstr) 2438 return; 2439 2440 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle) */ 2441 2442 map = other_cpus & ~stopped_cpus ; 2443 checkstate_probed_cpus = 0; 2444 if (map != 0) 2445 selected_apic_ipi(map, 2446 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED); 2447 2448 i = 0; 2449 while (checkstate_probed_cpus != map) { 2450 /* spin */ 2451 i++; 2452 if (i == 100000) { 2453#ifdef BETTER_CLOCK_DIAGNOSTIC 2454 printf("forward_hardclock: checkstate %x\n", 2455 checkstate_probed_cpus); 2456#endif 2457 break; 2458 } 2459 } 2460 2461 /* 2462 * Step 2: walk through other processors processes, update virtual 2463 * timer and profiling timer. If stathz == 0, also update ticks and 2464 * profiling info. 2465 */ 2466 2467 map = 0; 2468 for (id = 0; id < mp_ncpus; id++) { 2469 if (id == cpuid) 2470 continue; 2471 if (((1 << id) & checkstate_probed_cpus) == 0) 2472 continue; 2473 p = checkstate_curproc[id]; 2474 if (p) { 2475 pstats = p->p_stats; 2476 if (checkstate_cpustate[id] == CHECKSTATE_USER && 2477 timevalisset(&pstats->p_timer[ITIMER_VIRTUAL].it_value) && 2478 itimerdecr(&pstats->p_timer[ITIMER_VIRTUAL], tick) == 0) { 2479 psignal(p, SIGVTALRM); 2480 map |= (1 << id); 2481 } 2482 if (timevalisset(&pstats->p_timer[ITIMER_PROF].it_value) && 2483 itimerdecr(&pstats->p_timer[ITIMER_PROF], tick) == 0) { 2484 psignal(p, SIGPROF); 2485 map |= (1 << id); 2486 } 2487 } 2488 if (stathz == 0) { 2489 forwarded_statclock( id, pscnt, &map); 2490 } 2491 } 2492 if (map != 0) { 2493 checkstate_need_ast |= map; 2494 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED); 2495 i = 0; 2496 while ((checkstate_need_ast & map) != 0) { 2497 /* spin */ 2498 i++; 2499 if (i > 100000) { 2500#ifdef BETTER_CLOCK_DIAGNOSTIC 2501 printf("forward_hardclock: dropped ast 0x%x\n", 2502 checkstate_need_ast & map); 2503#endif 2504 break; 2505 } 2506 } 2507 } 2508} 2509 2510#endif /* BETTER_CLOCK */ 2511 2512void 2513forward_signal(struct proc *p) 2514{ 2515 int map; 2516 int id; 2517 int i; 2518 2519 /* Kludge. We don't yet have separate locks for the interrupts 2520 * and the kernel. This means that we cannot let the other processors 2521 * handle complex interrupts while inhibiting them from entering 2522 * the kernel in a non-interrupt context. 2523 * 2524 * What we can do, without changing the locking mechanisms yet, 2525 * is letting the other processors handle a very simple interrupt 2526 * (wich determines the processor states), and do the main 2527 * work ourself. 2528 */ 2529 2530 if (!smp_started || !invltlb_ok || cold || panicstr) 2531 return; 2532 if (!forward_signal_enabled) 2533 return; 2534 while (1) { 2535 if (p->p_stat != SRUN) 2536 return; 2537 id = p->p_oncpu; 2538 if (id == 0xff) 2539 return; 2540 map = (1<<id); 2541 checkstate_need_ast |= map; 2542 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED); 2543 i = 0; 2544 while ((checkstate_need_ast & map) != 0) { 2545 /* spin */ 2546 i++; 2547 if (i > 100000) { 2548#if 0 2549 printf("forward_signal: dropped ast 0x%x\n", 2550 checkstate_need_ast & map); 2551#endif 2552 break; 2553 } 2554 } 2555 if (id == p->p_oncpu) 2556 return; 2557 } 2558} 2559 2560void 2561forward_roundrobin(void) 2562{ 2563 u_int map; 2564 int i; 2565 2566 if (!smp_started || !invltlb_ok || cold || panicstr) 2567 return; 2568 if (!forward_roundrobin_enabled) 2569 return; 2570 resched_cpus |= other_cpus; 2571 map = other_cpus & ~stopped_cpus ; 2572#if 1 2573 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED); 2574#else 2575 (void) all_but_self_ipi(XCPUAST_OFFSET); 2576#endif 2577 i = 0; 2578 while ((checkstate_need_ast & map) != 0) { 2579 /* spin */ 2580 i++; 2581 if (i > 100000) { 2582#if 0 2583 printf("forward_roundrobin: dropped ast 0x%x\n", 2584 checkstate_need_ast & map); 2585#endif 2586 break; 2587 } 2588 } 2589} 2590 2591 2592#ifdef APIC_INTR_REORDER 2593/* 2594 * Maintain mapping from softintr vector to isr bit in local apic. 2595 */ 2596void 2597set_lapic_isrloc(int intr, int vector) 2598{ 2599 if (intr < 0 || intr > 32) 2600 panic("set_apic_isrloc: bad intr argument: %d",intr); 2601 if (vector < ICU_OFFSET || vector > 255) 2602 panic("set_apic_isrloc: bad vector argument: %d",vector); 2603 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2); 2604 apic_isrbit_location[intr].bit = (1<<(vector & 31)); 2605} 2606#endif 2607