mptable.c revision 45566
1/* 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $Id: mp_machdep.c,v 1.95 1999/04/10 22:58:28 tegge Exp $ 26 */ 27 28#include "opt_smp.h" 29#include "opt_vm86.h" 30#include "opt_cpu.h" 31#include "opt_user_ldt.h" 32 33#ifdef SMP 34#include <machine/smptests.h> 35#else 36#error 37#endif 38 39#include <sys/param.h> 40#include <sys/systm.h> 41#include <sys/kernel.h> 42#include <sys/proc.h> 43#include <sys/sysctl.h> 44#ifdef BETTER_CLOCK 45#include <sys/dkstat.h> 46#endif 47 48#include <vm/vm.h> 49#include <vm/vm_param.h> 50#include <vm/pmap.h> 51#include <vm/vm_kern.h> 52#include <vm/vm_extern.h> 53#ifdef BETTER_CLOCK 54#include <sys/lock.h> 55#include <vm/vm_map.h> 56#include <sys/user.h> 57#ifdef GPROF 58#include <sys/gmon.h> 59#endif 60#endif 61 62#include <machine/smp.h> 63#include <machine/apic.h> 64#include <machine/mpapic.h> 65#include <machine/segments.h> 66#include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */ 67#include <machine/tss.h> 68#include <machine/specialreg.h> 69#include <machine/cputypes.h> 70#include <machine/globaldata.h> 71 72#include <i386/i386/cons.h> /* cngetc() */ 73 74#if defined(APIC_IO) 75#include <machine/md_var.h> /* setidt() */ 76#include <i386/isa/icu.h> /* IPIs */ 77#include <i386/isa/intr_machdep.h> /* IPIs */ 78#endif /* APIC_IO */ 79 80#if defined(TEST_DEFAULT_CONFIG) 81#define MPFPS_MPFB1 TEST_DEFAULT_CONFIG 82#else 83#define MPFPS_MPFB1 mpfps->mpfb1 84#endif /* TEST_DEFAULT_CONFIG */ 85 86#define WARMBOOT_TARGET 0 87#define WARMBOOT_OFF (KERNBASE + 0x0467) 88#define WARMBOOT_SEG (KERNBASE + 0x0469) 89 90#ifdef PC98 91#define BIOS_BASE (0xe8000) 92#define BIOS_SIZE (0x18000) 93#else 94#define BIOS_BASE (0xf0000) 95#define BIOS_SIZE (0x10000) 96#endif 97#define BIOS_COUNT (BIOS_SIZE/4) 98 99#define CMOS_REG (0x70) 100#define CMOS_DATA (0x71) 101#define BIOS_RESET (0x0f) 102#define BIOS_WARM (0x0a) 103 104#define PROCENTRY_FLAG_EN 0x01 105#define PROCENTRY_FLAG_BP 0x02 106#define IOAPICENTRY_FLAG_EN 0x01 107 108 109/* MP Floating Pointer Structure */ 110typedef struct MPFPS { 111 char signature[4]; 112 void *pap; 113 u_char length; 114 u_char spec_rev; 115 u_char checksum; 116 u_char mpfb1; 117 u_char mpfb2; 118 u_char mpfb3; 119 u_char mpfb4; 120 u_char mpfb5; 121} *mpfps_t; 122 123/* MP Configuration Table Header */ 124typedef struct MPCTH { 125 char signature[4]; 126 u_short base_table_length; 127 u_char spec_rev; 128 u_char checksum; 129 u_char oem_id[8]; 130 u_char product_id[12]; 131 void *oem_table_pointer; 132 u_short oem_table_size; 133 u_short entry_count; 134 void *apic_address; 135 u_short extended_table_length; 136 u_char extended_table_checksum; 137 u_char reserved; 138} *mpcth_t; 139 140 141typedef struct PROCENTRY { 142 u_char type; 143 u_char apic_id; 144 u_char apic_version; 145 u_char cpu_flags; 146 u_long cpu_signature; 147 u_long feature_flags; 148 u_long reserved1; 149 u_long reserved2; 150} *proc_entry_ptr; 151 152typedef struct BUSENTRY { 153 u_char type; 154 u_char bus_id; 155 char bus_type[6]; 156} *bus_entry_ptr; 157 158typedef struct IOAPICENTRY { 159 u_char type; 160 u_char apic_id; 161 u_char apic_version; 162 u_char apic_flags; 163 void *apic_address; 164} *io_apic_entry_ptr; 165 166typedef struct INTENTRY { 167 u_char type; 168 u_char int_type; 169 u_short int_flags; 170 u_char src_bus_id; 171 u_char src_bus_irq; 172 u_char dst_apic_id; 173 u_char dst_apic_int; 174} *int_entry_ptr; 175 176/* descriptions of MP basetable entries */ 177typedef struct BASETABLE_ENTRY { 178 u_char type; 179 u_char length; 180 char name[16]; 181} basetable_entry; 182 183/* 184 * this code MUST be enabled here and in mpboot.s. 185 * it follows the very early stages of AP boot by placing values in CMOS ram. 186 * it NORMALLY will never be needed and thus the primitive method for enabling. 187 * 188#define CHECK_POINTS 189 */ 190 191#if defined(CHECK_POINTS) && !defined(PC98) 192#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 193#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 194 195#define CHECK_INIT(D); \ 196 CHECK_WRITE(0x34, (D)); \ 197 CHECK_WRITE(0x35, (D)); \ 198 CHECK_WRITE(0x36, (D)); \ 199 CHECK_WRITE(0x37, (D)); \ 200 CHECK_WRITE(0x38, (D)); \ 201 CHECK_WRITE(0x39, (D)); 202 203#define CHECK_PRINT(S); \ 204 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 205 (S), \ 206 CHECK_READ(0x34), \ 207 CHECK_READ(0x35), \ 208 CHECK_READ(0x36), \ 209 CHECK_READ(0x37), \ 210 CHECK_READ(0x38), \ 211 CHECK_READ(0x39)); 212 213#else /* CHECK_POINTS */ 214 215#define CHECK_INIT(D) 216#define CHECK_PRINT(S) 217 218#endif /* CHECK_POINTS */ 219 220/* 221 * Values to send to the POST hardware. 222 */ 223#define MP_BOOTADDRESS_POST 0x10 224#define MP_PROBE_POST 0x11 225#define MPTABLE_PASS1_POST 0x12 226 227#define MP_START_POST 0x13 228#define MP_ENABLE_POST 0x14 229#define MPTABLE_PASS2_POST 0x15 230 231#define START_ALL_APS_POST 0x16 232#define INSTALL_AP_TRAMP_POST 0x17 233#define START_AP_POST 0x18 234 235#define MP_ANNOUNCE_POST 0x19 236 237 238/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ 239int current_postcode; 240 241/** XXX FIXME: what system files declare these??? */ 242extern struct region_descriptor r_gdt, r_idt; 243 244int bsp_apic_ready = 0; /* flags useability of BSP apic */ 245int mp_ncpus; /* # of CPUs, including BSP */ 246int mp_naps; /* # of Applications processors */ 247int mp_nbusses; /* # of busses */ 248int mp_napics; /* # of IO APICs */ 249int boot_cpu_id; /* designated BSP */ 250vm_offset_t cpu_apic_address; 251vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */ 252extern int nkpt; 253 254u_int32_t cpu_apic_versions[NCPU]; 255u_int32_t io_apic_versions[NAPIC]; 256 257#ifdef APIC_INTR_DIAGNOSTIC 258int apic_itrace_enter[32]; 259int apic_itrace_tryisrlock[32]; 260int apic_itrace_gotisrlock[32]; 261int apic_itrace_active[32]; 262int apic_itrace_masked[32]; 263int apic_itrace_noisrlock[32]; 264int apic_itrace_masked2[32]; 265int apic_itrace_unmask[32]; 266int apic_itrace_noforward[32]; 267int apic_itrace_leave[32]; 268int apic_itrace_enter2[32]; 269int apic_itrace_doreti[32]; 270int apic_itrace_splz[32]; 271int apic_itrace_eoi[32]; 272#ifdef APIC_INTR_DIAGNOSTIC_IRQ 273unsigned short apic_itrace_debugbuffer[32768]; 274int apic_itrace_debugbuffer_idx; 275struct simplelock apic_itrace_debuglock; 276#endif 277#endif 278 279#ifdef APIC_INTR_REORDER 280struct { 281 volatile int *location; 282 int bit; 283} apic_isrbit_location[32]; 284#endif 285 286struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE]; 287 288/* 289 * APIC ID logical/physical mapping structures. 290 * We oversize these to simplify boot-time config. 291 */ 292int cpu_num_to_apic_id[NAPICID]; 293int io_num_to_apic_id[NAPICID]; 294int apic_id_to_logical[NAPICID]; 295 296 297/* Bitmap of all available CPUs */ 298u_int all_cpus; 299 300/* AP uses this PTD during bootstrap. Do not staticize. */ 301pd_entry_t *bootPTD; 302 303/* Hotwire a 0->4MB V==P mapping */ 304extern pt_entry_t *KPTphys; 305 306/* Virtual address of per-cpu common_tss */ 307extern struct i386tss common_tss; 308#ifdef VM86 309extern struct segment_descriptor common_tssd; 310extern u_int private_tss; /* flag indicating private tss */ 311extern u_int my_tr; 312#endif /* VM86 */ 313 314/* IdlePTD per cpu */ 315pd_entry_t *IdlePTDS[NCPU]; 316 317/* "my" private page table page, for BSP init */ 318extern pt_entry_t SMP_prvpt[]; 319 320/* Private page pointer to curcpu's PTD, used during BSP init */ 321extern pd_entry_t *my_idlePTD; 322 323struct pcb stoppcbs[NCPU]; 324 325int smp_started; /* has the system started? */ 326 327/* 328 * Local data and functions. 329 */ 330 331static int mp_capable; 332static u_int boot_address; 333static u_int base_memory; 334 335static int picmode; /* 0: virtual wire mode, 1: PIC mode */ 336static mpfps_t mpfps; 337static int search_for_sig(u_int32_t target, int count); 338static void mp_enable(u_int boot_addr); 339 340static int mptable_pass1(void); 341static int mptable_pass2(void); 342static void default_mp_table(int type); 343static void fix_mp_table(void); 344static void setup_apic_irq_mapping(void); 345static void init_locks(void); 346static int start_all_aps(u_int boot_addr); 347static void install_ap_tramp(u_int boot_addr); 348static int start_ap(int logicalCpu, u_int boot_addr); 349 350/* 351 * Calculate usable address in base memory for AP trampoline code. 352 */ 353u_int 354mp_bootaddress(u_int basemem) 355{ 356 POSTCODE(MP_BOOTADDRESS_POST); 357 358 base_memory = basemem * 1024; /* convert to bytes */ 359 360 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ 361 if ((base_memory - boot_address) < bootMP_size) 362 boot_address -= 4096; /* not enough, lower by 4k */ 363 364 return boot_address; 365} 366 367 368/* 369 * Look for an Intel MP spec table (ie, SMP capable hardware). 370 */ 371int 372mp_probe(void) 373{ 374 int x; 375 u_long segment; 376 u_int32_t target; 377 378 POSTCODE(MP_PROBE_POST); 379 380 /* see if EBDA exists */ 381 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) { 382 /* search first 1K of EBDA */ 383 target = (u_int32_t) (segment << 4); 384 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 385 goto found; 386 } else { 387 /* last 1K of base memory, effective 'top of base' passed in */ 388 target = (u_int32_t) (base_memory - 0x400); 389 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 390 goto found; 391 } 392 393 /* search the BIOS */ 394 target = (u_int32_t) BIOS_BASE; 395 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) 396 goto found; 397 398 /* nothing found */ 399 mpfps = (mpfps_t)0; 400 mp_capable = 0; 401 return 0; 402 403found: 404 /* calculate needed resources */ 405 mpfps = (mpfps_t)x; 406 if (mptable_pass1()) 407 panic("you must reconfigure your kernel"); 408 409 /* flag fact that we are running multiple processors */ 410 mp_capable = 1; 411 return 1; 412} 413 414 415/* 416 * Startup the SMP processors. 417 */ 418void 419mp_start(void) 420{ 421 POSTCODE(MP_START_POST); 422 423 /* look for MP capable motherboard */ 424 if (mp_capable) 425 mp_enable(boot_address); 426 else 427 panic("MP hardware not found!"); 428} 429 430 431/* 432 * Print various information about the SMP system hardware and setup. 433 */ 434void 435mp_announce(void) 436{ 437 int x; 438 439 POSTCODE(MP_ANNOUNCE_POST); 440 441 printf("FreeBSD/SMP: Multiprocessor motherboard\n"); 442 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0)); 443 printf(", version: 0x%08x", cpu_apic_versions[0]); 444 printf(", at 0x%08x\n", cpu_apic_address); 445 for (x = 1; x <= mp_naps; ++x) { 446 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x)); 447 printf(", version: 0x%08x", cpu_apic_versions[x]); 448 printf(", at 0x%08x\n", cpu_apic_address); 449 } 450 451#if defined(APIC_IO) 452 for (x = 0; x < mp_napics; ++x) { 453 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x)); 454 printf(", version: 0x%08x", io_apic_versions[x]); 455 printf(", at 0x%08x\n", io_apic_address[x]); 456 } 457#else 458 printf(" Warning: APIC I/O disabled\n"); 459#endif /* APIC_IO */ 460} 461 462/* 463 * AP cpu's call this to sync up protected mode. 464 */ 465void 466init_secondary(void) 467{ 468 int gsel_tss; 469#ifndef VM86 470 u_int my_tr; 471#endif 472 473 r_gdt.rd_limit = sizeof(gdt[0]) * (NGDT + NCPU) - 1; 474 r_gdt.rd_base = (int) gdt; 475 lgdt(&r_gdt); /* does magic intra-segment return */ 476 lidt(&r_idt); 477 lldt(_default_ldt); 478#ifdef USER_LDT 479 currentldt = _default_ldt; 480#endif 481 482 my_tr = NGDT + cpuid; 483 gsel_tss = GSEL(my_tr, SEL_KPL); 484 gdt[my_tr].sd.sd_type = SDT_SYS386TSS; 485 common_tss.tss_esp0 = 0; /* not used until after switch */ 486 common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 487 common_tss.tss_ioopt = (sizeof common_tss) << 16; 488#ifdef VM86 489 common_tssd = gdt[my_tr].sd; 490 private_tss = 0; 491#endif /* VM86 */ 492 ltr(gsel_tss); 493 494 load_cr0(0x8005003b); /* XXX! */ 495 496 PTD[0] = 0; 497 pmap_set_opt((unsigned *)PTD); 498 499#if 0 500 putmtrr(); 501 pmap_setvidram(); 502#endif 503 504 invltlb(); 505} 506 507 508#if defined(APIC_IO) 509/* 510 * Final configuration of the BSP's local APIC: 511 * - disable 'pic mode'. 512 * - disable 'virtual wire mode'. 513 * - enable NMI. 514 */ 515void 516bsp_apic_configure(void) 517{ 518 u_char byte; 519 u_int32_t temp; 520 521 /* leave 'pic mode' if necessary */ 522 if (picmode) { 523 outb(0x22, 0x70); /* select IMCR */ 524 byte = inb(0x23); /* current contents */ 525 byte |= 0x01; /* mask external INTR */ 526 outb(0x23, byte); /* disconnect 8259s/NMI */ 527 } 528 529 /* mask lint0 (the 8259 'virtual wire' connection) */ 530 temp = lapic.lvt_lint0; 531 temp |= APIC_LVT_M; /* set the mask */ 532 lapic.lvt_lint0 = temp; 533 534 /* setup lint1 to handle NMI */ 535 temp = lapic.lvt_lint1; 536 temp &= ~APIC_LVT_M; /* clear the mask */ 537 lapic.lvt_lint1 = temp; 538 539 if (bootverbose) 540 apic_dump("bsp_apic_configure()"); 541} 542#endif /* APIC_IO */ 543 544 545/******************************************************************* 546 * local functions and data 547 */ 548 549/* 550 * start the SMP system 551 */ 552static void 553mp_enable(u_int boot_addr) 554{ 555 int x; 556#if defined(APIC_IO) 557 int apic; 558 u_int ux; 559#endif /* APIC_IO */ 560 561#if 0 562 getmtrr(); 563 pmap_setvidram(); 564#endif 565 566 POSTCODE(MP_ENABLE_POST); 567 568 /* turn on 4MB of V == P addressing so we can get to MP table */ 569 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME); 570 invltlb(); 571 572 /* examine the MP table for needed info, uses physical addresses */ 573 x = mptable_pass2(); 574 575 *(int *)PTD = 0; 576 invltlb(); 577 578 /* can't process default configs till the CPU APIC is pmapped */ 579 if (x) 580 default_mp_table(x); 581 582 /* post scan cleanup */ 583 fix_mp_table(); 584 setup_apic_irq_mapping(); 585 586#if defined(APIC_IO) 587 588 /* fill the LOGICAL io_apic_versions table */ 589 for (apic = 0; apic < mp_napics; ++apic) { 590 ux = io_apic_read(apic, IOAPIC_VER); 591 io_apic_versions[apic] = ux; 592 } 593 594 /* program each IO APIC in the system */ 595 for (apic = 0; apic < mp_napics; ++apic) 596 if (io_apic_setup(apic) < 0) 597 panic("IO APIC setup failure"); 598 599 /* install a 'Spurious INTerrupt' vector */ 600 setidt(XSPURIOUSINT_OFFSET, Xspuriousint, 601 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 602 603 /* install an inter-CPU IPI for TLB invalidation */ 604 setidt(XINVLTLB_OFFSET, Xinvltlb, 605 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 606 607#ifdef BETTER_CLOCK 608 /* install an inter-CPU IPI for reading processor state */ 609 setidt(XCPUCHECKSTATE_OFFSET, Xcpucheckstate, 610 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 611#endif 612 613 /* install an inter-CPU IPI for forcing an additional software trap */ 614 setidt(XCPUAST_OFFSET, Xcpuast, 615 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 616 617 /* install an inter-CPU IPI for interrupt forwarding */ 618 setidt(XFORWARD_IRQ_OFFSET, Xforward_irq, 619 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 620 621 /* install an inter-CPU IPI for CPU stop/restart */ 622 setidt(XCPUSTOP_OFFSET, Xcpustop, 623 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 624 625#if defined(TEST_TEST1) 626 /* install a "fake hardware INTerrupt" vector */ 627 setidt(XTEST1_OFFSET, Xtest1, 628 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 629#endif /** TEST_TEST1 */ 630 631#endif /* APIC_IO */ 632 633 /* initialize all SMP locks */ 634 init_locks(); 635 636 /* start each Application Processor */ 637 start_all_aps(boot_addr); 638 639 /* 640 * The init process might be started on a different CPU now, 641 * and the boot CPU might not call prepare_usermode to get 642 * cr0 correctly configured. Thus we initialize cr0 here. 643 */ 644 load_cr0(rcr0() | CR0_WP | CR0_AM); 645} 646 647 648/* 649 * look for the MP spec signature 650 */ 651 652/* string defined by the Intel MP Spec as identifying the MP table */ 653#define MP_SIG 0x5f504d5f /* _MP_ */ 654#define NEXT(X) ((X) += 4) 655static int 656search_for_sig(u_int32_t target, int count) 657{ 658 int x; 659 u_int32_t *addr = (u_int32_t *) (KERNBASE + target); 660 661 for (x = 0; x < count; NEXT(x)) 662 if (addr[x] == MP_SIG) 663 /* make array index a byte index */ 664 return (target + (x * sizeof(u_int32_t))); 665 666 return -1; 667} 668 669 670static basetable_entry basetable_entry_types[] = 671{ 672 {0, 20, "Processor"}, 673 {1, 8, "Bus"}, 674 {2, 8, "I/O APIC"}, 675 {3, 8, "I/O INT"}, 676 {4, 8, "Local INT"} 677}; 678 679typedef struct BUSDATA { 680 u_char bus_id; 681 enum busTypes bus_type; 682} bus_datum; 683 684typedef struct INTDATA { 685 u_char int_type; 686 u_short int_flags; 687 u_char src_bus_id; 688 u_char src_bus_irq; 689 u_char dst_apic_id; 690 u_char dst_apic_int; 691 u_char int_vector; 692} io_int, local_int; 693 694typedef struct BUSTYPENAME { 695 u_char type; 696 char name[7]; 697} bus_type_name; 698 699static bus_type_name bus_type_table[] = 700{ 701 {CBUS, "CBUS"}, 702 {CBUSII, "CBUSII"}, 703 {EISA, "EISA"}, 704 {UNKNOWN_BUSTYPE, "---"}, 705 {UNKNOWN_BUSTYPE, "---"}, 706 {ISA, "ISA"}, 707 {UNKNOWN_BUSTYPE, "---"}, 708 {UNKNOWN_BUSTYPE, "---"}, 709 {UNKNOWN_BUSTYPE, "---"}, 710 {UNKNOWN_BUSTYPE, "---"}, 711 {UNKNOWN_BUSTYPE, "---"}, 712 {UNKNOWN_BUSTYPE, "---"}, 713 {PCI, "PCI"}, 714 {UNKNOWN_BUSTYPE, "---"}, 715 {UNKNOWN_BUSTYPE, "---"}, 716 {UNKNOWN_BUSTYPE, "---"}, 717 {UNKNOWN_BUSTYPE, "---"}, 718 {XPRESS, "XPRESS"}, 719 {UNKNOWN_BUSTYPE, "---"} 720}; 721/* from MP spec v1.4, table 5-1 */ 722static int default_data[7][5] = 723{ 724/* nbus, id0, type0, id1, type1 */ 725 {1, 0, ISA, 255, 255}, 726 {1, 0, EISA, 255, 255}, 727 {1, 0, EISA, 255, 255}, 728 {0, 255, 255, 255, 255},/* MCA not supported */ 729 {2, 0, ISA, 1, PCI}, 730 {2, 0, EISA, 1, PCI}, 731 {0, 255, 255, 255, 255} /* MCA not supported */ 732}; 733 734 735/* the bus data */ 736static bus_datum bus_data[NBUS]; 737 738/* the IO INT data, one entry per possible APIC INTerrupt */ 739static io_int io_apic_ints[NINTR]; 740 741static int nintrs; 742 743static int processor_entry __P((proc_entry_ptr entry, int cpu)); 744static int bus_entry __P((bus_entry_ptr entry, int bus)); 745static int io_apic_entry __P((io_apic_entry_ptr entry, int apic)); 746static int int_entry __P((int_entry_ptr entry, int intr)); 747static int lookup_bus_type __P((char *name)); 748 749 750/* 751 * 1st pass on motherboard's Intel MP specification table. 752 * 753 * initializes: 754 * mp_ncpus = 1 755 * 756 * determines: 757 * cpu_apic_address (common to all CPUs) 758 * io_apic_address[N] 759 * mp_naps 760 * mp_nbusses 761 * mp_napics 762 * nintrs 763 */ 764static int 765mptable_pass1(void) 766{ 767 int x; 768 mpcth_t cth; 769 int totalSize; 770 void* position; 771 int count; 772 int type; 773 int mustpanic; 774 775 POSTCODE(MPTABLE_PASS1_POST); 776 777 mustpanic = 0; 778 779 /* clear various tables */ 780 for (x = 0; x < NAPICID; ++x) { 781 io_apic_address[x] = ~0; /* IO APIC address table */ 782 } 783 784 /* init everything to empty */ 785 mp_naps = 0; 786 mp_nbusses = 0; 787 mp_napics = 0; 788 nintrs = 0; 789 790 /* check for use of 'default' configuration */ 791 if (MPFPS_MPFB1 != 0) { 792 /* use default addresses */ 793 cpu_apic_address = DEFAULT_APIC_BASE; 794 io_apic_address[0] = DEFAULT_IO_APIC_BASE; 795 796 /* fill in with defaults */ 797 mp_naps = 2; /* includes BSP */ 798 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0]; 799#if defined(APIC_IO) 800 mp_napics = 1; 801 nintrs = 16; 802#endif /* APIC_IO */ 803 } 804 else { 805 if ((cth = mpfps->pap) == 0) 806 panic("MP Configuration Table Header MISSING!"); 807 808 cpu_apic_address = (vm_offset_t) cth->apic_address; 809 810 /* walk the table, recording info of interest */ 811 totalSize = cth->base_table_length - sizeof(struct MPCTH); 812 position = (u_char *) cth + sizeof(struct MPCTH); 813 count = cth->entry_count; 814 815 while (count--) { 816 switch (type = *(u_char *) position) { 817 case 0: /* processor_entry */ 818 if (((proc_entry_ptr)position)->cpu_flags 819 & PROCENTRY_FLAG_EN) 820 ++mp_naps; 821 break; 822 case 1: /* bus_entry */ 823 ++mp_nbusses; 824 break; 825 case 2: /* io_apic_entry */ 826 if (((io_apic_entry_ptr)position)->apic_flags 827 & IOAPICENTRY_FLAG_EN) 828 io_apic_address[mp_napics++] = 829 (vm_offset_t)((io_apic_entry_ptr) 830 position)->apic_address; 831 break; 832 case 3: /* int_entry */ 833 ++nintrs; 834 break; 835 case 4: /* int_entry */ 836 break; 837 default: 838 panic("mpfps Base Table HOSED!"); 839 /* NOTREACHED */ 840 } 841 842 totalSize -= basetable_entry_types[type].length; 843 (u_char*)position += basetable_entry_types[type].length; 844 } 845 } 846 847 /* qualify the numbers */ 848 if (mp_naps > NCPU) 849#if 0 /* XXX FIXME: kern/4255 */ 850 printf("Warning: only using %d of %d available CPUs!\n", 851 NCPU, mp_naps); 852#else 853 { 854 printf("NCPU cannot be different than actual CPU count.\n"); 855 printf(" add 'options NCPU=%d' to your kernel config file,\n", 856 mp_naps); 857 printf(" then rerun config & rebuild your SMP kernel\n"); 858 mustpanic = 1; 859 } 860#endif /* XXX FIXME: kern/4255 */ 861 if (mp_nbusses > NBUS) { 862 printf("found %d busses, increase NBUS\n", mp_nbusses); 863 mustpanic = 1; 864 } 865 if (mp_napics > NAPIC) { 866 printf("found %d apics, increase NAPIC\n", mp_napics); 867 mustpanic = 1; 868 } 869 if (nintrs > NINTR) { 870 printf("found %d intrs, increase NINTR\n", nintrs); 871 mustpanic = 1; 872 } 873 874 /* 875 * Count the BSP. 876 * This is also used as a counter while starting the APs. 877 */ 878 mp_ncpus = 1; 879 880 --mp_naps; /* subtract the BSP */ 881 882 return mustpanic; 883} 884 885 886/* 887 * 2nd pass on motherboard's Intel MP specification table. 888 * 889 * sets: 890 * boot_cpu_id 891 * ID_TO_IO(N), phy APIC ID to log CPU/IO table 892 * CPU_TO_ID(N), logical CPU to APIC ID table 893 * IO_TO_ID(N), logical IO to APIC ID table 894 * bus_data[N] 895 * io_apic_ints[N] 896 */ 897static int 898mptable_pass2(void) 899{ 900 int x; 901 mpcth_t cth; 902 int totalSize; 903 void* position; 904 int count; 905 int type; 906 int apic, bus, cpu, intr; 907 908 POSTCODE(MPTABLE_PASS2_POST); 909 910 /* clear various tables */ 911 for (x = 0; x < NAPICID; ++x) { 912 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */ 913 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */ 914 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */ 915 } 916 917 /* clear bus data table */ 918 for (x = 0; x < NBUS; ++x) 919 bus_data[x].bus_id = 0xff; 920 921 /* clear IO APIC INT table */ 922 for (x = 0; x < NINTR; ++x) { 923 io_apic_ints[x].int_type = 0xff; 924 io_apic_ints[x].int_vector = 0xff; 925 } 926 927 /* setup the cpu/apic mapping arrays */ 928 boot_cpu_id = -1; 929 930 /* record whether PIC or virtual-wire mode */ 931 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0; 932 933 /* check for use of 'default' configuration */ 934 if (MPFPS_MPFB1 != 0) 935 return MPFPS_MPFB1; /* return default configuration type */ 936 937 if ((cth = mpfps->pap) == 0) 938 panic("MP Configuration Table Header MISSING!"); 939 940 /* walk the table, recording info of interest */ 941 totalSize = cth->base_table_length - sizeof(struct MPCTH); 942 position = (u_char *) cth + sizeof(struct MPCTH); 943 count = cth->entry_count; 944 apic = bus = intr = 0; 945 cpu = 1; /* pre-count the BSP */ 946 947 while (count--) { 948 switch (type = *(u_char *) position) { 949 case 0: 950 if (processor_entry(position, cpu)) 951 ++cpu; 952 break; 953 case 1: 954 if (bus_entry(position, bus)) 955 ++bus; 956 break; 957 case 2: 958 if (io_apic_entry(position, apic)) 959 ++apic; 960 break; 961 case 3: 962 if (int_entry(position, intr)) 963 ++intr; 964 break; 965 case 4: 966 /* int_entry(position); */ 967 break; 968 default: 969 panic("mpfps Base Table HOSED!"); 970 /* NOTREACHED */ 971 } 972 973 totalSize -= basetable_entry_types[type].length; 974 (u_char *) position += basetable_entry_types[type].length; 975 } 976 977 if (boot_cpu_id == -1) 978 panic("NO BSP found!"); 979 980 /* report fact that its NOT a default configuration */ 981 return 0; 982} 983 984 985static void 986assign_apic_irq(int apic, int intpin, int irq) 987{ 988 int x; 989 990 if (int_to_apicintpin[irq].ioapic != -1) 991 panic("assign_apic_irq: inconsistent table"); 992 993 int_to_apicintpin[irq].ioapic = apic; 994 int_to_apicintpin[irq].int_pin = intpin; 995 int_to_apicintpin[irq].apic_address = ioapic[apic]; 996 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin; 997 998 for (x = 0; x < nintrs; x++) { 999 if ((io_apic_ints[x].int_type == 0 || 1000 io_apic_ints[x].int_type == 3) && 1001 io_apic_ints[x].int_vector == 0xff && 1002 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) && 1003 io_apic_ints[x].dst_apic_int == intpin) 1004 io_apic_ints[x].int_vector = irq; 1005 } 1006} 1007 1008/* 1009 * parse an Intel MP specification table 1010 */ 1011static void 1012fix_mp_table(void) 1013{ 1014 int x; 1015 int id; 1016 int bus_0 = 0; /* Stop GCC warning */ 1017 int bus_pci = 0; /* Stop GCC warning */ 1018 int num_pci_bus; 1019 1020 /* 1021 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS 1022 * did it wrong. The MP spec says that when more than 1 PCI bus 1023 * exists the BIOS must begin with bus entries for the PCI bus and use 1024 * actual PCI bus numbering. This implies that when only 1 PCI bus 1025 * exists the BIOS can choose to ignore this ordering, and indeed many 1026 * MP motherboards do ignore it. This causes a problem when the PCI 1027 * sub-system makes requests of the MP sub-system based on PCI bus 1028 * numbers. So here we look for the situation and renumber the 1029 * busses and associated INTs in an effort to "make it right". 1030 */ 1031 1032 /* find bus 0, PCI bus, count the number of PCI busses */ 1033 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { 1034 if (bus_data[x].bus_id == 0) { 1035 bus_0 = x; 1036 } 1037 if (bus_data[x].bus_type == PCI) { 1038 ++num_pci_bus; 1039 bus_pci = x; 1040 } 1041 } 1042 /* 1043 * bus_0 == slot of bus with ID of 0 1044 * bus_pci == slot of last PCI bus encountered 1045 */ 1046 1047 /* check the 1 PCI bus case for sanity */ 1048 if (num_pci_bus == 1) { 1049 1050 /* if it is number 0 all is well */ 1051 if (bus_data[bus_pci].bus_id == 0) 1052 return; 1053 1054 /* mis-numbered, swap with whichever bus uses slot 0 */ 1055 1056 /* swap the bus entry types */ 1057 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type; 1058 bus_data[bus_0].bus_type = PCI; 1059 1060 /* swap each relavant INTerrupt entry */ 1061 id = bus_data[bus_pci].bus_id; 1062 for (x = 0; x < nintrs; ++x) { 1063 if (io_apic_ints[x].src_bus_id == id) { 1064 io_apic_ints[x].src_bus_id = 0; 1065 } 1066 else if (io_apic_ints[x].src_bus_id == 0) { 1067 io_apic_ints[x].src_bus_id = id; 1068 } 1069 } 1070 } 1071 /* sanity check if more than 1 PCI bus */ 1072 else if (num_pci_bus > 1) { 1073 for (x = 0; x < mp_nbusses; ++x) { 1074 if (bus_data[x].bus_type != PCI) 1075 continue; 1076 if (bus_data[x].bus_id >= num_pci_bus) 1077 panic("bad PCI bus numbering"); 1078 } 1079 } 1080} 1081 1082 1083static void 1084setup_apic_irq_mapping(void) 1085{ 1086 int x; 1087 int int_vector; 1088 1089 /* Assign low level interrupt handlers */ 1090 for (x = 0; x < APIC_INTMAPSIZE; x++) { 1091 int_to_apicintpin[x].ioapic = -1; 1092 int_to_apicintpin[x].int_pin = 0; 1093 int_to_apicintpin[x].apic_address = NULL; 1094 int_to_apicintpin[x].redirindex = 0; 1095 } 1096 for (x = 0; x < nintrs; x++) { 1097 if (io_apic_ints[x].dst_apic_int < APIC_INTMAPSIZE && 1098 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) && 1099 io_apic_ints[x].int_vector == 0xff && 1100 (io_apic_ints[x].int_type == 0 || 1101 io_apic_ints[x].int_type == 3)) { 1102 assign_apic_irq(0, 1103 io_apic_ints[x].dst_apic_int, 1104 io_apic_ints[x].dst_apic_int); 1105 } 1106 } 1107 int_vector = 0; 1108 while (int_vector < APIC_INTMAPSIZE && 1109 int_to_apicintpin[int_vector].ioapic != -1) 1110 int_vector++; 1111 for (x = 0; x < nintrs && int_vector < APIC_INTMAPSIZE; x++) { 1112 if ((io_apic_ints[x].int_type == 0 || 1113 io_apic_ints[x].int_type == 3) && 1114 io_apic_ints[x].int_vector == 0xff) { 1115 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id), 1116 io_apic_ints[x].dst_apic_int, 1117 int_vector); 1118 int_vector++; 1119 while (int_vector < APIC_INTMAPSIZE && 1120 int_to_apicintpin[int_vector].ioapic != -1) 1121 int_vector++; 1122 } 1123 } 1124} 1125 1126 1127static int 1128processor_entry(proc_entry_ptr entry, int cpu) 1129{ 1130 /* check for usability */ 1131 if ((cpu >= NCPU) || !(entry->cpu_flags & PROCENTRY_FLAG_EN)) 1132 return 0; 1133 1134 /* check for BSP flag */ 1135 if (entry->cpu_flags & PROCENTRY_FLAG_BP) { 1136 boot_cpu_id = entry->apic_id; 1137 CPU_TO_ID(0) = entry->apic_id; 1138 ID_TO_CPU(entry->apic_id) = 0; 1139 return 0; /* its already been counted */ 1140 } 1141 1142 /* add another AP to list, if less than max number of CPUs */ 1143 else { 1144 CPU_TO_ID(cpu) = entry->apic_id; 1145 ID_TO_CPU(entry->apic_id) = cpu; 1146 return 1; 1147 } 1148} 1149 1150 1151static int 1152bus_entry(bus_entry_ptr entry, int bus) 1153{ 1154 int x; 1155 char c, name[8]; 1156 1157 /* encode the name into an index */ 1158 for (x = 0; x < 6; ++x) { 1159 if ((c = entry->bus_type[x]) == ' ') 1160 break; 1161 name[x] = c; 1162 } 1163 name[x] = '\0'; 1164 1165 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) 1166 panic("unknown bus type: '%s'", name); 1167 1168 bus_data[bus].bus_id = entry->bus_id; 1169 bus_data[bus].bus_type = x; 1170 1171 return 1; 1172} 1173 1174 1175static int 1176io_apic_entry(io_apic_entry_ptr entry, int apic) 1177{ 1178 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) 1179 return 0; 1180 1181 IO_TO_ID(apic) = entry->apic_id; 1182 ID_TO_IO(entry->apic_id) = apic; 1183 1184 return 1; 1185} 1186 1187 1188static int 1189lookup_bus_type(char *name) 1190{ 1191 int x; 1192 1193 for (x = 0; x < MAX_BUSTYPE; ++x) 1194 if (strcmp(bus_type_table[x].name, name) == 0) 1195 return bus_type_table[x].type; 1196 1197 return UNKNOWN_BUSTYPE; 1198} 1199 1200 1201static int 1202int_entry(int_entry_ptr entry, int intr) 1203{ 1204 int apic; 1205 1206 io_apic_ints[intr].int_type = entry->int_type; 1207 io_apic_ints[intr].int_flags = entry->int_flags; 1208 io_apic_ints[intr].src_bus_id = entry->src_bus_id; 1209 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq; 1210 if (entry->dst_apic_id == 255) { 1211 /* This signal goes to all IO APICS. Select an IO APIC 1212 with sufficient number of interrupt pins */ 1213 for (apic = 0; apic < mp_napics; apic++) 1214 if (((io_apic_read(apic, IOAPIC_VER) & 1215 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >= 1216 entry->dst_apic_int) 1217 break; 1218 if (apic < mp_napics) 1219 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic); 1220 else 1221 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; 1222 } else 1223 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; 1224 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int; 1225 1226 return 1; 1227} 1228 1229 1230static int 1231apic_int_is_bus_type(int intr, int bus_type) 1232{ 1233 int bus; 1234 1235 for (bus = 0; bus < mp_nbusses; ++bus) 1236 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) 1237 && ((int) bus_data[bus].bus_type == bus_type)) 1238 return 1; 1239 1240 return 0; 1241} 1242 1243 1244/* 1245 * Given a traditional ISA INT mask, return an APIC mask. 1246 */ 1247u_int 1248isa_apic_mask(u_int isa_mask) 1249{ 1250 int isa_irq; 1251 int apic_pin; 1252 1253#if defined(SKIP_IRQ15_REDIRECT) 1254 if (isa_mask == (1 << 15)) { 1255 printf("skipping ISA IRQ15 redirect\n"); 1256 return isa_mask; 1257 } 1258#endif /* SKIP_IRQ15_REDIRECT */ 1259 1260 isa_irq = ffs(isa_mask); /* find its bit position */ 1261 if (isa_irq == 0) /* doesn't exist */ 1262 return 0; 1263 --isa_irq; /* make it zero based */ 1264 1265 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */ 1266 if (apic_pin == -1) 1267 return 0; 1268 1269 return (1 << apic_pin); /* convert pin# to a mask */ 1270} 1271 1272 1273/* 1274 * Determine which APIC pin an ISA/EISA INT is attached to. 1275 */ 1276#define INTTYPE(I) (io_apic_ints[(I)].int_type) 1277#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) 1278#define INTIRQ(I) (io_apic_ints[(I)].int_vector) 1279#define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id)) 1280 1281#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) 1282int 1283isa_apic_irq(int isa_irq) 1284{ 1285 int intr; 1286 1287 for (intr = 0; intr < nintrs; ++intr) { /* check each record */ 1288 if (INTTYPE(intr) == 0) { /* standard INT */ 1289 if (SRCBUSIRQ(intr) == isa_irq) { 1290 if (apic_int_is_bus_type(intr, ISA) || 1291 apic_int_is_bus_type(intr, EISA)) 1292 return INTIRQ(intr); /* found */ 1293 } 1294 } 1295 } 1296 return -1; /* NOT found */ 1297} 1298 1299 1300/* 1301 * Determine which APIC pin a PCI INT is attached to. 1302 */ 1303#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) 1304#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) 1305#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) 1306int 1307pci_apic_irq(int pciBus, int pciDevice, int pciInt) 1308{ 1309 int intr; 1310 1311 --pciInt; /* zero based */ 1312 1313 for (intr = 0; intr < nintrs; ++intr) /* check each record */ 1314 if ((INTTYPE(intr) == 0) /* standard INT */ 1315 && (SRCBUSID(intr) == pciBus) 1316 && (SRCBUSDEVICE(intr) == pciDevice) 1317 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ 1318 if (apic_int_is_bus_type(intr, PCI)) 1319 return INTIRQ(intr); /* exact match */ 1320 1321 return -1; /* NOT found */ 1322} 1323 1324int 1325next_apic_irq(int irq) 1326{ 1327 int intr, ointr; 1328 int bus, bustype; 1329 1330 bus = 0; 1331 bustype = 0; 1332 for (intr = 0; intr < nintrs; intr++) { 1333 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0) 1334 continue; 1335 bus = SRCBUSID(intr); 1336 bustype = apic_bus_type(bus); 1337 if (bustype != ISA && 1338 bustype != EISA && 1339 bustype != PCI) 1340 continue; 1341 break; 1342 } 1343 if (intr >= nintrs) { 1344 return -1; 1345 } 1346 for (ointr = intr + 1; ointr < nintrs; ointr++) { 1347 if (INTTYPE(ointr) != 0) 1348 continue; 1349 if (bus != SRCBUSID(ointr)) 1350 continue; 1351 if (bustype == PCI) { 1352 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr)) 1353 continue; 1354 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr)) 1355 continue; 1356 } 1357 if (bustype == ISA || bustype == EISA) { 1358 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr)) 1359 continue; 1360 } 1361 if (INTPIN(intr) == INTPIN(ointr)) 1362 continue; 1363 break; 1364 } 1365 if (ointr >= nintrs) { 1366 return -1; 1367 } 1368 return INTIRQ(ointr); 1369} 1370#undef SRCBUSLINE 1371#undef SRCBUSDEVICE 1372#undef SRCBUSID 1373#undef SRCBUSIRQ 1374 1375#undef INTPIN 1376#undef INTIRQ 1377#undef INTAPIC 1378#undef INTTYPE 1379 1380 1381/* 1382 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt. 1383 * 1384 * XXX FIXME: 1385 * Exactly what this means is unclear at this point. It is a solution 1386 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard 1387 * could route any of the ISA INTs to upper (>15) IRQ values. But most would 1388 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an 1389 * option. 1390 */ 1391int 1392undirect_isa_irq(int rirq) 1393{ 1394#if defined(READY) 1395 if (bootverbose) 1396 printf("Freeing redirected ISA irq %d.\n", rirq); 1397 /** FIXME: tickle the MB redirector chip */ 1398 return ???; 1399#else 1400 if (bootverbose) 1401 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq); 1402 return 0; 1403#endif /* READY */ 1404} 1405 1406 1407/* 1408 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt 1409 */ 1410int 1411undirect_pci_irq(int rirq) 1412{ 1413#if defined(READY) 1414 if (bootverbose) 1415 printf("Freeing redirected PCI irq %d.\n", rirq); 1416 1417 /** FIXME: tickle the MB redirector chip */ 1418 return ???; 1419#else 1420 if (bootverbose) 1421 printf("Freeing (NOT implemented) redirected PCI irq %d.\n", 1422 rirq); 1423 return 0; 1424#endif /* READY */ 1425} 1426 1427 1428/* 1429 * given a bus ID, return: 1430 * the bus type if found 1431 * -1 if NOT found 1432 */ 1433int 1434apic_bus_type(int id) 1435{ 1436 int x; 1437 1438 for (x = 0; x < mp_nbusses; ++x) 1439 if (bus_data[x].bus_id == id) 1440 return bus_data[x].bus_type; 1441 1442 return -1; 1443} 1444 1445 1446/* 1447 * given a LOGICAL APIC# and pin#, return: 1448 * the associated src bus ID if found 1449 * -1 if NOT found 1450 */ 1451int 1452apic_src_bus_id(int apic, int pin) 1453{ 1454 int x; 1455 1456 /* search each of the possible INTerrupt sources */ 1457 for (x = 0; x < nintrs; ++x) 1458 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1459 (pin == io_apic_ints[x].dst_apic_int)) 1460 return (io_apic_ints[x].src_bus_id); 1461 1462 return -1; /* NOT found */ 1463} 1464 1465 1466/* 1467 * given a LOGICAL APIC# and pin#, return: 1468 * the associated src bus IRQ if found 1469 * -1 if NOT found 1470 */ 1471int 1472apic_src_bus_irq(int apic, int pin) 1473{ 1474 int x; 1475 1476 for (x = 0; x < nintrs; x++) 1477 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1478 (pin == io_apic_ints[x].dst_apic_int)) 1479 return (io_apic_ints[x].src_bus_irq); 1480 1481 return -1; /* NOT found */ 1482} 1483 1484 1485/* 1486 * given a LOGICAL APIC# and pin#, return: 1487 * the associated INTerrupt type if found 1488 * -1 if NOT found 1489 */ 1490int 1491apic_int_type(int apic, int pin) 1492{ 1493 int x; 1494 1495 /* search each of the possible INTerrupt sources */ 1496 for (x = 0; x < nintrs; ++x) 1497 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1498 (pin == io_apic_ints[x].dst_apic_int)) 1499 return (io_apic_ints[x].int_type); 1500 1501 return -1; /* NOT found */ 1502} 1503 1504int 1505apic_irq(int apic, int pin) 1506{ 1507 int x; 1508 int res; 1509 1510 for (x = 0; x < nintrs; ++x) 1511 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1512 (pin == io_apic_ints[x].dst_apic_int)) { 1513 res = io_apic_ints[x].int_vector; 1514 if (res == 0xff) 1515 return -1; 1516 if (apic != int_to_apicintpin[res].ioapic) 1517 panic("apic_irq: inconsistent table"); 1518 if (pin != int_to_apicintpin[res].int_pin) 1519 panic("apic_irq inconsistent table (2)"); 1520 return res; 1521 } 1522 return -1; 1523} 1524 1525 1526/* 1527 * given a LOGICAL APIC# and pin#, return: 1528 * the associated trigger mode if found 1529 * -1 if NOT found 1530 */ 1531int 1532apic_trigger(int apic, int pin) 1533{ 1534 int x; 1535 1536 /* search each of the possible INTerrupt sources */ 1537 for (x = 0; x < nintrs; ++x) 1538 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1539 (pin == io_apic_ints[x].dst_apic_int)) 1540 return ((io_apic_ints[x].int_flags >> 2) & 0x03); 1541 1542 return -1; /* NOT found */ 1543} 1544 1545 1546/* 1547 * given a LOGICAL APIC# and pin#, return: 1548 * the associated 'active' level if found 1549 * -1 if NOT found 1550 */ 1551int 1552apic_polarity(int apic, int pin) 1553{ 1554 int x; 1555 1556 /* search each of the possible INTerrupt sources */ 1557 for (x = 0; x < nintrs; ++x) 1558 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1559 (pin == io_apic_ints[x].dst_apic_int)) 1560 return (io_apic_ints[x].int_flags & 0x03); 1561 1562 return -1; /* NOT found */ 1563} 1564 1565 1566/* 1567 * set data according to MP defaults 1568 * FIXME: probably not complete yet... 1569 */ 1570static void 1571default_mp_table(int type) 1572{ 1573 int ap_cpu_id; 1574#if defined(APIC_IO) 1575 u_int32_t ux; 1576 int io_apic_id; 1577 int pin; 1578#endif /* APIC_IO */ 1579 1580#if 0 1581 printf(" MP default config type: %d\n", type); 1582 switch (type) { 1583 case 1: 1584 printf(" bus: ISA, APIC: 82489DX\n"); 1585 break; 1586 case 2: 1587 printf(" bus: EISA, APIC: 82489DX\n"); 1588 break; 1589 case 3: 1590 printf(" bus: EISA, APIC: 82489DX\n"); 1591 break; 1592 case 4: 1593 printf(" bus: MCA, APIC: 82489DX\n"); 1594 break; 1595 case 5: 1596 printf(" bus: ISA+PCI, APIC: Integrated\n"); 1597 break; 1598 case 6: 1599 printf(" bus: EISA+PCI, APIC: Integrated\n"); 1600 break; 1601 case 7: 1602 printf(" bus: MCA+PCI, APIC: Integrated\n"); 1603 break; 1604 default: 1605 printf(" future type\n"); 1606 break; 1607 /* NOTREACHED */ 1608 } 1609#endif /* 0 */ 1610 1611 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24; 1612 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; 1613 1614 /* BSP */ 1615 CPU_TO_ID(0) = boot_cpu_id; 1616 ID_TO_CPU(boot_cpu_id) = 0; 1617 1618 /* one and only AP */ 1619 CPU_TO_ID(1) = ap_cpu_id; 1620 ID_TO_CPU(ap_cpu_id) = 1; 1621 1622#if defined(APIC_IO) 1623 /* one and only IO APIC */ 1624 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; 1625 1626 /* 1627 * sanity check, refer to MP spec section 3.6.6, last paragraph 1628 * necessary as some hardware isn't properly setting up the IO APIC 1629 */ 1630#if defined(REALLY_ANAL_IOAPICID_VALUE) 1631 if (io_apic_id != 2) { 1632#else 1633 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { 1634#endif /* REALLY_ANAL_IOAPICID_VALUE */ 1635 ux = io_apic_read(0, IOAPIC_ID); /* get current contents */ 1636 ux &= ~APIC_ID_MASK; /* clear the ID field */ 1637 ux |= 0x02000000; /* set it to '2' */ 1638 io_apic_write(0, IOAPIC_ID, ux); /* write new value */ 1639 ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */ 1640 if ((ux & APIC_ID_MASK) != 0x02000000) 1641 panic("can't control IO APIC ID, reg: 0x%08x", ux); 1642 io_apic_id = 2; 1643 } 1644 IO_TO_ID(0) = io_apic_id; 1645 ID_TO_IO(io_apic_id) = 0; 1646#endif /* APIC_IO */ 1647 1648 /* fill out bus entries */ 1649 switch (type) { 1650 case 1: 1651 case 2: 1652 case 3: 1653 case 5: 1654 case 6: 1655 bus_data[0].bus_id = default_data[type - 1][1]; 1656 bus_data[0].bus_type = default_data[type - 1][2]; 1657 bus_data[1].bus_id = default_data[type - 1][3]; 1658 bus_data[1].bus_type = default_data[type - 1][4]; 1659 break; 1660 1661 /* case 4: case 7: MCA NOT supported */ 1662 default: /* illegal/reserved */ 1663 panic("BAD default MP config: %d", type); 1664 /* NOTREACHED */ 1665 } 1666 1667#if defined(APIC_IO) 1668 /* general cases from MP v1.4, table 5-2 */ 1669 for (pin = 0; pin < 16; ++pin) { 1670 io_apic_ints[pin].int_type = 0; 1671 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */ 1672 io_apic_ints[pin].src_bus_id = 0; 1673 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */ 1674 io_apic_ints[pin].dst_apic_id = io_apic_id; 1675 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */ 1676 } 1677 1678 /* special cases from MP v1.4, table 5-2 */ 1679 if (type == 2) { 1680 io_apic_ints[2].int_type = 0xff; /* N/C */ 1681 io_apic_ints[13].int_type = 0xff; /* N/C */ 1682#if !defined(APIC_MIXED_MODE) 1683 /** FIXME: ??? */ 1684 panic("sorry, can't support type 2 default yet"); 1685#endif /* APIC_MIXED_MODE */ 1686 } 1687 else 1688 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ 1689 1690 if (type == 7) 1691 io_apic_ints[0].int_type = 0xff; /* N/C */ 1692 else 1693 io_apic_ints[0].int_type = 3; /* vectored 8259 */ 1694#endif /* APIC_IO */ 1695} 1696 1697 1698/* 1699 * initialize all the SMP locks 1700 */ 1701 1702/* critical region around IO APIC, apic_imen */ 1703struct simplelock imen_lock; 1704 1705/* critical region around splxx(), cpl, cml, cil, ipending */ 1706struct simplelock cpl_lock; 1707 1708/* Make FAST_INTR() routines sequential */ 1709struct simplelock fast_intr_lock; 1710 1711/* critical region around INTR() routines */ 1712struct simplelock intr_lock; 1713 1714/* lock regions protected in UP kernel via cli/sti */ 1715struct simplelock mpintr_lock; 1716 1717/* lock region used by kernel profiling */ 1718struct simplelock mcount_lock; 1719 1720#ifdef USE_COMLOCK 1721/* locks com (tty) data/hardware accesses: a FASTINTR() */ 1722struct simplelock com_lock; 1723#endif /* USE_COMLOCK */ 1724 1725#ifdef USE_CLOCKLOCK 1726/* lock regions around the clock hardware */ 1727struct simplelock clock_lock; 1728#endif /* USE_CLOCKLOCK */ 1729 1730static void 1731init_locks(void) 1732{ 1733 /* 1734 * Get the initial mp_lock with a count of 1 for the BSP. 1735 * This uses a LOGICAL cpu ID, ie BSP == 0. 1736 */ 1737 mp_lock = 0x00000001; 1738 1739 /* ISR uses its own "giant lock" */ 1740 isr_lock = FREE_LOCK; 1741 1742#if defined(APIC_INTR_DIAGNOSTIC) && defined(APIC_INTR_DIAGNOSTIC_IRQ) 1743 s_lock_init((struct simplelock*)&apic_itrace_debuglock); 1744#endif 1745 1746 s_lock_init((struct simplelock*)&mpintr_lock); 1747 1748 s_lock_init((struct simplelock*)&mcount_lock); 1749 1750 s_lock_init((struct simplelock*)&fast_intr_lock); 1751 s_lock_init((struct simplelock*)&intr_lock); 1752 s_lock_init((struct simplelock*)&imen_lock); 1753 s_lock_init((struct simplelock*)&cpl_lock); 1754 1755#ifdef USE_COMLOCK 1756 s_lock_init((struct simplelock*)&com_lock); 1757#endif /* USE_COMLOCK */ 1758#ifdef USE_CLOCKLOCK 1759 s_lock_init((struct simplelock*)&clock_lock); 1760#endif /* USE_CLOCKLOCK */ 1761} 1762 1763 1764/* Wait for all APs to be fully initialized */ 1765extern int wait_ap(unsigned int); 1766 1767/* 1768 * start each AP in our list 1769 */ 1770static int 1771start_all_aps(u_int boot_addr) 1772{ 1773 int x, i; 1774 u_char mpbiosreason; 1775 u_long mpbioswarmvec; 1776 pd_entry_t *newptd; 1777 pt_entry_t *newpt; 1778 struct globaldata *gd; 1779 char *stack; 1780 pd_entry_t *myPTD; 1781 1782 POSTCODE(START_ALL_APS_POST); 1783 1784 /* initialize BSP's local APIC */ 1785 apic_initialize(); 1786 bsp_apic_ready = 1; 1787 1788 /* install the AP 1st level boot code */ 1789 install_ap_tramp(boot_addr); 1790 1791 1792 /* save the current value of the warm-start vector */ 1793 mpbioswarmvec = *((u_long *) WARMBOOT_OFF); 1794#ifndef PC98 1795 outb(CMOS_REG, BIOS_RESET); 1796 mpbiosreason = inb(CMOS_DATA); 1797#endif 1798 1799 /* record BSP in CPU map */ 1800 all_cpus = 1; 1801 1802 /* start each AP */ 1803 for (x = 1; x <= mp_naps; ++x) { 1804 1805 /* This is a bit verbose, it will go away soon. */ 1806 1807 /* alloc new page table directory */ 1808 newptd = (pd_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE)); 1809 1810 /* Store the virtual PTD address for this CPU */ 1811 IdlePTDS[x] = newptd; 1812 1813 /* clone currently active one (ie: IdlePTD) */ 1814 bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */ 1815 1816 /* set up 0 -> 4MB P==V mapping for AP boot */ 1817 newptd[0] = (void *)(uintptr_t)(PG_V | PG_RW | 1818 ((uintptr_t)(void *)KPTphys & PG_FRAME)); 1819 1820 /* store PTD for this AP's boot sequence */ 1821 myPTD = (pd_entry_t *)vtophys(newptd); 1822 1823 /* alloc new page table page */ 1824 newpt = (pt_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE)); 1825 1826 /* set the new PTD's private page to point there */ 1827 newptd[MPPTDI] = (pt_entry_t)(PG_V | PG_RW | vtophys(newpt)); 1828 1829 /* install self referential entry */ 1830 newptd[PTDPTDI] = (pd_entry_t)(PG_V | PG_RW | vtophys(newptd)); 1831 1832 /* allocate a new private data page */ 1833 gd = (struct globaldata *)kmem_alloc(kernel_map, PAGE_SIZE); 1834 1835 /* wire it into the private page table page */ 1836 newpt[0] = (pt_entry_t)(PG_V | PG_RW | vtophys(gd)); 1837 1838 /* wire the ptp into itself for access */ 1839 newpt[1] = (pt_entry_t)(PG_V | PG_RW | vtophys(newpt)); 1840 1841 /* copy in the pointer to the local apic */ 1842 newpt[2] = SMP_prvpt[2]; 1843 1844 /* and the IO apic mapping[s] */ 1845 for (i = 16; i < 32; i++) 1846 newpt[i] = SMP_prvpt[i]; 1847 1848 /* allocate and set up an idle stack data page */ 1849 stack = (char *)kmem_alloc(kernel_map, UPAGES*PAGE_SIZE); 1850 for (i = 0; i < UPAGES; i++) 1851 newpt[i + 3] = (pt_entry_t)(PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 1852 1853 newpt[3 + UPAGES] = 0; /* *prv_CMAP1 */ 1854 newpt[4 + UPAGES] = 0; /* *prv_CMAP2 */ 1855 newpt[5 + UPAGES] = 0; /* *prv_CMAP3 */ 1856 newpt[6 + UPAGES] = 0; /* *prv_PMAP1 */ 1857 1858 /* prime data page for it to use */ 1859 gd->cpuid = x; 1860 gd->cpu_lockid = x << 24; 1861 gd->my_idlePTD = myPTD; 1862 gd->prv_CMAP1 = &newpt[3 + UPAGES]; 1863 gd->prv_CMAP2 = &newpt[4 + UPAGES]; 1864 gd->prv_CMAP3 = &newpt[5 + UPAGES]; 1865 gd->prv_PMAP1 = &newpt[6 + UPAGES]; 1866 1867 /* setup a vector to our boot code */ 1868 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 1869 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); 1870#ifndef PC98 1871 outb(CMOS_REG, BIOS_RESET); 1872 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 1873#endif 1874 1875 bootPTD = myPTD; 1876 /* attempt to start the Application Processor */ 1877 CHECK_INIT(99); /* setup checkpoints */ 1878 if (!start_ap(x, boot_addr)) { 1879 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); 1880 CHECK_PRINT("trace"); /* show checkpoints */ 1881 /* better panic as the AP may be running loose */ 1882 printf("panic y/n? [y] "); 1883 if (cngetc() != 'n') 1884 panic("bye-bye"); 1885 } 1886 CHECK_PRINT("trace"); /* show checkpoints */ 1887 1888 /* record its version info */ 1889 cpu_apic_versions[x] = cpu_apic_versions[0]; 1890 1891 all_cpus |= (1 << x); /* record AP in CPU map */ 1892 } 1893 1894 /* build our map of 'other' CPUs */ 1895 other_cpus = all_cpus & ~(1 << cpuid); 1896 1897 /* fill in our (BSP) APIC version */ 1898 cpu_apic_versions[0] = lapic.version; 1899 1900 /* restore the warmstart vector */ 1901 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 1902#ifndef PC98 1903 outb(CMOS_REG, BIOS_RESET); 1904 outb(CMOS_DATA, mpbiosreason); 1905#endif 1906 1907 /* 1908 * Set up the idle context for the BSP. Similar to above except 1909 * that some was done by locore, some by pmap.c and some is implicit 1910 * because the BSP is cpu#0 and the page is initially zero, and also 1911 * because we can refer to variables by name on the BSP.. 1912 */ 1913 newptd = (pd_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE)); 1914 1915 bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */ 1916 IdlePTDS[0] = newptd; 1917 1918 /* Point PTD[] to this page instead of IdlePTD's physical page */ 1919 newptd[PTDPTDI] = (pd_entry_t)(PG_V | PG_RW | vtophys(newptd)); 1920 1921 my_idlePTD = (pd_entry_t *)vtophys(newptd); 1922 1923 /* Allocate and setup BSP idle stack */ 1924 stack = (char *)kmem_alloc(kernel_map, UPAGES * PAGE_SIZE); 1925 for (i = 0; i < UPAGES; i++) 1926 SMP_prvpt[i + 3] = (pt_entry_t)(PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 1927 1928 pmap_set_opt_bsp(); 1929 1930 for (i = 0; i < mp_ncpus; i++) { 1931 bcopy( (int *) PTD + KPTDI, (int *) IdlePTDS[i] + KPTDI, NKPDE * sizeof (int)); 1932 } 1933 wait_ap(1000000); 1934 if (smp_started == 0) 1935 printf("WARNING: Failed to start all APs\n"); 1936 1937 /* number of APs actually started */ 1938 return mp_ncpus - 1; 1939} 1940 1941 1942/* 1943 * load the 1st level AP boot code into base memory. 1944 */ 1945 1946/* targets for relocation */ 1947extern void bigJump(void); 1948extern void bootCodeSeg(void); 1949extern void bootDataSeg(void); 1950extern void MPentry(void); 1951extern u_int MP_GDT; 1952extern u_int mp_gdtbase; 1953 1954static void 1955install_ap_tramp(u_int boot_addr) 1956{ 1957 int x; 1958 int size = *(int *) ((u_long) & bootMP_size); 1959 u_char *src = (u_char *) ((u_long) bootMP); 1960 u_char *dst = (u_char *) boot_addr + KERNBASE; 1961 u_int boot_base = (u_int) bootMP; 1962 u_int8_t *dst8; 1963 u_int16_t *dst16; 1964 u_int32_t *dst32; 1965 1966 POSTCODE(INSTALL_AP_TRAMP_POST); 1967 1968 for (x = 0; x < size; ++x) 1969 *dst++ = *src++; 1970 1971 /* 1972 * modify addresses in code we just moved to basemem. unfortunately we 1973 * need fairly detailed info about mpboot.s for this to work. changes 1974 * to mpboot.s might require changes here. 1975 */ 1976 1977 /* boot code is located in KERNEL space */ 1978 dst = (u_char *) boot_addr + KERNBASE; 1979 1980 /* modify the lgdt arg */ 1981 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 1982 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); 1983 1984 /* modify the ljmp target for MPentry() */ 1985 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 1986 *dst32 = ((u_int) MPentry - KERNBASE); 1987 1988 /* modify the target for boot code segment */ 1989 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 1990 dst8 = (u_int8_t *) (dst16 + 1); 1991 *dst16 = (u_int) boot_addr & 0xffff; 1992 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1993 1994 /* modify the target for boot data segment */ 1995 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 1996 dst8 = (u_int8_t *) (dst16 + 1); 1997 *dst16 = (u_int) boot_addr & 0xffff; 1998 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1999} 2000 2001 2002/* 2003 * this function starts the AP (application processor) identified 2004 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 2005 * to accomplish this. This is necessary because of the nuances 2006 * of the different hardware we might encounter. It ain't pretty, 2007 * but it seems to work. 2008 */ 2009static int 2010start_ap(int logical_cpu, u_int boot_addr) 2011{ 2012 int physical_cpu; 2013 int vector; 2014 int cpus; 2015 u_long icr_lo, icr_hi; 2016 2017 POSTCODE(START_AP_POST); 2018 2019 /* get the PHYSICAL APIC ID# */ 2020 physical_cpu = CPU_TO_ID(logical_cpu); 2021 2022 /* calculate the vector */ 2023 vector = (boot_addr >> 12) & 0xff; 2024 2025 /* used as a watchpoint to signal AP startup */ 2026 cpus = mp_ncpus; 2027 2028 /* 2029 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 2030 * and running the target CPU. OR this INIT IPI might be latched (P5 2031 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 2032 * ignored. 2033 */ 2034 2035 /* setup the address for the target AP */ 2036 icr_hi = lapic.icr_hi & ~APIC_ID_MASK; 2037 icr_hi |= (physical_cpu << 24); 2038 lapic.icr_hi = icr_hi; 2039 2040 /* do an INIT IPI: assert RESET */ 2041 icr_lo = lapic.icr_lo & 0xfff00000; 2042 lapic.icr_lo = icr_lo | 0x0000c500; 2043 2044 /* wait for pending status end */ 2045 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2046 /* spin */ ; 2047 2048 /* do an INIT IPI: deassert RESET */ 2049 lapic.icr_lo = icr_lo | 0x00008500; 2050 2051 /* wait for pending status end */ 2052 u_sleep(10000); /* wait ~10mS */ 2053 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2054 /* spin */ ; 2055 2056 /* 2057 * next we do a STARTUP IPI: the previous INIT IPI might still be 2058 * latched, (P5 bug) this 1st STARTUP would then terminate 2059 * immediately, and the previously started INIT IPI would continue. OR 2060 * the previous INIT IPI has already run. and this STARTUP IPI will 2061 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 2062 * will run. 2063 */ 2064 2065 /* do a STARTUP IPI */ 2066 lapic.icr_lo = icr_lo | 0x00000600 | vector; 2067 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2068 /* spin */ ; 2069 u_sleep(200); /* wait ~200uS */ 2070 2071 /* 2072 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 2073 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 2074 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 2075 * recognized after hardware RESET or INIT IPI. 2076 */ 2077 2078 lapic.icr_lo = icr_lo | 0x00000600 | vector; 2079 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2080 /* spin */ ; 2081 u_sleep(200); /* wait ~200uS */ 2082 2083 /* wait for it to start */ 2084 set_apic_timer(5000000);/* == 5 seconds */ 2085 while (read_apic_timer()) 2086 if (mp_ncpus > cpus) 2087 return 1; /* return SUCCESS */ 2088 2089 return 0; /* return FAILURE */ 2090} 2091 2092 2093/* 2094 * Flush the TLB on all other CPU's 2095 * 2096 * XXX: Needs to handshake and wait for completion before proceding. 2097 */ 2098void 2099smp_invltlb(void) 2100{ 2101#if defined(APIC_IO) 2102 if (smp_started && invltlb_ok) 2103 all_but_self_ipi(XINVLTLB_OFFSET); 2104#endif /* APIC_IO */ 2105} 2106 2107void 2108invlpg(u_int addr) 2109{ 2110 __asm __volatile("invlpg (%0)"::"r"(addr):"memory"); 2111 2112 /* send a message to the other CPUs */ 2113 smp_invltlb(); 2114} 2115 2116void 2117invltlb(void) 2118{ 2119 u_long temp; 2120 2121 /* 2122 * This should be implemented as load_cr3(rcr3()) when load_cr3() is 2123 * inlined. 2124 */ 2125 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory"); 2126 2127 /* send a message to the other CPUs */ 2128 smp_invltlb(); 2129} 2130 2131 2132/* 2133 * When called the executing CPU will send an IPI to all other CPUs 2134 * requesting that they halt execution. 2135 * 2136 * Usually (but not necessarily) called with 'other_cpus' as its arg. 2137 * 2138 * - Signals all CPUs in map to stop. 2139 * - Waits for each to stop. 2140 * 2141 * Returns: 2142 * -1: error 2143 * 0: NA 2144 * 1: ok 2145 * 2146 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs 2147 * from executing at same time. 2148 */ 2149int 2150stop_cpus(u_int map) 2151{ 2152 if (!smp_started) 2153 return 0; 2154 2155 /* send the Xcpustop IPI to all CPUs in map */ 2156 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED); 2157 2158 while ((stopped_cpus & map) != map) 2159 /* spin */ ; 2160 2161 return 1; 2162} 2163 2164 2165/* 2166 * Called by a CPU to restart stopped CPUs. 2167 * 2168 * Usually (but not necessarily) called with 'stopped_cpus' as its arg. 2169 * 2170 * - Signals all CPUs in map to restart. 2171 * - Waits for each to restart. 2172 * 2173 * Returns: 2174 * -1: error 2175 * 0: NA 2176 * 1: ok 2177 */ 2178int 2179restart_cpus(u_int map) 2180{ 2181 if (!smp_started) 2182 return 0; 2183 2184 started_cpus = map; /* signal other cpus to restart */ 2185 2186 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */ 2187 /* spin */ ; 2188 2189 return 1; 2190} 2191 2192int smp_active = 0; /* are the APs allowed to run? */ 2193SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RW, &smp_active, 0, ""); 2194 2195/* XXX maybe should be hw.ncpu */ 2196static int smp_cpus = 1; /* how many cpu's running */ 2197SYSCTL_INT(_machdep, OID_AUTO, smp_cpus, CTLFLAG_RD, &smp_cpus, 0, ""); 2198 2199int invltlb_ok = 0; /* throttle smp_invltlb() till safe */ 2200SYSCTL_INT(_machdep, OID_AUTO, invltlb_ok, CTLFLAG_RW, &invltlb_ok, 0, ""); 2201 2202/* Warning: Do not staticize. Used from swtch.s */ 2203int do_page_zero_idle = 1; /* bzero pages for fun and profit in idleloop */ 2204SYSCTL_INT(_machdep, OID_AUTO, do_page_zero_idle, CTLFLAG_RW, 2205 &do_page_zero_idle, 0, ""); 2206 2207/* Is forwarding of a interrupt to the CPU holding the ISR lock enabled ? */ 2208int forward_irq_enabled = 1; 2209SYSCTL_INT(_machdep, OID_AUTO, forward_irq_enabled, CTLFLAG_RW, 2210 &forward_irq_enabled, 0, ""); 2211 2212/* Enable forwarding of a signal to a process running on a different CPU */ 2213static int forward_signal_enabled = 1; 2214SYSCTL_INT(_machdep, OID_AUTO, forward_signal_enabled, CTLFLAG_RW, 2215 &forward_signal_enabled, 0, ""); 2216 2217/* Enable forwarding of roundrobin to all other cpus */ 2218static int forward_roundrobin_enabled = 1; 2219SYSCTL_INT(_machdep, OID_AUTO, forward_roundrobin_enabled, CTLFLAG_RW, 2220 &forward_roundrobin_enabled, 0, ""); 2221 2222/* 2223 * This is called once the rest of the system is up and running and we're 2224 * ready to let the AP's out of the pen. 2225 */ 2226void ap_init(void); 2227 2228void 2229ap_init() 2230{ 2231 u_int apic_id; 2232 2233 smp_cpus++; 2234 2235#if defined(I586_CPU) && !defined(NO_F00F_HACK) 2236 lidt(&r_idt); 2237#endif 2238 2239 /* Build our map of 'other' CPUs. */ 2240 other_cpus = all_cpus & ~(1 << cpuid); 2241 2242 printf("SMP: AP CPU #%d Launched!\n", cpuid); 2243 2244 /* XXX FIXME: i386 specific, and redundant: Setup the FPU. */ 2245 load_cr0((rcr0() & ~CR0_EM) | CR0_MP | CR0_NE | CR0_TS); 2246 2247 /* A quick check from sanity claus */ 2248 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]); 2249 if (cpuid != apic_id) { 2250 printf("SMP: cpuid = %d\n", cpuid); 2251 printf("SMP: apic_id = %d\n", apic_id); 2252 printf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]); 2253 panic("cpuid mismatch! boom!!"); 2254 } 2255 2256#if 0 2257 getmtrr(); 2258#endif 2259 2260 /* Init local apic for irq's */ 2261 apic_initialize(); 2262 2263 /* 2264 * Activate smp_invltlb, although strictly speaking, this isn't 2265 * quite correct yet. We should have a bitfield for cpus willing 2266 * to accept TLB flush IPI's or something and sync them. 2267 */ 2268 if (smp_cpus == mp_ncpus) { 2269 invltlb_ok = 1; 2270 smp_started = 1; /* enable IPI's, tlb shootdown, freezes etc */ 2271 smp_active = 1; /* historic */ 2272 } 2273 2274 curproc = NULL; /* make sure */ 2275} 2276 2277#ifdef BETTER_CLOCK 2278 2279#define CHECKSTATE_USER 0 2280#define CHECKSTATE_SYS 1 2281#define CHECKSTATE_INTR 2 2282 2283/* Do not staticize. Used from apic_vector.s */ 2284struct proc* checkstate_curproc[NCPU]; 2285int checkstate_cpustate[NCPU]; 2286u_long checkstate_pc[NCPU]; 2287 2288extern long cp_time[CPUSTATES]; 2289 2290#define PC_TO_INDEX(pc, prof) \ 2291 ((int)(((u_quad_t)((pc) - (prof)->pr_off) * \ 2292 (u_quad_t)((prof)->pr_scale)) >> 16) & ~1) 2293 2294static void 2295addupc_intr_forwarded(struct proc *p, int id, int *astmap) 2296{ 2297 int i; 2298 struct uprof *prof; 2299 u_long pc; 2300 2301 pc = checkstate_pc[id]; 2302 prof = &p->p_stats->p_prof; 2303 if (pc >= prof->pr_off && 2304 (i = PC_TO_INDEX(pc, prof)) < prof->pr_size) { 2305 if ((p->p_flag & P_OWEUPC) == 0) { 2306 prof->pr_addr = pc; 2307 prof->pr_ticks = 1; 2308 p->p_flag |= P_OWEUPC; 2309 } 2310 *astmap |= (1 << id); 2311 } 2312} 2313 2314static void 2315forwarded_statclock(int id, int pscnt, int *astmap) 2316{ 2317 struct pstats *pstats; 2318 long rss; 2319 struct rusage *ru; 2320 struct vmspace *vm; 2321 int cpustate; 2322 struct proc *p; 2323#ifdef GPROF 2324 register struct gmonparam *g; 2325 int i; 2326#endif 2327 2328 p = checkstate_curproc[id]; 2329 cpustate = checkstate_cpustate[id]; 2330 2331 switch (cpustate) { 2332 case CHECKSTATE_USER: 2333 if (p->p_flag & P_PROFIL) 2334 addupc_intr_forwarded(p, id, astmap); 2335 if (pscnt > 1) 2336 return; 2337 p->p_uticks++; 2338 if (p->p_nice > NZERO) 2339 cp_time[CP_NICE]++; 2340 else 2341 cp_time[CP_USER]++; 2342 break; 2343 case CHECKSTATE_SYS: 2344#ifdef GPROF 2345 /* 2346 * Kernel statistics are just like addupc_intr, only easier. 2347 */ 2348 g = &_gmonparam; 2349 if (g->state == GMON_PROF_ON) { 2350 i = checkstate_pc[id] - g->lowpc; 2351 if (i < g->textsize) { 2352 i /= HISTFRACTION * sizeof(*g->kcount); 2353 g->kcount[i]++; 2354 } 2355 } 2356#endif 2357 if (pscnt > 1) 2358 return; 2359 2360 if (!p) 2361 cp_time[CP_IDLE]++; 2362 else { 2363 p->p_sticks++; 2364 cp_time[CP_SYS]++; 2365 } 2366 break; 2367 case CHECKSTATE_INTR: 2368 default: 2369#ifdef GPROF 2370 /* 2371 * Kernel statistics are just like addupc_intr, only easier. 2372 */ 2373 g = &_gmonparam; 2374 if (g->state == GMON_PROF_ON) { 2375 i = checkstate_pc[id] - g->lowpc; 2376 if (i < g->textsize) { 2377 i /= HISTFRACTION * sizeof(*g->kcount); 2378 g->kcount[i]++; 2379 } 2380 } 2381#endif 2382 if (pscnt > 1) 2383 return; 2384 if (p) 2385 p->p_iticks++; 2386 cp_time[CP_INTR]++; 2387 } 2388 if (p != NULL) { 2389 p->p_cpticks++; 2390 if (++p->p_estcpu == 0) 2391 p->p_estcpu--; 2392 if ((p->p_estcpu & 3) == 0) { 2393 resetpriority(p); 2394 if (p->p_priority >= PUSER) 2395 p->p_priority = p->p_usrpri; 2396 } 2397 2398 /* Update resource usage integrals and maximums. */ 2399 if ((pstats = p->p_stats) != NULL && 2400 (ru = &pstats->p_ru) != NULL && 2401 (vm = p->p_vmspace) != NULL) { 2402 ru->ru_ixrss += pgtok(vm->vm_tsize); 2403 ru->ru_idrss += pgtok(vm->vm_dsize); 2404 ru->ru_isrss += pgtok(vm->vm_ssize); 2405 rss = pgtok(vmspace_resident_count(vm)); 2406 if (ru->ru_maxrss < rss) 2407 ru->ru_maxrss = rss; 2408 } 2409 } 2410} 2411 2412void 2413forward_statclock(int pscnt) 2414{ 2415 int map; 2416 int id; 2417 int i; 2418 2419 /* Kludge. We don't yet have separate locks for the interrupts 2420 * and the kernel. This means that we cannot let the other processors 2421 * handle complex interrupts while inhibiting them from entering 2422 * the kernel in a non-interrupt context. 2423 * 2424 * What we can do, without changing the locking mechanisms yet, 2425 * is letting the other processors handle a very simple interrupt 2426 * (wich determines the processor states), and do the main 2427 * work ourself. 2428 */ 2429 2430 if (!smp_started || !invltlb_ok || cold || panicstr) 2431 return; 2432 2433 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle ) */ 2434 2435 map = other_cpus & ~stopped_cpus ; 2436 checkstate_probed_cpus = 0; 2437 if (map != 0) 2438 selected_apic_ipi(map, 2439 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED); 2440 2441 i = 0; 2442 while (checkstate_probed_cpus != map) { 2443 /* spin */ 2444 i++; 2445 if (i == 100000) { 2446#ifdef BETTER_CLOCK_DIAGNOSTIC 2447 printf("forward_statclock: checkstate %x\n", 2448 checkstate_probed_cpus); 2449#endif 2450 break; 2451 } 2452 } 2453 2454 /* 2455 * Step 2: walk through other processors processes, update ticks and 2456 * profiling info. 2457 */ 2458 2459 map = 0; 2460 for (id = 0; id < mp_ncpus; id++) { 2461 if (id == cpuid) 2462 continue; 2463 if (((1 << id) & checkstate_probed_cpus) == 0) 2464 continue; 2465 forwarded_statclock(id, pscnt, &map); 2466 } 2467 if (map != 0) { 2468 checkstate_need_ast |= map; 2469 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED); 2470 i = 0; 2471 while ((checkstate_need_ast & map) != 0) { 2472 /* spin */ 2473 i++; 2474 if (i > 100000) { 2475#ifdef BETTER_CLOCK_DIAGNOSTIC 2476 printf("forward_statclock: dropped ast 0x%x\n", 2477 checkstate_need_ast & map); 2478#endif 2479 break; 2480 } 2481 } 2482 } 2483} 2484 2485void 2486forward_hardclock(int pscnt) 2487{ 2488 int map; 2489 int id; 2490 struct proc *p; 2491 struct pstats *pstats; 2492 int i; 2493 2494 /* Kludge. We don't yet have separate locks for the interrupts 2495 * and the kernel. This means that we cannot let the other processors 2496 * handle complex interrupts while inhibiting them from entering 2497 * the kernel in a non-interrupt context. 2498 * 2499 * What we can do, without changing the locking mechanisms yet, 2500 * is letting the other processors handle a very simple interrupt 2501 * (wich determines the processor states), and do the main 2502 * work ourself. 2503 */ 2504 2505 if (!smp_started || !invltlb_ok || cold || panicstr) 2506 return; 2507 2508 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle) */ 2509 2510 map = other_cpus & ~stopped_cpus ; 2511 checkstate_probed_cpus = 0; 2512 if (map != 0) 2513 selected_apic_ipi(map, 2514 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED); 2515 2516 i = 0; 2517 while (checkstate_probed_cpus != map) { 2518 /* spin */ 2519 i++; 2520 if (i == 100000) { 2521#ifdef BETTER_CLOCK_DIAGNOSTIC 2522 printf("forward_hardclock: checkstate %x\n", 2523 checkstate_probed_cpus); 2524#endif 2525 break; 2526 } 2527 } 2528 2529 /* 2530 * Step 2: walk through other processors processes, update virtual 2531 * timer and profiling timer. If stathz == 0, also update ticks and 2532 * profiling info. 2533 */ 2534 2535 map = 0; 2536 for (id = 0; id < mp_ncpus; id++) { 2537 if (id == cpuid) 2538 continue; 2539 if (((1 << id) & checkstate_probed_cpus) == 0) 2540 continue; 2541 p = checkstate_curproc[id]; 2542 if (p) { 2543 pstats = p->p_stats; 2544 if (checkstate_cpustate[id] == CHECKSTATE_USER && 2545 timevalisset(&pstats->p_timer[ITIMER_VIRTUAL].it_value) && 2546 itimerdecr(&pstats->p_timer[ITIMER_VIRTUAL], tick) == 0) { 2547 psignal(p, SIGVTALRM); 2548 map |= (1 << id); 2549 } 2550 if (timevalisset(&pstats->p_timer[ITIMER_PROF].it_value) && 2551 itimerdecr(&pstats->p_timer[ITIMER_PROF], tick) == 0) { 2552 psignal(p, SIGPROF); 2553 map |= (1 << id); 2554 } 2555 } 2556 if (stathz == 0) { 2557 forwarded_statclock( id, pscnt, &map); 2558 } 2559 } 2560 if (map != 0) { 2561 checkstate_need_ast |= map; 2562 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED); 2563 i = 0; 2564 while ((checkstate_need_ast & map) != 0) { 2565 /* spin */ 2566 i++; 2567 if (i > 100000) { 2568#ifdef BETTER_CLOCK_DIAGNOSTIC 2569 printf("forward_hardclock: dropped ast 0x%x\n", 2570 checkstate_need_ast & map); 2571#endif 2572 break; 2573 } 2574 } 2575 } 2576} 2577 2578#endif /* BETTER_CLOCK */ 2579 2580void 2581forward_signal(struct proc *p) 2582{ 2583 int map; 2584 int id; 2585 int i; 2586 2587 /* Kludge. We don't yet have separate locks for the interrupts 2588 * and the kernel. This means that we cannot let the other processors 2589 * handle complex interrupts while inhibiting them from entering 2590 * the kernel in a non-interrupt context. 2591 * 2592 * What we can do, without changing the locking mechanisms yet, 2593 * is letting the other processors handle a very simple interrupt 2594 * (wich determines the processor states), and do the main 2595 * work ourself. 2596 */ 2597 2598 if (!smp_started || !invltlb_ok || cold || panicstr) 2599 return; 2600 if (!forward_signal_enabled) 2601 return; 2602 while (1) { 2603 if (p->p_stat != SRUN) 2604 return; 2605 id = p->p_oncpu; 2606 if (id == 0xff) 2607 return; 2608 map = (1<<id); 2609 checkstate_need_ast |= map; 2610 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED); 2611 i = 0; 2612 while ((checkstate_need_ast & map) != 0) { 2613 /* spin */ 2614 i++; 2615 if (i > 100000) { 2616#if 0 2617 printf("forward_signal: dropped ast 0x%x\n", 2618 checkstate_need_ast & map); 2619#endif 2620 break; 2621 } 2622 } 2623 if (id == p->p_oncpu) 2624 return; 2625 } 2626} 2627 2628void 2629forward_roundrobin(void) 2630{ 2631 u_int map; 2632 int i; 2633 2634 if (!smp_started || !invltlb_ok || cold || panicstr) 2635 return; 2636 if (!forward_roundrobin_enabled) 2637 return; 2638 resched_cpus |= other_cpus; 2639 map = other_cpus & ~stopped_cpus ; 2640#if 1 2641 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED); 2642#else 2643 (void) all_but_self_ipi(XCPUAST_OFFSET); 2644#endif 2645 i = 0; 2646 while ((checkstate_need_ast & map) != 0) { 2647 /* spin */ 2648 i++; 2649 if (i > 100000) { 2650#if 0 2651 printf("forward_roundrobin: dropped ast 0x%x\n", 2652 checkstate_need_ast & map); 2653#endif 2654 break; 2655 } 2656 } 2657} 2658 2659 2660#ifdef APIC_INTR_REORDER 2661/* 2662 * Maintain mapping from softintr vector to isr bit in local apic. 2663 */ 2664void 2665set_lapic_isrloc(int intr, int vector) 2666{ 2667 if (intr < 0 || intr > 32) 2668 panic("set_apic_isrloc: bad intr argument: %d",intr); 2669 if (vector < ICU_OFFSET || vector > 255) 2670 panic("set_apic_isrloc: bad vector argument: %d",vector); 2671 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2); 2672 apic_isrbit_location[intr].bit = (1<<(vector & 31)); 2673} 2674#endif 2675