mptable.c revision 34990
1/* 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $Id: mp_machdep.c,v 1.70 1998/03/07 20:16:49 tegge Exp $ 26 */ 27 28#include "opt_smp.h" 29#include "opt_vm86.h" 30#include "opt_cpu.h" 31 32#ifdef SMP 33#include <machine/smptests.h> 34#else 35#error 36#endif 37 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/kernel.h> 41#include <sys/proc.h> 42#include <sys/sysctl.h> 43#ifdef BETTER_CLOCK 44#include <sys/dkstat.h> 45#endif 46 47#include <vm/vm.h> 48#include <vm/vm_param.h> 49#include <vm/pmap.h> 50#include <vm/vm_kern.h> 51#include <vm/vm_extern.h> 52#ifdef BETTER_CLOCK 53#include <sys/lock.h> 54#include <vm/vm_map.h> 55#include <sys/user.h> 56#ifdef GPROF 57#include <sys/gmon.h> 58#endif 59#endif 60 61#include <machine/smp.h> 62#include <machine/apic.h> 63#include <machine/mpapic.h> 64#include <machine/segments.h> 65#include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */ 66#include <machine/tss.h> 67#include <machine/specialreg.h> 68#include <machine/cputypes.h> 69 70#include <i386/i386/cons.h> /* cngetc() */ 71 72#if defined(APIC_IO) 73#include <machine/md_var.h> /* setidt() */ 74#include <i386/isa/icu.h> /* IPIs */ 75#include <i386/isa/intr_machdep.h> /* IPIs */ 76#endif /* APIC_IO */ 77 78#if defined(TEST_DEFAULT_CONFIG) 79#define MPFPS_MPFB1 TEST_DEFAULT_CONFIG 80#else 81#define MPFPS_MPFB1 mpfps->mpfb1 82#endif /* TEST_DEFAULT_CONFIG */ 83 84#define WARMBOOT_TARGET 0 85#define WARMBOOT_OFF (KERNBASE + 0x0467) 86#define WARMBOOT_SEG (KERNBASE + 0x0469) 87 88#define BIOS_BASE (0xf0000) 89#define BIOS_SIZE (0x10000) 90#define BIOS_COUNT (BIOS_SIZE/4) 91 92#define CMOS_REG (0x70) 93#define CMOS_DATA (0x71) 94#define BIOS_RESET (0x0f) 95#define BIOS_WARM (0x0a) 96 97#define PROCENTRY_FLAG_EN 0x01 98#define PROCENTRY_FLAG_BP 0x02 99#define IOAPICENTRY_FLAG_EN 0x01 100 101 102/* MP Floating Pointer Structure */ 103typedef struct MPFPS { 104 char signature[4]; 105 void *pap; 106 u_char length; 107 u_char spec_rev; 108 u_char checksum; 109 u_char mpfb1; 110 u_char mpfb2; 111 u_char mpfb3; 112 u_char mpfb4; 113 u_char mpfb5; 114} *mpfps_t; 115 116/* MP Configuration Table Header */ 117typedef struct MPCTH { 118 char signature[4]; 119 u_short base_table_length; 120 u_char spec_rev; 121 u_char checksum; 122 u_char oem_id[8]; 123 u_char product_id[12]; 124 void *oem_table_pointer; 125 u_short oem_table_size; 126 u_short entry_count; 127 void *apic_address; 128 u_short extended_table_length; 129 u_char extended_table_checksum; 130 u_char reserved; 131} *mpcth_t; 132 133 134typedef struct PROCENTRY { 135 u_char type; 136 u_char apic_id; 137 u_char apic_version; 138 u_char cpu_flags; 139 u_long cpu_signature; 140 u_long feature_flags; 141 u_long reserved1; 142 u_long reserved2; 143} *proc_entry_ptr; 144 145typedef struct BUSENTRY { 146 u_char type; 147 u_char bus_id; 148 char bus_type[6]; 149} *bus_entry_ptr; 150 151typedef struct IOAPICENTRY { 152 u_char type; 153 u_char apic_id; 154 u_char apic_version; 155 u_char apic_flags; 156 void *apic_address; 157} *io_apic_entry_ptr; 158 159typedef struct INTENTRY { 160 u_char type; 161 u_char int_type; 162 u_short int_flags; 163 u_char src_bus_id; 164 u_char src_bus_irq; 165 u_char dst_apic_id; 166 u_char dst_apic_int; 167} *int_entry_ptr; 168 169/* descriptions of MP basetable entries */ 170typedef struct BASETABLE_ENTRY { 171 u_char type; 172 u_char length; 173 char name[16]; 174} basetable_entry; 175 176/* 177 * this code MUST be enabled here and in mpboot.s. 178 * it follows the very early stages of AP boot by placing values in CMOS ram. 179 * it NORMALLY will never be needed and thus the primitive method for enabling. 180 * 181#define CHECK_POINTS 182 */ 183 184#if defined(CHECK_POINTS) 185#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 186#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 187 188#define CHECK_INIT(D); \ 189 CHECK_WRITE(0x34, (D)); \ 190 CHECK_WRITE(0x35, (D)); \ 191 CHECK_WRITE(0x36, (D)); \ 192 CHECK_WRITE(0x37, (D)); \ 193 CHECK_WRITE(0x38, (D)); \ 194 CHECK_WRITE(0x39, (D)); 195 196#define CHECK_PRINT(S); \ 197 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 198 (S), \ 199 CHECK_READ(0x34), \ 200 CHECK_READ(0x35), \ 201 CHECK_READ(0x36), \ 202 CHECK_READ(0x37), \ 203 CHECK_READ(0x38), \ 204 CHECK_READ(0x39)); 205 206#else /* CHECK_POINTS */ 207 208#define CHECK_INIT(D) 209#define CHECK_PRINT(S) 210 211#endif /* CHECK_POINTS */ 212 213/* 214 * Values to send to the POST hardware. 215 */ 216#define MP_BOOTADDRESS_POST 0x10 217#define MP_PROBE_POST 0x11 218#define MPTABLE_PASS1_POST 0x12 219 220#define MP_START_POST 0x13 221#define MP_ENABLE_POST 0x14 222#define MPTABLE_PASS2_POST 0x15 223 224#define START_ALL_APS_POST 0x16 225#define INSTALL_AP_TRAMP_POST 0x17 226#define START_AP_POST 0x18 227 228#define MP_ANNOUNCE_POST 0x19 229 230 231/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ 232int current_postcode; 233 234/** XXX FIXME: what system files declare these??? */ 235extern struct region_descriptor r_gdt, r_idt; 236 237int bsp_apic_ready = 0; /* flags useability of BSP apic */ 238int mp_ncpus; /* # of CPUs, including BSP */ 239int mp_naps; /* # of Applications processors */ 240int mp_nbusses; /* # of busses */ 241int mp_napics; /* # of IO APICs */ 242int boot_cpu_id; /* designated BSP */ 243vm_offset_t cpu_apic_address; 244vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */ 245extern int nkpt; 246 247u_int32_t cpu_apic_versions[NCPU]; 248u_int32_t io_apic_versions[NAPIC]; 249 250#ifdef APIC_INTR_DIAGNOSTIC 251int apic_itrace_enter[32]; 252int apic_itrace_tryisrlock[32]; 253int apic_itrace_gotisrlock[32]; 254int apic_itrace_active[32]; 255int apic_itrace_masked[32]; 256int apic_itrace_noisrlock[32]; 257int apic_itrace_masked2[32]; 258int apic_itrace_unmask[32]; 259int apic_itrace_noforward[32]; 260int apic_itrace_leave[32]; 261int apic_itrace_enter2[32]; 262int apic_itrace_doreti[32]; 263int apic_itrace_splz[32]; 264int apic_itrace_eoi[32]; 265#ifdef APIC_INTR_DIAGNOSTIC_IRQ 266unsigned short apic_itrace_debugbuffer[32768]; 267int apic_itrace_debugbuffer_idx; 268struct simplelock apic_itrace_debuglock; 269#endif 270#endif 271 272#ifdef APIC_INTR_REORDER 273struct { 274 volatile int *location; 275 int bit; 276} apic_isrbit_location[32]; 277#endif 278 279/* 280 * APIC ID logical/physical mapping structures. 281 * We oversize these to simplify boot-time config. 282 */ 283int cpu_num_to_apic_id[NAPICID]; 284int io_num_to_apic_id[NAPICID]; 285int apic_id_to_logical[NAPICID]; 286 287 288#define NPPROVMTRR 8 289#define PPRO_VMTRRphysBase0 0x200 290#define PPRO_VMTRRphysMask0 0x201 291static struct { 292 u_int64_t base, mask; 293} PPro_vmtrr[NPPROVMTRR]; 294 295/* Bitmap of all available CPUs */ 296u_int all_cpus; 297 298/* AP uses this PTD during bootstrap. Do not staticize. */ 299pd_entry_t *bootPTD; 300 301/* Hotwire a 0->4MB V==P mapping */ 302extern pt_entry_t *KPTphys; 303 304/* Virtual address of per-cpu common_tss */ 305extern struct i386tss common_tss; 306#ifdef VM86 307extern struct segment_descriptor common_tssd; 308extern u_int private_tss; /* flag indicating private tss */ 309extern u_int my_tr; 310#endif /* VM86 */ 311 312/* IdlePTD per cpu */ 313pd_entry_t *IdlePTDS[NCPU]; 314 315/* "my" private page table page, for BSP init */ 316extern pt_entry_t SMP_prvpt[]; 317 318/* Private page pointer to curcpu's PTD, used during BSP init */ 319extern pd_entry_t *my_idlePTD; 320 321static int smp_started; /* has the system started? */ 322 323/* 324 * Local data and functions. 325 */ 326 327static int mp_capable; 328static u_int boot_address; 329static u_int base_memory; 330 331static int picmode; /* 0: virtual wire mode, 1: PIC mode */ 332static mpfps_t mpfps; 333static int search_for_sig(u_int32_t target, int count); 334static void mp_enable(u_int boot_addr); 335 336static int mptable_pass1(void); 337static int mptable_pass2(void); 338static void default_mp_table(int type); 339static void fix_mp_table(void); 340static void init_locks(void); 341static int start_all_aps(u_int boot_addr); 342static void install_ap_tramp(u_int boot_addr); 343static int start_ap(int logicalCpu, u_int boot_addr); 344static void getmtrr(void); 345static void putmtrr(void); 346static void putfmtrr(void); 347 348 349/* 350 * Calculate usable address in base memory for AP trampoline code. 351 */ 352u_int 353mp_bootaddress(u_int basemem) 354{ 355 POSTCODE(MP_BOOTADDRESS_POST); 356 357 base_memory = basemem * 1024; /* convert to bytes */ 358 359 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ 360 if ((base_memory - boot_address) < bootMP_size) 361 boot_address -= 4096; /* not enough, lower by 4k */ 362 363 return boot_address; 364} 365 366 367/* 368 * Look for an Intel MP spec table (ie, SMP capable hardware). 369 */ 370int 371mp_probe(void) 372{ 373 int x; 374 u_long segment; 375 u_int32_t target; 376 377 POSTCODE(MP_PROBE_POST); 378 379 /* see if EBDA exists */ 380 if (segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) { 381 /* search first 1K of EBDA */ 382 target = (u_int32_t) (segment << 4); 383 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 384 goto found; 385 } else { 386 /* last 1K of base memory, effective 'top of base' passed in */ 387 target = (u_int32_t) (base_memory - 0x400); 388 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 389 goto found; 390 } 391 392 /* search the BIOS */ 393 target = (u_int32_t) BIOS_BASE; 394 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) 395 goto found; 396 397 /* nothing found */ 398 mpfps = (mpfps_t)0; 399 mp_capable = 0; 400 return 0; 401 402found: 403 /* calculate needed resources */ 404 mpfps = (mpfps_t)x; 405 if (mptable_pass1()) 406 panic("you must reconfigure your kernel"); 407 408 /* flag fact that we are running multiple processors */ 409 mp_capable = 1; 410 return 1; 411} 412 413 414/* 415 * Startup the SMP processors. 416 */ 417void 418mp_start(void) 419{ 420 POSTCODE(MP_START_POST); 421 422 /* look for MP capable motherboard */ 423 if (mp_capable) 424 mp_enable(boot_address); 425 else 426 panic("MP hardware not found!"); 427} 428 429 430/* 431 * Print various information about the SMP system hardware and setup. 432 */ 433void 434mp_announce(void) 435{ 436 int x; 437 438 POSTCODE(MP_ANNOUNCE_POST); 439 440 printf("FreeBSD/SMP: Multiprocessor motherboard\n"); 441 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0)); 442 printf(", version: 0x%08x", cpu_apic_versions[0]); 443 printf(", at 0x%08x\n", cpu_apic_address); 444 for (x = 1; x <= mp_naps; ++x) { 445 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x)); 446 printf(", version: 0x%08x", cpu_apic_versions[x]); 447 printf(", at 0x%08x\n", cpu_apic_address); 448 } 449 450#if defined(APIC_IO) 451 for (x = 0; x < mp_napics; ++x) { 452 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x)); 453 printf(", version: 0x%08x", io_apic_versions[x]); 454 printf(", at 0x%08x\n", io_apic_address[x]); 455 } 456#else 457 printf(" Warning: APIC I/O disabled\n"); 458#endif /* APIC_IO */ 459} 460 461/* 462 * AP cpu's call this to sync up protected mode. 463 */ 464void 465init_secondary(void) 466{ 467 int gsel_tss; 468#ifndef VM86 469 u_int my_tr; 470#endif 471 472 r_gdt.rd_limit = sizeof(gdt[0]) * (NGDT + NCPU) - 1; 473 r_gdt.rd_base = (int) gdt; 474 lgdt(&r_gdt); /* does magic intra-segment return */ 475 lidt(&r_idt); 476 lldt(_default_ldt); 477 478 my_tr = NGDT + cpuid; 479 gsel_tss = GSEL(my_tr, SEL_KPL); 480 gdt[my_tr].sd.sd_type = SDT_SYS386TSS; 481 common_tss.tss_esp0 = 0; /* not used until after switch */ 482 common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 483 common_tss.tss_ioopt = (sizeof common_tss) << 16; 484#ifdef VM86 485 common_tssd = gdt[my_tr].sd; 486 private_tss = 0; 487#endif /* VM86 */ 488 ltr(gsel_tss); 489 490 load_cr0(0x8005003b); /* XXX! */ 491 492 PTD[0] = 0; 493 pmap_set_opt((unsigned *)PTD); 494 495 putmtrr(); 496 putfmtrr(); 497 498 invltlb(); 499} 500 501 502#if defined(APIC_IO) 503/* 504 * Final configuration of the BSP's local APIC: 505 * - disable 'pic mode'. 506 * - disable 'virtual wire mode'. 507 * - enable NMI. 508 */ 509void 510bsp_apic_configure(void) 511{ 512 u_char byte; 513 u_int32_t temp; 514 515 /* leave 'pic mode' if necessary */ 516 if (picmode) { 517 outb(0x22, 0x70); /* select IMCR */ 518 byte = inb(0x23); /* current contents */ 519 byte |= 0x01; /* mask external INTR */ 520 outb(0x23, byte); /* disconnect 8259s/NMI */ 521 } 522 523 /* mask lint0 (the 8259 'virtual wire' connection) */ 524 temp = lapic.lvt_lint0; 525 temp |= APIC_LVT_M; /* set the mask */ 526 lapic.lvt_lint0 = temp; 527 528 /* setup lint1 to handle NMI */ 529 temp = lapic.lvt_lint1; 530 temp &= ~APIC_LVT_M; /* clear the mask */ 531 lapic.lvt_lint1 = temp; 532 533 if (bootverbose) 534 apic_dump("bsp_apic_configure()"); 535} 536#endif /* APIC_IO */ 537 538 539/******************************************************************* 540 * local functions and data 541 */ 542 543/* 544 * start the SMP system 545 */ 546static void 547mp_enable(u_int boot_addr) 548{ 549 int x; 550#if defined(APIC_IO) 551 int apic; 552 u_int ux; 553#endif /* APIC_IO */ 554 555 getmtrr(); 556 putfmtrr(); 557 558 POSTCODE(MP_ENABLE_POST); 559 560 /* turn on 4MB of V == P addressing so we can get to MP table */ 561 *(int *)PTD = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME); 562 invltlb(); 563 564 /* examine the MP table for needed info, uses physical addresses */ 565 x = mptable_pass2(); 566 567 *(int *)PTD = 0; 568 invltlb(); 569 570 /* can't process default configs till the CPU APIC is pmapped */ 571 if (x) 572 default_mp_table(x); 573 574 /* post scan cleanup */ 575 fix_mp_table(); 576 577#if defined(APIC_IO) 578 579 /* fill the LOGICAL io_apic_versions table */ 580 for (apic = 0; apic < mp_napics; ++apic) { 581 ux = io_apic_read(apic, IOAPIC_VER); 582 io_apic_versions[apic] = ux; 583 } 584 585 /* program each IO APIC in the system */ 586 for (apic = 0; apic < mp_napics; ++apic) 587 if (io_apic_setup(apic) < 0) 588 panic("IO APIC setup failure"); 589 590 /* install a 'Spurious INTerrupt' vector */ 591 setidt(XSPURIOUSINT_OFFSET, Xspuriousint, 592 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 593 594 /* install an inter-CPU IPI for TLB invalidation */ 595 setidt(XINVLTLB_OFFSET, Xinvltlb, 596 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 597 598#ifdef BETTER_CLOCK 599 /* install an inter-CPU IPI for reading processor state */ 600 setidt(XCPUCHECKSTATE_OFFSET, Xcpucheckstate, 601 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 602#endif 603 604 /* install an inter-CPU IPI for forcing an additional software trap */ 605 setidt(XCPUAST_OFFSET, Xcpuast, 606 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 607 608 /* install an inter-CPU IPI for interrupt forwarding */ 609 setidt(XFORWARD_IRQ_OFFSET, Xforward_irq, 610 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 611 612 /* install an inter-CPU IPI for CPU stop/restart */ 613 setidt(XCPUSTOP_OFFSET, Xcpustop, 614 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 615 616#if defined(TEST_TEST1) 617 /* install a "fake hardware INTerrupt" vector */ 618 setidt(XTEST1_OFFSET, Xtest1, 619 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 620#endif /** TEST_TEST1 */ 621 622#endif /* APIC_IO */ 623 624 /* initialize all SMP locks */ 625 init_locks(); 626 627 /* start each Application Processor */ 628 start_all_aps(boot_addr); 629 630 /* 631 * The init process might be started on a different CPU now, 632 * and the boot CPU might not call prepare_usermode to get 633 * cr0 correctly configured. Thus we initialize cr0 here. 634 */ 635 load_cr0(rcr0() | CR0_WP | CR0_AM); 636} 637 638 639/* 640 * look for the MP spec signature 641 */ 642 643/* string defined by the Intel MP Spec as identifying the MP table */ 644#define MP_SIG 0x5f504d5f /* _MP_ */ 645#define NEXT(X) ((X) += 4) 646static int 647search_for_sig(u_int32_t target, int count) 648{ 649 int x; 650 u_int32_t *addr = (u_int32_t *) (KERNBASE + target); 651 652 for (x = 0; x < count; NEXT(x)) 653 if (addr[x] == MP_SIG) 654 /* make array index a byte index */ 655 return (target + (x * sizeof(u_int32_t))); 656 657 return -1; 658} 659 660 661static basetable_entry basetable_entry_types[] = 662{ 663 {0, 20, "Processor"}, 664 {1, 8, "Bus"}, 665 {2, 8, "I/O APIC"}, 666 {3, 8, "I/O INT"}, 667 {4, 8, "Local INT"} 668}; 669 670typedef struct BUSDATA { 671 u_char bus_id; 672 enum busTypes bus_type; 673} bus_datum; 674 675typedef struct INTDATA { 676 u_char int_type; 677 u_short int_flags; 678 u_char src_bus_id; 679 u_char src_bus_irq; 680 u_char dst_apic_id; 681 u_char dst_apic_int; 682} io_int, local_int; 683 684typedef struct BUSTYPENAME { 685 u_char type; 686 char name[7]; 687} bus_type_name; 688 689static bus_type_name bus_type_table[] = 690{ 691 {CBUS, "CBUS"}, 692 {CBUSII, "CBUSII"}, 693 {EISA, "EISA"}, 694 {UNKNOWN_BUSTYPE, "---"}, 695 {UNKNOWN_BUSTYPE, "---"}, 696 {ISA, "ISA"}, 697 {UNKNOWN_BUSTYPE, "---"}, 698 {UNKNOWN_BUSTYPE, "---"}, 699 {UNKNOWN_BUSTYPE, "---"}, 700 {UNKNOWN_BUSTYPE, "---"}, 701 {UNKNOWN_BUSTYPE, "---"}, 702 {UNKNOWN_BUSTYPE, "---"}, 703 {PCI, "PCI"}, 704 {UNKNOWN_BUSTYPE, "---"}, 705 {UNKNOWN_BUSTYPE, "---"}, 706 {UNKNOWN_BUSTYPE, "---"}, 707 {UNKNOWN_BUSTYPE, "---"}, 708 {XPRESS, "XPRESS"}, 709 {UNKNOWN_BUSTYPE, "---"} 710}; 711/* from MP spec v1.4, table 5-1 */ 712static int default_data[7][5] = 713{ 714/* nbus, id0, type0, id1, type1 */ 715 {1, 0, ISA, 255, 255}, 716 {1, 0, EISA, 255, 255}, 717 {1, 0, EISA, 255, 255}, 718 {0, 255, 255, 255, 255},/* MCA not supported */ 719 {2, 0, ISA, 1, PCI}, 720 {2, 0, EISA, 1, PCI}, 721 {0, 255, 255, 255, 255} /* MCA not supported */ 722}; 723 724 725/* the bus data */ 726static bus_datum bus_data[NBUS]; 727 728/* the IO INT data, one entry per possible APIC INTerrupt */ 729static io_int io_apic_ints[NINTR]; 730 731static int nintrs; 732 733static int processor_entry __P((proc_entry_ptr entry, int cpu)); 734static int bus_entry __P((bus_entry_ptr entry, int bus)); 735static int io_apic_entry __P((io_apic_entry_ptr entry, int apic)); 736static int int_entry __P((int_entry_ptr entry, int intr)); 737static int lookup_bus_type __P((char *name)); 738 739 740/* 741 * 1st pass on motherboard's Intel MP specification table. 742 * 743 * initializes: 744 * mp_ncpus = 1 745 * 746 * determines: 747 * cpu_apic_address (common to all CPUs) 748 * io_apic_address[N] 749 * mp_naps 750 * mp_nbusses 751 * mp_napics 752 * nintrs 753 */ 754static int 755mptable_pass1(void) 756{ 757 int x; 758 mpcth_t cth; 759 int totalSize; 760 void* position; 761 int count; 762 int type; 763 int mustpanic; 764 765 POSTCODE(MPTABLE_PASS1_POST); 766 767 mustpanic = 0; 768 769 /* clear various tables */ 770 for (x = 0; x < NAPICID; ++x) { 771 io_apic_address[x] = ~0; /* IO APIC address table */ 772 } 773 774 /* init everything to empty */ 775 mp_naps = 0; 776 mp_nbusses = 0; 777 mp_napics = 0; 778 nintrs = 0; 779 780 /* check for use of 'default' configuration */ 781 if (MPFPS_MPFB1 != 0) { 782 /* use default addresses */ 783 cpu_apic_address = DEFAULT_APIC_BASE; 784 io_apic_address[0] = DEFAULT_IO_APIC_BASE; 785 786 /* fill in with defaults */ 787 mp_naps = 2; /* includes BSP */ 788 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0]; 789#if defined(APIC_IO) 790 mp_napics = 1; 791 nintrs = 16; 792#endif /* APIC_IO */ 793 } 794 else { 795 if ((cth = mpfps->pap) == 0) 796 panic("MP Configuration Table Header MISSING!"); 797 798 cpu_apic_address = (vm_offset_t) cth->apic_address; 799 800 /* walk the table, recording info of interest */ 801 totalSize = cth->base_table_length - sizeof(struct MPCTH); 802 position = (u_char *) cth + sizeof(struct MPCTH); 803 count = cth->entry_count; 804 805 while (count--) { 806 switch (type = *(u_char *) position) { 807 case 0: /* processor_entry */ 808 if (((proc_entry_ptr)position)->cpu_flags 809 & PROCENTRY_FLAG_EN) 810 ++mp_naps; 811 break; 812 case 1: /* bus_entry */ 813 ++mp_nbusses; 814 break; 815 case 2: /* io_apic_entry */ 816 if (((io_apic_entry_ptr)position)->apic_flags 817 & IOAPICENTRY_FLAG_EN) 818 io_apic_address[mp_napics++] = 819 (vm_offset_t)((io_apic_entry_ptr) 820 position)->apic_address; 821 break; 822 case 3: /* int_entry */ 823 ++nintrs; 824 break; 825 case 4: /* int_entry */ 826 break; 827 default: 828 panic("mpfps Base Table HOSED!"); 829 /* NOTREACHED */ 830 } 831 832 totalSize -= basetable_entry_types[type].length; 833 (u_char*)position += basetable_entry_types[type].length; 834 } 835 } 836 837 /* qualify the numbers */ 838 if (mp_naps > NCPU) 839#if 0 /* XXX FIXME: kern/4255 */ 840 printf("Warning: only using %d of %d available CPUs!\n", 841 NCPU, mp_naps); 842#else 843 { 844 printf("NCPU cannot be different than actual CPU count.\n"); 845 printf(" add 'options NCPU=%d' to your kernel config file,\n", 846 mp_naps); 847 printf(" then rerun config & rebuild your SMP kernel\n"); 848 mustpanic = 1; 849 } 850#endif /* XXX FIXME: kern/4255 */ 851 if (mp_nbusses > NBUS) { 852 printf("found %d busses, increase NBUS\n", mp_nbusses); 853 mustpanic = 1; 854 } 855 if (mp_napics > NAPIC) { 856 printf("found %d apics, increase NAPIC\n", mp_napics); 857 mustpanic = 1; 858 } 859 if (nintrs > NINTR) { 860 printf("found %d intrs, increase NINTR\n", nintrs); 861 mustpanic = 1; 862 } 863 864 /* 865 * Count the BSP. 866 * This is also used as a counter while starting the APs. 867 */ 868 mp_ncpus = 1; 869 870 --mp_naps; /* subtract the BSP */ 871 872 return mustpanic; 873} 874 875 876/* 877 * 2nd pass on motherboard's Intel MP specification table. 878 * 879 * sets: 880 * boot_cpu_id 881 * ID_TO_IO(N), phy APIC ID to log CPU/IO table 882 * CPU_TO_ID(N), logical CPU to APIC ID table 883 * IO_TO_ID(N), logical IO to APIC ID table 884 * bus_data[N] 885 * io_apic_ints[N] 886 */ 887static int 888mptable_pass2(void) 889{ 890 int x; 891 mpcth_t cth; 892 int totalSize; 893 void* position; 894 int count; 895 int type; 896 int apic, bus, cpu, intr; 897 898 POSTCODE(MPTABLE_PASS2_POST); 899 900 /* clear various tables */ 901 for (x = 0; x < NAPICID; ++x) { 902 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */ 903 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */ 904 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */ 905 } 906 907 /* clear bus data table */ 908 for (x = 0; x < NBUS; ++x) 909 bus_data[x].bus_id = 0xff; 910 911 /* clear IO APIC INT table */ 912 for (x = 0; x < NINTR; ++x) 913 io_apic_ints[x].int_type = 0xff; 914 915 /* setup the cpu/apic mapping arrays */ 916 boot_cpu_id = -1; 917 918 /* record whether PIC or virtual-wire mode */ 919 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0; 920 921 /* check for use of 'default' configuration */ 922 if (MPFPS_MPFB1 != 0) 923 return MPFPS_MPFB1; /* return default configuration type */ 924 925 if ((cth = mpfps->pap) == 0) 926 panic("MP Configuration Table Header MISSING!"); 927 928 /* walk the table, recording info of interest */ 929 totalSize = cth->base_table_length - sizeof(struct MPCTH); 930 position = (u_char *) cth + sizeof(struct MPCTH); 931 count = cth->entry_count; 932 apic = bus = intr = 0; 933 cpu = 1; /* pre-count the BSP */ 934 935 while (count--) { 936 switch (type = *(u_char *) position) { 937 case 0: 938 if (processor_entry(position, cpu)) 939 ++cpu; 940 break; 941 case 1: 942 if (bus_entry(position, bus)) 943 ++bus; 944 break; 945 case 2: 946 if (io_apic_entry(position, apic)) 947 ++apic; 948 break; 949 case 3: 950 if (int_entry(position, intr)) 951 ++intr; 952 break; 953 case 4: 954 /* int_entry(position); */ 955 break; 956 default: 957 panic("mpfps Base Table HOSED!"); 958 /* NOTREACHED */ 959 } 960 961 totalSize -= basetable_entry_types[type].length; 962 (u_char *) position += basetable_entry_types[type].length; 963 } 964 965 if (boot_cpu_id == -1) 966 panic("NO BSP found!"); 967 968 /* report fact that its NOT a default configuration */ 969 return 0; 970} 971 972 973/* 974 * parse an Intel MP specification table 975 */ 976static void 977fix_mp_table(void) 978{ 979 int x; 980 int id; 981 int bus_0; 982 int bus_pci; 983 int num_pci_bus; 984 985 /* 986 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS 987 * did it wrong. The MP spec says that when more than 1 PCI bus 988 * exists the BIOS must begin with bus entries for the PCI bus and use 989 * actual PCI bus numbering. This implies that when only 1 PCI bus 990 * exists the BIOS can choose to ignore this ordering, and indeed many 991 * MP motherboards do ignore it. This causes a problem when the PCI 992 * sub-system makes requests of the MP sub-system based on PCI bus 993 * numbers. So here we look for the situation and renumber the 994 * busses and associated INTs in an effort to "make it right". 995 */ 996 997 /* find bus 0, PCI bus, count the number of PCI busses */ 998 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { 999 if (bus_data[x].bus_id == 0) { 1000 bus_0 = x; 1001 } 1002 if (bus_data[x].bus_type == PCI) { 1003 ++num_pci_bus; 1004 bus_pci = x; 1005 } 1006 } 1007 /* 1008 * bus_0 == slot of bus with ID of 0 1009 * bus_pci == slot of last PCI bus encountered 1010 */ 1011 1012 /* check the 1 PCI bus case for sanity */ 1013 if (num_pci_bus == 1) { 1014 1015 /* if it is number 0 all is well */ 1016 if (bus_data[bus_pci].bus_id == 0) 1017 return; 1018 1019 /* mis-numbered, swap with whichever bus uses slot 0 */ 1020 1021 /* swap the bus entry types */ 1022 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type; 1023 bus_data[bus_0].bus_type = PCI; 1024 1025 /* swap each relavant INTerrupt entry */ 1026 id = bus_data[bus_pci].bus_id; 1027 for (x = 0; x < nintrs; ++x) { 1028 if (io_apic_ints[x].src_bus_id == id) { 1029 io_apic_ints[x].src_bus_id = 0; 1030 } 1031 else if (io_apic_ints[x].src_bus_id == 0) { 1032 io_apic_ints[x].src_bus_id = id; 1033 } 1034 } 1035 } 1036 /* sanity check if more than 1 PCI bus */ 1037 else if (num_pci_bus > 1) { 1038 for (x = 0; x < mp_nbusses; ++x) { 1039 if (bus_data[x].bus_type != PCI) 1040 continue; 1041 if (bus_data[x].bus_id >= num_pci_bus) 1042 panic("bad PCI bus numbering"); 1043 } 1044 } 1045} 1046 1047 1048static int 1049processor_entry(proc_entry_ptr entry, int cpu) 1050{ 1051 /* check for usability */ 1052 if ((cpu >= NCPU) || !(entry->cpu_flags & PROCENTRY_FLAG_EN)) 1053 return 0; 1054 1055 /* check for BSP flag */ 1056 if (entry->cpu_flags & PROCENTRY_FLAG_BP) { 1057 boot_cpu_id = entry->apic_id; 1058 CPU_TO_ID(0) = entry->apic_id; 1059 ID_TO_CPU(entry->apic_id) = 0; 1060 return 0; /* its already been counted */ 1061 } 1062 1063 /* add another AP to list, if less than max number of CPUs */ 1064 else { 1065 CPU_TO_ID(cpu) = entry->apic_id; 1066 ID_TO_CPU(entry->apic_id) = cpu; 1067 return 1; 1068 } 1069} 1070 1071 1072static int 1073bus_entry(bus_entry_ptr entry, int bus) 1074{ 1075 int x; 1076 char c, name[8]; 1077 1078 /* encode the name into an index */ 1079 for (x = 0; x < 6; ++x) { 1080 if ((c = entry->bus_type[x]) == ' ') 1081 break; 1082 name[x] = c; 1083 } 1084 name[x] = '\0'; 1085 1086 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) 1087 panic("unknown bus type: '%s'", name); 1088 1089 bus_data[bus].bus_id = entry->bus_id; 1090 bus_data[bus].bus_type = x; 1091 1092 return 1; 1093} 1094 1095 1096static int 1097io_apic_entry(io_apic_entry_ptr entry, int apic) 1098{ 1099 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) 1100 return 0; 1101 1102 IO_TO_ID(apic) = entry->apic_id; 1103 ID_TO_IO(entry->apic_id) = apic; 1104 1105 return 1; 1106} 1107 1108 1109static int 1110lookup_bus_type(char *name) 1111{ 1112 int x; 1113 1114 for (x = 0; x < MAX_BUSTYPE; ++x) 1115 if (strcmp(bus_type_table[x].name, name) == 0) 1116 return bus_type_table[x].type; 1117 1118 return UNKNOWN_BUSTYPE; 1119} 1120 1121 1122static int 1123int_entry(int_entry_ptr entry, int intr) 1124{ 1125 io_apic_ints[intr].int_type = entry->int_type; 1126 io_apic_ints[intr].int_flags = entry->int_flags; 1127 io_apic_ints[intr].src_bus_id = entry->src_bus_id; 1128 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq; 1129 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; 1130 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int; 1131 1132 return 1; 1133} 1134 1135 1136static int 1137apic_int_is_bus_type(int intr, int bus_type) 1138{ 1139 int bus; 1140 1141 for (bus = 0; bus < mp_nbusses; ++bus) 1142 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) 1143 && ((int) bus_data[bus].bus_type == bus_type)) 1144 return 1; 1145 1146 return 0; 1147} 1148 1149 1150/* 1151 * Given a traditional ISA INT mask, return an APIC mask. 1152 */ 1153u_int 1154isa_apic_mask(u_int isa_mask) 1155{ 1156 int isa_irq; 1157 int apic_pin; 1158 1159#if defined(SKIP_IRQ15_REDIRECT) 1160 if (isa_mask == (1 << 15)) { 1161 printf("skipping ISA IRQ15 redirect\n"); 1162 return isa_mask; 1163 } 1164#endif /* SKIP_IRQ15_REDIRECT */ 1165 1166 isa_irq = ffs(isa_mask); /* find its bit position */ 1167 if (isa_irq == 0) /* doesn't exist */ 1168 return 0; 1169 --isa_irq; /* make it zero based */ 1170 1171 apic_pin = isa_apic_pin(isa_irq); /* look for APIC connection */ 1172 if (apic_pin == -1) 1173 return 0; 1174 1175 return (1 << apic_pin); /* convert pin# to a mask */ 1176} 1177 1178 1179/* 1180 * Determine which APIC pin an ISA/EISA INT is attached to. 1181 */ 1182#define INTTYPE(I) (io_apic_ints[(I)].int_type) 1183#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) 1184 1185#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) 1186int 1187isa_apic_pin(int isa_irq) 1188{ 1189 int intr; 1190 1191 for (intr = 0; intr < nintrs; ++intr) { /* check each record */ 1192 if (INTTYPE(intr) == 0) { /* standard INT */ 1193 if (SRCBUSIRQ(intr) == isa_irq) { 1194 if (apic_int_is_bus_type(intr, ISA) || 1195 apic_int_is_bus_type(intr, EISA)) 1196 return INTPIN(intr); /* found */ 1197 } 1198 } 1199 } 1200 return -1; /* NOT found */ 1201} 1202 1203 1204/* 1205 * Determine which APIC pin a PCI INT is attached to. 1206 */ 1207#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) 1208#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) 1209#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) 1210int 1211pci_apic_pin(int pciBus, int pciDevice, int pciInt) 1212{ 1213 int intr; 1214 1215 --pciInt; /* zero based */ 1216 1217 for (intr = 0; intr < nintrs; ++intr) /* check each record */ 1218 if ((INTTYPE(intr) == 0) /* standard INT */ 1219 && (SRCBUSID(intr) == pciBus) 1220 && (SRCBUSDEVICE(intr) == pciDevice) 1221 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ 1222 if (apic_int_is_bus_type(intr, PCI)) 1223 return INTPIN(intr); /* exact match */ 1224 1225 return -1; /* NOT found */ 1226} 1227 1228int 1229next_apic_pin(int pin) 1230{ 1231 int intr, ointr; 1232 int bus, bustype; 1233 1234 bus = 0; 1235 bustype = 0; 1236 for (intr = 0; intr < nintrs; intr++) { 1237 if (INTPIN(intr) != pin || INTTYPE(intr) != 0) 1238 continue; 1239 bus = SRCBUSID(intr); 1240 bustype = apic_bus_type(bus); 1241 if (bustype != ISA && 1242 bustype != EISA && 1243 bustype != PCI) 1244 continue; 1245 break; 1246 } 1247 if (intr >= nintrs) { 1248 return -1; 1249 } 1250 for (ointr = intr + 1; ointr < nintrs; ointr++) { 1251 if (INTTYPE(ointr) != 0) 1252 continue; 1253 if (bus != SRCBUSID(ointr)) 1254 continue; 1255 if (bustype == PCI) { 1256 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr)) 1257 continue; 1258 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr)) 1259 continue; 1260 } 1261 if (bustype == ISA || bustype == EISA) { 1262 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr)) 1263 continue; 1264 } 1265 if (INTPIN(intr) == INTPIN(ointr)) 1266 continue; 1267 break; 1268 } 1269 if (ointr >= nintrs) { 1270 return -1; 1271 } 1272 return INTPIN(ointr); 1273} 1274#undef SRCBUSLINE 1275#undef SRCBUSDEVICE 1276#undef SRCBUSID 1277#undef SRCBUSIRQ 1278 1279#undef INTPIN 1280#undef INTTYPE 1281 1282 1283/* 1284 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt. 1285 * 1286 * XXX FIXME: 1287 * Exactly what this means is unclear at this point. It is a solution 1288 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard 1289 * could route any of the ISA INTs to upper (>15) IRQ values. But most would 1290 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an 1291 * option. 1292 */ 1293int 1294undirect_isa_irq(int rirq) 1295{ 1296#if defined(READY) 1297 printf("Freeing redirected ISA irq %d.\n", rirq); 1298 /** FIXME: tickle the MB redirector chip */ 1299 return ???; 1300#else 1301 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq); 1302 return 0; 1303#endif /* READY */ 1304} 1305 1306 1307/* 1308 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt 1309 */ 1310int 1311undirect_pci_irq(int rirq) 1312{ 1313#if defined(READY) 1314 if (bootverbose) 1315 printf("Freeing redirected PCI irq %d.\n", rirq); 1316 1317 /** FIXME: tickle the MB redirector chip */ 1318 return ???; 1319#else 1320 if (bootverbose) 1321 printf("Freeing (NOT implemented) redirected PCI irq %d.\n", 1322 rirq); 1323 return 0; 1324#endif /* READY */ 1325} 1326 1327 1328/* 1329 * given a bus ID, return: 1330 * the bus type if found 1331 * -1 if NOT found 1332 */ 1333int 1334apic_bus_type(int id) 1335{ 1336 int x; 1337 1338 for (x = 0; x < mp_nbusses; ++x) 1339 if (bus_data[x].bus_id == id) 1340 return bus_data[x].bus_type; 1341 1342 return -1; 1343} 1344 1345 1346/* 1347 * given a LOGICAL APIC# and pin#, return: 1348 * the associated src bus ID if found 1349 * -1 if NOT found 1350 */ 1351int 1352apic_src_bus_id(int apic, int pin) 1353{ 1354 int x; 1355 1356 /* search each of the possible INTerrupt sources */ 1357 for (x = 0; x < nintrs; ++x) 1358 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1359 (pin == io_apic_ints[x].dst_apic_int)) 1360 return (io_apic_ints[x].src_bus_id); 1361 1362 return -1; /* NOT found */ 1363} 1364 1365 1366/* 1367 * given a LOGICAL APIC# and pin#, return: 1368 * the associated src bus IRQ if found 1369 * -1 if NOT found 1370 */ 1371int 1372apic_src_bus_irq(int apic, int pin) 1373{ 1374 int x; 1375 1376 for (x = 0; x < nintrs; x++) 1377 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1378 (pin == io_apic_ints[x].dst_apic_int)) 1379 return (io_apic_ints[x].src_bus_irq); 1380 1381 return -1; /* NOT found */ 1382} 1383 1384 1385/* 1386 * given a LOGICAL APIC# and pin#, return: 1387 * the associated INTerrupt type if found 1388 * -1 if NOT found 1389 */ 1390int 1391apic_int_type(int apic, int pin) 1392{ 1393 int x; 1394 1395 /* search each of the possible INTerrupt sources */ 1396 for (x = 0; x < nintrs; ++x) 1397 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1398 (pin == io_apic_ints[x].dst_apic_int)) 1399 return (io_apic_ints[x].int_type); 1400 1401 return -1; /* NOT found */ 1402} 1403 1404 1405/* 1406 * given a LOGICAL APIC# and pin#, return: 1407 * the associated trigger mode if found 1408 * -1 if NOT found 1409 */ 1410int 1411apic_trigger(int apic, int pin) 1412{ 1413 int x; 1414 1415 /* search each of the possible INTerrupt sources */ 1416 for (x = 0; x < nintrs; ++x) 1417 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1418 (pin == io_apic_ints[x].dst_apic_int)) 1419 return ((io_apic_ints[x].int_flags >> 2) & 0x03); 1420 1421 return -1; /* NOT found */ 1422} 1423 1424 1425/* 1426 * given a LOGICAL APIC# and pin#, return: 1427 * the associated 'active' level if found 1428 * -1 if NOT found 1429 */ 1430int 1431apic_polarity(int apic, int pin) 1432{ 1433 int x; 1434 1435 /* search each of the possible INTerrupt sources */ 1436 for (x = 0; x < nintrs; ++x) 1437 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1438 (pin == io_apic_ints[x].dst_apic_int)) 1439 return (io_apic_ints[x].int_flags & 0x03); 1440 1441 return -1; /* NOT found */ 1442} 1443 1444 1445/* 1446 * set data according to MP defaults 1447 * FIXME: probably not complete yet... 1448 */ 1449static void 1450default_mp_table(int type) 1451{ 1452 int ap_cpu_id; 1453#if defined(APIC_IO) 1454 u_int32_t ux; 1455 int io_apic_id; 1456 int pin; 1457#endif /* APIC_IO */ 1458 1459#if 0 1460 printf(" MP default config type: %d\n", type); 1461 switch (type) { 1462 case 1: 1463 printf(" bus: ISA, APIC: 82489DX\n"); 1464 break; 1465 case 2: 1466 printf(" bus: EISA, APIC: 82489DX\n"); 1467 break; 1468 case 3: 1469 printf(" bus: EISA, APIC: 82489DX\n"); 1470 break; 1471 case 4: 1472 printf(" bus: MCA, APIC: 82489DX\n"); 1473 break; 1474 case 5: 1475 printf(" bus: ISA+PCI, APIC: Integrated\n"); 1476 break; 1477 case 6: 1478 printf(" bus: EISA+PCI, APIC: Integrated\n"); 1479 break; 1480 case 7: 1481 printf(" bus: MCA+PCI, APIC: Integrated\n"); 1482 break; 1483 default: 1484 printf(" future type\n"); 1485 break; 1486 /* NOTREACHED */ 1487 } 1488#endif /* 0 */ 1489 1490 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24; 1491 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; 1492 1493 /* BSP */ 1494 CPU_TO_ID(0) = boot_cpu_id; 1495 ID_TO_CPU(boot_cpu_id) = 0; 1496 1497 /* one and only AP */ 1498 CPU_TO_ID(1) = ap_cpu_id; 1499 ID_TO_CPU(ap_cpu_id) = 1; 1500 1501#if defined(APIC_IO) 1502 /* one and only IO APIC */ 1503 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; 1504 1505 /* 1506 * sanity check, refer to MP spec section 3.6.6, last paragraph 1507 * necessary as some hardware isn't properly setting up the IO APIC 1508 */ 1509#if defined(REALLY_ANAL_IOAPICID_VALUE) 1510 if (io_apic_id != 2) { 1511#else 1512 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { 1513#endif /* REALLY_ANAL_IOAPICID_VALUE */ 1514 ux = io_apic_read(0, IOAPIC_ID); /* get current contents */ 1515 ux &= ~APIC_ID_MASK; /* clear the ID field */ 1516 ux |= 0x02000000; /* set it to '2' */ 1517 io_apic_write(0, IOAPIC_ID, ux); /* write new value */ 1518 ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */ 1519 if ((ux & APIC_ID_MASK) != 0x02000000) 1520 panic("can't control IO APIC ID, reg: 0x%08x", ux); 1521 io_apic_id = 2; 1522 } 1523 IO_TO_ID(0) = io_apic_id; 1524 ID_TO_IO(io_apic_id) = 0; 1525#endif /* APIC_IO */ 1526 1527 /* fill out bus entries */ 1528 switch (type) { 1529 case 1: 1530 case 2: 1531 case 3: 1532 case 5: 1533 case 6: 1534 bus_data[0].bus_id = default_data[type - 1][1]; 1535 bus_data[0].bus_type = default_data[type - 1][2]; 1536 bus_data[1].bus_id = default_data[type - 1][3]; 1537 bus_data[1].bus_type = default_data[type - 1][4]; 1538 break; 1539 1540 /* case 4: case 7: MCA NOT supported */ 1541 default: /* illegal/reserved */ 1542 panic("BAD default MP config: %d", type); 1543 /* NOTREACHED */ 1544 } 1545 1546#if defined(APIC_IO) 1547 /* general cases from MP v1.4, table 5-2 */ 1548 for (pin = 0; pin < 16; ++pin) { 1549 io_apic_ints[pin].int_type = 0; 1550 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */ 1551 io_apic_ints[pin].src_bus_id = 0; 1552 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */ 1553 io_apic_ints[pin].dst_apic_id = io_apic_id; 1554 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */ 1555 } 1556 1557 /* special cases from MP v1.4, table 5-2 */ 1558 if (type == 2) { 1559 io_apic_ints[2].int_type = 0xff; /* N/C */ 1560 io_apic_ints[13].int_type = 0xff; /* N/C */ 1561#if !defined(APIC_MIXED_MODE) 1562 /** FIXME: ??? */ 1563 panic("sorry, can't support type 2 default yet"); 1564#endif /* APIC_MIXED_MODE */ 1565 } 1566 else 1567 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ 1568 1569 if (type == 7) 1570 io_apic_ints[0].int_type = 0xff; /* N/C */ 1571 else 1572 io_apic_ints[0].int_type = 3; /* vectored 8259 */ 1573#endif /* APIC_IO */ 1574} 1575 1576 1577/* 1578 * initialize all the SMP locks 1579 */ 1580 1581/* critical region around IO APIC, apic_imen */ 1582struct simplelock imen_lock; 1583 1584/* critical region around splxx(), cpl, cml, cil, ipending */ 1585struct simplelock cpl_lock; 1586 1587/* Make FAST_INTR() routines sequential */ 1588struct simplelock fast_intr_lock; 1589 1590/* critical region around INTR() routines */ 1591struct simplelock intr_lock; 1592 1593/* lock regions protected in UP kernel via cli/sti */ 1594struct simplelock mpintr_lock; 1595 1596/* lock region used by kernel profiling */ 1597struct simplelock mcount_lock; 1598 1599#ifdef USE_COMLOCK 1600/* locks com (tty) data/hardware accesses: a FASTINTR() */ 1601struct simplelock com_lock; 1602#endif /* USE_COMLOCK */ 1603 1604#ifdef USE_CLOCKLOCK 1605/* lock regions around the clock hardware */ 1606struct simplelock clock_lock; 1607#endif /* USE_CLOCKLOCK */ 1608 1609static void 1610init_locks(void) 1611{ 1612 /* 1613 * Get the initial mp_lock with a count of 1 for the BSP. 1614 * This uses a LOGICAL cpu ID, ie BSP == 0. 1615 */ 1616 mp_lock = 0x00000001; 1617 1618 /* ISR uses its own "giant lock" */ 1619 isr_lock = FREE_LOCK; 1620 1621#if defined(APIC_INTR_DIAGNOSTIC) && defined(APIC_INTR_DIAGNOSTIC_IRQ) 1622 s_lock_init((struct simplelock*)&apic_itrace_debuglock); 1623#endif 1624 1625 s_lock_init((struct simplelock*)&mpintr_lock); 1626 1627 s_lock_init((struct simplelock*)&mcount_lock); 1628 1629 s_lock_init((struct simplelock*)&fast_intr_lock); 1630 s_lock_init((struct simplelock*)&intr_lock); 1631 s_lock_init((struct simplelock*)&imen_lock); 1632 s_lock_init((struct simplelock*)&cpl_lock); 1633 1634#ifdef USE_COMLOCK 1635 s_lock_init((struct simplelock*)&com_lock); 1636#endif /* USE_COMLOCK */ 1637#ifdef USE_CLOCKLOCK 1638 s_lock_init((struct simplelock*)&clock_lock); 1639#endif /* USE_CLOCKLOCK */ 1640} 1641 1642 1643/* 1644 * start each AP in our list 1645 */ 1646static int 1647start_all_aps(u_int boot_addr) 1648{ 1649 int x, i; 1650 u_char mpbiosreason; 1651 u_long mpbioswarmvec; 1652 pd_entry_t *newptd; 1653 pt_entry_t *newpt; 1654 int *newpp; 1655 char *stack; 1656 pd_entry_t *myPTD; 1657 1658 POSTCODE(START_ALL_APS_POST); 1659 1660 /* initialize BSP's local APIC */ 1661 apic_initialize(); 1662 bsp_apic_ready = 1; 1663 1664 /* install the AP 1st level boot code */ 1665 install_ap_tramp(boot_addr); 1666 1667 1668 /* save the current value of the warm-start vector */ 1669 mpbioswarmvec = *((u_long *) WARMBOOT_OFF); 1670 outb(CMOS_REG, BIOS_RESET); 1671 mpbiosreason = inb(CMOS_DATA); 1672 1673 /* record BSP in CPU map */ 1674 all_cpus = 1; 1675 1676 /* start each AP */ 1677 for (x = 1; x <= mp_naps; ++x) { 1678 1679 /* This is a bit verbose, it will go away soon. */ 1680 1681 /* alloc new page table directory */ 1682 newptd = (pd_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE)); 1683 1684 /* Store the virtual PTD address for this CPU */ 1685 IdlePTDS[x] = newptd; 1686 1687 /* clone currently active one (ie: IdlePTD) */ 1688 bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */ 1689 1690 /* set up 0 -> 4MB P==V mapping for AP boot */ 1691 newptd[0] = (pd_entry_t) (PG_V | PG_RW | 1692 ((u_long)KPTphys & PG_FRAME)); 1693 1694 /* store PTD for this AP's boot sequence */ 1695 myPTD = (pd_entry_t *)vtophys(newptd); 1696 1697 /* alloc new page table page */ 1698 newpt = (pt_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE)); 1699 1700 /* set the new PTD's private page to point there */ 1701 newptd[MPPTDI] = (pt_entry_t)(PG_V | PG_RW | vtophys(newpt)); 1702 1703 /* install self referential entry */ 1704 newptd[PTDPTDI] = (pd_entry_t)(PG_V | PG_RW | vtophys(newptd)); 1705 1706 /* allocate a new private data page */ 1707 newpp = (int *)kmem_alloc(kernel_map, PAGE_SIZE); 1708 1709 /* wire it into the private page table page */ 1710 newpt[0] = (pt_entry_t)(PG_V | PG_RW | vtophys(newpp)); 1711 1712 /* wire the ptp into itself for access */ 1713 newpt[1] = (pt_entry_t)(PG_V | PG_RW | vtophys(newpt)); 1714 1715 /* copy in the pointer to the local apic */ 1716 newpt[2] = SMP_prvpt[2]; 1717 1718 /* and the IO apic mapping[s] */ 1719 for (i = 16; i < 32; i++) 1720 newpt[i] = SMP_prvpt[i]; 1721 1722 /* allocate and set up an idle stack data page */ 1723 stack = (char *)kmem_alloc(kernel_map, UPAGES*PAGE_SIZE); 1724 for (i = 0; i < UPAGES; i++) 1725 newpt[i + 3] = (pt_entry_t)(PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 1726 1727 newpt[3 + UPAGES] = 0; /* *prv_CMAP1 */ 1728 newpt[4 + UPAGES] = 0; /* *prv_CMAP2 */ 1729 newpt[5 + UPAGES] = 0; /* *prv_CMAP3 */ 1730 1731 /* prime data page for it to use */ 1732 newpp[0] = x; /* cpuid */ 1733 newpp[1] = 0; /* curproc */ 1734 newpp[2] = 0; /* curpcb */ 1735 newpp[3] = 0; /* npxproc */ 1736 newpp[4] = 0; /* runtime.tv_sec */ 1737 newpp[5] = 0; /* runtime.tv_usec */ 1738 newpp[6] = x << 24; /* cpu_lockid */ 1739 newpp[7] = 0; /* other_cpus */ 1740 newpp[8] = (int)myPTD; /* my_idlePTD */ 1741 newpp[9] = 0; /* ss_tpr */ 1742 newpp[10] = (int)&newpt[3 + UPAGES]; /* prv_CMAP1 */ 1743 newpp[11] = (int)&newpt[4 + UPAGES]; /* prv_CMAP2 */ 1744 newpp[12] = (int)&newpt[5 + UPAGES]; /* prv_CMAP3 */ 1745 1746 /* setup a vector to our boot code */ 1747 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 1748 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); 1749 outb(CMOS_REG, BIOS_RESET); 1750 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 1751 1752 bootPTD = myPTD; 1753 /* attempt to start the Application Processor */ 1754 CHECK_INIT(99); /* setup checkpoints */ 1755 if (!start_ap(x, boot_addr)) { 1756 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); 1757 CHECK_PRINT("trace"); /* show checkpoints */ 1758 /* better panic as the AP may be running loose */ 1759 printf("panic y/n? [y] "); 1760 if (cngetc() != 'n') 1761 panic("bye-bye"); 1762 } 1763 CHECK_PRINT("trace"); /* show checkpoints */ 1764 1765 /* record its version info */ 1766 cpu_apic_versions[x] = cpu_apic_versions[0]; 1767 1768 all_cpus |= (1 << x); /* record AP in CPU map */ 1769 } 1770 1771 /* build our map of 'other' CPUs */ 1772 other_cpus = all_cpus & ~(1 << cpuid); 1773 1774 /* fill in our (BSP) APIC version */ 1775 cpu_apic_versions[0] = lapic.version; 1776 1777 /* restore the warmstart vector */ 1778 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 1779 outb(CMOS_REG, BIOS_RESET); 1780 outb(CMOS_DATA, mpbiosreason); 1781 1782 /* 1783 * Set up the idle context for the BSP. Similar to above except 1784 * that some was done by locore, some by pmap.c and some is implicit 1785 * because the BSP is cpu#0 and the page is initially zero, and also 1786 * because we can refer to variables by name on the BSP.. 1787 */ 1788 newptd = (pd_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE)); 1789 1790 bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */ 1791 IdlePTDS[0] = newptd; 1792 1793 /* Point PTD[] to this page instead of IdlePTD's physical page */ 1794 newptd[PTDPTDI] = (pd_entry_t)(PG_V | PG_RW | vtophys(newptd)); 1795 1796 my_idlePTD = (pd_entry_t *)vtophys(newptd); 1797 1798 /* Allocate and setup BSP idle stack */ 1799 stack = (char *)kmem_alloc(kernel_map, UPAGES * PAGE_SIZE); 1800 for (i = 0; i < UPAGES; i++) 1801 SMP_prvpt[i + 3] = (pt_entry_t)(PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 1802 1803 pmap_set_opt_bsp(); 1804 1805 for (i = 0; i < mp_ncpus; i++) { 1806 bcopy( (int *) PTD + KPTDI, (int *) IdlePTDS[i] + KPTDI, NKPDE * sizeof (int)); 1807 } 1808 1809 /* number of APs actually started */ 1810 return mp_ncpus - 1; 1811} 1812 1813 1814/* 1815 * load the 1st level AP boot code into base memory. 1816 */ 1817 1818/* targets for relocation */ 1819extern void bigJump(void); 1820extern void bootCodeSeg(void); 1821extern void bootDataSeg(void); 1822extern void MPentry(void); 1823extern u_int MP_GDT; 1824extern u_int mp_gdtbase; 1825 1826static void 1827install_ap_tramp(u_int boot_addr) 1828{ 1829 int x; 1830 int size = *(int *) ((u_long) & bootMP_size); 1831 u_char *src = (u_char *) ((u_long) bootMP); 1832 u_char *dst = (u_char *) boot_addr + KERNBASE; 1833 u_int boot_base = (u_int) bootMP; 1834 u_int8_t *dst8; 1835 u_int16_t *dst16; 1836 u_int32_t *dst32; 1837 1838 POSTCODE(INSTALL_AP_TRAMP_POST); 1839 1840 for (x = 0; x < size; ++x) 1841 *dst++ = *src++; 1842 1843 /* 1844 * modify addresses in code we just moved to basemem. unfortunately we 1845 * need fairly detailed info about mpboot.s for this to work. changes 1846 * to mpboot.s might require changes here. 1847 */ 1848 1849 /* boot code is located in KERNEL space */ 1850 dst = (u_char *) boot_addr + KERNBASE; 1851 1852 /* modify the lgdt arg */ 1853 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 1854 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); 1855 1856 /* modify the ljmp target for MPentry() */ 1857 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 1858 *dst32 = ((u_int) MPentry - KERNBASE); 1859 1860 /* modify the target for boot code segment */ 1861 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 1862 dst8 = (u_int8_t *) (dst16 + 1); 1863 *dst16 = (u_int) boot_addr & 0xffff; 1864 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1865 1866 /* modify the target for boot data segment */ 1867 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 1868 dst8 = (u_int8_t *) (dst16 + 1); 1869 *dst16 = (u_int) boot_addr & 0xffff; 1870 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1871} 1872 1873 1874/* 1875 * this function starts the AP (application processor) identified 1876 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 1877 * to accomplish this. This is necessary because of the nuances 1878 * of the different hardware we might encounter. It ain't pretty, 1879 * but it seems to work. 1880 */ 1881static int 1882start_ap(int logical_cpu, u_int boot_addr) 1883{ 1884 int physical_cpu; 1885 int vector; 1886 int cpus; 1887 u_long icr_lo, icr_hi; 1888 1889 POSTCODE(START_AP_POST); 1890 1891 /* get the PHYSICAL APIC ID# */ 1892 physical_cpu = CPU_TO_ID(logical_cpu); 1893 1894 /* calculate the vector */ 1895 vector = (boot_addr >> 12) & 0xff; 1896 1897 /* used as a watchpoint to signal AP startup */ 1898 cpus = mp_ncpus; 1899 1900 /* 1901 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 1902 * and running the target CPU. OR this INIT IPI might be latched (P5 1903 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 1904 * ignored. 1905 */ 1906 1907 /* setup the address for the target AP */ 1908 icr_hi = lapic.icr_hi & ~APIC_ID_MASK; 1909 icr_hi |= (physical_cpu << 24); 1910 lapic.icr_hi = icr_hi; 1911 1912 /* do an INIT IPI: assert RESET */ 1913 icr_lo = lapic.icr_lo & 0xfff00000; 1914 lapic.icr_lo = icr_lo | 0x0000c500; 1915 1916 /* wait for pending status end */ 1917 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1918 /* spin */ ; 1919 1920 /* do an INIT IPI: deassert RESET */ 1921 lapic.icr_lo = icr_lo | 0x00008500; 1922 1923 /* wait for pending status end */ 1924 u_sleep(10000); /* wait ~10mS */ 1925 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1926 /* spin */ ; 1927 1928 /* 1929 * next we do a STARTUP IPI: the previous INIT IPI might still be 1930 * latched, (P5 bug) this 1st STARTUP would then terminate 1931 * immediately, and the previously started INIT IPI would continue. OR 1932 * the previous INIT IPI has already run. and this STARTUP IPI will 1933 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 1934 * will run. 1935 */ 1936 1937 /* do a STARTUP IPI */ 1938 lapic.icr_lo = icr_lo | 0x00000600 | vector; 1939 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1940 /* spin */ ; 1941 u_sleep(200); /* wait ~200uS */ 1942 1943 /* 1944 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 1945 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 1946 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 1947 * recognized after hardware RESET or INIT IPI. 1948 */ 1949 1950 lapic.icr_lo = icr_lo | 0x00000600 | vector; 1951 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1952 /* spin */ ; 1953 u_sleep(200); /* wait ~200uS */ 1954 1955 /* wait for it to start */ 1956 set_apic_timer(5000000);/* == 5 seconds */ 1957 while (read_apic_timer()) 1958 if (mp_ncpus > cpus) 1959 return 1; /* return SUCCESS */ 1960 1961 return 0; /* return FAILURE */ 1962} 1963 1964 1965/* 1966 * Flush the TLB on all other CPU's 1967 * 1968 * XXX: Needs to handshake and wait for completion before proceding. 1969 */ 1970void 1971smp_invltlb(void) 1972{ 1973#if defined(APIC_IO) 1974 if (smp_started && invltlb_ok) 1975 all_but_self_ipi(XINVLTLB_OFFSET); 1976#endif /* APIC_IO */ 1977} 1978 1979void 1980invlpg(u_int addr) 1981{ 1982 __asm __volatile("invlpg (%0)"::"r"(addr):"memory"); 1983 1984 /* send a message to the other CPUs */ 1985 smp_invltlb(); 1986} 1987 1988void 1989invltlb(void) 1990{ 1991 u_long temp; 1992 1993 /* 1994 * This should be implemented as load_cr3(rcr3()) when load_cr3() is 1995 * inlined. 1996 */ 1997 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory"); 1998 1999 /* send a message to the other CPUs */ 2000 smp_invltlb(); 2001} 2002 2003 2004/* 2005 * When called the executing CPU will send an IPI to all other CPUs 2006 * requesting that they halt execution. 2007 * 2008 * Usually (but not necessarily) called with 'other_cpus' as its arg. 2009 * 2010 * - Signals all CPUs in map to stop. 2011 * - Waits for each to stop. 2012 * 2013 * Returns: 2014 * -1: error 2015 * 0: NA 2016 * 1: ok 2017 * 2018 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs 2019 * from executing at same time. 2020 */ 2021int 2022stop_cpus(u_int map) 2023{ 2024 if (!smp_started) 2025 return 0; 2026 2027 /* send IPI to all CPUs in map */ 2028 stopped_cpus = 0; 2029 2030 /* send the Xcpustop IPI to all CPUs in map */ 2031 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED); 2032 2033 while (stopped_cpus != map) 2034 /* spin */ ; 2035 2036 return 1; 2037} 2038 2039 2040/* 2041 * Called by a CPU to restart stopped CPUs. 2042 * 2043 * Usually (but not necessarily) called with 'stopped_cpus' as its arg. 2044 * 2045 * - Signals all CPUs in map to restart. 2046 * - Waits for each to restart. 2047 * 2048 * Returns: 2049 * -1: error 2050 * 0: NA 2051 * 1: ok 2052 */ 2053int 2054restart_cpus(u_int map) 2055{ 2056 if (!smp_started) 2057 return 0; 2058 2059 started_cpus = map; /* signal other cpus to restart */ 2060 2061 while (started_cpus) /* wait for each to clear its bit */ 2062 /* spin */ ; 2063 stopped_cpus = 0; 2064 2065 return 1; 2066} 2067 2068int smp_active = 0; /* are the APs allowed to run? */ 2069SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RW, &smp_active, 0, ""); 2070 2071/* XXX maybe should be hw.ncpu */ 2072static int smp_cpus = 1; /* how many cpu's running */ 2073SYSCTL_INT(_machdep, OID_AUTO, smp_cpus, CTLFLAG_RD, &smp_cpus, 0, ""); 2074 2075int invltlb_ok = 0; /* throttle smp_invltlb() till safe */ 2076SYSCTL_INT(_machdep, OID_AUTO, invltlb_ok, CTLFLAG_RW, &invltlb_ok, 0, ""); 2077 2078/* Warning: Do not staticize. Used from swtch.s */ 2079int do_page_zero_idle = 1; /* bzero pages for fun and profit in idleloop */ 2080SYSCTL_INT(_machdep, OID_AUTO, do_page_zero_idle, CTLFLAG_RW, 2081 &do_page_zero_idle, 0, ""); 2082 2083/* Is forwarding of a interrupt to the CPU holding the ISR lock enabled ? */ 2084int forward_irq_enabled = 1; 2085SYSCTL_INT(_machdep, OID_AUTO, forward_irq_enabled, CTLFLAG_RW, 2086 &forward_irq_enabled, 0, ""); 2087 2088/* Enable forwarding of a signal to a process running on a different CPU */ 2089int forward_signal_enabled = 1; 2090SYSCTL_INT(_machdep, OID_AUTO, forward_signal_enabled, CTLFLAG_RW, 2091 &forward_signal_enabled, 0, ""); 2092 2093/* 2094 * This is called once the rest of the system is up and running and we're 2095 * ready to let the AP's out of the pen. 2096 */ 2097void ap_init(void); 2098 2099void 2100ap_init() 2101{ 2102 u_int temp; 2103 u_int apic_id; 2104 2105 smp_cpus++; 2106 2107#if defined(I586_CPU) && !defined(NO_F00F_HACK) 2108 lidt(&r_idt); 2109#endif 2110 2111 /* Build our map of 'other' CPUs. */ 2112 other_cpus = all_cpus & ~(1 << cpuid); 2113 2114 printf("SMP: AP CPU #%d Launched!\n", cpuid); 2115 2116 /* XXX FIXME: i386 specific, and redundant: Setup the FPU. */ 2117 load_cr0((rcr0() & ~CR0_EM) | CR0_MP | CR0_NE | CR0_TS); 2118 2119 /* A quick check from sanity claus */ 2120 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]); 2121 if (cpuid != apic_id) { 2122 printf("SMP: cpuid = %d\n", cpuid); 2123 printf("SMP: apic_id = %d\n", apic_id); 2124 printf("PTD[MPPTDI] = %08x\n", PTD[MPPTDI]); 2125 panic("cpuid mismatch! boom!!"); 2126 } 2127 2128 /* Init local apic for irq's */ 2129 apic_initialize(); 2130 2131 /* 2132 * Activate smp_invltlb, although strictly speaking, this isn't 2133 * quite correct yet. We should have a bitfield for cpus willing 2134 * to accept TLB flush IPI's or something and sync them. 2135 */ 2136 invltlb_ok = 1; 2137 smp_started = 1; /* enable IPI's, tlb shootdown, freezes etc */ 2138 smp_active = 1; /* historic */ 2139 2140 curproc = NULL; /* make sure */ 2141} 2142 2143void 2144getmtrr() 2145{ 2146 int i; 2147 2148 if (cpu_class == CPUCLASS_686) { 2149 for(i = 0; i < NPPROVMTRR; i++) { 2150 PPro_vmtrr[i].base = rdmsr(PPRO_VMTRRphysBase0 + i * 2); 2151 PPro_vmtrr[i].mask = rdmsr(PPRO_VMTRRphysMask0 + i * 2); 2152 } 2153 } 2154} 2155 2156void 2157putmtrr() 2158{ 2159 int i; 2160 2161 if (cpu_class == CPUCLASS_686) { 2162 wbinvd(); 2163 for(i = 0; i < NPPROVMTRR; i++) { 2164 wrmsr(PPRO_VMTRRphysBase0 + i * 2, PPro_vmtrr[i].base); 2165 wrmsr(PPRO_VMTRRphysMask0 + i * 2, PPro_vmtrr[i].mask); 2166 } 2167 } 2168} 2169 2170void 2171putfmtrr() 2172{ 2173 if (cpu_class == CPUCLASS_686) { 2174 wbinvd(); 2175 /* 2176 * Set memory between 0-640K to be WB 2177 */ 2178 wrmsr(0x250, 0x0606060606060606LL); 2179 wrmsr(0x258, 0x0606060606060606LL); 2180 /* 2181 * Set normal, PC video memory to be WC 2182 */ 2183 wrmsr(0x259, 0x0101010101010101LL); 2184 } 2185} 2186 2187 2188#ifdef BETTER_CLOCK 2189 2190#define CHECKSTATE_USER 0 2191#define CHECKSTATE_SYS 1 2192#define CHECKSTATE_INTR 2 2193 2194/* Do not staticize. Used from apic_vector.s */ 2195struct proc* checkstate_curproc[NCPU]; 2196int checkstate_cpustate[NCPU]; 2197u_long checkstate_pc[NCPU]; 2198 2199extern long cp_time[CPUSTATES]; 2200 2201#define PC_TO_INDEX(pc, prof) \ 2202 ((int)(((u_quad_t)((pc) - (prof)->pr_off) * \ 2203 (u_quad_t)((prof)->pr_scale)) >> 16) & ~1) 2204 2205static void 2206addupc_intr_forwarded(struct proc *p, int id, int *astmap) 2207{ 2208 int i; 2209 struct uprof *prof; 2210 u_long pc; 2211 2212 pc = checkstate_pc[id]; 2213 prof = &p->p_stats->p_prof; 2214 if (pc >= prof->pr_off && 2215 (i = PC_TO_INDEX(pc, prof)) < prof->pr_size) { 2216 if ((p->p_flag & P_OWEUPC) == 0) { 2217 prof->pr_addr = pc; 2218 prof->pr_ticks = 1; 2219 p->p_flag |= P_OWEUPC; 2220 } 2221 *astmap |= (1 << id); 2222 } 2223} 2224 2225static void 2226forwarded_statclock(int id, int pscnt, int *astmap) 2227{ 2228 struct pstats *pstats; 2229 long rss; 2230 struct rusage *ru; 2231 struct vmspace *vm; 2232 int cpustate; 2233 struct proc *p; 2234#ifdef GPROF 2235 register struct gmonparam *g; 2236 int i; 2237#endif 2238 2239 p = checkstate_curproc[id]; 2240 cpustate = checkstate_cpustate[id]; 2241 2242 switch (cpustate) { 2243 case CHECKSTATE_USER: 2244 if (p->p_flag & P_PROFIL) 2245 addupc_intr_forwarded(p, id, astmap); 2246 if (pscnt > 1) 2247 return; 2248 p->p_uticks++; 2249 if (p->p_nice > NZERO) 2250 cp_time[CP_NICE]++; 2251 else 2252 cp_time[CP_USER]++; 2253 break; 2254 case CHECKSTATE_SYS: 2255#ifdef GPROF 2256 /* 2257 * Kernel statistics are just like addupc_intr, only easier. 2258 */ 2259 g = &_gmonparam; 2260 if (g->state == GMON_PROF_ON) { 2261 i = checkstate_pc[id] - g->lowpc; 2262 if (i < g->textsize) { 2263 i /= HISTFRACTION * sizeof(*g->kcount); 2264 g->kcount[i]++; 2265 } 2266 } 2267#endif 2268 if (pscnt > 1) 2269 return; 2270 2271 if (!p) 2272 cp_time[CP_IDLE]++; 2273 else { 2274 p->p_sticks++; 2275 cp_time[CP_SYS]++; 2276 } 2277 break; 2278 case CHECKSTATE_INTR: 2279 default: 2280#ifdef GPROF 2281 /* 2282 * Kernel statistics are just like addupc_intr, only easier. 2283 */ 2284 g = &_gmonparam; 2285 if (g->state == GMON_PROF_ON) { 2286 i = checkstate_pc[id] - g->lowpc; 2287 if (i < g->textsize) { 2288 i /= HISTFRACTION * sizeof(*g->kcount); 2289 g->kcount[i]++; 2290 } 2291 } 2292#endif 2293 if (pscnt > 1) 2294 return; 2295 if (p) 2296 p->p_iticks++; 2297 cp_time[CP_INTR]++; 2298 } 2299 if (p != NULL) { 2300 p->p_cpticks++; 2301 if (++p->p_estcpu == 0) 2302 p->p_estcpu--; 2303 if ((p->p_estcpu & 3) == 0) { 2304 resetpriority(p); 2305 if (p->p_priority >= PUSER) 2306 p->p_priority = p->p_usrpri; 2307 } 2308 2309 /* Update resource usage integrals and maximums. */ 2310 if ((pstats = p->p_stats) != NULL && 2311 (ru = &pstats->p_ru) != NULL && 2312 (vm = p->p_vmspace) != NULL) { 2313 ru->ru_ixrss += vm->vm_tsize * PAGE_SIZE / 1024; 2314 ru->ru_idrss += vm->vm_dsize * PAGE_SIZE / 1024; 2315 ru->ru_isrss += vm->vm_ssize * PAGE_SIZE / 1024; 2316 rss = vm->vm_pmap.pm_stats.resident_count * 2317 PAGE_SIZE / 1024; 2318 if (ru->ru_maxrss < rss) 2319 ru->ru_maxrss = rss; 2320 } 2321 } 2322} 2323 2324void 2325forward_statclock(int pscnt) 2326{ 2327 int map; 2328 int id; 2329 int i; 2330 2331 /* Kludge. We don't yet have separate locks for the interrupts 2332 * and the kernel. This means that we cannot let the other processors 2333 * handle complex interrupts while inhibiting them from entering 2334 * the kernel in a non-interrupt context. 2335 * 2336 * What we can do, without changing the locking mechanisms yet, 2337 * is letting the other processors handle a very simple interrupt 2338 * (wich determines the processor states), and do the main 2339 * work ourself. 2340 */ 2341 2342 if (!smp_started || !invltlb_ok || cold || panicstr) 2343 return; 2344 2345 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle ) */ 2346 2347 map = other_cpus & ~stopped_cpus ; 2348 checkstate_probed_cpus = 0; 2349 if (map != 0) 2350 selected_apic_ipi(map, 2351 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED); 2352 2353 i = 0; 2354 while (checkstate_probed_cpus != map) { 2355 /* spin */ 2356 i++; 2357 if (i == 1000000) { 2358 printf("forward_statclock: checkstate %x\n", 2359 checkstate_probed_cpus); 2360 break; 2361 } 2362 } 2363 2364 /* 2365 * Step 2: walk through other processors processes, update ticks and 2366 * profiling info. 2367 */ 2368 2369 map = 0; 2370 for (id = 0; id < mp_ncpus; id++) { 2371 if (id == cpuid) 2372 continue; 2373 if (((1 << id) & checkstate_probed_cpus) == 0) 2374 continue; 2375 forwarded_statclock(id, pscnt, &map); 2376 } 2377 if (map != 0) { 2378 checkstate_need_ast |= map; 2379 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED); 2380 i = 0; 2381 while ((checkstate_need_ast & map) != 0) { 2382 /* spin */ 2383 i++; 2384 if (i > 100000) { 2385#ifdef BETTER_CLOCK_DIAGNOSTIC 2386 printf("forward_statclock: dropped ast 0x%x\n", 2387 checkstate_need_ast & map); 2388#endif 2389 break; 2390 } 2391 } 2392 } 2393} 2394 2395void 2396forward_hardclock(int pscnt) 2397{ 2398 int map; 2399 int id; 2400 struct proc *p; 2401 struct pstats *pstats; 2402 int i; 2403 2404 /* Kludge. We don't yet have separate locks for the interrupts 2405 * and the kernel. This means that we cannot let the other processors 2406 * handle complex interrupts while inhibiting them from entering 2407 * the kernel in a non-interrupt context. 2408 * 2409 * What we can do, without changing the locking mechanisms yet, 2410 * is letting the other processors handle a very simple interrupt 2411 * (wich determines the processor states), and do the main 2412 * work ourself. 2413 */ 2414 2415 if (!smp_started || !invltlb_ok || cold || panicstr) 2416 return; 2417 2418 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle) */ 2419 2420 map = other_cpus & ~stopped_cpus ; 2421 checkstate_probed_cpus = 0; 2422 if (map != 0) 2423 selected_apic_ipi(map, 2424 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED); 2425 2426 i = 0; 2427 while (checkstate_probed_cpus != map) { 2428 /* spin */ 2429 i++; 2430 if (i == 1000000) { 2431 printf("forward_hardclock: checkstate %x\n", 2432 checkstate_probed_cpus); 2433 break; 2434 } 2435 } 2436 2437 /* 2438 * Step 2: walk through other processors processes, update virtual 2439 * timer and profiling timer. If stathz == 0, also update ticks and 2440 * profiling info. 2441 */ 2442 2443 map = 0; 2444 for (id = 0; id < mp_ncpus; id++) { 2445 if (id == cpuid) 2446 continue; 2447 if (((1 << id) & checkstate_probed_cpus) == 0) 2448 continue; 2449 p = checkstate_curproc[id]; 2450 if (p) { 2451 pstats = p->p_stats; 2452 if (checkstate_cpustate[id] == CHECKSTATE_USER && 2453 timerisset(&pstats->p_timer[ITIMER_VIRTUAL].it_value) && 2454 itimerdecr(&pstats->p_timer[ITIMER_VIRTUAL], tick) == 0) { 2455 psignal(p, SIGVTALRM); 2456 map |= (1 << id); 2457 } 2458 if (timerisset(&pstats->p_timer[ITIMER_PROF].it_value) && 2459 itimerdecr(&pstats->p_timer[ITIMER_PROF], tick) == 0) { 2460 psignal(p, SIGPROF); 2461 map |= (1 << id); 2462 } 2463 } 2464 if (stathz == 0) { 2465 forwarded_statclock( id, pscnt, &map); 2466 } 2467 } 2468 if (map != 0) { 2469 checkstate_need_ast |= map; 2470 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED); 2471 i = 0; 2472 while ((checkstate_need_ast & map) != 0) { 2473 /* spin */ 2474 i++; 2475 if (i > 100000) { 2476#ifdef BETTER_CLOCK_DIAGNOSTIC 2477 printf("forward_hardclock: dropped ast 0x%x\n", 2478 checkstate_need_ast & map); 2479#endif 2480 break; 2481 } 2482 } 2483 } 2484} 2485 2486#endif /* BETTER_CLOCK */ 2487 2488void 2489forward_signal(struct proc *p) 2490{ 2491 int map; 2492 int id; 2493 int i; 2494 2495 /* Kludge. We don't yet have separate locks for the interrupts 2496 * and the kernel. This means that we cannot let the other processors 2497 * handle complex interrupts while inhibiting them from entering 2498 * the kernel in a non-interrupt context. 2499 * 2500 * What we can do, without changing the locking mechanisms yet, 2501 * is letting the other processors handle a very simple interrupt 2502 * (wich determines the processor states), and do the main 2503 * work ourself. 2504 */ 2505 2506 if (!smp_started || !invltlb_ok || cold || panicstr) 2507 return; 2508 if (!forward_signal_enabled) 2509 return; 2510 while (1) { 2511 if (p->p_stat != SRUN) 2512 return; 2513 id = (u_char) p->p_oncpu; 2514 if (id == 0xff) 2515 return; 2516 map = (1<<id); 2517 checkstate_need_ast |= map; 2518 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED); 2519 i = 0; 2520 while ((checkstate_need_ast & map) != 0) { 2521 /* spin */ 2522 i++; 2523 if (i > 100000) { 2524#if 0 2525 printf("forward_signal: dropped ast 0x%x\n", 2526 checkstate_need_ast & map); 2527#endif 2528 break; 2529 } 2530 } 2531 if (id == (u_char) p->p_oncpu) 2532 return; 2533 } 2534} 2535 2536 2537#ifdef APIC_INTR_REORDER 2538/* 2539 * Maintain mapping from softintr vector to isr bit in local apic. 2540 */ 2541void 2542set_lapic_isrloc(int intr, int vector) 2543{ 2544 if (intr < 0 || intr > 32) 2545 panic("set_apic_isrloc: bad intr argument: %d",intr); 2546 if (vector < ICU_OFFSET || vector > 255) 2547 panic("set_apic_isrloc: bad vector argument: %d",vector); 2548 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2); 2549 apic_isrbit_location[intr].bit = (1<<(vector & 31)); 2550} 2551#endif 2552