mptable.c revision 30813
1/* 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $Id: mp_machdep.c,v 1.58 1997/10/12 15:24:39 peter Exp $ 26 */ 27 28#include "opt_smp.h" 29#include "opt_vm86.h" 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/proc.h> 35#include <sys/sysctl.h> 36 37#include <vm/vm.h> 38#include <vm/vm_param.h> 39#include <vm/pmap.h> 40#include <vm/vm_kern.h> 41#include <vm/vm_extern.h> 42 43#include <machine/smp.h> 44#include <machine/apic.h> 45#include <machine/mpapic.h> 46#include <machine/segments.h> 47#include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */ 48#include <machine/tss.h> 49#include <machine/specialreg.h> 50#include <machine/cputypes.h> 51 52#include <i386/i386/cons.h> /* cngetc() */ 53 54#if defined(APIC_IO) 55#include <machine/md_var.h> /* setidt() */ 56#include <i386/isa/icu.h> /* IPIs */ 57#include <i386/isa/intr_machdep.h> /* IPIs */ 58#endif /* APIC_IO */ 59 60#if defined(TEST_DEFAULT_CONFIG) 61#define MPFPS_MPFB1 TEST_DEFAULT_CONFIG 62#else 63#define MPFPS_MPFB1 mpfps->mpfb1 64#endif /* TEST_DEFAULT_CONFIG */ 65 66#define WARMBOOT_TARGET 0 67#define WARMBOOT_OFF (KERNBASE + 0x0467) 68#define WARMBOOT_SEG (KERNBASE + 0x0469) 69 70#define BIOS_BASE (0xf0000) 71#define BIOS_SIZE (0x10000) 72#define BIOS_COUNT (BIOS_SIZE/4) 73 74#define CMOS_REG (0x70) 75#define CMOS_DATA (0x71) 76#define BIOS_RESET (0x0f) 77#define BIOS_WARM (0x0a) 78 79#define PROCENTRY_FLAG_EN 0x01 80#define PROCENTRY_FLAG_BP 0x02 81#define IOAPICENTRY_FLAG_EN 0x01 82 83 84/* MP Floating Pointer Structure */ 85typedef struct MPFPS { 86 char signature[4]; 87 void *pap; 88 u_char length; 89 u_char spec_rev; 90 u_char checksum; 91 u_char mpfb1; 92 u_char mpfb2; 93 u_char mpfb3; 94 u_char mpfb4; 95 u_char mpfb5; 96} *mpfps_t; 97 98/* MP Configuration Table Header */ 99typedef struct MPCTH { 100 char signature[4]; 101 u_short base_table_length; 102 u_char spec_rev; 103 u_char checksum; 104 u_char oem_id[8]; 105 u_char product_id[12]; 106 void *oem_table_pointer; 107 u_short oem_table_size; 108 u_short entry_count; 109 void *apic_address; 110 u_short extended_table_length; 111 u_char extended_table_checksum; 112 u_char reserved; 113} *mpcth_t; 114 115 116typedef struct PROCENTRY { 117 u_char type; 118 u_char apic_id; 119 u_char apic_version; 120 u_char cpu_flags; 121 u_long cpu_signature; 122 u_long feature_flags; 123 u_long reserved1; 124 u_long reserved2; 125} *proc_entry_ptr; 126 127typedef struct BUSENTRY { 128 u_char type; 129 u_char bus_id; 130 char bus_type[6]; 131} *bus_entry_ptr; 132 133typedef struct IOAPICENTRY { 134 u_char type; 135 u_char apic_id; 136 u_char apic_version; 137 u_char apic_flags; 138 void *apic_address; 139} *io_apic_entry_ptr; 140 141typedef struct INTENTRY { 142 u_char type; 143 u_char int_type; 144 u_short int_flags; 145 u_char src_bus_id; 146 u_char src_bus_irq; 147 u_char dst_apic_id; 148 u_char dst_apic_int; 149} *int_entry_ptr; 150 151/* descriptions of MP basetable entries */ 152typedef struct BASETABLE_ENTRY { 153 u_char type; 154 u_char length; 155 char name[16]; 156} basetable_entry; 157 158/* 159 * this code MUST be enabled here and in mpboot.s. 160 * it follows the very early stages of AP boot by placing values in CMOS ram. 161 * it NORMALLY will never be needed and thus the primitive method for enabling. 162 * 163#define CHECK_POINTS 164 */ 165 166#if defined(CHECK_POINTS) 167#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 168#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 169 170#define CHECK_INIT(D); \ 171 CHECK_WRITE(0x34, (D)); \ 172 CHECK_WRITE(0x35, (D)); \ 173 CHECK_WRITE(0x36, (D)); \ 174 CHECK_WRITE(0x37, (D)); \ 175 CHECK_WRITE(0x38, (D)); \ 176 CHECK_WRITE(0x39, (D)); 177 178#define CHECK_PRINT(S); \ 179 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 180 (S), \ 181 CHECK_READ(0x34), \ 182 CHECK_READ(0x35), \ 183 CHECK_READ(0x36), \ 184 CHECK_READ(0x37), \ 185 CHECK_READ(0x38), \ 186 CHECK_READ(0x39)); 187 188#else /* CHECK_POINTS */ 189 190#define CHECK_INIT(D) 191#define CHECK_PRINT(S) 192 193#endif /* CHECK_POINTS */ 194 195/* 196 * Values to send to the POST hardware. 197 */ 198#define MP_BOOTADDRESS_POST 0x10 199#define MP_PROBE_POST 0x11 200#define MPTABLE_PASS1_POST 0x12 201 202#define MP_START_POST 0x13 203#define MP_ENABLE_POST 0x14 204#define MPTABLE_PASS2_POST 0x15 205 206#define START_ALL_APS_POST 0x16 207#define INSTALL_AP_TRAMP_POST 0x17 208#define START_AP_POST 0x18 209 210#define MP_ANNOUNCE_POST 0x19 211 212 213/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ 214int current_postcode; 215 216/** XXX FIXME: what system files declare these??? */ 217extern struct region_descriptor r_gdt, r_idt; 218 219int bsp_apic_ready = 0; /* flags useability of BSP apic */ 220int mp_ncpus; /* # of CPUs, including BSP */ 221int mp_naps; /* # of Applications processors */ 222int mp_nbusses; /* # of busses */ 223int mp_napics; /* # of IO APICs */ 224int boot_cpu_id; /* designated BSP */ 225vm_offset_t cpu_apic_address; 226vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */ 227extern int nkpt; 228 229u_int32_t cpu_apic_versions[NCPU]; 230u_int32_t io_apic_versions[NAPIC]; 231 232/* 233 * APIC ID logical/physical mapping structures. 234 * We oversize these to simplify boot-time config. 235 */ 236int cpu_num_to_apic_id[NAPICID]; 237int io_num_to_apic_id[NAPICID]; 238int apic_id_to_logical[NAPICID]; 239 240 241#define NPPROVMTRR 8 242#define PPRO_VMTRRphysBase0 0x200 243#define PPRO_VMTRRphysMask0 0x201 244static struct { 245 u_int64_t base, mask; 246} PPro_vmtrr[NPPROVMTRR]; 247 248/* Bitmap of all available CPUs */ 249u_int all_cpus; 250 251/* AP uses this PTD during bootstrap */ 252pd_entry_t *bootPTD; 253 254/* Hotwire a 0->4MB V==P mapping */ 255extern pt_entry_t *KPTphys; 256 257/* Virtual address of per-cpu common_tss */ 258extern struct i386tss common_tss; 259#ifdef VM86 260extern struct segment_descriptor common_tssd; 261extern u_int private_tss; /* flag indicating private tss */ 262extern u_int my_tr; 263#endif /* VM86 */ 264 265/* IdlePTD per cpu */ 266pd_entry_t *IdlePTDS[NCPU]; 267 268/* "my" private page table page, for BSP init */ 269extern pt_entry_t SMP_prvpt[]; 270 271/* Private page pointer to curcpu's PTD, used during BSP init */ 272extern pd_entry_t *my_idlePTD; 273 274static int smp_started; /* has the system started? */ 275 276/* 277 * Local data and functions. 278 */ 279 280static int mp_capable; 281static u_int boot_address; 282static u_int base_memory; 283 284static int picmode; /* 0: virtual wire mode, 1: PIC mode */ 285static mpfps_t mpfps; 286static int search_for_sig(u_int32_t target, int count); 287static void mp_enable(u_int boot_addr); 288 289static int mptable_pass1(void); 290static int mptable_pass2(void); 291static void default_mp_table(int type); 292static void fix_mp_table(void); 293static void init_locks(void); 294static int start_all_aps(u_int boot_addr); 295static void install_ap_tramp(u_int boot_addr); 296static int start_ap(int logicalCpu, u_int boot_addr); 297static void getmtrr(void); 298static void putmtrr(void); 299static void putfmtrr(void); 300 301 302/* 303 * Calculate usable address in base memory for AP trampoline code. 304 */ 305u_int 306mp_bootaddress(u_int basemem) 307{ 308 POSTCODE(MP_BOOTADDRESS_POST); 309 310 base_memory = basemem * 1024; /* convert to bytes */ 311 312 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ 313 if ((base_memory - boot_address) < bootMP_size) 314 boot_address -= 4096; /* not enough, lower by 4k */ 315 316 return boot_address; 317} 318 319 320/* 321 * Look for an Intel MP spec table (ie, SMP capable hardware). 322 */ 323int 324mp_probe(void) 325{ 326 int x; 327 u_long segment; 328 u_int32_t target; 329 330 POSTCODE(MP_PROBE_POST); 331 332 /* see if EBDA exists */ 333 if (segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) { 334 /* search first 1K of EBDA */ 335 target = (u_int32_t) (segment << 4); 336 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 337 goto found; 338 } else { 339 /* last 1K of base memory, effective 'top of base' passed in */ 340 target = (u_int32_t) (base_memory - 0x400); 341 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 342 goto found; 343 } 344 345 /* search the BIOS */ 346 target = (u_int32_t) BIOS_BASE; 347 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) 348 goto found; 349 350 /* nothing found */ 351 mpfps = (mpfps_t)0; 352 mp_capable = 0; 353 return 0; 354 355found: 356 /* calculate needed resources */ 357 mpfps = (mpfps_t)x; 358 if (mptable_pass1()) 359 panic("you must reconfigure your kernel"); 360 361 /* flag fact that we are running multiple processors */ 362 mp_capable = 1; 363 return 1; 364} 365 366 367/* 368 * Startup the SMP processors. 369 */ 370void 371mp_start(void) 372{ 373 POSTCODE(MP_START_POST); 374 375 /* look for MP capable motherboard */ 376 if (mp_capable) 377 mp_enable(boot_address); 378 else 379 panic("MP hardware not found!"); 380} 381 382 383/* 384 * Print various information about the SMP system hardware and setup. 385 */ 386void 387mp_announce(void) 388{ 389 int x; 390 391 POSTCODE(MP_ANNOUNCE_POST); 392 393 printf("FreeBSD/SMP: Multiprocessor motherboard\n"); 394 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0)); 395 printf(", version: 0x%08x", cpu_apic_versions[0]); 396 printf(", at 0x%08x\n", cpu_apic_address); 397 for (x = 1; x <= mp_naps; ++x) { 398 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x)); 399 printf(", version: 0x%08x", cpu_apic_versions[x]); 400 printf(", at 0x%08x\n", cpu_apic_address); 401 } 402 403#if defined(APIC_IO) 404 for (x = 0; x < mp_napics; ++x) { 405 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x)); 406 printf(", version: 0x%08x", io_apic_versions[x]); 407 printf(", at 0x%08x\n", io_apic_address[x]); 408 } 409#else 410 printf(" Warning: APIC I/O disabled\n"); 411#endif /* APIC_IO */ 412} 413 414/* 415 * AP cpu's call this to sync up protected mode. 416 */ 417void 418init_secondary(void) 419{ 420 int gsel_tss; 421#ifndef VM86 422 u_int my_tr; 423#endif 424 425 r_gdt.rd_limit = sizeof(gdt[0]) * (NGDT + NCPU) - 1; 426 r_gdt.rd_base = (int) gdt; 427 lgdt(&r_gdt); /* does magic intra-segment return */ 428 lidt(&r_idt); 429 lldt(_default_ldt); 430 431 my_tr = NGDT + cpuid; 432 gsel_tss = GSEL(my_tr, SEL_KPL); 433 gdt[my_tr].sd.sd_type = SDT_SYS386TSS; 434 common_tss.tss_esp0 = 0; /* not used until after switch */ 435 common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 436 common_tss.tss_ioopt = (sizeof common_tss) << 16; 437#ifdef VM86 438 common_tssd = gdt[my_tr].sd; 439 private_tss = 0; 440#endif /* VM86 */ 441 ltr(gsel_tss); 442 443 load_cr0(0x8005003b); /* XXX! */ 444 445 PTD[0] = 0; 446 pmap_set_opt((unsigned *)PTD); 447 448 putmtrr(); 449 putfmtrr(); 450 451 invltlb(); 452} 453 454 455#if defined(APIC_IO) 456/* 457 * Final configuration of the BSP's local APIC: 458 * - disable 'pic mode'. 459 * - disable 'virtual wire mode'. 460 * - enable NMI. 461 */ 462void 463bsp_apic_configure(void) 464{ 465 u_char byte; 466 u_int32_t temp; 467 468 /* leave 'pic mode' if necessary */ 469 if (picmode) { 470 outb(0x22, 0x70); /* select IMCR */ 471 byte = inb(0x23); /* current contents */ 472 byte |= 0x01; /* mask external INTR */ 473 outb(0x23, byte); /* disconnect 8259s/NMI */ 474 } 475 476 /* mask lint0 (the 8259 'virtual wire' connection) */ 477 temp = lapic.lvt_lint0; 478 temp |= APIC_LVT_M; /* set the mask */ 479 lapic.lvt_lint0 = temp; 480 481 /* setup lint1 to handle NMI */ 482 temp = lapic.lvt_lint1; 483 temp &= ~APIC_LVT_M; /* clear the mask */ 484 lapic.lvt_lint1 = temp; 485 486 if (bootverbose) 487 apic_dump("bsp_apic_configure()"); 488} 489#endif /* APIC_IO */ 490 491 492/******************************************************************* 493 * local functions and data 494 */ 495 496/* 497 * start the SMP system 498 */ 499static void 500mp_enable(u_int boot_addr) 501{ 502 int x; 503#if defined(APIC_IO) 504 int apic; 505 u_int ux; 506#endif /* APIC_IO */ 507 508 getmtrr(); 509 putfmtrr(); 510 511 POSTCODE(MP_ENABLE_POST); 512 513 /* turn on 4MB of V == P addressing so we can get to MP table */ 514 *(int *)PTD = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME); 515 invltlb(); 516 517 /* examine the MP table for needed info, uses physical addresses */ 518 x = mptable_pass2(); 519 520 *(int *)PTD = 0; 521 invltlb(); 522 523 /* can't process default configs till the CPU APIC is pmapped */ 524 if (x) 525 default_mp_table(x); 526 527 /* post scan cleanup */ 528 fix_mp_table(); 529 530#if defined(APIC_IO) 531 532 /* fill the LOGICAL io_apic_versions table */ 533 for (apic = 0; apic < mp_napics; ++apic) { 534 ux = io_apic_read(apic, IOAPIC_VER); 535 io_apic_versions[apic] = ux; 536 } 537 538 /* program each IO APIC in the system */ 539 for (apic = 0; apic < mp_napics; ++apic) 540 if (io_apic_setup(apic) < 0) 541 panic("IO APIC setup failure"); 542 543 /* install a 'Spurious INTerrupt' vector */ 544 setidt(XSPURIOUSINT_OFFSET, Xspuriousint, 545 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 546 547 /* install an inter-CPU IPI for TLB invalidation */ 548 setidt(XINVLTLB_OFFSET, Xinvltlb, 549 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 550 551 /* install an inter-CPU IPI for CPU stop/restart */ 552 setidt(XCPUSTOP_OFFSET, Xcpustop, 553 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 554 555#if defined(TEST_TEST1) 556 /* install a "fake hardware INTerrupt" vector */ 557 setidt(XTEST1_OFFSET, Xtest1, 558 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 559#endif /** TEST_TEST1 */ 560 561#endif /* APIC_IO */ 562 563 /* initialize all SMP locks */ 564 init_locks(); 565 566 /* start each Application Processor */ 567 start_all_aps(boot_addr); 568 569 /* 570 * The init process might be started on a different CPU now, 571 * and the boot CPU might not call prepare_usermode to get 572 * cr0 correctly configured. Thus we initialize cr0 here. 573 */ 574 load_cr0(rcr0() | CR0_WP | CR0_AM); 575} 576 577 578/* 579 * look for the MP spec signature 580 */ 581 582/* string defined by the Intel MP Spec as identifying the MP table */ 583#define MP_SIG 0x5f504d5f /* _MP_ */ 584#define NEXT(X) ((X) += 4) 585static int 586search_for_sig(u_int32_t target, int count) 587{ 588 int x; 589 u_int32_t *addr = (u_int32_t *) (KERNBASE + target); 590 591 for (x = 0; x < count; NEXT(x)) 592 if (addr[x] == MP_SIG) 593 /* make array index a byte index */ 594 return (target + (x * sizeof(u_int32_t))); 595 596 return -1; 597} 598 599 600static basetable_entry basetable_entry_types[] = 601{ 602 {0, 20, "Processor"}, 603 {1, 8, "Bus"}, 604 {2, 8, "I/O APIC"}, 605 {3, 8, "I/O INT"}, 606 {4, 8, "Local INT"} 607}; 608 609typedef struct BUSDATA { 610 u_char bus_id; 611 enum busTypes bus_type; 612} bus_datum; 613 614typedef struct INTDATA { 615 u_char int_type; 616 u_short int_flags; 617 u_char src_bus_id; 618 u_char src_bus_irq; 619 u_char dst_apic_id; 620 u_char dst_apic_int; 621} io_int, local_int; 622 623typedef struct BUSTYPENAME { 624 u_char type; 625 char name[7]; 626} bus_type_name; 627 628static bus_type_name bus_type_table[] = 629{ 630 {CBUS, "CBUS"}, 631 {CBUSII, "CBUSII"}, 632 {EISA, "EISA"}, 633 {UNKNOWN_BUSTYPE, "---"}, 634 {UNKNOWN_BUSTYPE, "---"}, 635 {ISA, "ISA"}, 636 {UNKNOWN_BUSTYPE, "---"}, 637 {UNKNOWN_BUSTYPE, "---"}, 638 {UNKNOWN_BUSTYPE, "---"}, 639 {UNKNOWN_BUSTYPE, "---"}, 640 {UNKNOWN_BUSTYPE, "---"}, 641 {UNKNOWN_BUSTYPE, "---"}, 642 {PCI, "PCI"}, 643 {UNKNOWN_BUSTYPE, "---"}, 644 {UNKNOWN_BUSTYPE, "---"}, 645 {UNKNOWN_BUSTYPE, "---"}, 646 {UNKNOWN_BUSTYPE, "---"}, 647 {XPRESS, "XPRESS"}, 648 {UNKNOWN_BUSTYPE, "---"} 649}; 650/* from MP spec v1.4, table 5-1 */ 651static int default_data[7][5] = 652{ 653/* nbus, id0, type0, id1, type1 */ 654 {1, 0, ISA, 255, 255}, 655 {1, 0, EISA, 255, 255}, 656 {1, 0, EISA, 255, 255}, 657 {0, 255, 255, 255, 255},/* MCA not supported */ 658 {2, 0, ISA, 1, PCI}, 659 {2, 0, EISA, 1, PCI}, 660 {0, 255, 255, 255, 255} /* MCA not supported */ 661}; 662 663 664/* the bus data */ 665bus_datum bus_data[NBUS]; 666 667/* the IO INT data, one entry per possible APIC INTerrupt */ 668io_int io_apic_ints[NINTR]; 669 670static int nintrs; 671 672static int processor_entry __P((proc_entry_ptr entry, int cpu)); 673static int bus_entry __P((bus_entry_ptr entry, int bus)); 674static int io_apic_entry __P((io_apic_entry_ptr entry, int apic)); 675static int int_entry __P((int_entry_ptr entry, int intr)); 676static int lookup_bus_type __P((char *name)); 677 678 679/* 680 * 1st pass on motherboard's Intel MP specification table. 681 * 682 * initializes: 683 * mp_ncpus = 1 684 * 685 * determines: 686 * cpu_apic_address (common to all CPUs) 687 * io_apic_address[N] 688 * mp_naps 689 * mp_nbusses 690 * mp_napics 691 * nintrs 692 */ 693static int 694mptable_pass1(void) 695{ 696 int x; 697 mpcth_t cth; 698 int totalSize; 699 void* position; 700 int count; 701 int type; 702 int mustpanic; 703 704 POSTCODE(MPTABLE_PASS1_POST); 705 706 mustpanic = 0; 707 708 /* clear various tables */ 709 for (x = 0; x < NAPICID; ++x) { 710 io_apic_address[x] = ~0; /* IO APIC address table */ 711 } 712 713 /* init everything to empty */ 714 mp_naps = 0; 715 mp_nbusses = 0; 716 mp_napics = 0; 717 nintrs = 0; 718 719 /* check for use of 'default' configuration */ 720 if (MPFPS_MPFB1 != 0) { 721 /* use default addresses */ 722 cpu_apic_address = DEFAULT_APIC_BASE; 723 io_apic_address[0] = DEFAULT_IO_APIC_BASE; 724 725 /* fill in with defaults */ 726 mp_naps = 2; /* includes BSP */ 727 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0]; 728#if defined(APIC_IO) 729 mp_napics = 1; 730 nintrs = 16; 731#endif /* APIC_IO */ 732 } 733 else { 734 if ((cth = mpfps->pap) == 0) 735 panic("MP Configuration Table Header MISSING!"); 736 737 cpu_apic_address = (vm_offset_t) cth->apic_address; 738 739 /* walk the table, recording info of interest */ 740 totalSize = cth->base_table_length - sizeof(struct MPCTH); 741 position = (u_char *) cth + sizeof(struct MPCTH); 742 count = cth->entry_count; 743 744 while (count--) { 745 switch (type = *(u_char *) position) { 746 case 0: /* processor_entry */ 747 if (((proc_entry_ptr)position)->cpu_flags 748 & PROCENTRY_FLAG_EN) 749 ++mp_naps; 750 break; 751 case 1: /* bus_entry */ 752 ++mp_nbusses; 753 break; 754 case 2: /* io_apic_entry */ 755 if (((io_apic_entry_ptr)position)->apic_flags 756 & IOAPICENTRY_FLAG_EN) 757 io_apic_address[mp_napics++] = 758 (vm_offset_t)((io_apic_entry_ptr) 759 position)->apic_address; 760 break; 761 case 3: /* int_entry */ 762 ++nintrs; 763 break; 764 case 4: /* int_entry */ 765 break; 766 default: 767 panic("mpfps Base Table HOSED!"); 768 /* NOTREACHED */ 769 } 770 771 totalSize -= basetable_entry_types[type].length; 772 (u_char*)position += basetable_entry_types[type].length; 773 } 774 } 775 776 /* qualify the numbers */ 777 if (mp_naps > NCPU) 778#if 0 /* XXX FIXME: kern/4255 */ 779 printf("Warning: only using %d of %d available CPUs!\n", 780 NCPU, mp_naps); 781#else 782 { 783 printf("NCPU cannot be different than actual CPU count.\n"); 784 printf(" add 'options NCPU=%d' to your kernel config file,\n", 785 mp_naps); 786 printf(" then rerun config & rebuild your SMP kernel\n"); 787 mustpanic = 1; 788 } 789#endif /* XXX FIXME: kern/4255 */ 790 if (mp_nbusses > NBUS) { 791 printf("found %d busses, increase NBUS\n", mp_nbusses); 792 mustpanic = 1; 793 } 794 if (mp_napics > NAPIC) { 795 printf("found %d apics, increase NAPIC\n", mp_napics); 796 mustpanic = 1; 797 } 798 if (nintrs > NINTR) { 799 printf("found %d intrs, increase NINTR\n", nintrs); 800 mustpanic = 1; 801 } 802 803 /* 804 * Count the BSP. 805 * This is also used as a counter while starting the APs. 806 */ 807 mp_ncpus = 1; 808 809 --mp_naps; /* subtract the BSP */ 810 811 return mustpanic; 812} 813 814 815/* 816 * 2nd pass on motherboard's Intel MP specification table. 817 * 818 * sets: 819 * boot_cpu_id 820 * ID_TO_IO(N), phy APIC ID to log CPU/IO table 821 * CPU_TO_ID(N), logical CPU to APIC ID table 822 * IO_TO_ID(N), logical IO to APIC ID table 823 * bus_data[N] 824 * io_apic_ints[N] 825 */ 826static int 827mptable_pass2(void) 828{ 829 int x; 830 mpcth_t cth; 831 int totalSize; 832 void* position; 833 int count; 834 int type; 835 int apic, bus, cpu, intr; 836 837 POSTCODE(MPTABLE_PASS2_POST); 838 839 /* clear various tables */ 840 for (x = 0; x < NAPICID; ++x) { 841 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */ 842 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */ 843 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */ 844 } 845 846 /* clear bus data table */ 847 for (x = 0; x < NBUS; ++x) 848 bus_data[x].bus_id = 0xff; 849 850 /* clear IO APIC INT table */ 851 for (x = 0; x < NINTR; ++x) 852 io_apic_ints[x].int_type = 0xff; 853 854 /* setup the cpu/apic mapping arrays */ 855 boot_cpu_id = -1; 856 857 /* record whether PIC or virtual-wire mode */ 858 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0; 859 860 /* check for use of 'default' configuration */ 861 if (MPFPS_MPFB1 != 0) 862 return MPFPS_MPFB1; /* return default configuration type */ 863 864 if ((cth = mpfps->pap) == 0) 865 panic("MP Configuration Table Header MISSING!"); 866 867 /* walk the table, recording info of interest */ 868 totalSize = cth->base_table_length - sizeof(struct MPCTH); 869 position = (u_char *) cth + sizeof(struct MPCTH); 870 count = cth->entry_count; 871 apic = bus = intr = 0; 872 cpu = 1; /* pre-count the BSP */ 873 874 while (count--) { 875 switch (type = *(u_char *) position) { 876 case 0: 877 if (processor_entry(position, cpu)) 878 ++cpu; 879 break; 880 case 1: 881 if (bus_entry(position, bus)) 882 ++bus; 883 break; 884 case 2: 885 if (io_apic_entry(position, apic)) 886 ++apic; 887 break; 888 case 3: 889 if (int_entry(position, intr)) 890 ++intr; 891 break; 892 case 4: 893 /* int_entry(position); */ 894 break; 895 default: 896 panic("mpfps Base Table HOSED!"); 897 /* NOTREACHED */ 898 } 899 900 totalSize -= basetable_entry_types[type].length; 901 (u_char *) position += basetable_entry_types[type].length; 902 } 903 904 if (boot_cpu_id == -1) 905 panic("NO BSP found!"); 906 907 /* report fact that its NOT a default configuration */ 908 return 0; 909} 910 911 912/* 913 * parse an Intel MP specification table 914 */ 915static void 916fix_mp_table(void) 917{ 918 int x; 919 int id; 920 int bus_0; 921 int bus_pci; 922 int num_pci_bus; 923 924 /* 925 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS 926 * did it wrong. The MP spec says that when more than 1 PCI bus 927 * exists the BIOS must begin with bus entries for the PCI bus and use 928 * actual PCI bus numbering. This implies that when only 1 PCI bus 929 * exists the BIOS can choose to ignore this ordering, and indeed many 930 * MP motherboards do ignore it. This causes a problem when the PCI 931 * sub-system makes requests of the MP sub-system based on PCI bus 932 * numbers. So here we look for the situation and renumber the 933 * busses and associated INTs in an effort to "make it right". 934 */ 935 936 /* find bus 0, PCI bus, count the number of PCI busses */ 937 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { 938 if (bus_data[x].bus_id == 0) { 939 bus_0 = x; 940 } 941 if (bus_data[x].bus_type == PCI) { 942 ++num_pci_bus; 943 bus_pci = x; 944 } 945 } 946 /* 947 * bus_0 == slot of bus with ID of 0 948 * bus_pci == slot of last PCI bus encountered 949 */ 950 951 /* check the 1 PCI bus case for sanity */ 952 if (num_pci_bus == 1) { 953 954 /* if it is number 0 all is well */ 955 if (bus_data[bus_pci].bus_id == 0) 956 return; 957 958 /* mis-numbered, swap with whichever bus uses slot 0 */ 959 960 /* swap the bus entry types */ 961 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type; 962 bus_data[bus_0].bus_type = PCI; 963 964 /* swap each relavant INTerrupt entry */ 965 id = bus_data[bus_pci].bus_id; 966 for (x = 0; x < nintrs; ++x) { 967 if (io_apic_ints[x].src_bus_id == id) { 968 io_apic_ints[x].src_bus_id = 0; 969 } 970 else if (io_apic_ints[x].src_bus_id == 0) { 971 io_apic_ints[x].src_bus_id = id; 972 } 973 } 974 } 975 /* sanity check if more than 1 PCI bus */ 976 else if (num_pci_bus > 1) { 977 for (x = 0; x < mp_nbusses; ++x) { 978 if (bus_data[x].bus_type != PCI) 979 continue; 980 if (bus_data[x].bus_id >= num_pci_bus) 981 panic("bad PCI bus numbering"); 982 } 983 } 984} 985 986 987static int 988processor_entry(proc_entry_ptr entry, int cpu) 989{ 990 /* check for usability */ 991 if ((cpu >= NCPU) || !(entry->cpu_flags & PROCENTRY_FLAG_EN)) 992 return 0; 993 994 /* check for BSP flag */ 995 if (entry->cpu_flags & PROCENTRY_FLAG_BP) { 996 boot_cpu_id = entry->apic_id; 997 CPU_TO_ID(0) = entry->apic_id; 998 ID_TO_CPU(entry->apic_id) = 0; 999 return 0; /* its already been counted */ 1000 } 1001 1002 /* add another AP to list, if less than max number of CPUs */ 1003 else { 1004 CPU_TO_ID(cpu) = entry->apic_id; 1005 ID_TO_CPU(entry->apic_id) = cpu; 1006 return 1; 1007 } 1008} 1009 1010 1011static int 1012bus_entry(bus_entry_ptr entry, int bus) 1013{ 1014 int x; 1015 char c, name[8]; 1016 1017 /* encode the name into an index */ 1018 for (x = 0; x < 6; ++x) { 1019 if ((c = entry->bus_type[x]) == ' ') 1020 break; 1021 name[x] = c; 1022 } 1023 name[x] = '\0'; 1024 1025 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) 1026 panic("unknown bus type: '%s'", name); 1027 1028 bus_data[bus].bus_id = entry->bus_id; 1029 bus_data[bus].bus_type = x; 1030 1031 return 1; 1032} 1033 1034 1035static int 1036io_apic_entry(io_apic_entry_ptr entry, int apic) 1037{ 1038 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) 1039 return 0; 1040 1041 IO_TO_ID(apic) = entry->apic_id; 1042 ID_TO_IO(entry->apic_id) = apic; 1043 1044 return 1; 1045} 1046 1047 1048static int 1049lookup_bus_type(char *name) 1050{ 1051 int x; 1052 1053 for (x = 0; x < MAX_BUSTYPE; ++x) 1054 if (strcmp(bus_type_table[x].name, name) == 0) 1055 return bus_type_table[x].type; 1056 1057 return UNKNOWN_BUSTYPE; 1058} 1059 1060 1061static int 1062int_entry(int_entry_ptr entry, int intr) 1063{ 1064 io_apic_ints[intr].int_type = entry->int_type; 1065 io_apic_ints[intr].int_flags = entry->int_flags; 1066 io_apic_ints[intr].src_bus_id = entry->src_bus_id; 1067 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq; 1068 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; 1069 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int; 1070 1071 return 1; 1072} 1073 1074 1075static int 1076apic_int_is_bus_type(int intr, int bus_type) 1077{ 1078 int bus; 1079 1080 for (bus = 0; bus < mp_nbusses; ++bus) 1081 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) 1082 && ((int) bus_data[bus].bus_type == bus_type)) 1083 return 1; 1084 1085 return 0; 1086} 1087 1088 1089/* 1090 * Given a traditional ISA INT mask, return an APIC mask. 1091 */ 1092u_int 1093isa_apic_mask(u_int isa_mask) 1094{ 1095 int isa_irq; 1096 int apic_pin; 1097 1098#if defined(SKIP_IRQ15_REDIRECT) 1099 if (isa_mask == (1 << 15)) { 1100 printf("skipping ISA IRQ15 redirect\n"); 1101 return isa_mask; 1102 } 1103#endif /* SKIP_IRQ15_REDIRECT */ 1104 1105 isa_irq = ffs(isa_mask); /* find its bit position */ 1106 if (isa_irq == 0) /* doesn't exist */ 1107 return 0; 1108 --isa_irq; /* make it zero based */ 1109 1110 apic_pin = isa_apic_pin(isa_irq); /* look for APIC connection */ 1111 if (apic_pin == -1) 1112 return 0; 1113 1114 return (1 << apic_pin); /* convert pin# to a mask */ 1115} 1116 1117 1118/* 1119 * Determine which APIC pin an ISA/EISA INT is attached to. 1120 */ 1121#define INTTYPE(I) (io_apic_ints[(I)].int_type) 1122#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) 1123 1124#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) 1125int 1126isa_apic_pin(int isa_irq) 1127{ 1128 int intr; 1129 1130 for (intr = 0; intr < nintrs; ++intr) { /* check each record */ 1131 if (INTTYPE(intr) == 0) { /* standard INT */ 1132 if (SRCBUSIRQ(intr) == isa_irq) { 1133 if (apic_int_is_bus_type(intr, ISA) || 1134 apic_int_is_bus_type(intr, EISA)) 1135 return INTPIN(intr); /* found */ 1136 } 1137 } 1138 } 1139 return -1; /* NOT found */ 1140} 1141#undef SRCBUSIRQ 1142 1143 1144/* 1145 * Determine which APIC pin a PCI INT is attached to. 1146 */ 1147#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) 1148#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) 1149#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) 1150int 1151pci_apic_pin(int pciBus, int pciDevice, int pciInt) 1152{ 1153 int intr; 1154 1155 --pciInt; /* zero based */ 1156 1157 for (intr = 0; intr < nintrs; ++intr) /* check each record */ 1158 if ((INTTYPE(intr) == 0) /* standard INT */ 1159 && (SRCBUSID(intr) == pciBus) 1160 && (SRCBUSDEVICE(intr) == pciDevice) 1161 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ 1162 if (apic_int_is_bus_type(intr, PCI)) 1163 return INTPIN(intr); /* exact match */ 1164 1165 return -1; /* NOT found */ 1166} 1167#undef SRCBUSLINE 1168#undef SRCBUSDEVICE 1169#undef SRCBUSID 1170 1171#undef INTPIN 1172#undef INTTYPE 1173 1174 1175/* 1176 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt. 1177 * 1178 * XXX FIXME: 1179 * Exactly what this means is unclear at this point. It is a solution 1180 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard 1181 * could route any of the ISA INTs to upper (>15) IRQ values. But most would 1182 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an 1183 * option. 1184 */ 1185int 1186undirect_isa_irq(int rirq) 1187{ 1188#if defined(READY) 1189 printf("Freeing redirected ISA irq %d.\n", rirq); 1190 /** FIXME: tickle the MB redirector chip */ 1191 return ???; 1192#else 1193 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq); 1194 return 0; 1195#endif /* READY */ 1196} 1197 1198 1199/* 1200 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt 1201 */ 1202int 1203undirect_pci_irq(int rirq) 1204{ 1205#if defined(READY) 1206 if (bootverbose) 1207 printf("Freeing redirected PCI irq %d.\n", rirq); 1208 1209 /** FIXME: tickle the MB redirector chip */ 1210 return ???; 1211#else 1212 if (bootverbose) 1213 printf("Freeing (NOT implemented) redirected PCI irq %d.\n", 1214 rirq); 1215 return 0; 1216#endif /* READY */ 1217} 1218 1219 1220/* 1221 * given a bus ID, return: 1222 * the bus type if found 1223 * -1 if NOT found 1224 */ 1225int 1226apic_bus_type(int id) 1227{ 1228 int x; 1229 1230 for (x = 0; x < mp_nbusses; ++x) 1231 if (bus_data[x].bus_id == id) 1232 return bus_data[x].bus_type; 1233 1234 return -1; 1235} 1236 1237 1238/* 1239 * given a LOGICAL APIC# and pin#, return: 1240 * the associated src bus ID if found 1241 * -1 if NOT found 1242 */ 1243int 1244apic_src_bus_id(int apic, int pin) 1245{ 1246 int x; 1247 1248 /* search each of the possible INTerrupt sources */ 1249 for (x = 0; x < nintrs; ++x) 1250 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1251 (pin == io_apic_ints[x].dst_apic_int)) 1252 return (io_apic_ints[x].src_bus_id); 1253 1254 return -1; /* NOT found */ 1255} 1256 1257 1258/* 1259 * given a LOGICAL APIC# and pin#, return: 1260 * the associated src bus IRQ if found 1261 * -1 if NOT found 1262 */ 1263int 1264apic_src_bus_irq(int apic, int pin) 1265{ 1266 int x; 1267 1268 for (x = 0; x < nintrs; x++) 1269 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1270 (pin == io_apic_ints[x].dst_apic_int)) 1271 return (io_apic_ints[x].src_bus_irq); 1272 1273 return -1; /* NOT found */ 1274} 1275 1276 1277/* 1278 * given a LOGICAL APIC# and pin#, return: 1279 * the associated INTerrupt type if found 1280 * -1 if NOT found 1281 */ 1282int 1283apic_int_type(int apic, int pin) 1284{ 1285 int x; 1286 1287 /* search each of the possible INTerrupt sources */ 1288 for (x = 0; x < nintrs; ++x) 1289 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1290 (pin == io_apic_ints[x].dst_apic_int)) 1291 return (io_apic_ints[x].int_type); 1292 1293 return -1; /* NOT found */ 1294} 1295 1296 1297/* 1298 * given a LOGICAL APIC# and pin#, return: 1299 * the associated trigger mode if found 1300 * -1 if NOT found 1301 */ 1302int 1303apic_trigger(int apic, int pin) 1304{ 1305 int x; 1306 1307 /* search each of the possible INTerrupt sources */ 1308 for (x = 0; x < nintrs; ++x) 1309 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1310 (pin == io_apic_ints[x].dst_apic_int)) 1311 return ((io_apic_ints[x].int_flags >> 2) & 0x03); 1312 1313 return -1; /* NOT found */ 1314} 1315 1316 1317/* 1318 * given a LOGICAL APIC# and pin#, return: 1319 * the associated 'active' level if found 1320 * -1 if NOT found 1321 */ 1322int 1323apic_polarity(int apic, int pin) 1324{ 1325 int x; 1326 1327 /* search each of the possible INTerrupt sources */ 1328 for (x = 0; x < nintrs; ++x) 1329 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1330 (pin == io_apic_ints[x].dst_apic_int)) 1331 return (io_apic_ints[x].int_flags & 0x03); 1332 1333 return -1; /* NOT found */ 1334} 1335 1336 1337/* 1338 * set data according to MP defaults 1339 * FIXME: probably not complete yet... 1340 */ 1341static void 1342default_mp_table(int type) 1343{ 1344 int ap_cpu_id; 1345#if defined(APIC_IO) 1346 u_int32_t ux; 1347 int io_apic_id; 1348 int pin; 1349#endif /* APIC_IO */ 1350 1351#if 0 1352 printf(" MP default config type: %d\n", type); 1353 switch (type) { 1354 case 1: 1355 printf(" bus: ISA, APIC: 82489DX\n"); 1356 break; 1357 case 2: 1358 printf(" bus: EISA, APIC: 82489DX\n"); 1359 break; 1360 case 3: 1361 printf(" bus: EISA, APIC: 82489DX\n"); 1362 break; 1363 case 4: 1364 printf(" bus: MCA, APIC: 82489DX\n"); 1365 break; 1366 case 5: 1367 printf(" bus: ISA+PCI, APIC: Integrated\n"); 1368 break; 1369 case 6: 1370 printf(" bus: EISA+PCI, APIC: Integrated\n"); 1371 break; 1372 case 7: 1373 printf(" bus: MCA+PCI, APIC: Integrated\n"); 1374 break; 1375 default: 1376 printf(" future type\n"); 1377 break; 1378 /* NOTREACHED */ 1379 } 1380#endif /* 0 */ 1381 1382 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24; 1383 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; 1384 1385 /* BSP */ 1386 CPU_TO_ID(0) = boot_cpu_id; 1387 ID_TO_CPU(boot_cpu_id) = 0; 1388 1389 /* one and only AP */ 1390 CPU_TO_ID(1) = ap_cpu_id; 1391 ID_TO_CPU(ap_cpu_id) = 1; 1392 1393#if defined(APIC_IO) 1394 /* one and only IO APIC */ 1395 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; 1396 1397 /* 1398 * sanity check, refer to MP spec section 3.6.6, last paragraph 1399 * necessary as some hardware isn't properly setting up the IO APIC 1400 */ 1401#if defined(REALLY_ANAL_IOAPICID_VALUE) 1402 if (io_apic_id != 2) { 1403#else 1404 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { 1405#endif /* REALLY_ANAL_IOAPICID_VALUE */ 1406 ux = io_apic_read(0, IOAPIC_ID); /* get current contents */ 1407 ux &= ~APIC_ID_MASK; /* clear the ID field */ 1408 ux |= 0x02000000; /* set it to '2' */ 1409 io_apic_write(0, IOAPIC_ID, ux); /* write new value */ 1410 ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */ 1411 if ((ux & APIC_ID_MASK) != 0x02000000) 1412 panic("can't control IO APIC ID, reg: 0x%08x", ux); 1413 io_apic_id = 2; 1414 } 1415 IO_TO_ID(0) = io_apic_id; 1416 ID_TO_IO(io_apic_id) = 0; 1417#endif /* APIC_IO */ 1418 1419 /* fill out bus entries */ 1420 switch (type) { 1421 case 1: 1422 case 2: 1423 case 3: 1424 case 5: 1425 case 6: 1426 bus_data[0].bus_id = default_data[type - 1][1]; 1427 bus_data[0].bus_type = default_data[type - 1][2]; 1428 bus_data[1].bus_id = default_data[type - 1][3]; 1429 bus_data[1].bus_type = default_data[type - 1][4]; 1430 break; 1431 1432 /* case 4: case 7: MCA NOT supported */ 1433 default: /* illegal/reserved */ 1434 panic("BAD default MP config: %d", type); 1435 /* NOTREACHED */ 1436 } 1437 1438#if defined(APIC_IO) 1439 /* general cases from MP v1.4, table 5-2 */ 1440 for (pin = 0; pin < 16; ++pin) { 1441 io_apic_ints[pin].int_type = 0; 1442 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */ 1443 io_apic_ints[pin].src_bus_id = 0; 1444 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */ 1445 io_apic_ints[pin].dst_apic_id = io_apic_id; 1446 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */ 1447 } 1448 1449 /* special cases from MP v1.4, table 5-2 */ 1450 if (type == 2) { 1451 io_apic_ints[2].int_type = 0xff; /* N/C */ 1452 io_apic_ints[13].int_type = 0xff; /* N/C */ 1453#if !defined(APIC_MIXED_MODE) 1454 /** FIXME: ??? */ 1455 panic("sorry, can't support type 2 default yet"); 1456#endif /* APIC_MIXED_MODE */ 1457 } 1458 else 1459 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ 1460 1461 if (type == 7) 1462 io_apic_ints[0].int_type = 0xff; /* N/C */ 1463 else 1464 io_apic_ints[0].int_type = 3; /* vectored 8259 */ 1465#endif /* APIC_IO */ 1466} 1467 1468 1469/* 1470 * initialize all the SMP locks 1471 */ 1472 1473/* critical region around IO APIC, apic_imen */ 1474struct simplelock imen_lock; 1475 1476/* critical region around splxx(), cpl, cml, cil, ipending */ 1477struct simplelock cpl_lock; 1478 1479/* Make FAST_INTR() routines sequential */ 1480struct simplelock fast_intr_lock; 1481 1482/* critical region around INTR() routines */ 1483struct simplelock intr_lock; 1484 1485/* lock regions protected in UP kernel via cli/sti */ 1486struct simplelock mpintr_lock; 1487 1488#ifdef USE_COMLOCK 1489/* locks com (tty) data/hardware accesses: a FASTINTR() */ 1490struct simplelock com_lock; 1491#endif /* USE_COMLOCK */ 1492 1493#ifdef USE_CLOCKLOCK 1494/* lock regions around the clock hardware */ 1495struct simplelock clock_lock; 1496#endif /* USE_CLOCKLOCK */ 1497 1498static void 1499init_locks(void) 1500{ 1501 /* 1502 * Get the initial mp_lock with a count of 1 for the BSP. 1503 * This uses a LOGICAL cpu ID, ie BSP == 0. 1504 */ 1505 mp_lock = 0x00000001; 1506 1507 /* ISR uses its own "giant lock" */ 1508 isr_lock = FREE_LOCK; 1509 1510 s_lock_init((struct simplelock*)&mpintr_lock); 1511 1512 s_lock_init((struct simplelock*)&fast_intr_lock); 1513 s_lock_init((struct simplelock*)&intr_lock); 1514 s_lock_init((struct simplelock*)&imen_lock); 1515 s_lock_init((struct simplelock*)&cpl_lock); 1516 1517#ifdef USE_COMLOCK 1518 s_lock_init((struct simplelock*)&com_lock); 1519#endif /* USE_COMLOCK */ 1520#ifdef USE_CLOCKLOCK 1521 s_lock_init((struct simplelock*)&clock_lock); 1522#endif /* USE_CLOCKLOCK */ 1523} 1524 1525 1526/* 1527 * start each AP in our list 1528 */ 1529static int 1530start_all_aps(u_int boot_addr) 1531{ 1532 int x, i; 1533 u_char mpbiosreason; 1534 u_long mpbioswarmvec; 1535 pd_entry_t *newptd; 1536 pt_entry_t *newpt; 1537 int *newpp; 1538 char *stack; 1539 pd_entry_t *myPTD; 1540 1541 POSTCODE(START_ALL_APS_POST); 1542 1543 /* initialize BSP's local APIC */ 1544 apic_initialize(); 1545 bsp_apic_ready = 1; 1546 1547 /* install the AP 1st level boot code */ 1548 install_ap_tramp(boot_addr); 1549 1550 1551 /* save the current value of the warm-start vector */ 1552 mpbioswarmvec = *((u_long *) WARMBOOT_OFF); 1553 outb(CMOS_REG, BIOS_RESET); 1554 mpbiosreason = inb(CMOS_DATA); 1555 1556 /* record BSP in CPU map */ 1557 all_cpus = 1; 1558 1559 /* start each AP */ 1560 for (x = 1; x <= mp_naps; ++x) { 1561 1562 /* This is a bit verbose, it will go away soon. */ 1563 1564 /* alloc new page table directory */ 1565 newptd = (pd_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE)); 1566 1567 /* Store the virtual PTD address for this CPU */ 1568 IdlePTDS[x] = newptd; 1569 1570 /* clone currently active one (ie: IdlePTD) */ 1571 bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */ 1572 1573 /* set up 0 -> 4MB P==V mapping for AP boot */ 1574 newptd[0] = (pd_entry_t) (PG_V | PG_RW | 1575 ((u_long)KPTphys & PG_FRAME)); 1576 1577 /* store PTD for this AP's boot sequence */ 1578 myPTD = (pd_entry_t *)vtophys(newptd); 1579 1580 /* alloc new page table page */ 1581 newpt = (pt_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE)); 1582 1583 /* set the new PTD's private page to point there */ 1584 newptd[MPPTDI] = (pt_entry_t)(PG_V | PG_RW | vtophys(newpt)); 1585 1586 /* install self referential entry */ 1587 newptd[PTDPTDI] = (pd_entry_t)(PG_V | PG_RW | vtophys(newptd)); 1588 1589 /* allocate a new private data page */ 1590 newpp = (int *)kmem_alloc(kernel_map, PAGE_SIZE); 1591 1592 /* wire it into the private page table page */ 1593 newpt[0] = (pt_entry_t)(PG_V | PG_RW | vtophys(newpp)); 1594 1595 /* wire the ptp into itself for access */ 1596 newpt[1] = (pt_entry_t)(PG_V | PG_RW | vtophys(newpt)); 1597 1598 /* copy in the pointer to the local apic */ 1599 newpt[2] = SMP_prvpt[2]; 1600 1601 /* and the IO apic mapping[s] */ 1602 for (i = 16; i < 32; i++) 1603 newpt[i] = SMP_prvpt[i]; 1604 1605 /* allocate and set up an idle stack data page */ 1606 stack = (char *)kmem_alloc(kernel_map, UPAGES*PAGE_SIZE); 1607 for (i = 0; i < UPAGES; i++) 1608 newpt[i + 3] = (pt_entry_t)(PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 1609 1610 newpt[5] = 0; /* *prv_CMAP1 */ 1611 newpt[6] = 0; /* *prv_CMAP2 */ 1612 newpt[7] = 0; /* *prv_CMAP3 */ 1613 1614 /* prime data page for it to use */ 1615 newpp[0] = x; /* cpuid */ 1616 newpp[1] = 0; /* curproc */ 1617 newpp[2] = 0; /* curpcb */ 1618 newpp[3] = 0; /* npxproc */ 1619 newpp[4] = 0; /* runtime.tv_sec */ 1620 newpp[5] = 0; /* runtime.tv_usec */ 1621 newpp[6] = x << 24; /* cpu_lockid */ 1622 newpp[7] = 0; /* other_cpus */ 1623 newpp[8] = (int)myPTD; /* my_idlePTD */ 1624 newpp[9] = 0; /* ss_tpr */ 1625 newpp[10] = (int)&newpt[5]; /* prv_CMAP1 */ 1626 newpp[11] = (int)&newpt[6]; /* prv_CMAP2 */ 1627 newpp[12] = (int)&newpt[7]; /* prv_CMAP3 */ 1628 1629 /* setup a vector to our boot code */ 1630 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 1631 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); 1632 outb(CMOS_REG, BIOS_RESET); 1633 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 1634 1635 bootPTD = myPTD; 1636 /* attempt to start the Application Processor */ 1637 CHECK_INIT(99); /* setup checkpoints */ 1638 if (!start_ap(x, boot_addr)) { 1639 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); 1640 CHECK_PRINT("trace"); /* show checkpoints */ 1641 /* better panic as the AP may be running loose */ 1642 printf("panic y/n? [y] "); 1643 if (cngetc() != 'n') 1644 panic("bye-bye"); 1645 } 1646 CHECK_PRINT("trace"); /* show checkpoints */ 1647 1648 /* record its version info */ 1649 cpu_apic_versions[x] = cpu_apic_versions[0]; 1650 1651 all_cpus |= (1 << x); /* record AP in CPU map */ 1652 } 1653 1654 /* build our map of 'other' CPUs */ 1655 other_cpus = all_cpus & ~(1 << cpuid); 1656 1657 /* fill in our (BSP) APIC version */ 1658 cpu_apic_versions[0] = lapic.version; 1659 1660 /* restore the warmstart vector */ 1661 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 1662 outb(CMOS_REG, BIOS_RESET); 1663 outb(CMOS_DATA, mpbiosreason); 1664 1665 /* 1666 * Set up the idle context for the BSP. Similar to above except 1667 * that some was done by locore, some by pmap.c and some is implicit 1668 * because the BSP is cpu#0 and the page is initially zero, and also 1669 * because we can refer to variables by name on the BSP.. 1670 */ 1671 newptd = (pd_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE)); 1672 1673 bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */ 1674 IdlePTDS[0] = newptd; 1675 1676 /* Point PTD[] to this page instead of IdlePTD's physical page */ 1677 newptd[PTDPTDI] = (pd_entry_t)(PG_V | PG_RW | vtophys(newptd)); 1678 1679 my_idlePTD = (pd_entry_t *)vtophys(newptd); 1680 1681 /* Allocate and setup BSP idle stack */ 1682 stack = (char *)kmem_alloc(kernel_map, UPAGES * PAGE_SIZE); 1683 for (i = 0; i < UPAGES; i++) 1684 SMP_prvpt[i + 3] = (pt_entry_t)(PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 1685 1686 pmap_set_opt_bsp(); 1687 1688 for (i = 0; i < mp_ncpus; i++) { 1689 bcopy( (int *) PTD + KPTDI, (int *) IdlePTDS[i] + KPTDI, NKPDE * sizeof (int)); 1690 } 1691 1692 /* number of APs actually started */ 1693 return mp_ncpus - 1; 1694} 1695 1696 1697/* 1698 * load the 1st level AP boot code into base memory. 1699 */ 1700 1701/* targets for relocation */ 1702extern void bigJump(void); 1703extern void bootCodeSeg(void); 1704extern void bootDataSeg(void); 1705extern void MPentry(void); 1706extern u_int MP_GDT; 1707extern u_int mp_gdtbase; 1708 1709static void 1710install_ap_tramp(u_int boot_addr) 1711{ 1712 int x; 1713 int size = *(int *) ((u_long) & bootMP_size); 1714 u_char *src = (u_char *) ((u_long) bootMP); 1715 u_char *dst = (u_char *) boot_addr + KERNBASE; 1716 u_int boot_base = (u_int) bootMP; 1717 u_int8_t *dst8; 1718 u_int16_t *dst16; 1719 u_int32_t *dst32; 1720 1721 POSTCODE(INSTALL_AP_TRAMP_POST); 1722 1723 for (x = 0; x < size; ++x) 1724 *dst++ = *src++; 1725 1726 /* 1727 * modify addresses in code we just moved to basemem. unfortunately we 1728 * need fairly detailed info about mpboot.s for this to work. changes 1729 * to mpboot.s might require changes here. 1730 */ 1731 1732 /* boot code is located in KERNEL space */ 1733 dst = (u_char *) boot_addr + KERNBASE; 1734 1735 /* modify the lgdt arg */ 1736 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 1737 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); 1738 1739 /* modify the ljmp target for MPentry() */ 1740 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 1741 *dst32 = ((u_int) MPentry - KERNBASE); 1742 1743 /* modify the target for boot code segment */ 1744 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 1745 dst8 = (u_int8_t *) (dst16 + 1); 1746 *dst16 = (u_int) boot_addr & 0xffff; 1747 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1748 1749 /* modify the target for boot data segment */ 1750 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 1751 dst8 = (u_int8_t *) (dst16 + 1); 1752 *dst16 = (u_int) boot_addr & 0xffff; 1753 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1754} 1755 1756 1757/* 1758 * this function starts the AP (application processor) identified 1759 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 1760 * to accomplish this. This is necessary because of the nuances 1761 * of the different hardware we might encounter. It ain't pretty, 1762 * but it seems to work. 1763 */ 1764static int 1765start_ap(int logical_cpu, u_int boot_addr) 1766{ 1767 int physical_cpu; 1768 int vector; 1769 int cpus; 1770 u_long icr_lo, icr_hi; 1771 1772 POSTCODE(START_AP_POST); 1773 1774 /* get the PHYSICAL APIC ID# */ 1775 physical_cpu = CPU_TO_ID(logical_cpu); 1776 1777 /* calculate the vector */ 1778 vector = (boot_addr >> 12) & 0xff; 1779 1780 /* used as a watchpoint to signal AP startup */ 1781 cpus = mp_ncpus; 1782 1783 /* 1784 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 1785 * and running the target CPU. OR this INIT IPI might be latched (P5 1786 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 1787 * ignored. 1788 */ 1789 1790 /* setup the address for the target AP */ 1791 icr_hi = lapic.icr_hi & ~APIC_ID_MASK; 1792 icr_hi |= (physical_cpu << 24); 1793 lapic.icr_hi = icr_hi; 1794 1795 /* do an INIT IPI: assert RESET */ 1796 icr_lo = lapic.icr_lo & 0xfff00000; 1797 lapic.icr_lo = icr_lo | 0x0000c500; 1798 1799 /* wait for pending status end */ 1800 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1801 /* spin */ ; 1802 1803 /* do an INIT IPI: deassert RESET */ 1804 lapic.icr_lo = icr_lo | 0x00008500; 1805 1806 /* wait for pending status end */ 1807 u_sleep(10000); /* wait ~10mS */ 1808 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1809 /* spin */ ; 1810 1811 /* 1812 * next we do a STARTUP IPI: the previous INIT IPI might still be 1813 * latched, (P5 bug) this 1st STARTUP would then terminate 1814 * immediately, and the previously started INIT IPI would continue. OR 1815 * the previous INIT IPI has already run. and this STARTUP IPI will 1816 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 1817 * will run. 1818 */ 1819 1820 /* do a STARTUP IPI */ 1821 lapic.icr_lo = icr_lo | 0x00000600 | vector; 1822 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1823 /* spin */ ; 1824 u_sleep(200); /* wait ~200uS */ 1825 1826 /* 1827 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 1828 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 1829 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 1830 * recognized after hardware RESET or INIT IPI. 1831 */ 1832 1833 lapic.icr_lo = icr_lo | 0x00000600 | vector; 1834 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1835 /* spin */ ; 1836 u_sleep(200); /* wait ~200uS */ 1837 1838 /* wait for it to start */ 1839 set_apic_timer(5000000);/* == 5 seconds */ 1840 while (read_apic_timer()) 1841 if (mp_ncpus > cpus) 1842 return 1; /* return SUCCESS */ 1843 1844 return 0; /* return FAILURE */ 1845} 1846 1847 1848/* 1849 * Flush the TLB on all other CPU's 1850 * 1851 * XXX: Needs to handshake and wait for completion before proceding. 1852 */ 1853void 1854smp_invltlb(void) 1855{ 1856#if defined(APIC_IO) 1857 if (smp_started && invltlb_ok) 1858 all_but_self_ipi(XINVLTLB_OFFSET); 1859#endif /* APIC_IO */ 1860} 1861 1862void 1863invlpg(u_int addr) 1864{ 1865 __asm __volatile("invlpg (%0)"::"r"(addr):"memory"); 1866 1867 /* send a message to the other CPUs */ 1868 smp_invltlb(); 1869} 1870 1871void 1872invltlb(void) 1873{ 1874 u_long temp; 1875 1876 /* 1877 * This should be implemented as load_cr3(rcr3()) when load_cr3() is 1878 * inlined. 1879 */ 1880 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory"); 1881 1882 /* send a message to the other CPUs */ 1883 smp_invltlb(); 1884} 1885 1886 1887/* 1888 * When called the executing CPU will send an IPI to all other CPUs 1889 * requesting that they halt execution. 1890 * 1891 * Usually (but not necessarily) called with 'other_cpus' as its arg. 1892 * 1893 * - Signals all CPUs in map to stop. 1894 * - Waits for each to stop. 1895 * 1896 * Returns: 1897 * -1: error 1898 * 0: NA 1899 * 1: ok 1900 * 1901 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs 1902 * from executing at same time. 1903 */ 1904int 1905stop_cpus(u_int map) 1906{ 1907 if (!smp_started) 1908 return 0; 1909 1910 /* send IPI to all CPUs in map */ 1911 stopped_cpus = 0; 1912 1913 /* send the Xcpustop IPI to all CPUs in map */ 1914 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED); 1915 1916 while (stopped_cpus != map) 1917 /* spin */ ; 1918 1919 return 1; 1920} 1921 1922 1923/* 1924 * Called by a CPU to restart stopped CPUs. 1925 * 1926 * Usually (but not necessarily) called with 'stopped_cpus' as its arg. 1927 * 1928 * - Signals all CPUs in map to restart. 1929 * - Waits for each to restart. 1930 * 1931 * Returns: 1932 * -1: error 1933 * 0: NA 1934 * 1: ok 1935 */ 1936int 1937restart_cpus(u_int map) 1938{ 1939 if (!smp_started) 1940 return 0; 1941 1942 started_cpus = map; /* signal other cpus to restart */ 1943 1944 while (started_cpus) /* wait for each to clear its bit */ 1945 /* spin */ ; 1946 1947 return 1; 1948} 1949 1950int smp_active = 0; /* are the APs allowed to run? */ 1951SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RW, &smp_active, 0, ""); 1952 1953/* XXX maybe should be hw.ncpu */ 1954int smp_cpus = 1; /* how many cpu's running */ 1955SYSCTL_INT(_machdep, OID_AUTO, smp_cpus, CTLFLAG_RD, &smp_cpus, 0, ""); 1956 1957int invltlb_ok = 0; /* throttle smp_invltlb() till safe */ 1958SYSCTL_INT(_machdep, OID_AUTO, invltlb_ok, CTLFLAG_RW, &invltlb_ok, 0, ""); 1959 1960int do_page_zero_idle = 0; /* bzero pages for fun and profit in idleloop */ 1961SYSCTL_INT(_machdep, OID_AUTO, do_page_zero_idle, CTLFLAG_RW, 1962 &do_page_zero_idle, 0, ""); 1963 1964 1965/* 1966 * This is called once the rest of the system is up and running and we're 1967 * ready to let the AP's out of the pen. 1968 */ 1969void ap_init(void); 1970 1971void 1972ap_init() 1973{ 1974 u_int temp; 1975 u_int apic_id; 1976 1977 smp_cpus++; 1978 1979 /* Build our map of 'other' CPUs. */ 1980 other_cpus = all_cpus & ~(1 << cpuid); 1981 1982 printf("SMP: AP CPU #%d Launched!\n", cpuid); 1983 1984 /* XXX FIXME: i386 specific, and redundant: Setup the FPU. */ 1985 load_cr0((rcr0() & ~CR0_EM) | CR0_MP | CR0_NE | CR0_TS); 1986 1987 /* A quick check from sanity claus */ 1988 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]); 1989 if (cpuid != apic_id) { 1990 printf("SMP: cpuid = %d\n", cpuid); 1991 printf("SMP: apic_id = %d\n", apic_id); 1992 printf("PTD[MPPTDI] = %08x\n", PTD[MPPTDI]); 1993 panic("cpuid mismatch! boom!!"); 1994 } 1995 1996 /* Init local apic for irq's */ 1997 apic_initialize(); 1998 1999 /* 2000 * Activate smp_invltlb, although strictly speaking, this isn't 2001 * quite correct yet. We should have a bitfield for cpus willing 2002 * to accept TLB flush IPI's or something and sync them. 2003 */ 2004 invltlb_ok = 1; 2005 smp_started = 1; /* enable IPI's, tlb shootdown, freezes etc */ 2006 smp_active = 1; /* historic */ 2007 2008 curproc = NULL; /* make sure */ 2009} 2010 2011void 2012getmtrr() 2013{ 2014 int i; 2015 2016 if (cpu_class == CPUCLASS_686) { 2017 for(i = 0; i < NPPROVMTRR; i++) { 2018 PPro_vmtrr[i].base = rdmsr(PPRO_VMTRRphysBase0 + i * 2); 2019 PPro_vmtrr[i].mask = rdmsr(PPRO_VMTRRphysMask0 + i * 2); 2020 } 2021 } 2022} 2023 2024void 2025putmtrr() 2026{ 2027 int i; 2028 2029 if (cpu_class == CPUCLASS_686) { 2030 wbinvd(); 2031 for(i = 0; i < NPPROVMTRR; i++) { 2032 wrmsr(PPRO_VMTRRphysBase0 + i * 2, PPro_vmtrr[i].base); 2033 wrmsr(PPRO_VMTRRphysMask0 + i * 2, PPro_vmtrr[i].mask); 2034 } 2035 } 2036} 2037 2038void 2039putfmtrr() 2040{ 2041 if (cpu_class == CPUCLASS_686) { 2042 wbinvd(); 2043 /* 2044 * Set memory between 0-640K to be WB 2045 */ 2046 wrmsr(0x250, 0x0606060606060606LL); 2047 wrmsr(0x258, 0x0606060606060606LL); 2048 /* 2049 * Set normal, PC video memory to be WC 2050 */ 2051 wrmsr(0x259, 0x0101010101010101LL); 2052 } 2053} 2054