mptable.c revision 28999
1/* 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $Id: mp_machdep.c,v 1.49 1997/08/31 03:17:47 fsmp Exp $ 26 */ 27 28#include "opt_smp.h" 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/kernel.h> 33#include <sys/proc.h> 34#include <sys/sysctl.h> 35 36#include <vm/vm.h> 37#include <vm/vm_param.h> 38#include <vm/pmap.h> 39#include <vm/vm_kern.h> 40#include <vm/vm_extern.h> 41 42#include <machine/smp.h> 43#include <machine/apic.h> 44#include <machine/mpapic.h> 45#include <machine/segments.h> 46#include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */ 47#include <machine/tss.h> 48#include <machine/specialreg.h> 49 50#include <i386/i386/cons.h> /* cngetc() */ 51 52#if defined(APIC_IO) 53#include <machine/md_var.h> /* setidt() */ 54#include <i386/isa/icu.h> /* IPIs */ 55#include <i386/isa/intr_machdep.h> /* IPIs */ 56#endif /* APIC_IO */ 57 58#if defined(TEST_DEFAULT_CONFIG) 59#define MPFPS_MPFB1 TEST_DEFAULT_CONFIG 60#else 61#define MPFPS_MPFB1 mpfps->mpfb1 62#endif /* TEST_DEFAULT_CONFIG */ 63 64#define WARMBOOT_TARGET 0 65#define WARMBOOT_OFF (KERNBASE + 0x0467) 66#define WARMBOOT_SEG (KERNBASE + 0x0469) 67 68#define BIOS_BASE (0xf0000) 69#define BIOS_SIZE (0x10000) 70#define BIOS_COUNT (BIOS_SIZE/4) 71 72#define CMOS_REG (0x70) 73#define CMOS_DATA (0x71) 74#define BIOS_RESET (0x0f) 75#define BIOS_WARM (0x0a) 76 77#define PROCENTRY_FLAG_EN 0x01 78#define PROCENTRY_FLAG_BP 0x02 79#define IOAPICENTRY_FLAG_EN 0x01 80 81 82/* MP Floating Pointer Structure */ 83typedef struct MPFPS { 84 char signature[4]; 85 void *pap; 86 u_char length; 87 u_char spec_rev; 88 u_char checksum; 89 u_char mpfb1; 90 u_char mpfb2; 91 u_char mpfb3; 92 u_char mpfb4; 93 u_char mpfb5; 94} *mpfps_t; 95 96/* MP Configuration Table Header */ 97typedef struct MPCTH { 98 char signature[4]; 99 u_short base_table_length; 100 u_char spec_rev; 101 u_char checksum; 102 u_char oem_id[8]; 103 u_char product_id[12]; 104 void *oem_table_pointer; 105 u_short oem_table_size; 106 u_short entry_count; 107 void *apic_address; 108 u_short extended_table_length; 109 u_char extended_table_checksum; 110 u_char reserved; 111} *mpcth_t; 112 113 114typedef struct PROCENTRY { 115 u_char type; 116 u_char apic_id; 117 u_char apic_version; 118 u_char cpu_flags; 119 u_long cpu_signature; 120 u_long feature_flags; 121 u_long reserved1; 122 u_long reserved2; 123} *proc_entry_ptr; 124 125typedef struct BUSENTRY { 126 u_char type; 127 u_char bus_id; 128 char bus_type[6]; 129} *bus_entry_ptr; 130 131typedef struct IOAPICENTRY { 132 u_char type; 133 u_char apic_id; 134 u_char apic_version; 135 u_char apic_flags; 136 void *apic_address; 137} *io_apic_entry_ptr; 138 139typedef struct INTENTRY { 140 u_char type; 141 u_char int_type; 142 u_short int_flags; 143 u_char src_bus_id; 144 u_char src_bus_irq; 145 u_char dst_apic_id; 146 u_char dst_apic_int; 147} *int_entry_ptr; 148 149/* descriptions of MP basetable entries */ 150typedef struct BASETABLE_ENTRY { 151 u_char type; 152 u_char length; 153 char name[16]; 154} basetable_entry; 155 156/* 157 * this code MUST be enabled here and in mpboot.s. 158 * it follows the very early stages of AP boot by placing values in CMOS ram. 159 * it NORMALLY will never be needed and thus the primitive method for enabling. 160 * 161#define CHECK_POINTS 162 */ 163 164#if defined(CHECK_POINTS) 165#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 166#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 167 168#define CHECK_INIT(D); \ 169 CHECK_WRITE(0x34, (D)); \ 170 CHECK_WRITE(0x35, (D)); \ 171 CHECK_WRITE(0x36, (D)); \ 172 CHECK_WRITE(0x37, (D)); \ 173 CHECK_WRITE(0x38, (D)); \ 174 CHECK_WRITE(0x39, (D)); 175 176#define CHECK_PRINT(S); \ 177 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 178 (S), \ 179 CHECK_READ(0x34), \ 180 CHECK_READ(0x35), \ 181 CHECK_READ(0x36), \ 182 CHECK_READ(0x37), \ 183 CHECK_READ(0x38), \ 184 CHECK_READ(0x39)); 185 186#else /* CHECK_POINTS */ 187 188#define CHECK_INIT(D) 189#define CHECK_PRINT(S) 190 191#endif /* CHECK_POINTS */ 192 193/* 194 * Values to send to the POST hardware. 195 */ 196#define MP_BOOTADDRESS_POST 0x10 197#define MP_PROBE_POST 0x11 198#define MP_START_POST 0x12 199#define MP_ANNOUNCE_POST 0x13 200#define MPTABLE_PASS1_POST 0x14 201#define MPTABLE_PASS2_POST 0x15 202#define MP_ENABLE_POST 0x16 203#define START_ALL_APS_POST 0x17 204#define INSTALL_AP_TRAMP_POST 0x18 205#define START_AP_POST 0x19 206 207/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ 208int current_postcode; 209 210/** XXX FIXME: what system files declare these??? */ 211extern struct region_descriptor r_gdt, r_idt; 212 213int bsp_apic_ready = 0; /* flags useability of BSP apic */ 214int mp_ncpus; /* # of CPUs, including BSP */ 215int mp_naps; /* # of Applications processors */ 216int mp_nbusses; /* # of busses */ 217int mp_napics; /* # of IO APICs */ 218int boot_cpu_id; /* designated BSP */ 219vm_offset_t cpu_apic_address; 220vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */ 221 222u_int32_t cpu_apic_versions[NCPU]; 223u_int32_t io_apic_versions[NAPIC]; 224 225/* 226 * APIC ID logical/physical mapping structures. 227 * We oversize these to simplify boot-time config. 228 */ 229int cpu_num_to_apic_id[NAPICID]; 230int io_num_to_apic_id[NAPICID]; 231int apic_id_to_logical[NAPICID]; 232 233/* Bitmap of all available CPUs */ 234u_int all_cpus; 235 236/* AP uses this PTD during bootstrap */ 237pd_entry_t *bootPTD; 238 239/* Hotwire a 0->4MB V==P mapping */ 240extern pt_entry_t *KPTphys; 241 242/* Virtual address of per-cpu common_tss */ 243extern struct i386tss common_tss; 244#ifdef VM86 245extern u_int private_tss; /* flag indicating private tss */ 246extern struct segment_descriptor common_tssd; 247#endif /* VM86 */ 248 249/* IdlePTD per cpu */ 250pd_entry_t *IdlePTDS[NCPU]; 251 252/* "my" private page table page, for BSP init */ 253extern pt_entry_t SMP_prvpt[]; 254 255/* Private page pointer to curcpu's PTD, used during BSP init */ 256extern pd_entry_t *my_idlePTD; 257 258static int smp_started; /* has the system started? */ 259 260/* 261 * Local data and functions. 262 */ 263 264static int mp_capable; 265static u_int boot_address; 266static u_int base_memory; 267 268static int picmode; /* 0: virtual wire mode, 1: PIC mode */ 269static mpfps_t mpfps; 270static int search_for_sig(u_int32_t target, int count); 271static void mp_enable(u_int boot_addr); 272 273static int mptable_pass1(void); 274static int mptable_pass2(void); 275static void default_mp_table(int type); 276static void fix_mp_table(void); 277static void init_locks(void); 278static int start_all_aps(u_int boot_addr); 279static void install_ap_tramp(u_int boot_addr); 280static int start_ap(int logicalCpu, u_int boot_addr); 281 282 283/* 284 * Calculate usable address in base memory for AP trampoline code. 285 */ 286u_int 287mp_bootaddress(u_int basemem) 288{ 289 POSTCODE(MP_BOOTADDRESS_POST); 290 291 base_memory = basemem * 1024; /* convert to bytes */ 292 293 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ 294 if ((base_memory - boot_address) < bootMP_size) 295 boot_address -= 4096; /* not enough, lower by 4k */ 296 297 return boot_address; 298} 299 300 301/* 302 * Look for an Intel MP spec table (ie, SMP capable hardware). 303 */ 304int 305mp_probe(void) 306{ 307 int x; 308 u_long segment; 309 u_int32_t target; 310 311 POSTCODE(MP_PROBE_POST); 312 313 /* see if EBDA exists */ 314 if (segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) { 315 /* search first 1K of EBDA */ 316 target = (u_int32_t) (segment << 4); 317 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 318 goto found; 319 } else { 320 /* last 1K of base memory, effective 'top of base' passed in */ 321 target = (u_int32_t) (base_memory - 0x400); 322 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 323 goto found; 324 } 325 326 /* search the BIOS */ 327 target = (u_int32_t) BIOS_BASE; 328 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) 329 goto found; 330 331 /* nothing found */ 332 mpfps = (mpfps_t)0; 333 mp_capable = 0; 334 return 0; 335 336found: 337 /* calculate needed resources */ 338 mpfps = (mpfps_t)x; 339 if (mptable_pass1()) 340 panic("you must reconfigure your kernel"); 341 342 /* flag fact that we are running multiple processors */ 343 mp_capable = 1; 344 return 1; 345} 346 347 348/* 349 * Startup the SMP processors. 350 */ 351void 352mp_start(void) 353{ 354 POSTCODE(MP_START_POST); 355 356 /* look for MP capable motherboard */ 357 if (mp_capable) 358 mp_enable(boot_address); 359 else 360 panic("MP hardware not found!"); 361} 362 363 364/* 365 * Print various information about the SMP system hardware and setup. 366 */ 367void 368mp_announce(void) 369{ 370 int x; 371 372 POSTCODE(MP_ANNOUNCE_POST); 373 374 printf("FreeBSD/SMP: Multiprocessor motherboard\n"); 375 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0)); 376 printf(", version: 0x%08x", cpu_apic_versions[0]); 377 printf(", at 0x%08x\n", cpu_apic_address); 378 for (x = 1; x <= mp_naps; ++x) { 379 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x)); 380 printf(", version: 0x%08x", cpu_apic_versions[x]); 381 printf(", at 0x%08x\n", cpu_apic_address); 382 } 383 384#if defined(APIC_IO) 385 for (x = 0; x < mp_napics; ++x) { 386 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x)); 387 printf(", version: 0x%08x", io_apic_versions[x]); 388 printf(", at 0x%08x\n", io_apic_address[x]); 389 } 390#else 391 printf(" Warning: APIC I/O disabled\n"); 392#endif /* APIC_IO */ 393} 394 395/* 396 * AP cpu's call this to sync up protected mode. 397 */ 398void 399init_secondary(void) 400{ 401 int gsel_tss, slot; 402 403 r_gdt.rd_limit = sizeof(gdt[0]) * (NGDT + NCPU) - 1; 404 r_gdt.rd_base = (int) gdt; 405 lgdt(&r_gdt); /* does magic intra-segment return */ 406 lidt(&r_idt); 407 lldt(_default_ldt); 408 409 slot = NGDT + cpuid; 410 gsel_tss = GSEL(slot, SEL_KPL); 411 gdt[slot].sd.sd_type = SDT_SYS386TSS; 412 common_tss.tss_esp0 = 0; /* not used until after switch */ 413 common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 414 common_tss.tss_ioopt = (sizeof common_tss) << 16; 415#ifdef VM86 416 common_tssd = gdt[slot].sd; 417 private_tss = 0; 418#endif /* VM86 */ 419 ltr(gsel_tss); 420 421 load_cr0(0x8005003b); /* XXX! */ 422 423 PTD[0] = 0; 424 pmap_set_opt((unsigned *)PTD); 425 426 invltlb(); 427} 428 429 430#if defined(APIC_IO) 431/* 432 * Final configuration of the BSP's local APIC: 433 * - disable 'pic mode'. 434 * - disable 'virtual wire mode'. 435 * - enable NMI. 436 */ 437void 438bsp_apic_configure(void) 439{ 440 u_char byte; 441 u_int32_t temp; 442 443 /* leave 'pic mode' if necessary */ 444 if (picmode) { 445 outb(0x22, 0x70); /* select IMCR */ 446 byte = inb(0x23); /* current contents */ 447 byte |= 0x01; /* mask external INTR */ 448 outb(0x23, byte); /* disconnect 8259s/NMI */ 449 } 450 451 /* mask lint0 (the 8259 'virtual wire' connection) */ 452 temp = lapic.lvt_lint0; 453 temp |= APIC_LVT_M; /* set the mask */ 454 lapic.lvt_lint0 = temp; 455 456 /* setup lint1 to handle NMI */ 457 temp = lapic.lvt_lint1; 458 temp &= ~APIC_LVT_M; /* clear the mask */ 459 lapic.lvt_lint1 = temp; 460 461 if (bootverbose) 462 apic_dump("bsp_apic_configure()"); 463} 464#endif /* APIC_IO */ 465 466 467/******************************************************************* 468 * local functions and data 469 */ 470 471/* 472 * start the SMP system 473 */ 474static void 475mp_enable(u_int boot_addr) 476{ 477 int x; 478#if defined(APIC_IO) 479 int apic; 480 u_int ux; 481#endif /* APIC_IO */ 482 483 POSTCODE(MP_ENABLE_POST); 484 485 /* turn on 4MB of V == P addressing so we can get to MP table */ 486 *(int *)PTD = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME); 487 invltlb(); 488 489 /* examine the MP table for needed info, uses physical addresses */ 490 x = mptable_pass2(); 491 492 *(int *)PTD = 0; 493 invltlb(); 494 495 /* can't process default configs till the CPU APIC is pmapped */ 496 if (x) 497 default_mp_table(x); 498 499 /* post scan cleanup */ 500 fix_mp_table(); 501 502#if defined(APIC_IO) 503 504 /* fill the LOGICAL io_apic_versions table */ 505 for (apic = 0; apic < mp_napics; ++apic) { 506 ux = io_apic_read(apic, IOAPIC_VER); 507 io_apic_versions[apic] = ux; 508 } 509 510 /* program each IO APIC in the system */ 511 for (apic = 0; apic < mp_napics; ++apic) 512 if (io_apic_setup(apic) < 0) 513 panic("IO APIC setup failure"); 514 515 /* install a 'Spurious INTerrupt' vector */ 516 setidt(XSPURIOUSINT_OFFSET, Xspuriousint, 517 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 518 519 /* install an inter-CPU IPI for TLB invalidation */ 520 setidt(XINVLTLB_OFFSET, Xinvltlb, 521 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 522 523 /* install an inter-CPU IPI for CPU stop/restart */ 524 setidt(XCPUSTOP_OFFSET, Xcpustop, 525 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 526 527#if defined(TEST_TEST1) 528 /* install a "fake hardware INTerrupt" vector */ 529 setidt(XTEST1_OFFSET, Xtest1, 530 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 531#endif /** TEST_TEST1 */ 532 533#endif /* APIC_IO */ 534 535 /* initialize all SMP locks */ 536 init_locks(); 537 538 /* start each Application Processor */ 539 start_all_aps(boot_addr); 540 541 /* 542 * The init process might be started on a different CPU now, 543 * and the boot CPU might not call prepare_usermode to get 544 * cr0 correctly configured. Thus we initialize cr0 here. 545 */ 546 load_cr0(rcr0() | CR0_WP | CR0_AM); 547} 548 549 550/* 551 * look for the MP spec signature 552 */ 553 554/* string defined by the Intel MP Spec as identifying the MP table */ 555#define MP_SIG 0x5f504d5f /* _MP_ */ 556#define NEXT(X) ((X) += 4) 557static int 558search_for_sig(u_int32_t target, int count) 559{ 560 int x; 561 u_int32_t *addr = (u_int32_t *) (KERNBASE + target); 562 563 for (x = 0; x < count; NEXT(x)) 564 if (addr[x] == MP_SIG) 565 /* make array index a byte index */ 566 return (target + (x * sizeof(u_int32_t))); 567 568 return -1; 569} 570 571 572static basetable_entry basetable_entry_types[] = 573{ 574 {0, 20, "Processor"}, 575 {1, 8, "Bus"}, 576 {2, 8, "I/O APIC"}, 577 {3, 8, "I/O INT"}, 578 {4, 8, "Local INT"} 579}; 580 581typedef struct BUSDATA { 582 u_char bus_id; 583 enum busTypes bus_type; 584} bus_datum; 585 586typedef struct INTDATA { 587 u_char int_type; 588 u_short int_flags; 589 u_char src_bus_id; 590 u_char src_bus_irq; 591 u_char dst_apic_id; 592 u_char dst_apic_int; 593} io_int, local_int; 594 595typedef struct BUSTYPENAME { 596 u_char type; 597 char name[7]; 598} bus_type_name; 599 600static bus_type_name bus_type_table[] = 601{ 602 {CBUS, "CBUS"}, 603 {CBUSII, "CBUSII"}, 604 {EISA, "EISA"}, 605 {UNKNOWN_BUSTYPE, "---"}, 606 {UNKNOWN_BUSTYPE, "---"}, 607 {ISA, "ISA"}, 608 {UNKNOWN_BUSTYPE, "---"}, 609 {UNKNOWN_BUSTYPE, "---"}, 610 {UNKNOWN_BUSTYPE, "---"}, 611 {UNKNOWN_BUSTYPE, "---"}, 612 {UNKNOWN_BUSTYPE, "---"}, 613 {UNKNOWN_BUSTYPE, "---"}, 614 {PCI, "PCI"}, 615 {UNKNOWN_BUSTYPE, "---"}, 616 {UNKNOWN_BUSTYPE, "---"}, 617 {UNKNOWN_BUSTYPE, "---"}, 618 {UNKNOWN_BUSTYPE, "---"}, 619 {XPRESS, "XPRESS"}, 620 {UNKNOWN_BUSTYPE, "---"} 621}; 622/* from MP spec v1.4, table 5-1 */ 623static int default_data[7][5] = 624{ 625/* nbus, id0, type0, id1, type1 */ 626 {1, 0, ISA, 255, 255}, 627 {1, 0, EISA, 255, 255}, 628 {1, 0, EISA, 255, 255}, 629 {0, 255, 255, 255, 255},/* MCA not supported */ 630 {2, 0, ISA, 1, PCI}, 631 {2, 0, EISA, 1, PCI}, 632 {0, 255, 255, 255, 255} /* MCA not supported */ 633}; 634 635 636/* the bus data */ 637bus_datum bus_data[NBUS]; 638 639/* the IO INT data, one entry per possible APIC INTerrupt */ 640io_int io_apic_ints[NINTR]; 641 642static int nintrs; 643 644static int processor_entry __P((proc_entry_ptr entry, int cpu)); 645static int bus_entry __P((bus_entry_ptr entry, int bus)); 646static int io_apic_entry __P((io_apic_entry_ptr entry, int apic)); 647static int int_entry __P((int_entry_ptr entry, int intr)); 648static int lookup_bus_type __P((char *name)); 649 650 651/* 652 * 1st pass on motherboard's Intel MP specification table. 653 * 654 * initializes: 655 * mp_ncpus = 1 656 * 657 * determines: 658 * cpu_apic_address (common to all CPUs) 659 * io_apic_address[N] 660 * mp_naps 661 * mp_nbusses 662 * mp_napics 663 * nintrs 664 */ 665static int 666mptable_pass1(void) 667{ 668 int x; 669 mpcth_t cth; 670 int totalSize; 671 void* position; 672 int count; 673 int type; 674 int mustpanic; 675 676 POSTCODE(MPTABLE_PASS1_POST); 677 678 mustpanic = 0; 679 680 /* clear various tables */ 681 for (x = 0; x < NAPICID; ++x) { 682 io_apic_address[x] = ~0; /* IO APIC address table */ 683 } 684 685 /* init everything to empty */ 686 mp_naps = 0; 687 mp_nbusses = 0; 688 mp_napics = 0; 689 nintrs = 0; 690 691 /* check for use of 'default' configuration */ 692 if (MPFPS_MPFB1 != 0) { 693 /* use default addresses */ 694 cpu_apic_address = DEFAULT_APIC_BASE; 695 io_apic_address[0] = DEFAULT_IO_APIC_BASE; 696 697 /* fill in with defaults */ 698 mp_naps = 2; /* includes BSP */ 699 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0]; 700#if defined(APIC_IO) 701 mp_napics = 1; 702 nintrs = 16; 703#endif /* APIC_IO */ 704 } 705 else { 706 if ((cth = mpfps->pap) == 0) 707 panic("MP Configuration Table Header MISSING!"); 708 709 cpu_apic_address = (vm_offset_t) cth->apic_address; 710 711 /* walk the table, recording info of interest */ 712 totalSize = cth->base_table_length - sizeof(struct MPCTH); 713 position = (u_char *) cth + sizeof(struct MPCTH); 714 count = cth->entry_count; 715 716 while (count--) { 717 switch (type = *(u_char *) position) { 718 case 0: /* processor_entry */ 719 if (((proc_entry_ptr)position)->cpu_flags 720 & PROCENTRY_FLAG_EN) 721 ++mp_naps; 722 break; 723 case 1: /* bus_entry */ 724 ++mp_nbusses; 725 break; 726 case 2: /* io_apic_entry */ 727 if (((io_apic_entry_ptr)position)->apic_flags 728 & IOAPICENTRY_FLAG_EN) 729 io_apic_address[mp_napics++] = 730 (vm_offset_t)((io_apic_entry_ptr) 731 position)->apic_address; 732 break; 733 case 3: /* int_entry */ 734 ++nintrs; 735 break; 736 case 4: /* int_entry */ 737 break; 738 default: 739 panic("mpfps Base Table HOSED!"); 740 /* NOTREACHED */ 741 } 742 743 totalSize -= basetable_entry_types[type].length; 744 (u_char*)position += basetable_entry_types[type].length; 745 } 746 } 747 748 /* qualify the numbers */ 749 if (mp_naps > NCPU) 750#if 0 /* XXX FIXME: kern/4255 */ 751 printf("Warning: only using %d of %d available CPUs!\n", 752 NCPU, mp_naps); 753#else 754 { 755 printf("NCPU cannot be different than actual CPU count.\n"); 756 printf(" add 'options NCPU=%d' to your kernel config file,\n", 757 mp_naps); 758 printf(" then rerun config & rebuild your SMP kernel\n"); 759 mustpanic = 1; 760 } 761#endif /* XXX FIXME: kern/4255 */ 762 if (mp_nbusses > NBUS) { 763 printf("found %d busses, increase NBUS\n", mp_nbusses); 764 mustpanic = 1; 765 } 766 if (mp_napics > NAPIC) { 767 printf("found %d apics, increase NAPIC\n", mp_napics); 768 mustpanic = 1; 769 } 770 if (nintrs > NINTR) { 771 printf("found %d intrs, increase NINTR\n", nintrs); 772 mustpanic = 1; 773 } 774 775 /* 776 * Count the BSP. 777 * This is also used as a counter while starting the APs. 778 */ 779 mp_ncpus = 1; 780 781 --mp_naps; /* subtract the BSP */ 782 783 return mustpanic; 784} 785 786 787/* 788 * 2nd pass on motherboard's Intel MP specification table. 789 * 790 * sets: 791 * boot_cpu_id 792 * ID_TO_IO(N), phy APIC ID to log CPU/IO table 793 * CPU_TO_ID(N), logical CPU to APIC ID table 794 * IO_TO_ID(N), logical IO to APIC ID table 795 * bus_data[N] 796 * io_apic_ints[N] 797 */ 798static int 799mptable_pass2(void) 800{ 801 int x; 802 mpcth_t cth; 803 int totalSize; 804 void* position; 805 int count; 806 int type; 807 int apic, bus, cpu, intr; 808 809 POSTCODE(MPTABLE_PASS2_POST); 810 811 /* clear various tables */ 812 for (x = 0; x < NAPICID; ++x) { 813 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */ 814 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */ 815 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */ 816 } 817 818 /* clear bus data table */ 819 for (x = 0; x < NBUS; ++x) 820 bus_data[x].bus_id = 0xff; 821 822 /* clear IO APIC INT table */ 823 for (x = 0; x < NINTR; ++x) 824 io_apic_ints[x].int_type = 0xff; 825 826 /* setup the cpu/apic mapping arrays */ 827 boot_cpu_id = -1; 828 829 /* record whether PIC or virtual-wire mode */ 830 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0; 831 832 /* check for use of 'default' configuration */ 833 if (MPFPS_MPFB1 != 0) 834 return MPFPS_MPFB1; /* return default configuration type */ 835 836 if ((cth = mpfps->pap) == 0) 837 panic("MP Configuration Table Header MISSING!"); 838 839 /* walk the table, recording info of interest */ 840 totalSize = cth->base_table_length - sizeof(struct MPCTH); 841 position = (u_char *) cth + sizeof(struct MPCTH); 842 count = cth->entry_count; 843 apic = bus = intr = 0; 844 cpu = 1; /* pre-count the BSP */ 845 846 while (count--) { 847 switch (type = *(u_char *) position) { 848 case 0: 849 if (processor_entry(position, cpu)) 850 ++cpu; 851 break; 852 case 1: 853 if (bus_entry(position, bus)) 854 ++bus; 855 break; 856 case 2: 857 if (io_apic_entry(position, apic)) 858 ++apic; 859 break; 860 case 3: 861 if (int_entry(position, intr)) 862 ++intr; 863 break; 864 case 4: 865 /* int_entry(position); */ 866 break; 867 default: 868 panic("mpfps Base Table HOSED!"); 869 /* NOTREACHED */ 870 } 871 872 totalSize -= basetable_entry_types[type].length; 873 (u_char *) position += basetable_entry_types[type].length; 874 } 875 876 if (boot_cpu_id == -1) 877 panic("NO BSP found!"); 878 879 /* report fact that its NOT a default configuration */ 880 return 0; 881} 882 883 884/* 885 * parse an Intel MP specification table 886 */ 887static void 888fix_mp_table(void) 889{ 890 int x; 891 int id; 892 int bus_0; 893 int bus_pci; 894 int num_pci_bus; 895 896 /* 897 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS 898 * did it wrong. The MP spec says that when more than 1 PCI bus 899 * exists the BIOS must begin with bus entries for the PCI bus and use 900 * actual PCI bus numbering. This implies that when only 1 PCI bus 901 * exists the BIOS can choose to ignore this ordering, and indeed many 902 * MP motherboards do ignore it. This causes a problem when the PCI 903 * sub-system makes requests of the MP sub-system based on PCI bus 904 * numbers. So here we look for the situation and renumber the 905 * busses and associated INTs in an effort to "make it right". 906 */ 907 908 /* find bus 0, PCI bus, count the number of PCI busses */ 909 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { 910 if (bus_data[x].bus_id == 0) { 911 bus_0 = x; 912 } 913 if (bus_data[x].bus_type == PCI) { 914 ++num_pci_bus; 915 bus_pci = x; 916 } 917 } 918 /* 919 * bus_0 == slot of bus with ID of 0 920 * bus_pci == slot of last PCI bus encountered 921 */ 922 923 /* check the 1 PCI bus case for sanity */ 924 if (num_pci_bus == 1) { 925 926 /* if it is number 0 all is well */ 927 if (bus_data[bus_pci].bus_id == 0) 928 return; 929 930 /* mis-numbered, swap with whichever bus uses slot 0 */ 931 932 /* swap the bus entry types */ 933 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type; 934 bus_data[bus_0].bus_type = PCI; 935 936 /* swap each relavant INTerrupt entry */ 937 id = bus_data[bus_pci].bus_id; 938 for (x = 0; x < nintrs; ++x) { 939 if (io_apic_ints[x].src_bus_id == id) { 940 io_apic_ints[x].src_bus_id = 0; 941 } 942 else if (io_apic_ints[x].src_bus_id == 0) { 943 io_apic_ints[x].src_bus_id = id; 944 } 945 } 946 } 947 /* sanity check if more than 1 PCI bus */ 948 else if (num_pci_bus > 1) { 949 for (x = 0; x < mp_nbusses; ++x) { 950 if (bus_data[x].bus_type != PCI) 951 continue; 952 if (bus_data[x].bus_id >= num_pci_bus) 953 panic("bad PCI bus numbering"); 954 } 955 } 956} 957 958 959static int 960processor_entry(proc_entry_ptr entry, int cpu) 961{ 962 /* check for usability */ 963 if ((cpu >= NCPU) || !(entry->cpu_flags & PROCENTRY_FLAG_EN)) 964 return 0; 965 966 /* check for BSP flag */ 967 if (entry->cpu_flags & PROCENTRY_FLAG_BP) { 968 boot_cpu_id = entry->apic_id; 969 CPU_TO_ID(0) = entry->apic_id; 970 ID_TO_CPU(entry->apic_id) = 0; 971 return 0; /* its already been counted */ 972 } 973 974 /* add another AP to list, if less than max number of CPUs */ 975 else { 976 CPU_TO_ID(cpu) = entry->apic_id; 977 ID_TO_CPU(entry->apic_id) = cpu; 978 return 1; 979 } 980} 981 982 983static int 984bus_entry(bus_entry_ptr entry, int bus) 985{ 986 int x; 987 char c, name[8]; 988 989 /* encode the name into an index */ 990 for (x = 0; x < 6; ++x) { 991 if ((c = entry->bus_type[x]) == ' ') 992 break; 993 name[x] = c; 994 } 995 name[x] = '\0'; 996 997 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) 998 panic("unknown bus type: '%s'", name); 999 1000 bus_data[bus].bus_id = entry->bus_id; 1001 bus_data[bus].bus_type = x; 1002 1003 return 1; 1004} 1005 1006 1007static int 1008io_apic_entry(io_apic_entry_ptr entry, int apic) 1009{ 1010 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) 1011 return 0; 1012 1013 IO_TO_ID(apic) = entry->apic_id; 1014 ID_TO_IO(entry->apic_id) = apic; 1015 1016 return 1; 1017} 1018 1019 1020static int 1021lookup_bus_type(char *name) 1022{ 1023 int x; 1024 1025 for (x = 0; x < MAX_BUSTYPE; ++x) 1026 if (strcmp(bus_type_table[x].name, name) == 0) 1027 return bus_type_table[x].type; 1028 1029 return UNKNOWN_BUSTYPE; 1030} 1031 1032 1033static int 1034int_entry(int_entry_ptr entry, int intr) 1035{ 1036 io_apic_ints[intr].int_type = entry->int_type; 1037 io_apic_ints[intr].int_flags = entry->int_flags; 1038 io_apic_ints[intr].src_bus_id = entry->src_bus_id; 1039 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq; 1040 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; 1041 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int; 1042 1043 return 1; 1044} 1045 1046 1047static int 1048apic_int_is_bus_type(int intr, int bus_type) 1049{ 1050 int bus; 1051 1052 for (bus = 0; bus < mp_nbusses; ++bus) 1053 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) 1054 && ((int) bus_data[bus].bus_type == bus_type)) 1055 return 1; 1056 1057 return 0; 1058} 1059 1060 1061/* 1062 * Given a traditional ISA INT mask, return an APIC mask. 1063 */ 1064u_int 1065isa_apic_mask(u_int isa_mask) 1066{ 1067 int isa_irq; 1068 int apic_pin; 1069 1070#if defined(SKIP_IRQ15_REDIRECT) 1071 if (isa_mask == (1 << 15)) { 1072 printf("skipping ISA IRQ15 redirect\n"); 1073 return isa_mask; 1074 } 1075#endif /* SKIP_IRQ15_REDIRECT */ 1076 1077 isa_irq = ffs(isa_mask); /* find its bit position */ 1078 if (isa_irq == 0) /* doesn't exist */ 1079 return 0; 1080 --isa_irq; /* make it zero based */ 1081 1082 apic_pin = isa_apic_pin(isa_irq); /* look for APIC connection */ 1083 if (apic_pin == -1) 1084 return 0; 1085 1086 return (1 << apic_pin); /* convert pin# to a mask */ 1087} 1088 1089 1090/* 1091 * Determine which APIC pin an ISA/EISA INT is attached to. 1092 */ 1093#define INTTYPE(I) (io_apic_ints[(I)].int_type) 1094#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) 1095 1096#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) 1097int 1098isa_apic_pin(int isa_irq) 1099{ 1100 int intr; 1101 1102 for (intr = 0; intr < nintrs; ++intr) { /* check each record */ 1103 if (INTTYPE(intr) == 0) { /* standard INT */ 1104 if (SRCBUSIRQ(intr) == isa_irq) { 1105 if (apic_int_is_bus_type(intr, ISA) || 1106 apic_int_is_bus_type(intr, EISA)) 1107 return INTPIN(intr); /* found */ 1108 } 1109 } 1110 } 1111 return -1; /* NOT found */ 1112} 1113#undef SRCBUSIRQ 1114 1115 1116/* 1117 * Determine which APIC pin a PCI INT is attached to. 1118 */ 1119#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) 1120#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) 1121#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) 1122int 1123pci_apic_pin(int pciBus, int pciDevice, int pciInt) 1124{ 1125 int intr; 1126 1127 --pciInt; /* zero based */ 1128 1129 for (intr = 0; intr < nintrs; ++intr) /* check each record */ 1130 if ((INTTYPE(intr) == 0) /* standard INT */ 1131 && (SRCBUSID(intr) == pciBus) 1132 && (SRCBUSDEVICE(intr) == pciDevice) 1133 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ 1134 if (apic_int_is_bus_type(intr, PCI)) 1135 return INTPIN(intr); /* exact match */ 1136 1137 return -1; /* NOT found */ 1138} 1139#undef SRCBUSLINE 1140#undef SRCBUSDEVICE 1141#undef SRCBUSID 1142 1143#undef INTPIN 1144#undef INTTYPE 1145 1146 1147/* 1148 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt. 1149 * 1150 * XXX FIXME: 1151 * Exactly what this means is unclear at this point. It is a solution 1152 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard 1153 * could route any of the ISA INTs to upper (>15) IRQ values. But most would 1154 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an 1155 * option. 1156 */ 1157int 1158undirect_isa_irq(int rirq) 1159{ 1160#if defined(READY) 1161 printf("Freeing redirected ISA irq %d.\n", rirq); 1162 /** FIXME: tickle the MB redirector chip */ 1163 return ???; 1164#else 1165 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq); 1166 return 0; 1167#endif /* READY */ 1168} 1169 1170 1171/* 1172 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt 1173 */ 1174int 1175undirect_pci_irq(int rirq) 1176{ 1177#if defined(READY) 1178 if (bootverbose) 1179 printf("Freeing redirected PCI irq %d.\n", rirq); 1180 1181 /** FIXME: tickle the MB redirector chip */ 1182 return ???; 1183#else 1184 if (bootverbose) 1185 printf("Freeing (NOT implemented) redirected PCI irq %d.\n", 1186 rirq); 1187 return 0; 1188#endif /* READY */ 1189} 1190 1191 1192/* 1193 * given a bus ID, return: 1194 * the bus type if found 1195 * -1 if NOT found 1196 */ 1197int 1198apic_bus_type(int id) 1199{ 1200 int x; 1201 1202 for (x = 0; x < mp_nbusses; ++x) 1203 if (bus_data[x].bus_id == id) 1204 return bus_data[x].bus_type; 1205 1206 return -1; 1207} 1208 1209 1210/* 1211 * given a LOGICAL APIC# and pin#, return: 1212 * the associated src bus ID if found 1213 * -1 if NOT found 1214 */ 1215int 1216apic_src_bus_id(int apic, int pin) 1217{ 1218 int x; 1219 1220 /* search each of the possible INTerrupt sources */ 1221 for (x = 0; x < nintrs; ++x) 1222 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1223 (pin == io_apic_ints[x].dst_apic_int)) 1224 return (io_apic_ints[x].src_bus_id); 1225 1226 return -1; /* NOT found */ 1227} 1228 1229 1230/* 1231 * given a LOGICAL APIC# and pin#, return: 1232 * the associated src bus IRQ if found 1233 * -1 if NOT found 1234 */ 1235int 1236apic_src_bus_irq(int apic, int pin) 1237{ 1238 int x; 1239 1240 for (x = 0; x < nintrs; x++) 1241 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1242 (pin == io_apic_ints[x].dst_apic_int)) 1243 return (io_apic_ints[x].src_bus_irq); 1244 1245 return -1; /* NOT found */ 1246} 1247 1248 1249/* 1250 * given a LOGICAL APIC# and pin#, return: 1251 * the associated INTerrupt type if found 1252 * -1 if NOT found 1253 */ 1254int 1255apic_int_type(int apic, int pin) 1256{ 1257 int x; 1258 1259 /* search each of the possible INTerrupt sources */ 1260 for (x = 0; x < nintrs; ++x) 1261 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1262 (pin == io_apic_ints[x].dst_apic_int)) 1263 return (io_apic_ints[x].int_type); 1264 1265 return -1; /* NOT found */ 1266} 1267 1268 1269/* 1270 * given a LOGICAL APIC# and pin#, return: 1271 * the associated trigger mode if found 1272 * -1 if NOT found 1273 */ 1274int 1275apic_trigger(int apic, int pin) 1276{ 1277 int x; 1278 1279 /* search each of the possible INTerrupt sources */ 1280 for (x = 0; x < nintrs; ++x) 1281 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1282 (pin == io_apic_ints[x].dst_apic_int)) 1283 return ((io_apic_ints[x].int_flags >> 2) & 0x03); 1284 1285 return -1; /* NOT found */ 1286} 1287 1288 1289/* 1290 * given a LOGICAL APIC# and pin#, return: 1291 * the associated 'active' level if found 1292 * -1 if NOT found 1293 */ 1294int 1295apic_polarity(int apic, int pin) 1296{ 1297 int x; 1298 1299 /* search each of the possible INTerrupt sources */ 1300 for (x = 0; x < nintrs; ++x) 1301 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1302 (pin == io_apic_ints[x].dst_apic_int)) 1303 return (io_apic_ints[x].int_flags & 0x03); 1304 1305 return -1; /* NOT found */ 1306} 1307 1308 1309/* 1310 * set data according to MP defaults 1311 * FIXME: probably not complete yet... 1312 */ 1313static void 1314default_mp_table(int type) 1315{ 1316 int ap_cpu_id; 1317#if defined(APIC_IO) 1318 u_int32_t ux; 1319 int io_apic_id; 1320 int pin; 1321#endif /* APIC_IO */ 1322 1323#if 0 1324 printf(" MP default config type: %d\n", type); 1325 switch (type) { 1326 case 1: 1327 printf(" bus: ISA, APIC: 82489DX\n"); 1328 break; 1329 case 2: 1330 printf(" bus: EISA, APIC: 82489DX\n"); 1331 break; 1332 case 3: 1333 printf(" bus: EISA, APIC: 82489DX\n"); 1334 break; 1335 case 4: 1336 printf(" bus: MCA, APIC: 82489DX\n"); 1337 break; 1338 case 5: 1339 printf(" bus: ISA+PCI, APIC: Integrated\n"); 1340 break; 1341 case 6: 1342 printf(" bus: EISA+PCI, APIC: Integrated\n"); 1343 break; 1344 case 7: 1345 printf(" bus: MCA+PCI, APIC: Integrated\n"); 1346 break; 1347 default: 1348 printf(" future type\n"); 1349 break; 1350 /* NOTREACHED */ 1351 } 1352#endif /* 0 */ 1353 1354 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24; 1355 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; 1356 1357 /* BSP */ 1358 CPU_TO_ID(0) = boot_cpu_id; 1359 ID_TO_CPU(boot_cpu_id) = 0; 1360 1361 /* one and only AP */ 1362 CPU_TO_ID(1) = ap_cpu_id; 1363 ID_TO_CPU(ap_cpu_id) = 1; 1364 1365#if defined(APIC_IO) 1366 /* one and only IO APIC */ 1367 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; 1368 1369 /* 1370 * sanity check, refer to MP spec section 3.6.6, last paragraph 1371 * necessary as some hardware isn't properly setting up the IO APIC 1372 */ 1373#if defined(REALLY_ANAL_IOAPICID_VALUE) 1374 if (io_apic_id != 2) { 1375#else 1376 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { 1377#endif /* REALLY_ANAL_IOAPICID_VALUE */ 1378 ux = io_apic_read(0, IOAPIC_ID); /* get current contents */ 1379 ux &= ~APIC_ID_MASK; /* clear the ID field */ 1380 ux |= 0x02000000; /* set it to '2' */ 1381 io_apic_write(0, IOAPIC_ID, ux); /* write new value */ 1382 ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */ 1383 if ((ux & APIC_ID_MASK) != 0x02000000) 1384 panic("can't control IO APIC ID, reg: 0x%08x", ux); 1385 io_apic_id = 2; 1386 } 1387 IO_TO_ID(0) = io_apic_id; 1388 ID_TO_IO(io_apic_id) = 0; 1389#endif /* APIC_IO */ 1390 1391 /* fill out bus entries */ 1392 switch (type) { 1393 case 1: 1394 case 2: 1395 case 3: 1396 case 5: 1397 case 6: 1398 bus_data[0].bus_id = default_data[type - 1][1]; 1399 bus_data[0].bus_type = default_data[type - 1][2]; 1400 bus_data[1].bus_id = default_data[type - 1][3]; 1401 bus_data[1].bus_type = default_data[type - 1][4]; 1402 break; 1403 1404 /* case 4: case 7: MCA NOT supported */ 1405 default: /* illegal/reserved */ 1406 panic("BAD default MP config: %d", type); 1407 /* NOTREACHED */ 1408 } 1409 1410#if defined(APIC_IO) 1411 /* general cases from MP v1.4, table 5-2 */ 1412 for (pin = 0; pin < 16; ++pin) { 1413 io_apic_ints[pin].int_type = 0; 1414 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */ 1415 io_apic_ints[pin].src_bus_id = 0; 1416 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */ 1417 io_apic_ints[pin].dst_apic_id = io_apic_id; 1418 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */ 1419 } 1420 1421 /* special cases from MP v1.4, table 5-2 */ 1422 if (type == 2) { 1423 io_apic_ints[2].int_type = 0xff; /* N/C */ 1424 io_apic_ints[13].int_type = 0xff; /* N/C */ 1425#if !defined(APIC_MIXED_MODE) 1426 /** FIXME: ??? */ 1427 panic("sorry, can't support type 2 default yet"); 1428#endif /* APIC_MIXED_MODE */ 1429 } 1430 else 1431 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ 1432 1433 if (type == 7) 1434 io_apic_ints[0].int_type = 0xff; /* N/C */ 1435 else 1436 io_apic_ints[0].int_type = 3; /* vectored 8259 */ 1437#endif /* APIC_IO */ 1438} 1439 1440 1441/* 1442 * initialize all the SMP locks 1443 */ 1444 1445/* critical region around IO APIC, apic_imen */ 1446struct simplelock imen_lock; 1447 1448/* critical region around splxx(), cpl, cil, ipending */ 1449struct simplelock cpl_lock; 1450 1451/* Make FAST_INTR() routines sequential */ 1452struct simplelock fast_intr_lock; 1453 1454/* critical region around INTR() routines */ 1455struct simplelock intr_lock; 1456 1457/* lock regions protected in UP kernel via cli/sti */ 1458struct simplelock mpintr_lock; 1459 1460#ifdef USE_COMLOCK 1461/* locks com (tty) data/hardware accesses: a FASTINTR() */ 1462struct simplelock com_lock; 1463#endif /* USE_COMLOCK */ 1464 1465#ifdef USE_CLOCKLOCK 1466/* lock regions around the clock hardware */ 1467struct simplelock clock_lock; 1468#endif /* USE_CLOCKLOCK */ 1469 1470static void 1471init_locks(void) 1472{ 1473 /* 1474 * Get the initial mp_lock with a count of 1 for the BSP. 1475 * This uses a LOGICAL cpu ID, ie BSP == 0. 1476 */ 1477 mp_lock = 0x00000001; 1478 1479 /* ISR uses its own "giant lock" */ 1480 isr_lock = FREE_LOCK; 1481 1482 s_lock_init((struct simplelock*)&mpintr_lock); 1483 1484 s_lock_init((struct simplelock*)&fast_intr_lock); 1485 s_lock_init((struct simplelock*)&intr_lock); 1486 s_lock_init((struct simplelock*)&imen_lock); 1487 s_lock_init((struct simplelock*)&cpl_lock); 1488 1489#ifdef USE_COMLOCK 1490 s_lock_init((struct simplelock*)&com_lock); 1491#endif /* USE_COMLOCK */ 1492#ifdef USE_CLOCKLOCK 1493 s_lock_init((struct simplelock*)&clock_lock); 1494#endif /* USE_CLOCKLOCK */ 1495} 1496 1497 1498/* 1499 * start each AP in our list 1500 */ 1501static int 1502start_all_aps(u_int boot_addr) 1503{ 1504 int x, i; 1505 u_char mpbiosreason; 1506 u_long mpbioswarmvec; 1507 pd_entry_t *newptd; 1508 pt_entry_t *newpt; 1509 int *newpp, *stack; 1510 1511 POSTCODE(START_ALL_APS_POST); 1512 1513 /* initialize BSP's local APIC */ 1514 apic_initialize(); 1515 bsp_apic_ready = 1; 1516 1517 /* install the AP 1st level boot code */ 1518 install_ap_tramp(boot_addr); 1519 1520 1521 /* save the current value of the warm-start vector */ 1522 mpbioswarmvec = *((u_long *) WARMBOOT_OFF); 1523 outb(CMOS_REG, BIOS_RESET); 1524 mpbiosreason = inb(CMOS_DATA); 1525 1526 /* record BSP in CPU map */ 1527 all_cpus = 1; 1528 1529 /* start each AP */ 1530 for (x = 1; x <= mp_naps; ++x) { 1531 1532 /* This is a bit verbose, it will go away soon. */ 1533 1534 /* alloc new page table directory */ 1535 newptd = (pd_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE)); 1536 1537 /* Store the virtual PTD address for this CPU */ 1538 IdlePTDS[x] = newptd; 1539 1540 /* clone currently active one (ie: IdlePTD) */ 1541 bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */ 1542 1543 /* set up 0 -> 4MB P==V mapping for AP boot */ 1544 newptd[0] = (pd_entry_t) (PG_V | PG_RW | 1545 ((u_long)KPTphys & PG_FRAME)); 1546 1547 /* store PTD for this AP's boot sequence */ 1548 bootPTD = (pd_entry_t *)vtophys(newptd); 1549 1550 /* alloc new page table page */ 1551 newpt = (pt_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE)); 1552 1553 /* set the new PTD's private page to point there */ 1554 newptd[MPPTDI] = (pt_entry_t)(PG_V | PG_RW | vtophys(newpt)); 1555 1556 /* install self referential entry */ 1557 newptd[PTDPTDI] = (pd_entry_t)(PG_V | PG_RW | vtophys(newptd)); 1558 1559 /* allocate a new private data page */ 1560 newpp = (int *)kmem_alloc(kernel_map, PAGE_SIZE); 1561 1562 /* wire it into the private page table page */ 1563 newpt[0] = (pt_entry_t)(PG_V | PG_RW | vtophys(newpp)); 1564 1565 /* wire the ptp into itself for access */ 1566 newpt[1] = (pt_entry_t)(PG_V | PG_RW | vtophys(newpt)); 1567 1568 /* copy in the pointer to the local apic */ 1569 newpt[2] = SMP_prvpt[2]; 1570 1571 /* and the IO apic mapping[s] */ 1572 for (i = 16; i < 32; i++) 1573 newpt[i] = SMP_prvpt[i]; 1574 1575 /* allocate and set up an idle stack data page */ 1576 stack = (int *)kmem_alloc(kernel_map, PAGE_SIZE); 1577 newpt[3] = (pt_entry_t)(PG_V | PG_RW | vtophys(stack)); 1578 1579 newpt[4] = 0; /* *prv_CMAP1 */ 1580 newpt[5] = 0; /* *prv_CMAP2 */ 1581 newpt[6] = 0; /* *prv_CMAP3 */ 1582 1583 /* prime data page for it to use */ 1584 newpp[0] = x; /* cpuid */ 1585 newpp[1] = 0; /* curproc */ 1586 newpp[2] = 0; /* curpcb */ 1587 newpp[3] = 0; /* npxproc */ 1588 newpp[4] = 0; /* runtime.tv_sec */ 1589 newpp[5] = 0; /* runtime.tv_usec */ 1590 newpp[6] = x << 24; /* cpu_lockid */ 1591 newpp[7] = 0; /* other_cpus */ 1592 newpp[8] = (int)bootPTD; /* my_idlePTD */ 1593 newpp[9] = 0; /* ss_tpr */ 1594 newpp[10] = (int)&newpt[4]; /* prv_CMAP1 */ 1595 newpp[11] = (int)&newpt[5]; /* prv_CMAP2 */ 1596 newpp[12] = (int)&newpt[6]; /* prv_CMAP3 */ 1597 1598 /* setup a vector to our boot code */ 1599 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 1600 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); 1601 outb(CMOS_REG, BIOS_RESET); 1602 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 1603 1604 /* attempt to start the Application Processor */ 1605 CHECK_INIT(99); /* setup checkpoints */ 1606 if (!start_ap(x, boot_addr)) { 1607 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); 1608 CHECK_PRINT("trace"); /* show checkpoints */ 1609 /* better panic as the AP may be running loose */ 1610 printf("panic y/n? [y] "); 1611 if (cngetc() != 'n') 1612 panic("bye-bye"); 1613 } 1614 CHECK_PRINT("trace"); /* show checkpoints */ 1615 1616 /* record its version info */ 1617 cpu_apic_versions[x] = cpu_apic_versions[0]; 1618 1619 all_cpus |= (1 << x); /* record AP in CPU map */ 1620 } 1621 1622 /* build our map of 'other' CPUs */ 1623 other_cpus = all_cpus & ~(1 << cpuid); 1624 1625 /* fill in our (BSP) APIC version */ 1626 cpu_apic_versions[0] = lapic.version; 1627 1628 /* restore the warmstart vector */ 1629 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 1630 outb(CMOS_REG, BIOS_RESET); 1631 outb(CMOS_DATA, mpbiosreason); 1632 1633 /* 1634 * Set up the idle context for the BSP. Similar to above except 1635 * that some was done by locore, some by pmap.c and some is implicit 1636 * because the BSP is cpu#0 and the page is initially zero, and also 1637 * because we can refer to variables by name on the BSP.. 1638 */ 1639 newptd = (pd_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE)); 1640 1641 bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */ 1642 IdlePTDS[0] = newptd; 1643 1644 /* Point PTD[] to this page instead of IdlePTD's physical page */ 1645 newptd[PTDPTDI] = (pd_entry_t)(PG_V | PG_RW | vtophys(newptd)); 1646 1647 my_idlePTD = (pd_entry_t *)vtophys(newptd); 1648 1649 /* Allocate and setup BSP idle stack */ 1650 stack = (int *)kmem_alloc(kernel_map, PAGE_SIZE); 1651 SMP_prvpt[3] = (pt_entry_t)(PG_V | PG_RW | vtophys(stack)); 1652 1653 pmap_set_opt_bsp(); 1654 1655 /* number of APs actually started */ 1656 return mp_ncpus - 1; 1657} 1658 1659 1660/* 1661 * load the 1st level AP boot code into base memory. 1662 */ 1663 1664/* targets for relocation */ 1665extern void bigJump(void); 1666extern void bootCodeSeg(void); 1667extern void bootDataSeg(void); 1668extern void MPentry(void); 1669extern u_int MP_GDT; 1670extern u_int mp_gdtbase; 1671 1672static void 1673install_ap_tramp(u_int boot_addr) 1674{ 1675 int x; 1676 int size = *(int *) ((u_long) & bootMP_size); 1677 u_char *src = (u_char *) ((u_long) bootMP); 1678 u_char *dst = (u_char *) boot_addr + KERNBASE; 1679 u_int boot_base = (u_int) bootMP; 1680 u_int8_t *dst8; 1681 u_int16_t *dst16; 1682 u_int32_t *dst32; 1683 1684 POSTCODE(INSTALL_AP_TRAMP_POST); 1685 1686 for (x = 0; x < size; ++x) 1687 *dst++ = *src++; 1688 1689 /* 1690 * modify addresses in code we just moved to basemem. unfortunately we 1691 * need fairly detailed info about mpboot.s for this to work. changes 1692 * to mpboot.s might require changes here. 1693 */ 1694 1695 /* boot code is located in KERNEL space */ 1696 dst = (u_char *) boot_addr + KERNBASE; 1697 1698 /* modify the lgdt arg */ 1699 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 1700 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); 1701 1702 /* modify the ljmp target for MPentry() */ 1703 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 1704 *dst32 = ((u_int) MPentry - KERNBASE); 1705 1706 /* modify the target for boot code segment */ 1707 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 1708 dst8 = (u_int8_t *) (dst16 + 1); 1709 *dst16 = (u_int) boot_addr & 0xffff; 1710 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1711 1712 /* modify the target for boot data segment */ 1713 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 1714 dst8 = (u_int8_t *) (dst16 + 1); 1715 *dst16 = (u_int) boot_addr & 0xffff; 1716 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1717} 1718 1719 1720/* 1721 * this function starts the AP (application processor) identified 1722 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 1723 * to accomplish this. This is necessary because of the nuances 1724 * of the different hardware we might encounter. It ain't pretty, 1725 * but it seems to work. 1726 */ 1727static int 1728start_ap(int logical_cpu, u_int boot_addr) 1729{ 1730 int physical_cpu; 1731 int vector; 1732 int cpus; 1733 u_long icr_lo, icr_hi; 1734 1735 POSTCODE(START_AP_POST); 1736 1737 /* get the PHYSICAL APIC ID# */ 1738 physical_cpu = CPU_TO_ID(logical_cpu); 1739 1740 /* calculate the vector */ 1741 vector = (boot_addr >> 12) & 0xff; 1742 1743 /* used as a watchpoint to signal AP startup */ 1744 cpus = mp_ncpus; 1745 1746 /* 1747 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 1748 * and running the target CPU. OR this INIT IPI might be latched (P5 1749 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 1750 * ignored. 1751 */ 1752 1753 /* setup the address for the target AP */ 1754 icr_hi = lapic.icr_hi & ~APIC_ID_MASK; 1755 icr_hi |= (physical_cpu << 24); 1756 lapic.icr_hi = icr_hi; 1757 1758 /* do an INIT IPI: assert RESET */ 1759 icr_lo = lapic.icr_lo & 0xfff00000; 1760 lapic.icr_lo = icr_lo | 0x0000c500; 1761 1762 /* wait for pending status end */ 1763 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1764 /* spin */ ; 1765 1766 /* do an INIT IPI: deassert RESET */ 1767 lapic.icr_lo = icr_lo | 0x00008500; 1768 1769 /* wait for pending status end */ 1770 u_sleep(10000); /* wait ~10mS */ 1771 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1772 /* spin */ ; 1773 1774 /* 1775 * next we do a STARTUP IPI: the previous INIT IPI might still be 1776 * latched, (P5 bug) this 1st STARTUP would then terminate 1777 * immediately, and the previously started INIT IPI would continue. OR 1778 * the previous INIT IPI has already run. and this STARTUP IPI will 1779 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 1780 * will run. 1781 */ 1782 1783 /* do a STARTUP IPI */ 1784 lapic.icr_lo = icr_lo | 0x00000600 | vector; 1785 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1786 /* spin */ ; 1787 u_sleep(200); /* wait ~200uS */ 1788 1789 /* 1790 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 1791 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 1792 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 1793 * recognized after hardware RESET or INIT IPI. 1794 */ 1795 1796 lapic.icr_lo = icr_lo | 0x00000600 | vector; 1797 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1798 /* spin */ ; 1799 u_sleep(200); /* wait ~200uS */ 1800 1801 /* wait for it to start */ 1802 set_apic_timer(5000000);/* == 5 seconds */ 1803 while (read_apic_timer()) 1804 if (mp_ncpus > cpus) 1805 return 1; /* return SUCCESS */ 1806 1807 return 0; /* return FAILURE */ 1808} 1809 1810 1811/* 1812 * Flush the TLB on all other CPU's 1813 * 1814 * XXX: Needs to handshake and wait for completion before proceding. 1815 */ 1816void 1817smp_invltlb(void) 1818{ 1819#if defined(APIC_IO) 1820 if (smp_started && invltlb_ok) 1821 all_but_self_ipi(XINVLTLB_OFFSET); 1822#endif /* APIC_IO */ 1823} 1824 1825void 1826invlpg(u_int addr) 1827{ 1828 __asm __volatile("invlpg (%0)"::"r"(addr):"memory"); 1829 1830 /* send a message to the other CPUs */ 1831 smp_invltlb(); 1832} 1833 1834void 1835invltlb(void) 1836{ 1837 u_long temp; 1838 1839 /* 1840 * This should be implemented as load_cr3(rcr3()) when load_cr3() is 1841 * inlined. 1842 */ 1843 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory"); 1844 1845 /* send a message to the other CPUs */ 1846 smp_invltlb(); 1847} 1848 1849 1850/* 1851 * When called the executing CPU will send an IPI to all other CPUs 1852 * requesting that they halt execution. 1853 * 1854 * Usually (but not necessarily) called with 'other_cpus' as its arg. 1855 * 1856 * - Signals all CPUs in map to stop. 1857 * - Waits for each to stop. 1858 * 1859 * Returns: 1860 * -1: error 1861 * 0: NA 1862 * 1: ok 1863 * 1864 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs 1865 * from executing at same time. 1866 */ 1867int 1868stop_cpus(u_int map) 1869{ 1870 if (!smp_started) 1871 return 0; 1872 1873 /* send IPI to all CPUs in map */ 1874 stopped_cpus = 0; 1875 1876 /* send the Xcpustop IPI to all CPUs in map */ 1877 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED); 1878 1879 while (stopped_cpus != map) 1880 /* spin */ ; 1881 1882 return 1; 1883} 1884 1885 1886/* 1887 * Called by a CPU to restart stopped CPUs. 1888 * 1889 * Usually (but not necessarily) called with 'stopped_cpus' as its arg. 1890 * 1891 * - Signals all CPUs in map to restart. 1892 * - Waits for each to restart. 1893 * 1894 * Returns: 1895 * -1: error 1896 * 0: NA 1897 * 1: ok 1898 */ 1899int 1900restart_cpus(u_int map) 1901{ 1902 if (!smp_started) 1903 return 0; 1904 1905 started_cpus = map; /* signal other cpus to restart */ 1906 1907 while (started_cpus) /* wait for each to clear its bit */ 1908 /* spin */ ; 1909 1910 return 1; 1911} 1912 1913int smp_active = 0; /* are the APs allowed to run? */ 1914SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RW, &smp_active, 0, ""); 1915 1916/* XXX maybe should be hw.ncpu */ 1917int smp_cpus = 1; /* how many cpu's running */ 1918SYSCTL_INT(_machdep, OID_AUTO, smp_cpus, CTLFLAG_RD, &smp_cpus, 0, ""); 1919 1920int invltlb_ok = 0; /* throttle smp_invltlb() till safe */ 1921SYSCTL_INT(_machdep, OID_AUTO, invltlb_ok, CTLFLAG_RW, &invltlb_ok, 0, ""); 1922 1923int do_page_zero_idle = 0; /* bzero pages for fun and profit in idleloop */ 1924SYSCTL_INT(_machdep, OID_AUTO, do_page_zero_idle, CTLFLAG_RW, 1925 &do_page_zero_idle, 0, ""); 1926 1927 1928/* 1929 * This is called once the rest of the system is up and running and we're 1930 * ready to let the AP's out of the pen. 1931 */ 1932void ap_init(void); 1933 1934void 1935ap_init() 1936{ 1937 u_int temp; 1938 u_int apic_id; 1939 1940 smp_cpus++; 1941 1942 /* Build our map of 'other' CPUs. */ 1943 other_cpus = all_cpus & ~(1 << cpuid); 1944 1945 printf("SMP: AP CPU #%d Launched!\n", cpuid); 1946 1947 /* XXX FIXME: i386 specific, and redundant: Setup the FPU. */ 1948 load_cr0((rcr0() & ~CR0_EM) | CR0_MP | CR0_NE | CR0_TS); 1949 1950 /* A quick check from sanity claus */ 1951 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]); 1952 if (cpuid != apic_id) { 1953 printf("SMP: cpuid = %d\n", cpuid); 1954 printf("SMP: apic_id = %d\n", apic_id); 1955 printf("PTD[MPPTDI] = %08x\n", PTD[MPPTDI]); 1956 panic("cpuid mismatch! boom!!"); 1957 } 1958 1959 /* Init local apic for irq's */ 1960 apic_initialize(); 1961 1962 /* 1963 * Activate smp_invltlb, although strictly speaking, this isn't 1964 * quite correct yet. We should have a bitfield for cpus willing 1965 * to accept TLB flush IPI's or something and sync them. 1966 */ 1967 invltlb_ok = 1; 1968 smp_started = 1; /* enable IPI's, tlb shootdown, freezes etc */ 1969 smp_active = 1; /* historic */ 1970 1971 curproc = NULL; /* make sure */ 1972} 1973