mptable.c revision 28809
1/* 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $Id: mp_machdep.c,v 1.46 1997/08/26 18:10:31 peter Exp $ 26 */ 27 28#include "opt_smp.h" 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/kernel.h> 33#include <sys/proc.h> 34#include <sys/sysctl.h> 35 36#include <vm/vm.h> 37#include <vm/vm_param.h> 38#include <vm/pmap.h> 39#include <vm/vm_kern.h> 40#include <vm/vm_extern.h> 41 42#include <machine/smp.h> 43#include <machine/apic.h> 44#include <machine/mpapic.h> 45#include <machine/segments.h> 46#include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */ 47#include <machine/tss.h> 48#include <machine/specialreg.h> 49 50#include <i386/i386/cons.h> /* cngetc() */ 51 52#if defined(APIC_IO) 53#include <machine/md_var.h> /* setidt() */ 54#include <i386/isa/icu.h> /* IPIs */ 55#include <i386/isa/intr_machdep.h> /* IPIs */ 56#endif /* APIC_IO */ 57 58#if defined(TEST_DEFAULT_CONFIG) 59#define MPFPS_MPFB1 TEST_DEFAULT_CONFIG 60#else 61#define MPFPS_MPFB1 mpfps->mpfb1 62#endif /* TEST_DEFAULT_CONFIG */ 63 64#define WARMBOOT_TARGET 0 65#define WARMBOOT_OFF (KERNBASE + 0x0467) 66#define WARMBOOT_SEG (KERNBASE + 0x0469) 67 68#define BIOS_BASE (0xf0000) 69#define BIOS_SIZE (0x10000) 70#define BIOS_COUNT (BIOS_SIZE/4) 71 72#define CMOS_REG (0x70) 73#define CMOS_DATA (0x71) 74#define BIOS_RESET (0x0f) 75#define BIOS_WARM (0x0a) 76 77#define PROCENTRY_FLAG_EN 0x01 78#define PROCENTRY_FLAG_BP 0x02 79#define IOAPICENTRY_FLAG_EN 0x01 80 81 82/* MP Floating Pointer Structure */ 83typedef struct MPFPS { 84 char signature[4]; 85 void *pap; 86 u_char length; 87 u_char spec_rev; 88 u_char checksum; 89 u_char mpfb1; 90 u_char mpfb2; 91 u_char mpfb3; 92 u_char mpfb4; 93 u_char mpfb5; 94} *mpfps_t; 95 96/* MP Configuration Table Header */ 97typedef struct MPCTH { 98 char signature[4]; 99 u_short base_table_length; 100 u_char spec_rev; 101 u_char checksum; 102 u_char oem_id[8]; 103 u_char product_id[12]; 104 void *oem_table_pointer; 105 u_short oem_table_size; 106 u_short entry_count; 107 void *apic_address; 108 u_short extended_table_length; 109 u_char extended_table_checksum; 110 u_char reserved; 111} *mpcth_t; 112 113 114typedef struct PROCENTRY { 115 u_char type; 116 u_char apic_id; 117 u_char apic_version; 118 u_char cpu_flags; 119 u_long cpu_signature; 120 u_long feature_flags; 121 u_long reserved1; 122 u_long reserved2; 123} *proc_entry_ptr; 124 125typedef struct BUSENTRY { 126 u_char type; 127 u_char bus_id; 128 char bus_type[6]; 129} *bus_entry_ptr; 130 131typedef struct IOAPICENTRY { 132 u_char type; 133 u_char apic_id; 134 u_char apic_version; 135 u_char apic_flags; 136 void *apic_address; 137} *io_apic_entry_ptr; 138 139typedef struct INTENTRY { 140 u_char type; 141 u_char int_type; 142 u_short int_flags; 143 u_char src_bus_id; 144 u_char src_bus_irq; 145 u_char dst_apic_id; 146 u_char dst_apic_int; 147} *int_entry_ptr; 148 149/* descriptions of MP basetable entries */ 150typedef struct BASETABLE_ENTRY { 151 u_char type; 152 u_char length; 153 char name[16]; 154} basetable_entry; 155 156/* 157 * this code MUST be enabled here and in mpboot.s. 158 * it follows the very early stages of AP boot by placing values in CMOS ram. 159 * it NORMALLY will never be needed and thus the primitive method for enabling. 160 * 161#define CHECK_POINTS 162 */ 163 164#if defined(CHECK_POINTS) 165#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 166#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 167 168#define CHECK_INIT(D); \ 169 CHECK_WRITE(0x34, (D)); \ 170 CHECK_WRITE(0x35, (D)); \ 171 CHECK_WRITE(0x36, (D)); \ 172 CHECK_WRITE(0x37, (D)); \ 173 CHECK_WRITE(0x38, (D)); \ 174 CHECK_WRITE(0x39, (D)); 175 176#define CHECK_PRINT(S); \ 177 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 178 (S), \ 179 CHECK_READ(0x34), \ 180 CHECK_READ(0x35), \ 181 CHECK_READ(0x36), \ 182 CHECK_READ(0x37), \ 183 CHECK_READ(0x38), \ 184 CHECK_READ(0x39)); 185 186#else /* CHECK_POINTS */ 187 188#define CHECK_INIT(D) 189#define CHECK_PRINT(S) 190 191#endif /* CHECK_POINTS */ 192 193/* 194 * Values to send to the POST hardware. 195 */ 196#define MP_BOOTADDRESS_POST 0x10 197#define MP_PROBE_POST 0x11 198#define MP_START_POST 0x12 199#define MP_ANNOUNCE_POST 0x13 200#define MPTABLE_PASS1_POST 0x14 201#define MPTABLE_PASS2_POST 0x15 202#define MP_ENABLE_POST 0x16 203#define START_ALL_APS_POST 0x17 204#define INSTALL_AP_TRAMP_POST 0x18 205#define START_AP_POST 0x19 206 207/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ 208int current_postcode; 209 210/** XXX FIXME: what system files declare these??? */ 211extern struct region_descriptor r_gdt, r_idt; 212 213int bsp_apic_ready = 0; /* flags useability of BSP apic */ 214int mp_ncpus; /* # of CPUs, including BSP */ 215int mp_naps; /* # of Applications processors */ 216int mp_nbusses; /* # of busses */ 217int mp_napics; /* # of IO APICs */ 218int boot_cpu_id; /* designated BSP */ 219vm_offset_t cpu_apic_address; 220vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */ 221 222u_int32_t cpu_apic_versions[NCPU]; 223u_int32_t io_apic_versions[NAPIC]; 224 225/* 226 * APIC ID logical/physical mapping structures. 227 * We oversize these to simplify boot-time config. 228 */ 229int cpu_num_to_apic_id[NAPICID]; 230int io_num_to_apic_id[NAPICID]; 231int apic_id_to_logical[NAPICID]; 232 233/* Bitmap of all available CPUs */ 234u_int all_cpus; 235 236/* AP uses this PTD during bootstrap */ 237pd_entry_t *bootPTD; 238 239/* Hotwire a 0->4MB V==P mapping */ 240extern pt_entry_t *KPTphys; 241 242/* Virtual address of per-cpu common_tss */ 243extern struct i386tss common_tss; 244 245/* IdlePTD per cpu */ 246pd_entry_t *IdlePTDS[NCPU]; 247 248/* "my" private page table page, for BSP init */ 249extern pt_entry_t SMP_prvpt[]; 250 251/* Private page pointer to curcpu's PTD, used during BSP init */ 252extern pd_entry_t *my_idlePTD; 253 254static int smp_started; /* has the system started? */ 255 256/* 257 * Local data and functions. 258 */ 259 260static int mp_capable; 261static u_int boot_address; 262static u_int base_memory; 263 264static int picmode; /* 0: virtual wire mode, 1: PIC mode */ 265static mpfps_t mpfps; 266static int search_for_sig(u_int32_t target, int count); 267static void mp_enable(u_int boot_addr); 268 269static int mptable_pass1(void); 270static int mptable_pass2(void); 271static void default_mp_table(int type); 272static void fix_mp_table(void); 273static void init_locks(void); 274static int start_all_aps(u_int boot_addr); 275static void install_ap_tramp(u_int boot_addr); 276static int start_ap(int logicalCpu, u_int boot_addr); 277 278 279/* 280 * Calculate usable address in base memory for AP trampoline code. 281 */ 282u_int 283mp_bootaddress(u_int basemem) 284{ 285 POSTCODE(MP_BOOTADDRESS_POST); 286 287 base_memory = basemem * 1024; /* convert to bytes */ 288 289 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ 290 if ((base_memory - boot_address) < bootMP_size) 291 boot_address -= 4096; /* not enough, lower by 4k */ 292 293 return boot_address; 294} 295 296 297/* 298 * Look for an Intel MP spec table (ie, SMP capable hardware). 299 */ 300int 301mp_probe(void) 302{ 303 int x; 304 u_long segment; 305 u_int32_t target; 306 307 POSTCODE(MP_PROBE_POST); 308 309 /* see if EBDA exists */ 310 if (segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) { 311 /* search first 1K of EBDA */ 312 target = (u_int32_t) (segment << 4); 313 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 314 goto found; 315 } else { 316 /* last 1K of base memory, effective 'top of base' passed in */ 317 target = (u_int32_t) (base_memory - 0x400); 318 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 319 goto found; 320 } 321 322 /* search the BIOS */ 323 target = (u_int32_t) BIOS_BASE; 324 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) 325 goto found; 326 327 /* nothing found */ 328 mpfps = (mpfps_t)0; 329 mp_capable = 0; 330 return 0; 331 332found: 333 /* calculate needed resources */ 334 mpfps = (mpfps_t)x; 335 if (mptable_pass1()) 336 panic("you must reconfigure your kernel"); 337 338 /* flag fact that we are running multiple processors */ 339 mp_capable = 1; 340 return 1; 341} 342 343 344/* 345 * Startup the SMP processors. 346 */ 347void 348mp_start(void) 349{ 350 POSTCODE(MP_START_POST); 351 352 /* look for MP capable motherboard */ 353 if (mp_capable) 354 mp_enable(boot_address); 355 else 356 panic("MP hardware not found!"); 357} 358 359 360/* 361 * Print various information about the SMP system hardware and setup. 362 */ 363void 364mp_announce(void) 365{ 366 int x; 367 368 POSTCODE(MP_ANNOUNCE_POST); 369 370 printf("FreeBSD/SMP: Multiprocessor motherboard\n"); 371 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0)); 372 printf(", version: 0x%08x", cpu_apic_versions[0]); 373 printf(", at 0x%08x\n", cpu_apic_address); 374 for (x = 1; x <= mp_naps; ++x) { 375 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x)); 376 printf(", version: 0x%08x", cpu_apic_versions[x]); 377 printf(", at 0x%08x\n", cpu_apic_address); 378 } 379 380#if defined(APIC_IO) 381 for (x = 0; x < mp_napics; ++x) { 382 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x)); 383 printf(", version: 0x%08x", io_apic_versions[x]); 384 printf(", at 0x%08x\n", io_apic_address[x]); 385 } 386#else 387 printf(" Warning: APIC I/O disabled\n"); 388#endif /* APIC_IO */ 389} 390 391/* 392 * AP cpu's call this to sync up protected mode. 393 */ 394void 395init_secondary(void) 396{ 397 int gsel_tss, slot; 398 399 r_gdt.rd_limit = sizeof(gdt[0]) * (NGDT + NCPU) - 1; 400 r_gdt.rd_base = (int) gdt; 401 lgdt(&r_gdt); /* does magic intra-segment return */ 402 lidt(&r_idt); 403 lldt(_default_ldt); 404 405 slot = NGDT + cpuid; 406 gsel_tss = GSEL(slot, SEL_KPL); 407 gdt[slot].sd.sd_type = SDT_SYS386TSS; 408 common_tss.tss_esp0 = 0; /* not used until after switch */ 409 common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 410 common_tss.tss_ioopt = (sizeof common_tss) << 16; 411 ltr(gsel_tss); 412 413 load_cr0(0x8005003b); /* XXX! */ 414 415 PTD[0] = 0; 416 pmap_set_opt((unsigned *)PTD); 417 418 invltlb(); 419} 420 421 422#if defined(APIC_IO) 423/* 424 * Final configuration of the BSP's local APIC: 425 * - disable 'pic mode'. 426 * - disable 'virtual wire mode'. 427 * - enable NMI. 428 */ 429void 430bsp_apic_configure(void) 431{ 432 u_char byte; 433 u_int32_t temp; 434 435 /* leave 'pic mode' if necessary */ 436 if (picmode) { 437 outb(0x22, 0x70); /* select IMCR */ 438 byte = inb(0x23); /* current contents */ 439 byte |= 0x01; /* mask external INTR */ 440 outb(0x23, byte); /* disconnect 8259s/NMI */ 441 } 442 443 /* mask lint0 (the 8259 'virtual wire' connection) */ 444 temp = lapic.lvt_lint0; 445 temp |= APIC_LVT_M; /* set the mask */ 446 lapic.lvt_lint0 = temp; 447 448 /* setup lint1 to handle NMI */ 449 temp = lapic.lvt_lint1; 450 temp &= ~APIC_LVT_M; /* clear the mask */ 451 lapic.lvt_lint1 = temp; 452 453 if (bootverbose) 454 apic_dump("bsp_apic_configure()"); 455} 456#endif /* APIC_IO */ 457 458 459/******************************************************************* 460 * local functions and data 461 */ 462 463/* 464 * start the SMP system 465 */ 466static void 467mp_enable(u_int boot_addr) 468{ 469 int x; 470#if defined(APIC_IO) 471 int apic; 472 u_int ux; 473#endif /* APIC_IO */ 474 475 POSTCODE(MP_ENABLE_POST); 476 477 /* turn on 4MB of V == P addressing so we can get to MP table */ 478 *(int *)PTD = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME); 479 invltlb(); 480 481 /* examine the MP table for needed info, uses physical addresses */ 482 x = mptable_pass2(); 483 484 *(int *)PTD = 0; 485 invltlb(); 486 487 /* can't process default configs till the CPU APIC is pmapped */ 488 if (x) 489 default_mp_table(x); 490 491 /* post scan cleanup */ 492 fix_mp_table(); 493 494#if defined(APIC_IO) 495 496 /* fill the LOGICAL io_apic_versions table */ 497 for (apic = 0; apic < mp_napics; ++apic) { 498 ux = io_apic_read(apic, IOAPIC_VER); 499 io_apic_versions[apic] = ux; 500 } 501 502 /* program each IO APIC in the system */ 503 for (apic = 0; apic < mp_napics; ++apic) 504 if (io_apic_setup(apic) < 0) 505 panic("IO APIC setup failure"); 506 507 /* install a 'Spurious INTerrupt' vector */ 508 setidt(XSPURIOUSINT_OFFSET, Xspuriousint, 509 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 510 511 /* install an inter-CPU IPI for TLB invalidation */ 512 setidt(XINVLTLB_OFFSET, Xinvltlb, 513 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 514 515 /* install an inter-CPU IPI for CPU stop/restart */ 516 setidt(XCPUSTOP_OFFSET, Xcpustop, 517 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 518 519#if defined(TEST_TEST1) 520 /* install a "fake hardware INTerrupt" vector */ 521 setidt(XTEST1_OFFSET, Xtest1, 522 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 523#endif /** TEST_TEST1 */ 524 525#endif /* APIC_IO */ 526 527 /* initialize all SMP locks */ 528 init_locks(); 529 530 /* start each Application Processor */ 531 start_all_aps(boot_addr); 532 533 /* 534 * The init process might be started on a different CPU now, 535 * and the boot CPU might not call prepare_usermode to get 536 * cr0 correctly configured. Thus we initialize cr0 here. 537 */ 538 load_cr0(rcr0() | CR0_WP | CR0_AM); 539} 540 541 542/* 543 * look for the MP spec signature 544 */ 545 546/* string defined by the Intel MP Spec as identifying the MP table */ 547#define MP_SIG 0x5f504d5f /* _MP_ */ 548#define NEXT(X) ((X) += 4) 549static int 550search_for_sig(u_int32_t target, int count) 551{ 552 int x; 553 u_int32_t *addr = (u_int32_t *) (KERNBASE + target); 554 555 for (x = 0; x < count; NEXT(x)) 556 if (addr[x] == MP_SIG) 557 /* make array index a byte index */ 558 return (target + (x * sizeof(u_int32_t))); 559 560 return -1; 561} 562 563 564static basetable_entry basetable_entry_types[] = 565{ 566 {0, 20, "Processor"}, 567 {1, 8, "Bus"}, 568 {2, 8, "I/O APIC"}, 569 {3, 8, "I/O INT"}, 570 {4, 8, "Local INT"} 571}; 572 573typedef struct BUSDATA { 574 u_char bus_id; 575 enum busTypes bus_type; 576} bus_datum; 577 578typedef struct INTDATA { 579 u_char int_type; 580 u_short int_flags; 581 u_char src_bus_id; 582 u_char src_bus_irq; 583 u_char dst_apic_id; 584 u_char dst_apic_int; 585} io_int, local_int; 586 587typedef struct BUSTYPENAME { 588 u_char type; 589 char name[7]; 590} bus_type_name; 591 592static bus_type_name bus_type_table[] = 593{ 594 {CBUS, "CBUS"}, 595 {CBUSII, "CBUSII"}, 596 {EISA, "EISA"}, 597 {UNKNOWN_BUSTYPE, "---"}, 598 {UNKNOWN_BUSTYPE, "---"}, 599 {ISA, "ISA"}, 600 {UNKNOWN_BUSTYPE, "---"}, 601 {UNKNOWN_BUSTYPE, "---"}, 602 {UNKNOWN_BUSTYPE, "---"}, 603 {UNKNOWN_BUSTYPE, "---"}, 604 {UNKNOWN_BUSTYPE, "---"}, 605 {UNKNOWN_BUSTYPE, "---"}, 606 {PCI, "PCI"}, 607 {UNKNOWN_BUSTYPE, "---"}, 608 {UNKNOWN_BUSTYPE, "---"}, 609 {UNKNOWN_BUSTYPE, "---"}, 610 {UNKNOWN_BUSTYPE, "---"}, 611 {XPRESS, "XPRESS"}, 612 {UNKNOWN_BUSTYPE, "---"} 613}; 614/* from MP spec v1.4, table 5-1 */ 615static int default_data[7][5] = 616{ 617/* nbus, id0, type0, id1, type1 */ 618 {1, 0, ISA, 255, 255}, 619 {1, 0, EISA, 255, 255}, 620 {1, 0, EISA, 255, 255}, 621 {0, 255, 255, 255, 255},/* MCA not supported */ 622 {2, 0, ISA, 1, PCI}, 623 {2, 0, EISA, 1, PCI}, 624 {0, 255, 255, 255, 255} /* MCA not supported */ 625}; 626 627 628/* the bus data */ 629bus_datum bus_data[NBUS]; 630 631/* the IO INT data, one entry per possible APIC INTerrupt */ 632io_int io_apic_ints[NINTR]; 633 634static int nintrs; 635 636static int processor_entry __P((proc_entry_ptr entry, int cpu)); 637static int bus_entry __P((bus_entry_ptr entry, int bus)); 638static int io_apic_entry __P((io_apic_entry_ptr entry, int apic)); 639static int int_entry __P((int_entry_ptr entry, int intr)); 640static int lookup_bus_type __P((char *name)); 641 642 643/* 644 * 1st pass on motherboard's Intel MP specification table. 645 * 646 * initializes: 647 * mp_ncpus = 1 648 * 649 * determines: 650 * cpu_apic_address (common to all CPUs) 651 * io_apic_address[N] 652 * mp_naps 653 * mp_nbusses 654 * mp_napics 655 * nintrs 656 */ 657static int 658mptable_pass1(void) 659{ 660 int x; 661 mpcth_t cth; 662 int totalSize; 663 void* position; 664 int count; 665 int type; 666 int mustpanic; 667 668 POSTCODE(MPTABLE_PASS1_POST); 669 670 mustpanic = 0; 671 672 /* clear various tables */ 673 for (x = 0; x < NAPICID; ++x) { 674 io_apic_address[x] = ~0; /* IO APIC address table */ 675 } 676 677 /* init everything to empty */ 678 mp_naps = 0; 679 mp_nbusses = 0; 680 mp_napics = 0; 681 nintrs = 0; 682 683 /* check for use of 'default' configuration */ 684 if (MPFPS_MPFB1 != 0) { 685 /* use default addresses */ 686 cpu_apic_address = DEFAULT_APIC_BASE; 687 io_apic_address[0] = DEFAULT_IO_APIC_BASE; 688 689 /* fill in with defaults */ 690 mp_naps = 2; /* includes BSP */ 691 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0]; 692#if defined(APIC_IO) 693 mp_napics = 1; 694 nintrs = 16; 695#endif /* APIC_IO */ 696 } 697 else { 698 if ((cth = mpfps->pap) == 0) 699 panic("MP Configuration Table Header MISSING!"); 700 701 cpu_apic_address = (vm_offset_t) cth->apic_address; 702 703 /* walk the table, recording info of interest */ 704 totalSize = cth->base_table_length - sizeof(struct MPCTH); 705 position = (u_char *) cth + sizeof(struct MPCTH); 706 count = cth->entry_count; 707 708 while (count--) { 709 switch (type = *(u_char *) position) { 710 case 0: /* processor_entry */ 711 if (((proc_entry_ptr)position)->cpu_flags 712 & PROCENTRY_FLAG_EN) 713 ++mp_naps; 714 break; 715 case 1: /* bus_entry */ 716 ++mp_nbusses; 717 break; 718 case 2: /* io_apic_entry */ 719 if (((io_apic_entry_ptr)position)->apic_flags 720 & IOAPICENTRY_FLAG_EN) 721 io_apic_address[mp_napics++] = 722 (vm_offset_t)((io_apic_entry_ptr) 723 position)->apic_address; 724 break; 725 case 3: /* int_entry */ 726 ++nintrs; 727 break; 728 case 4: /* int_entry */ 729 break; 730 default: 731 panic("mpfps Base Table HOSED!"); 732 /* NOTREACHED */ 733 } 734 735 totalSize -= basetable_entry_types[type].length; 736 (u_char*)position += basetable_entry_types[type].length; 737 } 738 } 739 740 /* qualify the numbers */ 741 if (mp_naps > NCPU) 742#if 0 /* XXX FIXME: kern/4255 */ 743 printf("Warning: only using %d of %d available CPUs!\n", 744 NCPU, mp_naps); 745#else 746 { 747 printf("NCPU cannot be different than actual CPU count.\n"); 748 printf(" add 'options NCPU=%d' to your kernel config file,\n", 749 mp_naps); 750 printf(" then rerun config & rebuild your SMP kernel\n"); 751 mustpanic = 1; 752 } 753#endif /* XXX FIXME: kern/4255 */ 754 if (mp_nbusses > NBUS) { 755 printf("found %d busses, increase NBUS\n", mp_nbusses); 756 mustpanic = 1; 757 } 758 if (mp_napics > NAPIC) { 759 printf("found %d apics, increase NAPIC\n", mp_napics); 760 mustpanic = 1; 761 } 762 if (nintrs > NINTR) { 763 printf("found %d intrs, increase NINTR\n", nintrs); 764 mustpanic = 1; 765 } 766 767 /* 768 * Count the BSP. 769 * This is also used as a counter while starting the APs. 770 */ 771 mp_ncpus = 1; 772 773 --mp_naps; /* subtract the BSP */ 774 775 return mustpanic; 776} 777 778 779/* 780 * 2nd pass on motherboard's Intel MP specification table. 781 * 782 * sets: 783 * boot_cpu_id 784 * ID_TO_IO(N), phy APIC ID to log CPU/IO table 785 * CPU_TO_ID(N), logical CPU to APIC ID table 786 * IO_TO_ID(N), logical IO to APIC ID table 787 * bus_data[N] 788 * io_apic_ints[N] 789 */ 790static int 791mptable_pass2(void) 792{ 793 int x; 794 mpcth_t cth; 795 int totalSize; 796 void* position; 797 int count; 798 int type; 799 int apic, bus, cpu, intr; 800 801 POSTCODE(MPTABLE_PASS2_POST); 802 803 /* clear various tables */ 804 for (x = 0; x < NAPICID; ++x) { 805 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */ 806 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */ 807 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */ 808 } 809 810 /* clear bus data table */ 811 for (x = 0; x < NBUS; ++x) 812 bus_data[x].bus_id = 0xff; 813 814 /* clear IO APIC INT table */ 815 for (x = 0; x < NINTR; ++x) 816 io_apic_ints[x].int_type = 0xff; 817 818 /* setup the cpu/apic mapping arrays */ 819 boot_cpu_id = -1; 820 821 /* record whether PIC or virtual-wire mode */ 822 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0; 823 824 /* check for use of 'default' configuration */ 825 if (MPFPS_MPFB1 != 0) 826 return MPFPS_MPFB1; /* return default configuration type */ 827 828 if ((cth = mpfps->pap) == 0) 829 panic("MP Configuration Table Header MISSING!"); 830 831 /* walk the table, recording info of interest */ 832 totalSize = cth->base_table_length - sizeof(struct MPCTH); 833 position = (u_char *) cth + sizeof(struct MPCTH); 834 count = cth->entry_count; 835 apic = bus = intr = 0; 836 cpu = 1; /* pre-count the BSP */ 837 838 while (count--) { 839 switch (type = *(u_char *) position) { 840 case 0: 841 if (processor_entry(position, cpu)) 842 ++cpu; 843 break; 844 case 1: 845 if (bus_entry(position, bus)) 846 ++bus; 847 break; 848 case 2: 849 if (io_apic_entry(position, apic)) 850 ++apic; 851 break; 852 case 3: 853 if (int_entry(position, intr)) 854 ++intr; 855 break; 856 case 4: 857 /* int_entry(position); */ 858 break; 859 default: 860 panic("mpfps Base Table HOSED!"); 861 /* NOTREACHED */ 862 } 863 864 totalSize -= basetable_entry_types[type].length; 865 (u_char *) position += basetable_entry_types[type].length; 866 } 867 868 if (boot_cpu_id == -1) 869 panic("NO BSP found!"); 870 871 /* report fact that its NOT a default configuration */ 872 return 0; 873} 874 875 876/* 877 * parse an Intel MP specification table 878 */ 879static void 880fix_mp_table(void) 881{ 882 int x; 883 int id; 884 int bus_0; 885 int bus_pci; 886 int num_pci_bus; 887 888 /* 889 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS 890 * did it wrong. The MP spec says that when more than 1 PCI bus 891 * exists the BIOS must begin with bus entries for the PCI bus and use 892 * actual PCI bus numbering. This implies that when only 1 PCI bus 893 * exists the BIOS can choose to ignore this ordering, and indeed many 894 * MP motherboards do ignore it. This causes a problem when the PCI 895 * sub-system makes requests of the MP sub-system based on PCI bus 896 * numbers. So here we look for the situation and renumber the 897 * busses and associated INTs in an effort to "make it right". 898 */ 899 900 /* find bus 0, PCI bus, count the number of PCI busses */ 901 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { 902 if (bus_data[x].bus_id == 0) { 903 bus_0 = x; 904 } 905 if (bus_data[x].bus_type == PCI) { 906 ++num_pci_bus; 907 bus_pci = x; 908 } 909 } 910 /* 911 * bus_0 == slot of bus with ID of 0 912 * bus_pci == slot of last PCI bus encountered 913 */ 914 915 /* check the 1 PCI bus case for sanity */ 916 if (num_pci_bus == 1) { 917 918 /* if it is number 0 all is well */ 919 if (bus_data[bus_pci].bus_id == 0) 920 return; 921 922 /* mis-numbered, swap with whichever bus uses slot 0 */ 923 924 /* swap the bus entry types */ 925 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type; 926 bus_data[bus_0].bus_type = PCI; 927 928 /* swap each relavant INTerrupt entry */ 929 id = bus_data[bus_pci].bus_id; 930 for (x = 0; x < nintrs; ++x) { 931 if (io_apic_ints[x].src_bus_id == id) { 932 io_apic_ints[x].src_bus_id = 0; 933 } 934 else if (io_apic_ints[x].src_bus_id == 0) { 935 io_apic_ints[x].src_bus_id = id; 936 } 937 } 938 } 939 /* sanity check if more than 1 PCI bus */ 940 else if (num_pci_bus > 1) { 941 for (x = 0; x < mp_nbusses; ++x) { 942 if (bus_data[x].bus_type != PCI) 943 continue; 944 if (bus_data[x].bus_id >= num_pci_bus) 945 panic("bad PCI bus numbering"); 946 } 947 } 948} 949 950 951static int 952processor_entry(proc_entry_ptr entry, int cpu) 953{ 954 /* check for usability */ 955 if ((cpu >= NCPU) || !(entry->cpu_flags & PROCENTRY_FLAG_EN)) 956 return 0; 957 958 /* check for BSP flag */ 959 if (entry->cpu_flags & PROCENTRY_FLAG_BP) { 960 boot_cpu_id = entry->apic_id; 961 CPU_TO_ID(0) = entry->apic_id; 962 ID_TO_CPU(entry->apic_id) = 0; 963 return 0; /* its already been counted */ 964 } 965 966 /* add another AP to list, if less than max number of CPUs */ 967 else { 968 CPU_TO_ID(cpu) = entry->apic_id; 969 ID_TO_CPU(entry->apic_id) = cpu; 970 return 1; 971 } 972} 973 974 975static int 976bus_entry(bus_entry_ptr entry, int bus) 977{ 978 int x; 979 char c, name[8]; 980 981 /* encode the name into an index */ 982 for (x = 0; x < 6; ++x) { 983 if ((c = entry->bus_type[x]) == ' ') 984 break; 985 name[x] = c; 986 } 987 name[x] = '\0'; 988 989 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) 990 panic("unknown bus type: '%s'", name); 991 992 bus_data[bus].bus_id = entry->bus_id; 993 bus_data[bus].bus_type = x; 994 995 return 1; 996} 997 998 999static int 1000io_apic_entry(io_apic_entry_ptr entry, int apic) 1001{ 1002 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) 1003 return 0; 1004 1005 IO_TO_ID(apic) = entry->apic_id; 1006 ID_TO_IO(entry->apic_id) = apic; 1007 1008 return 1; 1009} 1010 1011 1012static int 1013lookup_bus_type(char *name) 1014{ 1015 int x; 1016 1017 for (x = 0; x < MAX_BUSTYPE; ++x) 1018 if (strcmp(bus_type_table[x].name, name) == 0) 1019 return bus_type_table[x].type; 1020 1021 return UNKNOWN_BUSTYPE; 1022} 1023 1024 1025static int 1026int_entry(int_entry_ptr entry, int intr) 1027{ 1028 io_apic_ints[intr].int_type = entry->int_type; 1029 io_apic_ints[intr].int_flags = entry->int_flags; 1030 io_apic_ints[intr].src_bus_id = entry->src_bus_id; 1031 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq; 1032 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; 1033 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int; 1034 1035 return 1; 1036} 1037 1038 1039static int 1040apic_int_is_bus_type(int intr, int bus_type) 1041{ 1042 int bus; 1043 1044 for (bus = 0; bus < mp_nbusses; ++bus) 1045 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) 1046 && ((int) bus_data[bus].bus_type == bus_type)) 1047 return 1; 1048 1049 return 0; 1050} 1051 1052 1053/* 1054 * Given a traditional ISA INT mask, return an APIC mask. 1055 */ 1056u_int 1057isa_apic_mask(u_int isa_mask) 1058{ 1059 int isa_irq; 1060 int apic_pin; 1061 1062#if defined(SKIP_IRQ15_REDIRECT) 1063 if (isa_mask == (1 << 15)) { 1064 printf("skipping ISA IRQ15 redirect\n"); 1065 return isa_mask; 1066 } 1067#endif /* SKIP_IRQ15_REDIRECT */ 1068 1069 isa_irq = ffs(isa_mask); /* find its bit position */ 1070 if (isa_irq == 0) /* doesn't exist */ 1071 return 0; 1072 --isa_irq; /* make it zero based */ 1073 1074 apic_pin = isa_apic_pin(isa_irq); /* look for APIC connection */ 1075 if (apic_pin == -1) 1076 return 0; 1077 1078 return (1 << apic_pin); /* convert pin# to a mask */ 1079} 1080 1081 1082/* 1083 * Determine which APIC pin an ISA/EISA INT is attached to. 1084 */ 1085#define INTTYPE(I) (io_apic_ints[(I)].int_type) 1086#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) 1087 1088#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) 1089int 1090isa_apic_pin(int isa_irq) 1091{ 1092 int intr; 1093 1094 for (intr = 0; intr < nintrs; ++intr) { /* check each record */ 1095 if (INTTYPE(intr) == 0) { /* standard INT */ 1096 if (SRCBUSIRQ(intr) == isa_irq) { 1097 if (apic_int_is_bus_type(intr, ISA) || 1098 apic_int_is_bus_type(intr, EISA)) 1099 return INTPIN(intr); /* found */ 1100 } 1101 } 1102 } 1103 return -1; /* NOT found */ 1104} 1105#undef SRCBUSIRQ 1106 1107 1108/* 1109 * Determine which APIC pin a PCI INT is attached to. 1110 */ 1111#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) 1112#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) 1113#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) 1114int 1115pci_apic_pin(int pciBus, int pciDevice, int pciInt) 1116{ 1117 int intr; 1118 1119 --pciInt; /* zero based */ 1120 1121 for (intr = 0; intr < nintrs; ++intr) /* check each record */ 1122 if ((INTTYPE(intr) == 0) /* standard INT */ 1123 && (SRCBUSID(intr) == pciBus) 1124 && (SRCBUSDEVICE(intr) == pciDevice) 1125 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ 1126 if (apic_int_is_bus_type(intr, PCI)) 1127 return INTPIN(intr); /* exact match */ 1128 1129 return -1; /* NOT found */ 1130} 1131#undef SRCBUSLINE 1132#undef SRCBUSDEVICE 1133#undef SRCBUSID 1134 1135#undef INTPIN 1136#undef INTTYPE 1137 1138 1139/* 1140 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt. 1141 * 1142 * XXX FIXME: 1143 * Exactly what this means is unclear at this point. It is a solution 1144 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard 1145 * could route any of the ISA INTs to upper (>15) IRQ values. But most would 1146 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an 1147 * option. 1148 */ 1149int 1150undirect_isa_irq(int rirq) 1151{ 1152#if defined(READY) 1153 printf("Freeing redirected ISA irq %d.\n", rirq); 1154 /** FIXME: tickle the MB redirector chip */ 1155 return ???; 1156#else 1157 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq); 1158 return 0; 1159#endif /* READY */ 1160} 1161 1162 1163/* 1164 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt 1165 */ 1166int 1167undirect_pci_irq(int rirq) 1168{ 1169#if defined(READY) 1170 if (bootverbose) 1171 printf("Freeing redirected PCI irq %d.\n", rirq); 1172 1173 /** FIXME: tickle the MB redirector chip */ 1174 return ???; 1175#else 1176 if (bootverbose) 1177 printf("Freeing (NOT implemented) redirected PCI irq %d.\n", 1178 rirq); 1179 return 0; 1180#endif /* READY */ 1181} 1182 1183 1184/* 1185 * given a bus ID, return: 1186 * the bus type if found 1187 * -1 if NOT found 1188 */ 1189int 1190apic_bus_type(int id) 1191{ 1192 int x; 1193 1194 for (x = 0; x < mp_nbusses; ++x) 1195 if (bus_data[x].bus_id == id) 1196 return bus_data[x].bus_type; 1197 1198 return -1; 1199} 1200 1201 1202/* 1203 * given a LOGICAL APIC# and pin#, return: 1204 * the associated src bus ID if found 1205 * -1 if NOT found 1206 */ 1207int 1208apic_src_bus_id(int apic, int pin) 1209{ 1210 int x; 1211 1212 /* search each of the possible INTerrupt sources */ 1213 for (x = 0; x < nintrs; ++x) 1214 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1215 (pin == io_apic_ints[x].dst_apic_int)) 1216 return (io_apic_ints[x].src_bus_id); 1217 1218 return -1; /* NOT found */ 1219} 1220 1221 1222/* 1223 * given a LOGICAL APIC# and pin#, return: 1224 * the associated src bus IRQ if found 1225 * -1 if NOT found 1226 */ 1227int 1228apic_src_bus_irq(int apic, int pin) 1229{ 1230 int x; 1231 1232 for (x = 0; x < nintrs; x++) 1233 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1234 (pin == io_apic_ints[x].dst_apic_int)) 1235 return (io_apic_ints[x].src_bus_irq); 1236 1237 return -1; /* NOT found */ 1238} 1239 1240 1241/* 1242 * given a LOGICAL APIC# and pin#, return: 1243 * the associated INTerrupt type if found 1244 * -1 if NOT found 1245 */ 1246int 1247apic_int_type(int apic, int pin) 1248{ 1249 int x; 1250 1251 /* search each of the possible INTerrupt sources */ 1252 for (x = 0; x < nintrs; ++x) 1253 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1254 (pin == io_apic_ints[x].dst_apic_int)) 1255 return (io_apic_ints[x].int_type); 1256 1257 return -1; /* NOT found */ 1258} 1259 1260 1261/* 1262 * given a LOGICAL APIC# and pin#, return: 1263 * the associated trigger mode if found 1264 * -1 if NOT found 1265 */ 1266int 1267apic_trigger(int apic, int pin) 1268{ 1269 int x; 1270 1271 /* search each of the possible INTerrupt sources */ 1272 for (x = 0; x < nintrs; ++x) 1273 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1274 (pin == io_apic_ints[x].dst_apic_int)) 1275 return ((io_apic_ints[x].int_flags >> 2) & 0x03); 1276 1277 return -1; /* NOT found */ 1278} 1279 1280 1281/* 1282 * given a LOGICAL APIC# and pin#, return: 1283 * the associated 'active' level if found 1284 * -1 if NOT found 1285 */ 1286int 1287apic_polarity(int apic, int pin) 1288{ 1289 int x; 1290 1291 /* search each of the possible INTerrupt sources */ 1292 for (x = 0; x < nintrs; ++x) 1293 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1294 (pin == io_apic_ints[x].dst_apic_int)) 1295 return (io_apic_ints[x].int_flags & 0x03); 1296 1297 return -1; /* NOT found */ 1298} 1299 1300 1301/* 1302 * set data according to MP defaults 1303 * FIXME: probably not complete yet... 1304 */ 1305static void 1306default_mp_table(int type) 1307{ 1308 int ap_cpu_id; 1309#if defined(APIC_IO) 1310 u_int32_t ux; 1311 int io_apic_id; 1312 int pin; 1313#endif /* APIC_IO */ 1314 1315#if 0 1316 printf(" MP default config type: %d\n", type); 1317 switch (type) { 1318 case 1: 1319 printf(" bus: ISA, APIC: 82489DX\n"); 1320 break; 1321 case 2: 1322 printf(" bus: EISA, APIC: 82489DX\n"); 1323 break; 1324 case 3: 1325 printf(" bus: EISA, APIC: 82489DX\n"); 1326 break; 1327 case 4: 1328 printf(" bus: MCA, APIC: 82489DX\n"); 1329 break; 1330 case 5: 1331 printf(" bus: ISA+PCI, APIC: Integrated\n"); 1332 break; 1333 case 6: 1334 printf(" bus: EISA+PCI, APIC: Integrated\n"); 1335 break; 1336 case 7: 1337 printf(" bus: MCA+PCI, APIC: Integrated\n"); 1338 break; 1339 default: 1340 printf(" future type\n"); 1341 break; 1342 /* NOTREACHED */ 1343 } 1344#endif /* 0 */ 1345 1346 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24; 1347 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; 1348 1349 /* BSP */ 1350 CPU_TO_ID(0) = boot_cpu_id; 1351 ID_TO_CPU(boot_cpu_id) = 0; 1352 1353 /* one and only AP */ 1354 CPU_TO_ID(1) = ap_cpu_id; 1355 ID_TO_CPU(ap_cpu_id) = 1; 1356 1357#if defined(APIC_IO) 1358 /* one and only IO APIC */ 1359 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; 1360 1361 /* 1362 * sanity check, refer to MP spec section 3.6.6, last paragraph 1363 * necessary as some hardware isn't properly setting up the IO APIC 1364 */ 1365#if defined(REALLY_ANAL_IOAPICID_VALUE) 1366 if (io_apic_id != 2) { 1367#else 1368 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { 1369#endif /* REALLY_ANAL_IOAPICID_VALUE */ 1370 ux = io_apic_read(0, IOAPIC_ID); /* get current contents */ 1371 ux &= ~APIC_ID_MASK; /* clear the ID field */ 1372 ux |= 0x02000000; /* set it to '2' */ 1373 io_apic_write(0, IOAPIC_ID, ux); /* write new value */ 1374 ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */ 1375 if ((ux & APIC_ID_MASK) != 0x02000000) 1376 panic("can't control IO APIC ID, reg: 0x%08x", ux); 1377 io_apic_id = 2; 1378 } 1379 IO_TO_ID(0) = io_apic_id; 1380 ID_TO_IO(io_apic_id) = 0; 1381#endif /* APIC_IO */ 1382 1383 /* fill out bus entries */ 1384 switch (type) { 1385 case 1: 1386 case 2: 1387 case 3: 1388 case 5: 1389 case 6: 1390 bus_data[0].bus_id = default_data[type - 1][1]; 1391 bus_data[0].bus_type = default_data[type - 1][2]; 1392 bus_data[1].bus_id = default_data[type - 1][3]; 1393 bus_data[1].bus_type = default_data[type - 1][4]; 1394 break; 1395 1396 /* case 4: case 7: MCA NOT supported */ 1397 default: /* illegal/reserved */ 1398 panic("BAD default MP config: %d", type); 1399 /* NOTREACHED */ 1400 } 1401 1402#if defined(APIC_IO) 1403 /* general cases from MP v1.4, table 5-2 */ 1404 for (pin = 0; pin < 16; ++pin) { 1405 io_apic_ints[pin].int_type = 0; 1406 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */ 1407 io_apic_ints[pin].src_bus_id = 0; 1408 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */ 1409 io_apic_ints[pin].dst_apic_id = io_apic_id; 1410 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */ 1411 } 1412 1413 /* special cases from MP v1.4, table 5-2 */ 1414 if (type == 2) { 1415 io_apic_ints[2].int_type = 0xff; /* N/C */ 1416 io_apic_ints[13].int_type = 0xff; /* N/C */ 1417#if !defined(APIC_MIXED_MODE) 1418 /** FIXME: ??? */ 1419 panic("sorry, can't support type 2 default yet"); 1420#endif /* APIC_MIXED_MODE */ 1421 } 1422 else 1423 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ 1424 1425 if (type == 7) 1426 io_apic_ints[0].int_type = 0xff; /* N/C */ 1427 else 1428 io_apic_ints[0].int_type = 3; /* vectored 8259 */ 1429#endif /* APIC_IO */ 1430} 1431 1432 1433/* 1434 * initialize all the SMP locks 1435 */ 1436 1437/* critical region around IO APIC, apic_imen */ 1438struct simplelock imen_lock; 1439 1440/* critical region around splxx(), cpl, cil, ipending */ 1441struct simplelock cpl_lock; 1442 1443/* Make FAST_INTR() routines sequential */ 1444struct simplelock fast_intr_lock; 1445 1446/* critical region around INTR() routines */ 1447struct simplelock intr_lock; 1448 1449/* lock the com (tty) data structures */ 1450struct simplelock com_lock; 1451 1452static void 1453init_locks(void) 1454{ 1455 /* 1456 * Get the initial mp_lock with a count of 1 for the BSP. 1457 * This uses a LOGICAL cpu ID, ie BSP == 0. 1458 */ 1459 mp_lock = 0x00000001; 1460 1461 /* ISR uses its own "giant lock" */ 1462 isr_lock = 0x00000000; 1463 1464 /* serializes FAST_INTR() accesses */ 1465 s_lock_init((struct simplelock*)&fast_intr_lock); 1466 1467 /* serializes INTR() accesses */ 1468 s_lock_init((struct simplelock*)&intr_lock); 1469 1470 /* locks the IO APIC and apic_imen accesses */ 1471 s_lock_init((struct simplelock*)&imen_lock); 1472 1473 /* locks cpl accesses */ 1474 s_lock_init((struct simplelock*)&cpl_lock); 1475 1476 /* locks com (tty) data/hardware accesses: a FASTINTR() */ 1477 s_lock_init((struct simplelock*)&com_lock); 1478} 1479 1480 1481/* 1482 * start each AP in our list 1483 */ 1484static int 1485start_all_aps(u_int boot_addr) 1486{ 1487 int x, i; 1488 u_char mpbiosreason; 1489 u_long mpbioswarmvec; 1490 pd_entry_t *newptd; 1491 pt_entry_t *newpt; 1492 int *newpp, *stack; 1493 1494 POSTCODE(START_ALL_APS_POST); 1495 1496 /* initialize BSP's local APIC */ 1497 apic_initialize(); 1498 bsp_apic_ready = 1; 1499 1500 /* install the AP 1st level boot code */ 1501 install_ap_tramp(boot_addr); 1502 1503 1504 /* save the current value of the warm-start vector */ 1505 mpbioswarmvec = *((u_long *) WARMBOOT_OFF); 1506 outb(CMOS_REG, BIOS_RESET); 1507 mpbiosreason = inb(CMOS_DATA); 1508 1509 /* record BSP in CPU map */ 1510 all_cpus = 1; 1511 1512 /* start each AP */ 1513 for (x = 1; x <= mp_naps; ++x) { 1514 1515 /* This is a bit verbose, it will go away soon. */ 1516 1517 /* alloc new page table directory */ 1518 newptd = (pd_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE)); 1519 1520 /* Store the virtual PTD address for this CPU */ 1521 IdlePTDS[x] = newptd; 1522 1523 /* clone currently active one (ie: IdlePTD) */ 1524 bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */ 1525 1526 /* set up 0 -> 4MB P==V mapping for AP boot */ 1527 newptd[0] = (pd_entry_t) (PG_V | PG_RW | 1528 ((u_long)KPTphys & PG_FRAME)); 1529 1530 /* store PTD for this AP's boot sequence */ 1531 bootPTD = (pd_entry_t *)vtophys(newptd); 1532 1533 /* alloc new page table page */ 1534 newpt = (pt_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE)); 1535 1536 /* set the new PTD's private page to point there */ 1537 newptd[MPPTDI] = (pt_entry_t)(PG_V | PG_RW | vtophys(newpt)); 1538 1539 /* install self referential entry */ 1540 newptd[PTDPTDI] = (pd_entry_t)(PG_V | PG_RW | vtophys(newptd)); 1541 1542 /* allocate a new private data page */ 1543 newpp = (int *)kmem_alloc(kernel_map, PAGE_SIZE); 1544 1545 /* wire it into the private page table page */ 1546 newpt[0] = (pt_entry_t)(PG_V | PG_RW | vtophys(newpp)); 1547 1548 /* wire the ptp into itself for access */ 1549 newpt[1] = (pt_entry_t)(PG_V | PG_RW | vtophys(newpt)); 1550 1551 /* copy in the pointer to the local apic */ 1552 newpt[2] = SMP_prvpt[2]; 1553 1554 /* and the IO apic mapping[s] */ 1555 for (i = 16; i < 32; i++) 1556 newpt[i] = SMP_prvpt[i]; 1557 1558 /* allocate and set up an idle stack data page */ 1559 stack = (int *)kmem_alloc(kernel_map, PAGE_SIZE); 1560 newpt[3] = (pt_entry_t)(PG_V | PG_RW | vtophys(stack)); 1561 1562 newpt[4] = 0; /* *prv_CMAP1 */ 1563 newpt[5] = 0; /* *prv_CMAP2 */ 1564 newpt[6] = 0; /* *prv_CMAP3 */ 1565 1566 /* prime data page for it to use */ 1567 newpp[0] = x; /* cpuid */ 1568 newpp[1] = 0; /* curproc */ 1569 newpp[2] = 0; /* curpcb */ 1570 newpp[3] = 0; /* npxproc */ 1571 newpp[4] = 0; /* runtime.tv_sec */ 1572 newpp[5] = 0; /* runtime.tv_usec */ 1573 newpp[6] = x << 24; /* cpu_lockid */ 1574 newpp[7] = 0; /* other_cpus */ 1575 newpp[8] = (int)bootPTD; /* my_idlePTD */ 1576 newpp[9] = 0; /* ss_tpr */ 1577 newpp[10] = (int)&newpt[4]; /* prv_CMAP1 */ 1578 newpp[11] = (int)&newpt[5]; /* prv_CMAP2 */ 1579 newpp[12] = (int)&newpt[6]; /* prv_CMAP3 */ 1580 1581 /* setup a vector to our boot code */ 1582 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 1583 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); 1584 outb(CMOS_REG, BIOS_RESET); 1585 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 1586 1587 /* attempt to start the Application Processor */ 1588 CHECK_INIT(99); /* setup checkpoints */ 1589 if (!start_ap(x, boot_addr)) { 1590 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); 1591 CHECK_PRINT("trace"); /* show checkpoints */ 1592 /* better panic as the AP may be running loose */ 1593 printf("panic y/n? [y] "); 1594 if (cngetc() != 'n') 1595 panic("bye-bye"); 1596 } 1597 CHECK_PRINT("trace"); /* show checkpoints */ 1598 1599 /* record its version info */ 1600 cpu_apic_versions[x] = cpu_apic_versions[0]; 1601 1602 all_cpus |= (1 << x); /* record AP in CPU map */ 1603 } 1604 1605 /* build our map of 'other' CPUs */ 1606 other_cpus = all_cpus & ~(1 << cpuid); 1607 1608 /* fill in our (BSP) APIC version */ 1609 cpu_apic_versions[0] = lapic.version; 1610 1611 /* restore the warmstart vector */ 1612 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 1613 outb(CMOS_REG, BIOS_RESET); 1614 outb(CMOS_DATA, mpbiosreason); 1615 1616 /* 1617 * Set up the idle context for the BSP. Similar to above except 1618 * that some was done by locore, some by pmap.c and some is implicit 1619 * because the BSP is cpu#0 and the page is initially zero, and also 1620 * because we can refer to variables by name on the BSP.. 1621 */ 1622 newptd = (pd_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE)); 1623 1624 bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */ 1625 IdlePTDS[0] = newptd; 1626 1627 /* Point PTD[] to this page instead of IdlePTD's physical page */ 1628 newptd[PTDPTDI] = (pd_entry_t)(PG_V | PG_RW | vtophys(newptd)); 1629 1630 my_idlePTD = (pd_entry_t *)vtophys(newptd); 1631 1632 /* Allocate and setup BSP idle stack */ 1633 stack = (int *)kmem_alloc(kernel_map, PAGE_SIZE); 1634 SMP_prvpt[3] = (pt_entry_t)(PG_V | PG_RW | vtophys(stack)); 1635 1636 pmap_set_opt_bsp(); 1637 1638 /* number of APs actually started */ 1639 return mp_ncpus - 1; 1640} 1641 1642 1643/* 1644 * load the 1st level AP boot code into base memory. 1645 */ 1646 1647/* targets for relocation */ 1648extern void bigJump(void); 1649extern void bootCodeSeg(void); 1650extern void bootDataSeg(void); 1651extern void MPentry(void); 1652extern u_int MP_GDT; 1653extern u_int mp_gdtbase; 1654 1655static void 1656install_ap_tramp(u_int boot_addr) 1657{ 1658 int x; 1659 int size = *(int *) ((u_long) & bootMP_size); 1660 u_char *src = (u_char *) ((u_long) bootMP); 1661 u_char *dst = (u_char *) boot_addr + KERNBASE; 1662 u_int boot_base = (u_int) bootMP; 1663 u_int8_t *dst8; 1664 u_int16_t *dst16; 1665 u_int32_t *dst32; 1666 1667 POSTCODE(INSTALL_AP_TRAMP_POST); 1668 1669 for (x = 0; x < size; ++x) 1670 *dst++ = *src++; 1671 1672 /* 1673 * modify addresses in code we just moved to basemem. unfortunately we 1674 * need fairly detailed info about mpboot.s for this to work. changes 1675 * to mpboot.s might require changes here. 1676 */ 1677 1678 /* boot code is located in KERNEL space */ 1679 dst = (u_char *) boot_addr + KERNBASE; 1680 1681 /* modify the lgdt arg */ 1682 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 1683 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); 1684 1685 /* modify the ljmp target for MPentry() */ 1686 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 1687 *dst32 = ((u_int) MPentry - KERNBASE); 1688 1689 /* modify the target for boot code segment */ 1690 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 1691 dst8 = (u_int8_t *) (dst16 + 1); 1692 *dst16 = (u_int) boot_addr & 0xffff; 1693 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1694 1695 /* modify the target for boot data segment */ 1696 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 1697 dst8 = (u_int8_t *) (dst16 + 1); 1698 *dst16 = (u_int) boot_addr & 0xffff; 1699 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1700} 1701 1702 1703/* 1704 * this function starts the AP (application processor) identified 1705 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 1706 * to accomplish this. This is necessary because of the nuances 1707 * of the different hardware we might encounter. It ain't pretty, 1708 * but it seems to work. 1709 */ 1710static int 1711start_ap(int logical_cpu, u_int boot_addr) 1712{ 1713 int physical_cpu; 1714 int vector; 1715 int cpus; 1716 u_long icr_lo, icr_hi; 1717 1718 POSTCODE(START_AP_POST); 1719 1720 /* get the PHYSICAL APIC ID# */ 1721 physical_cpu = CPU_TO_ID(logical_cpu); 1722 1723 /* calculate the vector */ 1724 vector = (boot_addr >> 12) & 0xff; 1725 1726 /* used as a watchpoint to signal AP startup */ 1727 cpus = mp_ncpus; 1728 1729 /* 1730 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 1731 * and running the target CPU. OR this INIT IPI might be latched (P5 1732 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 1733 * ignored. 1734 */ 1735 1736 /* setup the address for the target AP */ 1737 icr_hi = lapic.icr_hi & ~APIC_ID_MASK; 1738 icr_hi |= (physical_cpu << 24); 1739 lapic.icr_hi = icr_hi; 1740 1741 /* do an INIT IPI: assert RESET */ 1742 icr_lo = lapic.icr_lo & 0xfff00000; 1743 lapic.icr_lo = icr_lo | 0x0000c500; 1744 1745 /* wait for pending status end */ 1746 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1747 /* spin */ ; 1748 1749 /* do an INIT IPI: deassert RESET */ 1750 lapic.icr_lo = icr_lo | 0x00008500; 1751 1752 /* wait for pending status end */ 1753 u_sleep(10000); /* wait ~10mS */ 1754 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1755 /* spin */ ; 1756 1757 /* 1758 * next we do a STARTUP IPI: the previous INIT IPI might still be 1759 * latched, (P5 bug) this 1st STARTUP would then terminate 1760 * immediately, and the previously started INIT IPI would continue. OR 1761 * the previous INIT IPI has already run. and this STARTUP IPI will 1762 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 1763 * will run. 1764 */ 1765 1766 /* do a STARTUP IPI */ 1767 lapic.icr_lo = icr_lo | 0x00000600 | vector; 1768 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1769 /* spin */ ; 1770 u_sleep(200); /* wait ~200uS */ 1771 1772 /* 1773 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 1774 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 1775 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 1776 * recognized after hardware RESET or INIT IPI. 1777 */ 1778 1779 lapic.icr_lo = icr_lo | 0x00000600 | vector; 1780 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1781 /* spin */ ; 1782 u_sleep(200); /* wait ~200uS */ 1783 1784 /* wait for it to start */ 1785 set_apic_timer(5000000);/* == 5 seconds */ 1786 while (read_apic_timer()) 1787 if (mp_ncpus > cpus) 1788 return 1; /* return SUCCESS */ 1789 1790 return 0; /* return FAILURE */ 1791} 1792 1793 1794/* 1795 * Flush the TLB on all other CPU's 1796 * 1797 * XXX: Needs to handshake and wait for completion before proceding. 1798 */ 1799void 1800smp_invltlb(void) 1801{ 1802#if defined(APIC_IO) 1803 if (smp_started && invltlb_ok) 1804 all_but_self_ipi(XINVLTLB_OFFSET); 1805#endif /* APIC_IO */ 1806} 1807 1808void 1809invlpg(u_int addr) 1810{ 1811 __asm __volatile("invlpg (%0)"::"r"(addr):"memory"); 1812 1813 /* send a message to the other CPUs */ 1814 smp_invltlb(); 1815} 1816 1817void 1818invltlb(void) 1819{ 1820 u_long temp; 1821 1822 /* 1823 * This should be implemented as load_cr3(rcr3()) when load_cr3() is 1824 * inlined. 1825 */ 1826 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory"); 1827 1828 /* send a message to the other CPUs */ 1829 smp_invltlb(); 1830} 1831 1832 1833/* 1834 * When called the executing CPU will send an IPI to all other CPUs 1835 * requesting that they halt execution. 1836 * 1837 * Usually (but not necessarily) called with 'other_cpus' as its arg. 1838 * 1839 * - Signals all CPUs in map to stop. 1840 * - Waits for each to stop. 1841 * 1842 * Returns: 1843 * -1: error 1844 * 0: NA 1845 * 1: ok 1846 * 1847 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs 1848 * from executing at same time. 1849 */ 1850int 1851stop_cpus(u_int map) 1852{ 1853 if (!smp_started) 1854 return 0; 1855 1856 /* send IPI to all CPUs in map */ 1857 stopped_cpus = 0; 1858 1859 /* send the Xcpustop IPI to all CPUs in map */ 1860 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED); 1861 1862 while (stopped_cpus != map) 1863 /* spin */ ; 1864 1865 return 1; 1866} 1867 1868 1869/* 1870 * Called by a CPU to restart stopped CPUs. 1871 * 1872 * Usually (but not necessarily) called with 'stopped_cpus' as its arg. 1873 * 1874 * - Signals all CPUs in map to restart. 1875 * - Waits for each to restart. 1876 * 1877 * Returns: 1878 * -1: error 1879 * 0: NA 1880 * 1: ok 1881 */ 1882int 1883restart_cpus(u_int map) 1884{ 1885 if (!smp_started) 1886 return 0; 1887 1888 started_cpus = map; /* signal other cpus to restart */ 1889 1890 while (started_cpus) /* wait for each to clear its bit */ 1891 /* spin */ ; 1892 1893 return 1; 1894} 1895 1896int smp_active = 0; /* are the APs allowed to run? */ 1897SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RW, &smp_active, 0, ""); 1898 1899/* XXX maybe should be hw.ncpu */ 1900int smp_cpus = 1; /* how many cpu's running */ 1901SYSCTL_INT(_machdep, OID_AUTO, smp_cpus, CTLFLAG_RD, &smp_cpus, 0, ""); 1902 1903int invltlb_ok = 0; /* throttle smp_invltlb() till safe */ 1904SYSCTL_INT(_machdep, OID_AUTO, invltlb_ok, CTLFLAG_RW, &invltlb_ok, 0, ""); 1905 1906int do_page_zero_idle = 0; /* bzero pages for fun and profit in idleloop */ 1907SYSCTL_INT(_machdep, OID_AUTO, do_page_zero_idle, CTLFLAG_RW, 1908 &do_page_zero_idle, 0, ""); 1909 1910 1911/* 1912 * This is called once the rest of the system is up and running and we're 1913 * ready to let the AP's out of the pen. 1914 */ 1915void ap_init(void); 1916 1917void 1918ap_init() 1919{ 1920 u_int temp; 1921 u_int apic_id; 1922 1923 smp_cpus++; 1924 1925 /* Build our map of 'other' CPUs. */ 1926 other_cpus = all_cpus & ~(1 << cpuid); 1927 1928 printf("SMP: AP CPU #%d Launched!\n", cpuid); 1929 1930 /* XXX FIXME: i386 specific, and redundant: Setup the FPU. */ 1931 load_cr0((rcr0() & ~CR0_EM) | CR0_MP | CR0_NE | CR0_TS); 1932 1933 /* A quick check from sanity claus */ 1934 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]); 1935 if (cpuid != apic_id) { 1936 printf("SMP: cpuid = %d\n", cpuid); 1937 printf("SMP: apic_id = %d\n", apic_id); 1938 printf("PTD[MPPTDI] = %08x\n", PTD[MPPTDI]); 1939 panic("cpuid mismatch! boom!!"); 1940 } 1941 1942 /* Init local apic for irq's */ 1943 apic_initialize(); 1944 1945 /* 1946 * Activate smp_invltlb, although strictly speaking, this isn't 1947 * quite correct yet. We should have a bitfield for cpus willing 1948 * to accept TLB flush IPI's or something and sync them. 1949 */ 1950 invltlb_ok = 1; 1951 smp_started = 1; /* enable IPI's, tlb shootdown, freezes etc */ 1952 smp_active = 1; /* historic */ 1953 1954 curproc = NULL; /* make sure */ 1955} 1956