mptable.c revision 27289
1/* 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $Id: mp_machdep.c,v 1.7 1997/07/08 23:42:28 smp Exp smp $ 26 */ 27 28#include "opt_smp.h" 29 30#include <sys/param.h> /* for KERNBASE */ 31#include <sys/types.h> 32#include <sys/sysproto.h> 33#include <sys/time.h> 34#include <sys/systm.h> 35 36#include <vm/vm.h> /* for KERNBASE */ 37#include <vm/vm_param.h> /* for KERNBASE */ 38#include <vm/pmap.h> /* for KERNBASE */ 39#include <machine/pmap.h> /* for KERNBASE */ 40#include <vm/vm_kern.h> 41#include <vm/vm_extern.h> 42 43#include <machine/smp.h> 44#include <machine/apic.h> 45#include <machine/mpapic.h> 46#include <machine/cpufunc.h> 47#include <machine/segments.h> 48#include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_CPUSTOP */ 49#include <machine/tss.h> 50#include <machine/specialreg.h> 51 52#include <i386/i386/cons.h> /* cngetc() */ 53 54#if defined(TEST_CPUSTOP) 55void db_printf __P((const char *fmt, ...)); 56#endif /* TEST_CPUSTOP */ 57 58#if defined(APIC_IO) 59#include <machine/md_var.h> /* setidt() */ 60#include <i386/isa/icu.h> /* IPIs */ 61#include <i386/isa/intr_machdep.h> /* IPIs */ 62#endif /* APIC_IO */ 63 64#define WARMBOOT_TARGET 0 65#define WARMBOOT_OFF (KERNBASE + 0x0467) 66#define WARMBOOT_SEG (KERNBASE + 0x0469) 67 68#define BIOS_BASE (0xf0000) 69#define BIOS_SIZE (0x10000) 70#define BIOS_COUNT (BIOS_SIZE/4) 71 72#define CMOS_REG (0x70) 73#define CMOS_DATA (0x71) 74#define BIOS_RESET (0x0f) 75#define BIOS_WARM (0x0a) 76 77#define PROCENTRY_FLAG_EN 0x01 78#define PROCENTRY_FLAG_BP 0x02 79#define IOAPICENTRY_FLAG_EN 0x01 80 81 82/* MP Floating Pointer Structure */ 83typedef struct MPFPS { 84 char signature[4]; 85 void *pap; 86 u_char length; 87 u_char spec_rev; 88 u_char checksum; 89 u_char mpfb1; 90 u_char mpfb2; 91 u_char mpfb3; 92 u_char mpfb4; 93 u_char mpfb5; 94} *mpfps_t; 95 96/* MP Configuration Table Header */ 97typedef struct MPCTH { 98 char signature[4]; 99 u_short base_table_length; 100 u_char spec_rev; 101 u_char checksum; 102 u_char oem_id[8]; 103 u_char product_id[12]; 104 void *oem_table_pointer; 105 u_short oem_table_size; 106 u_short entry_count; 107 void *apic_address; 108 u_short extended_table_length; 109 u_char extended_table_checksum; 110 u_char reserved; 111} *mpcth_t; 112 113 114typedef struct PROCENTRY { 115 u_char type; 116 u_char apic_id; 117 u_char apic_version; 118 u_char cpu_flags; 119 u_long cpu_signature; 120 u_long feature_flags; 121 u_long reserved1; 122 u_long reserved2; 123} *proc_entry_ptr; 124 125typedef struct BUSENTRY { 126 u_char type; 127 u_char bus_id; 128 char bus_type[6]; 129} *bus_entry_ptr; 130 131typedef struct IOAPICENTRY { 132 u_char type; 133 u_char apic_id; 134 u_char apic_version; 135 u_char apic_flags; 136 void *apic_address; 137} *io_apic_entry_ptr; 138 139typedef struct INTENTRY { 140 u_char type; 141 u_char int_type; 142 u_short int_flags; 143 u_char src_bus_id; 144 u_char src_bus_irq; 145 u_char dst_apic_id; 146 u_char dst_apic_int; 147} *int_entry_ptr; 148 149/* descriptions of MP basetable entries */ 150typedef struct BASETABLE_ENTRY { 151 u_char type; 152 u_char length; 153 char name[16]; 154} basetable_entry; 155 156/* 157 * this code MUST be enabled here and in mpboot.s. 158 * it follows the very early stages of AP boot by placing values in CMOS ram. 159 * it NORMALLY will never be needed and thus the primitive method for enabling. 160 * 161#define CHECK_POINTS 162 */ 163 164#if defined(CHECK_POINTS) 165#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 166#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 167 168#define CHECK_INIT(D); \ 169 CHECK_WRITE(0x34, (D)); \ 170 CHECK_WRITE(0x35, (D)); \ 171 CHECK_WRITE(0x36, (D)); \ 172 CHECK_WRITE(0x37, (D)); \ 173 CHECK_WRITE(0x38, (D)); \ 174 CHECK_WRITE(0x39, (D)); 175 176#define CHECK_PRINT(S); \ 177 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 178 (S), \ 179 CHECK_READ(0x34), \ 180 CHECK_READ(0x35), \ 181 CHECK_READ(0x36), \ 182 CHECK_READ(0x37), \ 183 CHECK_READ(0x38), \ 184 CHECK_READ(0x39)); 185 186#else /* CHECK_POINTS */ 187 188#define CHECK_INIT(D) 189#define CHECK_PRINT(S) 190 191#endif /* CHECK_POINTS */ 192 193/* 194 * Values to send to the POST hardware. 195 */ 196#define MP_BOOTADDRESS_POST 0x10 197#define MP_PROBE_POST 0x11 198#define MP_START_POST 0x12 199#define MP_ANNOUNCE_POST 0x13 200#define MPTABLE_PASS1_POST 0x14 201#define MPTABLE_PASS2_POST 0x15 202#define MP_ENABLE_POST 0x16 203#define START_ALL_APS_POST 0x17 204#define INSTALL_AP_TRAMP_POST 0x18 205#define START_AP_POST 0x19 206 207/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ 208int current_postcode; 209 210/** XXX FIXME: what system files declare these??? */ 211extern struct region_descriptor r_gdt, r_idt; 212 213int mp_ncpus; /* # of CPUs, including BSP */ 214int mp_naps; /* # of Applications processors */ 215int mp_nbusses; /* # of busses */ 216int mp_napics; /* # of IO APICs */ 217int boot_cpu_id; /* designated BSP */ 218vm_offset_t cpu_apic_address; 219vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */ 220 221u_int32_t cpu_apic_versions[NCPU]; 222u_int32_t io_apic_versions[NAPIC]; 223 224/* 225 * APIC ID logical/physical mapping structures. 226 * We oversize these to simplify boot-time config. 227 */ 228int cpu_num_to_apic_id[NAPICID]; 229int io_num_to_apic_id[NAPICID]; 230int apic_id_to_logical[NAPICID]; 231 232/* Bitmap of all available CPUs */ 233u_int all_cpus; 234 235/* Boot of AP uses this PTD */ 236u_int *bootPTD; 237 238/* Hotwire a 0->4MB V==P mapping */ 239extern pt_entry_t KPTphys; 240 241/* Virtual address of per-cpu common_tss */ 242extern struct i386tss common_tss; 243 244/* 245 * Local data and functions. 246 */ 247 248static int mp_capable; 249static u_int boot_address; 250static u_int base_memory; 251 252static int picmode; /* 0: virtual wire mode, 1: PIC mode */ 253static mpfps_t mpfps; 254static int search_for_sig(u_int32_t target, int count); 255static void mp_enable(u_int boot_addr); 256 257static int mptable_pass1(void); 258static int mptable_pass2(void); 259static void default_mp_table(int type); 260static int start_all_aps(u_int boot_addr); 261static void install_ap_tramp(u_int boot_addr); 262static int start_ap(int logicalCpu, u_int boot_addr); 263 264 265/* 266 * Calculate usable address in base memory for AP trampoline code. 267 */ 268u_int 269mp_bootaddress(u_int basemem) 270{ 271 POSTCODE(MP_BOOTADDRESS_POST); 272 273 base_memory = basemem * 1024; /* convert to bytes */ 274 275 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ 276 if ((base_memory - boot_address) < bootMP_size) 277 boot_address -= 4096; /* not enough, lower by 4k */ 278 279 return boot_address; 280} 281 282 283/* 284 * Look for an Intel MP spec table (ie, SMP capable hardware). 285 */ 286int 287mp_probe(void) 288{ 289 int x; 290 u_long segment; 291 u_int32_t target; 292 293 POSTCODE(MP_PROBE_POST); 294 295 /* see if EBDA exists */ 296 if (segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) { 297 /* search first 1K of EBDA */ 298 target = (u_int32_t) (segment << 4); 299 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 300 goto found; 301 } else { 302 /* last 1K of base memory, effective 'top of base' passed in */ 303 target = (u_int32_t) (base_memory - 0x400); 304 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 305 goto found; 306 } 307 308 /* search the BIOS */ 309 target = (u_int32_t) BIOS_BASE; 310 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) 311 goto found; 312 313 /* nothing found */ 314 mpfps = (mpfps_t)0; 315 mp_capable = 0; 316 return 0; 317 318found: 319 /* calculate needed resources */ 320 mpfps = (mpfps_t)x; 321 if (mptable_pass1()) 322 panic("you must reconfigure your kernel"); 323 324 /* flag fact that we are running multiple processors */ 325 mp_capable = 1; 326 return 1; 327} 328 329 330/* 331 * Startup the SMP processors. 332 */ 333void 334mp_start(void) 335{ 336 POSTCODE(MP_START_POST); 337 338 /* look for MP capable motherboard */ 339 if (mp_capable) 340 mp_enable(boot_address); 341 else 342 panic("MP hardware not found!"); 343} 344 345 346/* 347 * Print various information about the SMP system hardware and setup. 348 */ 349void 350mp_announce(void) 351{ 352 int x; 353 354 POSTCODE(MP_ANNOUNCE_POST); 355 356 printf("FreeBSD/SMP: Multiprocessor motherboard\n"); 357 printf(" cpu0 (BSP): apic id: %d", CPU_TO_ID(0)); 358 printf(", version: 0x%08x", cpu_apic_versions[0]); 359 printf(", at 0x%08x\n", cpu_apic_address); 360 for (x = 1; x <= mp_naps; ++x) { 361 printf(" cpu%d (AP): apic id: %d", x, CPU_TO_ID(x)); 362 printf(", version: 0x%08x", cpu_apic_versions[x]); 363 printf(", at 0x%08x\n", cpu_apic_address); 364 } 365 366#if defined(APIC_IO) 367 for (x = 0; x < mp_napics; ++x) { 368 printf(" io%d (APIC): apic id: %d", x, IO_TO_ID(x)); 369 printf(", version: 0x%08x", io_apic_versions[x]); 370 printf(", at 0x%08x\n", io_apic_address[x]); 371 } 372#else 373 printf(" Warning: APIC I/O disabled\n"); 374#endif /* APIC_IO */ 375} 376 377/* 378 * AP cpu's call this to sync up protected mode. 379 */ 380void 381init_secondary(void) 382{ 383 int gsel_tss, slot; 384 385 r_gdt.rd_limit = sizeof(gdt[0]) * (NGDT + NCPU) - 1; 386 r_gdt.rd_base = (int) gdt; 387 lgdt(&r_gdt); /* does magic intra-segment return */ 388 lidt(&r_idt); 389 lldt(_default_ldt); 390 391 slot = NGDT + cpuid; 392 gsel_tss = GSEL(slot, SEL_KPL); 393 gdt[slot].sd.sd_type = SDT_SYS386TSS; 394 common_tss.tss_esp0 = 0; /* not used until after switch */ 395 common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 396 common_tss.tss_ioopt = (sizeof common_tss) << 16; 397 ltr(gsel_tss); 398 399 load_cr0(0x8005003b); /* XXX! */ 400 401 PTD[0] = 0; 402 invltlb(); 403} 404 405 406#if defined(APIC_IO) 407/* 408 * Final configuration of the BSP's local APIC: 409 * - disable 'pic mode'. 410 * - disable 'virtual wire mode'. 411 * - enable NMI. 412 */ 413void 414bsp_apic_configure(void) 415{ 416 u_char byte; 417 u_int32_t temp; 418 419 /* leave 'pic mode' if necessary */ 420 if (picmode) { 421 outb(0x22, 0x70); /* select IMCR */ 422 byte = inb(0x23); /* current contents */ 423 byte |= 0x01; /* mask external INTR */ 424 outb(0x23, byte); /* disconnect 8259s/NMI */ 425 } 426 427 /* mask lint0 (the 8259 'virtual wire' connection) */ 428 temp = lapic.lvt_lint0; 429 temp |= APIC_LVT_M; /* set the mask */ 430 lapic.lvt_lint0 = temp; 431 432 /* setup lint1 to handle NMI */ 433 temp = lapic.lvt_lint1; 434 temp &= ~APIC_LVT_M; /* clear the mask */ 435 lapic.lvt_lint1 = temp; 436 437#if defined(TEST_CPUSTOP) 438 printf(">>> CPU%02d bsp_apic_configure() lint0: 0x%08x\n", 439 cpuid, lapic.lvt_lint0); 440 printf(">>> lint1: 0x%08x\n", 441 lapic.lvt_lint1); 442 printf(">>> TPR: 0x%08x\n", lapic.tpr); 443 printf(">>> SVR: 0x%08x\n", lapic.svr); 444#endif /* TEST_CPUSTOP */ 445} 446#endif /* APIC_IO */ 447 448 449/******************************************************************* 450 * local functions and data 451 */ 452 453/* 454 * start the SMP system 455 */ 456static void 457mp_enable(u_int boot_addr) 458{ 459 int x; 460#if defined(APIC_IO) 461 int apic; 462 u_int ux; 463#endif /* APIC_IO */ 464 465 POSTCODE(MP_ENABLE_POST); 466 467 /* turn on 4MB of V == P addressing so we can get to MP table */ 468 *(int *)PTD = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME); 469 invltlb(); 470 471 /* examine the MP table for needed info, uses physical addresses */ 472 x = mptable_pass2(); 473 474 *(int *)PTD = 0; 475 invltlb(); 476 477 /* can't process default configs till the CPU APIC is pmapped */ 478 if (x) 479 default_mp_table(x); 480 481#if defined(APIC_IO) 482 /* fill the LOGICAL io_apic_versions table */ 483 for (apic = 0; apic < mp_napics; ++apic) { 484 ux = io_apic_read(apic, IOAPIC_VER); 485 io_apic_versions[apic] = ux; 486 } 487 488 /* program each IO APIC in the system */ 489 for (apic = 0; apic < mp_napics; ++apic) 490 if (io_apic_setup(apic) < 0) 491 panic("IO APIC setup failure"); 492 493 /* install an inter-CPU IPI for TLB invalidation */ 494 setidt(XINVLTLB_OFFSET, Xinvltlb, 495 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 496 497#if defined(TEST_CPUSTOP) 498 /* install an inter-CPU IPI for CPU stop/restart */ 499 setidt(XCPUSTOP_OFFSET, Xcpustop, 500 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 501 502 /* install a 'Spurious INTerrupt' vector */ 503 setidt(XSPURIOUSINT_OFFSET, Xspuriousint, 504 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 505#endif /* TEST_CPUSTOP */ 506#endif /* APIC_IO */ 507 508 /* start each Application Processor */ 509 start_all_aps(boot_addr); 510 511 /* 512 * The init process might be started on a different CPU now, 513 * and the boot CPU might not call prepare_usermode to get 514 * cr0 correctly configured. Thus we initialize cr0 here. 515 */ 516 load_cr0(rcr0() | CR0_WP | CR0_AM); 517} 518 519 520/* 521 * look for the MP spec signature 522 */ 523 524/* string defined by the Intel MP Spec as identifying the MP table */ 525#define MP_SIG 0x5f504d5f /* _MP_ */ 526#define NEXT(X) ((X) += 4) 527static int 528search_for_sig(u_int32_t target, int count) 529{ 530 int x; 531 u_int32_t *addr = (u_int32_t *) (KERNBASE + target); 532 533 for (x = 0; x < count; NEXT(x)) 534 if (addr[x] == MP_SIG) 535 /* make array index a byte index */ 536 return (target + (x * sizeof(u_int32_t))); 537 538 return -1; 539} 540 541 542static basetable_entry basetable_entry_types[] = 543{ 544 {0, 20, "Processor"}, 545 {1, 8, "Bus"}, 546 {2, 8, "I/O APIC"}, 547 {3, 8, "I/O INT"}, 548 {4, 8, "Local INT"} 549}; 550 551typedef struct BUSDATA { 552 u_char bus_id; 553 enum busTypes bus_type; 554} bus_datum; 555 556typedef struct INTDATA { 557 u_char int_type; 558 u_short int_flags; 559 u_char src_bus_id; 560 u_char src_bus_irq; 561 u_char dst_apic_id; 562 u_char dst_apic_int; 563} io_int, local_int; 564 565typedef struct BUSTYPENAME { 566 u_char type; 567 char name[7]; 568} bus_type_name; 569 570static bus_type_name bus_type_table[] = 571{ 572 {CBUS, "CBUS"}, 573 {CBUSII, "CBUSII"}, 574 {EISA, "EISA"}, 575 {UNKNOWN_BUSTYPE, "---"}, 576 {UNKNOWN_BUSTYPE, "---"}, 577 {ISA, "ISA"}, 578 {UNKNOWN_BUSTYPE, "---"}, 579 {UNKNOWN_BUSTYPE, "---"}, 580 {UNKNOWN_BUSTYPE, "---"}, 581 {UNKNOWN_BUSTYPE, "---"}, 582 {UNKNOWN_BUSTYPE, "---"}, 583 {UNKNOWN_BUSTYPE, "---"}, 584 {PCI, "PCI"}, 585 {UNKNOWN_BUSTYPE, "---"}, 586 {UNKNOWN_BUSTYPE, "---"}, 587 {UNKNOWN_BUSTYPE, "---"}, 588 {UNKNOWN_BUSTYPE, "---"}, 589 {XPRESS, "XPRESS"}, 590 {UNKNOWN_BUSTYPE, "---"} 591}; 592/* from MP spec v1.4, table 5-1 */ 593static int default_data[7][5] = 594{ 595/* nbus, id0, type0, id1, type1 */ 596 {1, 0, ISA, 255, 255}, 597 {1, 0, EISA, 255, 255}, 598 {1, 0, EISA, 255, 255}, 599 {0, 255, 255, 255, 255},/* MCA not supported */ 600 {2, 0, ISA, 1, PCI}, 601 {2, 0, EISA, 1, PCI}, 602 {0, 255, 255, 255, 255} /* MCA not supported */ 603}; 604 605 606/* the bus data */ 607bus_datum bus_data[NBUS]; 608 609/* the IO INT data, one entry per possible APIC INTerrupt */ 610io_int io_apic_ints[NINTR]; 611 612static int nintrs; 613 614static void fix_mp_table __P((void)); 615static int processor_entry __P((proc_entry_ptr entry, int cpu)); 616static int bus_entry __P((bus_entry_ptr entry, int bus)); 617static int io_apic_entry __P((io_apic_entry_ptr entry, int apic)); 618static int int_entry __P((int_entry_ptr entry, int intr)); 619static int lookup_bus_type __P((char *name)); 620 621 622/* 623 * 1st pass on motherboard's Intel MP specification table. 624 * 625 * initializes: 626 * mp_ncpus = 1 627 * 628 * determines: 629 * cpu_apic_address (common to all CPUs) 630 * io_apic_address[N] 631 * mp_naps 632 * mp_nbusses 633 * mp_napics 634 * nintrs 635 */ 636static int 637mptable_pass1(void) 638{ 639 int x; 640 mpcth_t cth; 641 int totalSize; 642 void* position; 643 int count; 644 int type; 645 int mustpanic; 646 647 POSTCODE(MPTABLE_PASS1_POST); 648 649 mustpanic = 0; 650 651 /* clear various tables */ 652 for (x = 0; x < NAPICID; ++x) { 653 io_apic_address[x] = ~0; /* IO APIC address table */ 654 } 655 656 /* init everything to empty */ 657 mp_naps = 0; 658 mp_nbusses = 0; 659 mp_napics = 0; 660 nintrs = 0; 661 662 /* check for use of 'default' configuration */ 663 if (mpfps->mpfb1 != 0) { 664 /* use default addresses */ 665 cpu_apic_address = DEFAULT_APIC_BASE; 666 io_apic_address[0] = DEFAULT_IO_APIC_BASE; 667 668 /* fill in with defaults */ 669 mp_naps = 2; /* includes BSP */ 670 mp_nbusses = default_data[mpfps->mpfb1 - 1][0]; 671#if defined(APIC_IO) 672 mp_napics = 1; 673 nintrs = 16; 674#endif /* APIC_IO */ 675 } 676 else { 677 if ((cth = mpfps->pap) == 0) 678 panic("MP Configuration Table Header MISSING!"); 679 680 cpu_apic_address = (vm_offset_t) cth->apic_address; 681 682 /* walk the table, recording info of interest */ 683 totalSize = cth->base_table_length - sizeof(struct MPCTH); 684 position = (u_char *) cth + sizeof(struct MPCTH); 685 count = cth->entry_count; 686 687 while (count--) { 688 switch (type = *(u_char *) position) { 689 case 0: /* processor_entry */ 690 if (((proc_entry_ptr)position)->cpu_flags 691 & PROCENTRY_FLAG_EN) 692 ++mp_naps; 693 break; 694 case 1: /* bus_entry */ 695 ++mp_nbusses; 696 break; 697 case 2: /* io_apic_entry */ 698 if (((io_apic_entry_ptr)position)->apic_flags 699 & IOAPICENTRY_FLAG_EN) 700 io_apic_address[mp_napics++] = 701 (vm_offset_t)((io_apic_entry_ptr) 702 position)->apic_address; 703 break; 704 case 3: /* int_entry */ 705 ++nintrs; 706 break; 707 case 4: /* int_entry */ 708 break; 709 default: 710 panic("mpfps Base Table HOSED!"); 711 /* NOTREACHED */ 712 } 713 714 totalSize -= basetable_entry_types[type].length; 715 (u_char*)position += basetable_entry_types[type].length; 716 } 717 } 718 719 /* qualify the numbers */ 720 if (mp_naps > NCPU) 721 printf("Warning: only using %d of %d available CPUs!\n", 722 NCPU, mp_naps); 723#if 0 724 /** XXX we consider this legal now (but should we?) */ 725 mustpanic = 1; 726#endif 727 if (mp_nbusses > NBUS) { 728 printf("found %d busses, increase NBUS\n", mp_nbusses); 729 mustpanic = 1; 730 } 731 if (mp_napics > NAPIC) { 732 printf("found %d apics, increase NAPIC\n", mp_napics); 733 mustpanic = 1; 734 } 735 if (nintrs > NINTR) { 736 printf("found %d intrs, increase NINTR\n", nintrs); 737 mustpanic = 1; 738 } 739 740 /* 741 * Count the BSP. 742 * This is also used as a counter while starting the APs. 743 */ 744 mp_ncpus = 1; 745 746 --mp_naps; /* subtract the BSP */ 747 748 return mustpanic; 749} 750 751 752/* 753 * 2nd pass on motherboard's Intel MP specification table. 754 * 755 * sets: 756 * boot_cpu_id 757 * ID_TO_IO(N), phy APIC ID to log CPU/IO table 758 * CPU_TO_ID(N), logical CPU to APIC ID table 759 * IO_TO_ID(N), logical IO to APIC ID table 760 * bus_data[N] 761 * io_apic_ints[N] 762 */ 763static int 764mptable_pass2(void) 765{ 766 int x; 767 mpcth_t cth; 768 int totalSize; 769 void* position; 770 int count; 771 int type; 772 int apic, bus, cpu, intr; 773 774 POSTCODE(MPTABLE_PASS2_POST); 775 776 /* clear various tables */ 777 for (x = 0; x < NAPICID; ++x) { 778 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */ 779 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */ 780 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */ 781 } 782 783 /* clear bus data table */ 784 for (x = 0; x < NBUS; ++x) 785 bus_data[x].bus_id = 0xff; 786 787 /* clear IO APIC INT table */ 788 for (x = 0; x < NINTR; ++x) 789 io_apic_ints[x].int_type = 0xff; 790 791 /* setup the cpu/apic mapping arrays */ 792 boot_cpu_id = -1; 793 794 /* record whether PIC or virtual-wire mode */ 795 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0; 796 797 /* check for use of 'default' configuration */ 798#if defined(TEST_DEFAULT_CONFIG) 799 return TEST_DEFAULT_CONFIG; 800#else 801 if (mpfps->mpfb1 != 0) 802 return mpfps->mpfb1; /* return default configuration type */ 803#endif /* TEST_DEFAULT_CONFIG */ 804 805 if ((cth = mpfps->pap) == 0) 806 panic("MP Configuration Table Header MISSING!"); 807 808 /* walk the table, recording info of interest */ 809 totalSize = cth->base_table_length - sizeof(struct MPCTH); 810 position = (u_char *) cth + sizeof(struct MPCTH); 811 count = cth->entry_count; 812 apic = bus = intr = 0; 813 cpu = 1; /* pre-count the BSP */ 814 815 while (count--) { 816 switch (type = *(u_char *) position) { 817 case 0: 818 if (processor_entry(position, cpu)) 819 ++cpu; 820 break; 821 case 1: 822 if (bus_entry(position, bus)) 823 ++bus; 824 break; 825 case 2: 826 if (io_apic_entry(position, apic)) 827 ++apic; 828 break; 829 case 3: 830 if (int_entry(position, intr)) 831 ++intr; 832 break; 833 case 4: 834 /* int_entry(position); */ 835 break; 836 default: 837 panic("mpfps Base Table HOSED!"); 838 /* NOTREACHED */ 839 } 840 841 totalSize -= basetable_entry_types[type].length; 842 (u_char *) position += basetable_entry_types[type].length; 843 } 844 845 if (boot_cpu_id == -1) 846 panic("NO BSP found!"); 847 848 /* post scan cleanup */ 849 fix_mp_table(); 850 851 /* report fact that its NOT a default configuration */ 852 return 0; 853} 854 855 856/* 857 * parse an Intel MP specification table 858 */ 859static void 860fix_mp_table(void) 861{ 862 int x; 863 int id; 864 int bus_0; 865 int bus_pci; 866 int num_pci_bus; 867 868 /* 869 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS 870 * did it wrong. The MP spec says that when more than 1 PCI bus 871 * exists the BIOS must begin with bus entries for the PCI bus and use 872 * actual PCI bus numbering. This implies that when only 1 PCI bus 873 * exists the BIOS can choose to ignore this ordering, and indeed many 874 * MP motherboards do ignore it. This causes a problem when the PCI 875 * sub-system makes requests of the MP sub-system based on PCI bus 876 * numbers. So here we look for the situation and renumber the 877 * busses and associated INTs in an effort to "make it right". 878 */ 879 880 /* find bus 0, PCI bus, count the number of PCI busses */ 881 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { 882 if (bus_data[x].bus_id == 0) { 883 bus_0 = x; 884 } 885 if (bus_data[x].bus_type == PCI) { 886 ++num_pci_bus; 887 bus_pci = x; 888 } 889 } 890 /* 891 * bus_0 == slot of bus with ID of 0 892 * bus_pci == slot of last PCI bus encountered 893 */ 894 895 /* check the 1 PCI bus case for sanity */ 896 if (num_pci_bus == 1) { 897 898 /* if it is number 0 all is well */ 899 if (bus_data[bus_pci].bus_id == 0) 900 return; 901 902 /* mis-numbered, swap with whichever bus uses slot 0 */ 903 904 /* swap the bus entry types */ 905 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type; 906 bus_data[bus_0].bus_type = PCI; 907 908 /* swap each relavant INTerrupt entry */ 909 id = bus_data[bus_pci].bus_id; 910 for (x = 0; x < nintrs; ++x) { 911 if (io_apic_ints[x].src_bus_id == id) { 912 io_apic_ints[x].src_bus_id = 0; 913 } 914 else if (io_apic_ints[x].src_bus_id == 0) { 915 io_apic_ints[x].src_bus_id = id; 916 } 917 } 918 } 919 /* sanity check if more than 1 PCI bus */ 920 else if (num_pci_bus > 1) { 921 for (x = 0; x < mp_nbusses; ++x) { 922 if (bus_data[x].bus_type != PCI) 923 continue; 924 if (bus_data[x].bus_id >= num_pci_bus) 925 panic("bad PCI bus numbering"); 926 } 927 } 928} 929 930 931static int 932processor_entry(proc_entry_ptr entry, int cpu) 933{ 934 /* check for usability */ 935 if ((cpu >= NCPU) || !(entry->cpu_flags & PROCENTRY_FLAG_EN)) 936 return 0; 937 938 /* check for BSP flag */ 939 if (entry->cpu_flags & PROCENTRY_FLAG_BP) { 940 boot_cpu_id = entry->apic_id; 941 CPU_TO_ID(0) = entry->apic_id; 942 ID_TO_CPU(entry->apic_id) = 0; 943 return 0; /* its already been counted */ 944 } 945 946 /* add another AP to list, if less than max number of CPUs */ 947 else { 948 CPU_TO_ID(cpu) = entry->apic_id; 949 ID_TO_CPU(entry->apic_id) = cpu; 950 return 1; 951 } 952} 953 954 955static int 956bus_entry(bus_entry_ptr entry, int bus) 957{ 958 int x; 959 char c, name[8]; 960 961 /* encode the name into an index */ 962 for (x = 0; x < 6; ++x) { 963 if ((c = entry->bus_type[x]) == ' ') 964 break; 965 name[x] = c; 966 } 967 name[x] = '\0'; 968 969 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) 970 panic("unknown bus type: '%s'", name); 971 972 bus_data[bus].bus_id = entry->bus_id; 973 bus_data[bus].bus_type = x; 974 975 return 1; 976} 977 978 979static int 980io_apic_entry(io_apic_entry_ptr entry, int apic) 981{ 982 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) 983 return 0; 984 985 IO_TO_ID(apic) = entry->apic_id; 986 ID_TO_IO(entry->apic_id) = apic; 987 988 return 1; 989} 990 991 992static int 993lookup_bus_type(char *name) 994{ 995 int x; 996 997 for (x = 0; x < MAX_BUSTYPE; ++x) 998 if (strcmp(bus_type_table[x].name, name) == 0) 999 return bus_type_table[x].type; 1000 1001 return UNKNOWN_BUSTYPE; 1002} 1003 1004 1005static int 1006int_entry(int_entry_ptr entry, int intr) 1007{ 1008 io_apic_ints[intr].int_type = entry->int_type; 1009 io_apic_ints[intr].int_flags = entry->int_flags; 1010 io_apic_ints[intr].src_bus_id = entry->src_bus_id; 1011 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq; 1012 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; 1013 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int; 1014 1015 return 1; 1016} 1017 1018 1019static int 1020apic_int_is_bus_type(int intr, int bus_type) 1021{ 1022 int bus; 1023 1024 for (bus = 0; bus < mp_nbusses; ++bus) 1025 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) 1026 && ((int) bus_data[bus].bus_type == bus_type)) 1027 return 1; 1028 1029 return 0; 1030} 1031 1032 1033/* 1034 * Given a traditional ISA INT mask, return an APIC mask. 1035 */ 1036u_int 1037isa_apic_mask(u_int isa_mask) 1038{ 1039 int isa_irq; 1040 int apic_pin; 1041 1042#if defined(SKIP_IRQ15_REDIRECT) 1043 if (isa_mask == (1 << 15)) { 1044 printf("skipping ISA IRQ15 redirect\n"); 1045 return isa_mask; 1046 } 1047#endif /* SKIP_IRQ15_REDIRECT */ 1048 1049 isa_irq = ffs(isa_mask); /* find its bit position */ 1050 if (isa_irq == 0) /* doesn't exist */ 1051 return 0; 1052 --isa_irq; /* make it zero based */ 1053 1054 apic_pin = isa_apic_pin(isa_irq); /* look for APIC connection */ 1055 if (apic_pin == -1) 1056 return 0; 1057 1058 return (1 << apic_pin); /* convert pin# to a mask */ 1059} 1060 1061 1062/* 1063 * Determine which APIC pin an ISA/EISA INT is attached to. 1064 */ 1065#define INTTYPE(I) (io_apic_ints[(I)].int_type) 1066#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) 1067 1068#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) 1069int 1070isa_apic_pin(int isa_irq) 1071{ 1072 int intr; 1073 1074#if defined(SMP_TIMER_NC) 1075 if (isa_irq == 0) 1076 return -1; 1077#endif /* SMP_TIMER_NC */ 1078 1079 for (intr = 0; intr < nintrs; ++intr) { /* check each record */ 1080 if (INTTYPE(intr) == 0) { /* standard INT */ 1081 if (SRCBUSIRQ(intr) == isa_irq) { 1082 if (apic_int_is_bus_type(intr, ISA) || 1083 apic_int_is_bus_type(intr, EISA)) 1084 return INTPIN(intr); /* found */ 1085 } 1086 } 1087 } 1088 return -1; /* NOT found */ 1089} 1090#undef SRCBUSIRQ 1091 1092 1093/* 1094 * Determine which APIC pin a PCI INT is attached to. 1095 */ 1096#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) 1097#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) 1098#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) 1099int 1100pci_apic_pin(int pciBus, int pciDevice, int pciInt) 1101{ 1102 int intr; 1103 1104 --pciInt; /* zero based */ 1105 1106 for (intr = 0; intr < nintrs; ++intr) /* check each record */ 1107 if ((INTTYPE(intr) == 0) /* standard INT */ 1108 && (SRCBUSID(intr) == pciBus) 1109 && (SRCBUSDEVICE(intr) == pciDevice) 1110 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ 1111 if (apic_int_is_bus_type(intr, PCI)) 1112 return INTPIN(intr); /* exact match */ 1113 1114 return -1; /* NOT found */ 1115} 1116#undef SRCBUSLINE 1117#undef SRCBUSDEVICE 1118#undef SRCBUSID 1119 1120#undef INTPIN 1121#undef INTTYPE 1122 1123 1124/* 1125 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt. 1126 * 1127 * XXX FIXME: 1128 * Exactly what this means is unclear at this point. It is a solution 1129 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard 1130 * could route any of the ISA INTs to upper (>15) IRQ values. But most would 1131 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an 1132 * option. 1133 */ 1134int 1135undirect_isa_irq(int rirq) 1136{ 1137#if defined(READY) 1138 printf("Freeing redirected ISA irq %d.\n", rirq); 1139 /** FIXME: tickle the MB redirector chip */ 1140 return ???; 1141#else 1142 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq); 1143 return 0; 1144#endif /* READY */ 1145} 1146 1147 1148/* 1149 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt 1150 */ 1151int 1152undirect_pci_irq(int rirq) 1153{ 1154#if defined(READY) 1155 if (bootverbose) 1156 printf("Freeing redirected PCI irq %d.\n", rirq); 1157 1158 /** FIXME: tickle the MB redirector chip */ 1159 return ???; 1160#else 1161 if (bootverbose) 1162 printf("Freeing (NOT implemented) redirected PCI irq %d.\n", 1163 rirq); 1164 return 0; 1165#endif /* READY */ 1166} 1167 1168 1169/* 1170 * given a bus ID, return: 1171 * the bus type if found 1172 * -1 if NOT found 1173 */ 1174int 1175apic_bus_type(int id) 1176{ 1177 int x; 1178 1179 for (x = 0; x < mp_nbusses; ++x) 1180 if (bus_data[x].bus_id == id) 1181 return bus_data[x].bus_type; 1182 1183 return -1; 1184} 1185 1186 1187/* 1188 * given a LOGICAL APIC# and pin#, return: 1189 * the associated src bus ID if found 1190 * -1 if NOT found 1191 */ 1192int 1193apic_src_bus_id(int apic, int pin) 1194{ 1195 int x; 1196 1197 /* search each of the possible INTerrupt sources */ 1198 for (x = 0; x < nintrs; ++x) 1199 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1200 (pin == io_apic_ints[x].dst_apic_int)) 1201 return (io_apic_ints[x].src_bus_id); 1202 1203 return -1; /* NOT found */ 1204} 1205 1206 1207/* 1208 * given a LOGICAL APIC# and pin#, return: 1209 * the associated src bus IRQ if found 1210 * -1 if NOT found 1211 */ 1212int 1213apic_src_bus_irq(int apic, int pin) 1214{ 1215 int x; 1216 1217 for (x = 0; x < nintrs; x++) 1218 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1219 (pin == io_apic_ints[x].dst_apic_int)) 1220 return (io_apic_ints[x].src_bus_irq); 1221 1222 return -1; /* NOT found */ 1223} 1224 1225 1226/* 1227 * given a LOGICAL APIC# and pin#, return: 1228 * the associated INTerrupt type if found 1229 * -1 if NOT found 1230 */ 1231int 1232apic_int_type(int apic, int pin) 1233{ 1234 int x; 1235 1236 /* search each of the possible INTerrupt sources */ 1237 for (x = 0; x < nintrs; ++x) 1238 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1239 (pin == io_apic_ints[x].dst_apic_int)) 1240 return (io_apic_ints[x].int_type); 1241 1242 return -1; /* NOT found */ 1243} 1244 1245 1246/* 1247 * given a LOGICAL APIC# and pin#, return: 1248 * the associated trigger mode if found 1249 * -1 if NOT found 1250 */ 1251int 1252apic_trigger(int apic, int pin) 1253{ 1254 int x; 1255 1256 /* search each of the possible INTerrupt sources */ 1257 for (x = 0; x < nintrs; ++x) 1258 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1259 (pin == io_apic_ints[x].dst_apic_int)) 1260 return ((io_apic_ints[x].int_flags >> 2) & 0x03); 1261 1262 return -1; /* NOT found */ 1263} 1264 1265 1266/* 1267 * given a LOGICAL APIC# and pin#, return: 1268 * the associated 'active' level if found 1269 * -1 if NOT found 1270 */ 1271int 1272apic_polarity(int apic, int pin) 1273{ 1274 int x; 1275 1276 /* search each of the possible INTerrupt sources */ 1277 for (x = 0; x < nintrs; ++x) 1278 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1279 (pin == io_apic_ints[x].dst_apic_int)) 1280 return (io_apic_ints[x].int_flags & 0x03); 1281 1282 return -1; /* NOT found */ 1283} 1284 1285 1286/* 1287 * set data according to MP defaults 1288 * FIXME: probably not complete yet... 1289 */ 1290static void 1291default_mp_table(int type) 1292{ 1293 int ap_cpu_id; 1294#if defined(APIC_IO) 1295 u_int32_t ux; 1296 int io_apic_id; 1297 int pin; 1298#endif /* APIC_IO */ 1299 1300#if 0 1301 printf(" MP default config type: %d\n", type); 1302 switch (type) { 1303 case 1: 1304 printf(" bus: ISA, APIC: 82489DX\n"); 1305 break; 1306 case 2: 1307 printf(" bus: EISA, APIC: 82489DX\n"); 1308 break; 1309 case 3: 1310 printf(" bus: EISA, APIC: 82489DX\n"); 1311 break; 1312 case 4: 1313 printf(" bus: MCA, APIC: 82489DX\n"); 1314 break; 1315 case 5: 1316 printf(" bus: ISA+PCI, APIC: Integrated\n"); 1317 break; 1318 case 6: 1319 printf(" bus: EISA+PCI, APIC: Integrated\n"); 1320 break; 1321 case 7: 1322 printf(" bus: MCA+PCI, APIC: Integrated\n"); 1323 break; 1324 default: 1325 printf(" future type\n"); 1326 break; 1327 /* NOTREACHED */ 1328 } 1329#endif /* 0 */ 1330 1331 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24; 1332 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; 1333 1334 /* BSP */ 1335 CPU_TO_ID(0) = boot_cpu_id; 1336 ID_TO_CPU(boot_cpu_id) = 0; 1337 1338 /* one and only AP */ 1339 CPU_TO_ID(1) = ap_cpu_id; 1340 ID_TO_CPU(ap_cpu_id) = 1; 1341 1342#if defined(APIC_IO) 1343 /* one and only IO APIC */ 1344 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; 1345 1346 /* 1347 * sanity check, refer to MP spec section 3.6.6, last paragraph 1348 * necessary as some hardware isn't properly setting up the IO APIC 1349 */ 1350#if defined(REALLY_ANAL_IOAPICID_VALUE) 1351 if (io_apic_id != 2) { 1352#else 1353 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { 1354#endif /* REALLY_ANAL_IOAPICID_VALUE */ 1355 ux = io_apic_read(0, IOAPIC_ID); /* get current contents */ 1356 ux &= ~APIC_ID_MASK; /* clear the ID field */ 1357 ux |= 0x02000000; /* set it to '2' */ 1358 io_apic_write(0, IOAPIC_ID, ux); /* write new value */ 1359 ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */ 1360 if ((ux & APIC_ID_MASK) != 0x02000000) 1361 panic("can't control IO APIC ID, reg: 0x%08x", ux); 1362 io_apic_id = 2; 1363 } 1364 IO_TO_ID(0) = io_apic_id; 1365 ID_TO_IO(io_apic_id) = 0; 1366#endif /* APIC_IO */ 1367 1368 /* fill out bus entries */ 1369 switch (type) { 1370 case 1: 1371 case 2: 1372 case 3: 1373 case 5: 1374 case 6: 1375 bus_data[0].bus_id = default_data[type - 1][1]; 1376 bus_data[0].bus_type = default_data[type - 1][2]; 1377 bus_data[1].bus_id = default_data[type - 1][3]; 1378 bus_data[1].bus_type = default_data[type - 1][4]; 1379 break; 1380 1381 /* case 4: case 7: MCA NOT supported */ 1382 default: /* illegal/reserved */ 1383 panic("BAD default MP config: %d", type); 1384 /* NOTREACHED */ 1385 } 1386 1387#if defined(APIC_IO) 1388 /* general cases from MP v1.4, table 5-2 */ 1389 for (pin = 0; pin < 16; ++pin) { 1390 io_apic_ints[pin].int_type = 0; 1391 io_apic_ints[pin].int_flags = 0x05; /* edge-triggered/active-hi */ 1392 io_apic_ints[pin].src_bus_id = 0; 1393 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 is caught below */ 1394 io_apic_ints[pin].dst_apic_id = io_apic_id; 1395 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 correspondence */ 1396 } 1397 1398 /* special cases from MP v1.4, table 5-2 */ 1399 if (type == 2) { 1400 io_apic_ints[2].int_type = 0xff; /* N/C */ 1401 io_apic_ints[13].int_type = 0xff; /* N/C */ 1402#if !defined(APIC_MIXED_MODE) 1403 /** FIXME: ??? */ 1404 panic("sorry, can't support type 2 default yet"); 1405#endif /* APIC_MIXED_MODE */ 1406 } 1407 else 1408 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ 1409 1410 if (type == 7) 1411 io_apic_ints[0].int_type = 0xff; /* N/C */ 1412 else 1413 io_apic_ints[0].int_type = 3; /* vectored 8259 */ 1414#endif /* APIC_IO */ 1415} 1416 1417 1418/* 1419 * start each AP in our list 1420 */ 1421static int 1422start_all_aps(u_int boot_addr) 1423{ 1424 int x, i; 1425 u_char mpbiosreason; 1426 u_long mpbioswarmvec; 1427 pd_entry_t newptd; 1428 pt_entry_t newpt; 1429 int *newpp; 1430 1431 POSTCODE(START_ALL_APS_POST); 1432 1433 /** 1434 * NOTE: this needs further thought: 1435 * where does it get released? 1436 * should it be set to empy? 1437 * 1438 * get the initial mp_lock with a count of 1 for the BSP 1439 */ 1440 mp_lock = 1; /* this uses a LOGICAL cpu ID, ie BSP == 0 */ 1441 1442 /* initialize BSP's local APIC */ 1443 apic_initialize(); 1444 1445 /* install the AP 1st level boot code */ 1446 install_ap_tramp(boot_addr); 1447 1448 1449 /* save the current value of the warm-start vector */ 1450 mpbioswarmvec = *((u_long *) WARMBOOT_OFF); 1451 outb(CMOS_REG, BIOS_RESET); 1452 mpbiosreason = inb(CMOS_DATA); 1453 1454 /* record BSP in CPU map */ 1455 all_cpus = 1; 1456 1457 /* start each AP */ 1458 for (x = 1; x <= mp_naps; ++x) { 1459 1460 /* HACK HACK HACK !!! */ 1461 1462 /* alloc new page table directory */ 1463 newptd = (pd_entry_t)(kmem_alloc(kernel_map, PAGE_SIZE)); 1464 1465 /* clone currently active one (ie: IdlePTD) */ 1466 bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */ 1467 1468 /* set up 0 -> 4MB P==V mapping for AP boot */ 1469 newptd[0] = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME); 1470 1471 /* store PTD for this AP */ 1472 bootPTD = (pd_entry_t)vtophys(newptd); 1473 1474 /* alloc new page table page */ 1475 newpt = (pt_entry_t)(kmem_alloc(kernel_map, PAGE_SIZE)); 1476 1477 /* set the new PTD's private page to point there */ 1478 newptd[MPPTDI] = PG_V | PG_RW | vtophys(newpt); 1479 1480 /* install self referential entry */ 1481 newptd[PTDPTDI] = PG_V | PG_RW | vtophys(newptd); 1482 1483 /* get a new private data page */ 1484 newpp = (int *)kmem_alloc(kernel_map, PAGE_SIZE); 1485 1486 /* wire it into the private page table page */ 1487 newpt[0] = PG_V | PG_RW | vtophys(newpp); 1488 1489 /* wire the ptp into itself for access */ 1490 newpt[1] = PG_V | PG_RW | vtophys(newpt); 1491 1492 /* and the local apic */ 1493 newpt[2] = SMP_prvpt[2]; 1494 1495 /* and the IO apic mapping[s] */ 1496 for (i = 16; i < 32; i++) 1497 newpt[i] = SMP_prvpt[i]; 1498 1499 /* prime data page for it to use */ 1500 newpp[0] = x; /* cpuid */ 1501 newpp[1] = 0; /* curproc */ 1502 newpp[2] = 0; /* curpcb */ 1503 newpp[3] = 0; /* npxproc */ 1504 newpp[4] = 0; /* runtime.tv_sec */ 1505 newpp[5] = 0; /* runtime.tv_usec */ 1506 newpp[6] = x << 24; /* cpu_lockid */ 1507 1508 /* XXX NOTE: ABANDON bootPTD for now!!!! */ 1509 1510 /* END REVOLTING HACKERY */ 1511 1512 /* setup a vector to our boot code */ 1513 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 1514 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); 1515 outb(CMOS_REG, BIOS_RESET); 1516 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 1517 1518 /* attempt to start the Application Processor */ 1519 CHECK_INIT(99); /* setup checkpoints */ 1520 if (!start_ap(x, boot_addr)) { 1521 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); 1522 CHECK_PRINT("trace"); /* show checkpoints */ 1523 /* better panic as the AP may be running loose */ 1524 printf("panic y/n? [y] "); 1525 if (cngetc() != 'n') 1526 panic("bye-bye"); 1527 } 1528 CHECK_PRINT("trace"); /* show checkpoints */ 1529 1530 /* record its version info */ 1531 cpu_apic_versions[x] = cpu_apic_versions[0]; 1532 1533 all_cpus |= (1 << x); /* record AP in CPU map */ 1534 } 1535 1536 /* build our map of 'other' CPUs */ 1537 other_cpus = all_cpus & ~(1 << cpuid); 1538 1539 /* fill in our (BSP) APIC version */ 1540 cpu_apic_versions[0] = lapic.version; 1541 1542 /* restore the warmstart vector */ 1543 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 1544 outb(CMOS_REG, BIOS_RESET); 1545 outb(CMOS_DATA, mpbiosreason); 1546 1547 /* number of APs actually started */ 1548 return mp_ncpus - 1; 1549} 1550 1551 1552/* 1553 * load the 1st level AP boot code into base memory. 1554 */ 1555 1556/* targets for relocation */ 1557extern void bigJump(void); 1558extern void bootCodeSeg(void); 1559extern void bootDataSeg(void); 1560extern void MPentry(void); 1561extern u_int MP_GDT; 1562extern u_int mp_gdtbase; 1563 1564static void 1565install_ap_tramp(u_int boot_addr) 1566{ 1567 int x; 1568 int size = *(int *) ((u_long) & bootMP_size); 1569 u_char *src = (u_char *) ((u_long) bootMP); 1570 u_char *dst = (u_char *) boot_addr + KERNBASE; 1571 u_int boot_base = (u_int) bootMP; 1572 u_int8_t *dst8; 1573 u_int16_t *dst16; 1574 u_int32_t *dst32; 1575 1576 POSTCODE(INSTALL_AP_TRAMP_POST); 1577 1578 for (x = 0; x < size; ++x) 1579 *dst++ = *src++; 1580 1581 /* 1582 * modify addresses in code we just moved to basemem. unfortunately we 1583 * need fairly detailed info about mpboot.s for this to work. changes 1584 * to mpboot.s might require changes here. 1585 */ 1586 1587 /* boot code is located in KERNEL space */ 1588 dst = (u_char *) boot_addr + KERNBASE; 1589 1590 /* modify the lgdt arg */ 1591 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 1592 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); 1593 1594 /* modify the ljmp target for MPentry() */ 1595 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 1596 *dst32 = ((u_int) MPentry - KERNBASE); 1597 1598 /* modify the target for boot code segment */ 1599 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 1600 dst8 = (u_int8_t *) (dst16 + 1); 1601 *dst16 = (u_int) boot_addr & 0xffff; 1602 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1603 1604 /* modify the target for boot data segment */ 1605 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 1606 dst8 = (u_int8_t *) (dst16 + 1); 1607 *dst16 = (u_int) boot_addr & 0xffff; 1608 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1609} 1610 1611 1612/* 1613 * this function starts the AP (application processor) identified 1614 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 1615 * to accomplish this. This is necessary because of the nuances 1616 * of the different hardware we might encounter. It ain't pretty, 1617 * but it seems to work. 1618 */ 1619static int 1620start_ap(int logical_cpu, u_int boot_addr) 1621{ 1622 int physical_cpu; 1623 int vector; 1624 int cpus; 1625 u_long icr_lo, icr_hi; 1626 1627 POSTCODE(START_AP_POST); 1628 1629 /* get the PHYSICAL APIC ID# */ 1630 physical_cpu = CPU_TO_ID(logical_cpu); 1631 1632 /* calculate the vector */ 1633 vector = (boot_addr >> 12) & 0xff; 1634 1635 /* used as a watchpoint to signal AP startup */ 1636 cpus = mp_ncpus; 1637 1638 /* 1639 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 1640 * and running the target CPU. OR this INIT IPI might be latched (P5 1641 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 1642 * ignored. 1643 */ 1644 1645 /* setup the address for the target AP */ 1646 icr_hi = lapic.icr_hi & ~APIC_ID_MASK; 1647 icr_hi |= (physical_cpu << 24); 1648 lapic.icr_hi = icr_hi; 1649 1650 /* do an INIT IPI: assert RESET */ 1651 icr_lo = lapic.icr_lo & 0xfff00000; 1652 lapic.icr_lo = icr_lo | 0x0000c500; 1653 1654 /* wait for pending status end */ 1655 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1656 /* spin */ ; 1657 1658 /* do an INIT IPI: deassert RESET */ 1659 lapic.icr_lo = icr_lo | 0x00008500; 1660 1661 /* wait for pending status end */ 1662 u_sleep(10000); /* wait ~10mS */ 1663 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1664 /* spin */ ; 1665 1666 /* 1667 * next we do a STARTUP IPI: the previous INIT IPI might still be 1668 * latched, (P5 bug) this 1st STARTUP would then terminate 1669 * immediately, and the previously started INIT IPI would continue. OR 1670 * the previous INIT IPI has already run. and this STARTUP IPI will 1671 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 1672 * will run. 1673 */ 1674 1675 /* do a STARTUP IPI */ 1676 lapic.icr_lo = icr_lo | 0x00000600 | vector; 1677 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1678 /* spin */ ; 1679 u_sleep(200); /* wait ~200uS */ 1680 1681 /* 1682 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 1683 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 1684 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 1685 * recognized after hardware RESET or INIT IPI. 1686 */ 1687 1688 lapic.icr_lo = icr_lo | 0x00000600 | vector; 1689 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1690 /* spin */ ; 1691 u_sleep(200); /* wait ~200uS */ 1692 1693 /* wait for it to start */ 1694 set_apic_timer(5000000);/* == 5 seconds */ 1695 while (read_apic_timer()) 1696 if (mp_ncpus > cpus) 1697 return 1; /* return SUCCESS */ 1698 1699 return 0; /* return FAILURE */ 1700} 1701 1702 1703/* 1704 * Flush the TLB on all other CPU's 1705 * 1706 * XXX: Needs to handshake and wait for completion before proceding. 1707 */ 1708void 1709smp_invltlb(void) 1710{ 1711#if defined(APIC_IO) 1712 if (smp_active && invltlb_ok) 1713 all_but_self_ipi(XINVLTLB_OFFSET); 1714#endif /* APIC_IO */ 1715} 1716 1717void 1718invlpg(u_int addr) 1719{ 1720 __asm __volatile("invlpg (%0)"::"r"(addr):"memory"); 1721 1722 /* send a message to the other CPUs */ 1723 smp_invltlb(); 1724} 1725 1726void 1727invltlb(void) 1728{ 1729 u_long temp; 1730 1731 /* 1732 * This should be implemented as load_cr3(rcr3()) when load_cr3() is 1733 * inlined. 1734 */ 1735 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory"); 1736 1737 /* send a message to the other CPUs */ 1738 smp_invltlb(); 1739} 1740 1741 1742#if defined(TEST_CPUSTOP) 1743 1744/* 1745 * When called the executing CPU will send an IPI to all other CPUs 1746 * requesting that they halt execution. 1747 * 1748 * Usually (but not necessarily) called with 'other_cpus' as its arg. 1749 * 1750 * - Signals all CPUs in map to stop. 1751 * - Waits for each to stop. 1752 * 1753 * Returns: 1754 * -1: error 1755 * 0: NA 1756 * 1: ok 1757 * 1758 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs 1759 * from executing at same time. 1760 1761 */ 1762extern int cshits[4]; 1763extern int lhits[4]; 1764extern int sihits; 1765int 1766stop_cpus( u_int map ) 1767{ 1768#if 1 1769 int x, y; 1770#endif 1771 if (!smp_active) 1772 return 0; 1773 1774 /* send IPI to all CPUs in map */ 1775#if defined(DEBUG_CPUSTOP) 1776#if 0 1777 POSTCODE(0xF0); 1778#endif 1779 db_printf("\nCPU%d stopping CPUs: 0x%08x\n", cpuid, map); 1780 db_printf("b4 stop: cshits: %d, %d, mplock: 0x%08x, lhits: %d, %d, sihits: %d\n", 1781 cshits[0], cshits[1], mp_lock, lhits[0], lhits[1], sihits); 1782#endif /* DEBUG_CPUSTOP */ 1783 1784 stopped_cpus = 0; 1785#if 0 1786 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED); 1787#else 1788 all_but_self_ipi(XCPUSTOP_OFFSET); 1789#endif 1790 1791#if defined(DEBUG_CPUSTOP) 1792 db_printf(" spin\n"); 1793#endif /* DEBUG_CPUSTOP */ 1794 1795#if 0 /** */ 1796 y = 0; 1797 while (stopped_cpus != map) { 1798#if 0 1799 /* spin */ ; 1800#else 1801 POSTCODE_LO(stopped_cpus & 0x0f); 1802#define MAX_SPIN 20000000 1803 for ( x = 0; x < MAX_SPIN; ++x ) 1804 ; 1805 if (++y > 20) { 1806 stopped_cpus = map; 1807 break; 1808 } 1809 POSTCODE_LO(0x0f); 1810 for ( x = 0; x < MAX_SPIN; ++x ) 1811 ; 1812#endif 1813 } 1814#endif /** 0 */ 1815 1816#if defined(DEBUG_CPUSTOP) 1817 db_printf(" spun\nstopped, sihits: %d\n", sihits); 1818 cngetc(); 1819#endif /* DEBUG_CPUSTOP */ 1820 1821 return 1; 1822} 1823 1824 1825/* 1826 * Called by a CPU to restart stopped CPUs. 1827 * 1828 * Usually (but not necessarily) called with 'stopped_cpus' as its arg. 1829 * 1830 * - Signals all CPUs in map to restart. 1831 * - Waits for each to restart. 1832 * 1833 * Returns: 1834 * -1: error 1835 * 0: NA 1836 * 1: ok 1837 */ 1838int 1839restart_cpus( u_int map ) 1840{ 1841 if (!smp_active) 1842 return 0; 1843 1844#if defined(DEBUG_CPUSTOP) 1845#if 0 1846 POSTCODE(0x90); 1847#endif 1848 db_printf("\nCPU%d restarting CPUs: 0x%08x (0x%08x)\n", 1849 cpuid, map, stopped_cpus); 1850 db_printf("b4 restart: cshits: %d, %d, mplock: 0x%08x, lhits: %d, %d, sihits: %d\n", 1851 cshits[0], cshits[1], mp_lock, lhits[0], lhits[1], sihits); 1852#endif /* DEBUG_CPUSTOP */ 1853 1854 started_cpus = map; /* signal other cpus to restart */ 1855 1856#if 0 /** */ 1857 while (started_cpus) /* wait for each to clear its bit */ 1858 /* spin */ ; 1859#endif /** 0 */ 1860 1861#if defined(DEBUG_CPUSTOP) 1862#if 0 1863 POSTCODE(0xA0); 1864#endif 1865 db_printf(" restarted\n"); 1866#endif /* DEBUG_CPUSTOP */ 1867 1868 return 1; 1869} 1870 1871#endif /* TEST_CPUSTOP */ 1872