mptable.c revision 27005
1/* 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $Id: mp_machdep.c,v 1.22 1997/06/25 21:01:52 fsmp Exp $ 26 */ 27 28#include "opt_smp.h" 29 30#include <sys/param.h> /* for KERNBASE */ 31#include <sys/types.h> 32#include <sys/sysproto.h> 33#include <sys/time.h> 34#include <sys/systm.h> 35 36#include <vm/vm.h> /* for KERNBASE */ 37#include <vm/vm_param.h> /* for KERNBASE */ 38#include <vm/pmap.h> /* for KERNBASE */ 39#include <machine/pmap.h> /* for KERNBASE */ 40#include <vm/vm_kern.h> 41#include <vm/vm_extern.h> 42 43#include <machine/smp.h> 44#include <machine/apic.h> 45#include <machine/mpapic.h> 46#include <machine/cpufunc.h> 47#include <machine/segments.h> 48#include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_CPUSTOP */ 49#include <machine/tss.h> 50#include <machine/specialreg.h> 51 52#include <i386/i386/cons.h> /* cngetc() */ 53 54#if defined(APIC_IO) 55#include <machine/md_var.h> /* setidt() */ 56#include <i386/isa/icu.h> /* Xinvltlb() */ 57#include <i386/isa/intr_machdep.h> /* Xinvltlb() */ 58#endif /* APIC_IO */ 59 60#define WARMBOOT_TARGET 0 61#define WARMBOOT_OFF (KERNBASE + 0x0467) 62#define WARMBOOT_SEG (KERNBASE + 0x0469) 63 64#define BIOS_BASE (0xf0000) 65#define BIOS_SIZE (0x10000) 66#define BIOS_COUNT (BIOS_SIZE/4) 67 68#define CMOS_REG (0x70) 69#define CMOS_DATA (0x71) 70#define BIOS_RESET (0x0f) 71#define BIOS_WARM (0x0a) 72 73#define PROCENTRY_FLAG_EN 0x01 74#define PROCENTRY_FLAG_BP 0x02 75#define IOAPICENTRY_FLAG_EN 0x01 76 77 78/* MP Floating Pointer Structure */ 79typedef struct MPFPS { 80 char signature[4]; 81 void *pap; 82 u_char length; 83 u_char spec_rev; 84 u_char checksum; 85 u_char mpfb1; 86 u_char mpfb2; 87 u_char mpfb3; 88 u_char mpfb4; 89 u_char mpfb5; 90} *mpfps_t; 91 92/* MP Configuration Table Header */ 93typedef struct MPCTH { 94 char signature[4]; 95 u_short base_table_length; 96 u_char spec_rev; 97 u_char checksum; 98 u_char oem_id[8]; 99 u_char product_id[12]; 100 void *oem_table_pointer; 101 u_short oem_table_size; 102 u_short entry_count; 103 void *apic_address; 104 u_short extended_table_length; 105 u_char extended_table_checksum; 106 u_char reserved; 107} *mpcth_t; 108 109 110typedef struct PROCENTRY { 111 u_char type; 112 u_char apic_id; 113 u_char apic_version; 114 u_char cpu_flags; 115 u_long cpu_signature; 116 u_long feature_flags; 117 u_long reserved1; 118 u_long reserved2; 119} *proc_entry_ptr; 120 121typedef struct BUSENTRY { 122 u_char type; 123 u_char bus_id; 124 char bus_type[6]; 125} *bus_entry_ptr; 126 127typedef struct IOAPICENTRY { 128 u_char type; 129 u_char apic_id; 130 u_char apic_version; 131 u_char apic_flags; 132 void *apic_address; 133} *io_apic_entry_ptr; 134 135typedef struct INTENTRY { 136 u_char type; 137 u_char int_type; 138 u_short int_flags; 139 u_char src_bus_id; 140 u_char src_bus_irq; 141 u_char dst_apic_id; 142 u_char dst_apic_int; 143} *int_entry_ptr; 144 145/* descriptions of MP basetable entries */ 146typedef struct BASETABLE_ENTRY { 147 u_char type; 148 u_char length; 149 char name[16]; 150} basetable_entry; 151 152/* 153 * this code MUST be enabled here and in mpboot.s. 154 * it follows the very early stages of AP boot by placing values in CMOS ram. 155 * it NORMALLY will never be needed and thus the primitive method for enabling. 156 * 157#define CHECK_POINTS 158 */ 159 160#if defined(CHECK_POINTS) 161#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 162#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 163 164#define CHECK_INIT(D); \ 165 CHECK_WRITE(0x34, (D)); \ 166 CHECK_WRITE(0x35, (D)); \ 167 CHECK_WRITE(0x36, (D)); \ 168 CHECK_WRITE(0x37, (D)); \ 169 CHECK_WRITE(0x38, (D)); \ 170 CHECK_WRITE(0x39, (D)); 171 172#define CHECK_PRINT(S); \ 173 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 174 (S), \ 175 CHECK_READ(0x34), \ 176 CHECK_READ(0x35), \ 177 CHECK_READ(0x36), \ 178 CHECK_READ(0x37), \ 179 CHECK_READ(0x38), \ 180 CHECK_READ(0x39)); 181 182#else /* CHECK_POINTS */ 183 184#define CHECK_INIT(D) 185#define CHECK_PRINT(S) 186 187#endif /* CHECK_POINTS */ 188 189/* 190 * Values to send to the POST hardware. 191 */ 192#ifndef POSTCODE 193#define POSTCODE(X) 194#endif 195 196#define MP_BOOTADDRESS_POST 0x10 197#define MP_PROBE_POST 0x11 198#define MP_START_POST 0x12 199#define MP_ANNOUNCE_POST 0x13 200#define MPTABLE_PASS1_POST 0x14 201#define MPTABLE_PASS2_POST 0x15 202#define MP_ENABLE_POST 0x16 203#define START_ALL_APS_POST 0x17 204#define INSTALL_AP_TRAMP_POST 0x18 205#define START_AP_POST 0x19 206 207/** FIXME: what system files declare these??? */ 208extern struct region_descriptor r_gdt, r_idt; 209 210int mp_ncpus; /* # of CPUs, including BSP */ 211int mp_naps; /* # of Applications processors */ 212int mp_nbusses; /* # of busses */ 213int mp_napics; /* # of IO APICs */ 214int boot_cpu_id; /* designated BSP */ 215vm_offset_t cpu_apic_address; 216vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */ 217 218u_int32_t cpu_apic_versions[NCPU]; 219u_int32_t io_apic_versions[NAPIC]; 220 221/* 222 * APIC ID logical/physical mapping structures. 223 * We oversize these to simplify boot-time config. 224 */ 225int cpu_num_to_apic_id[NAPICID]; 226int io_num_to_apic_id[NAPICID]; 227int apic_id_to_logical[NAPICID]; 228 229/* Bitmap of all available CPUs */ 230u_int all_cpus; 231 232/* Boot of AP uses this PTD */ 233u_int *bootPTD; 234 235/* Hotwire a 0->4MB V==P mapping */ 236extern pt_entry_t KPTphys; 237 238/* virtual address of per-cpu common_tss */ 239extern struct i386tss common_tss; 240 241/* 242 * look for MP compliant motherboard. 243 */ 244 245static int mp_capable; 246static u_int boot_address; 247static u_int base_memory; 248 249static int picmode; /* 0: virtual wire mode, 1: PIC mode */ 250static mpfps_t mpfps; 251static int search_for_sig(u_int32_t target, int count); 252static void mp_enable(u_int boot_addr); 253 254static int mptable_pass1(void); 255static int mptable_pass2(void); 256static void default_mp_table(int type); 257static int start_all_aps(u_int boot_addr); 258static void install_ap_tramp(u_int boot_addr); 259static int start_ap(int logicalCpu, u_int boot_addr); 260 261 262/* 263 * calculate usable address in base memory for AP trampoline code 264 */ 265u_int 266mp_bootaddress(u_int basemem) 267{ 268 POSTCODE(MP_BOOTADDRESS_POST); 269 270 base_memory = basemem * 1024; /* convert to bytes */ 271 272 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ 273 if ((base_memory - boot_address) < bootMP_size) 274 boot_address -= 4096; /* not enough, lower by 4k */ 275 276 return boot_address; 277} 278 279 280int 281mp_probe(void) 282{ 283 int x; 284 u_long segment; 285 u_int32_t target; 286 287 POSTCODE(MP_PROBE_POST); 288 289 /* see if EBDA exists */ 290 if (segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) { 291 /* search first 1K of EBDA */ 292 target = (u_int32_t) (segment << 4); 293 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 294 goto found; 295 } else { 296 /* last 1K of base memory, effective 'top of base' passed in */ 297 target = (u_int32_t) (base_memory - 0x400); 298 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 299 goto found; 300 } 301 302 /* search the BIOS */ 303 target = (u_int32_t) BIOS_BASE; 304 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) 305 goto found; 306 307 /* nothing found */ 308 mpfps = (mpfps_t)0; 309 mp_capable = 0; 310 return 0; 311 312found: /* please forgive the 'goto'! */ 313 /* calculate needed resources */ 314 mpfps = (mpfps_t)x; 315 if (mptable_pass1()) 316 panic("you must reconfigure your kernel"); 317 318 /* flag fact that we are running multiple processors */ 319 mp_capable = 1; 320 return 1; 321} 322 323 324/* 325 * startup the SMP processors 326 */ 327void 328mp_start(void) 329{ 330 POSTCODE(MP_START_POST); 331 332 /* look for MP capable motherboard */ 333 if (mp_capable) 334 mp_enable(boot_address); 335 else 336 panic("MP hardware not found!"); 337} 338 339 340/* 341 * print various information about the SMP system hardware and setup 342 */ 343void 344mp_announce(void) 345{ 346 int x; 347 348 POSTCODE(MP_ANNOUNCE_POST); 349 350 printf("FreeBSD/SMP: Multiprocessor motherboard\n"); 351 printf(" cpu0 (BSP): apic id: %d", CPU_TO_ID(0)); 352 printf(", version: 0x%08x", cpu_apic_versions[0]); 353 printf(", at 0x%08x\n", cpu_apic_address); 354 for (x = 1; x <= mp_naps; ++x) { 355 printf(" cpu%d (AP): apic id: %d", x, CPU_TO_ID(x)); 356 printf(", version: 0x%08x", cpu_apic_versions[x]); 357 printf(", at 0x%08x\n", cpu_apic_address); 358 } 359 360#if defined(APIC_IO) 361 for (x = 0; x < mp_napics; ++x) { 362 printf(" io%d (APIC): apic id: %d", x, IO_TO_ID(x)); 363 printf(", version: 0x%08x", io_apic_versions[x]); 364 printf(", at 0x%08x\n", io_apic_address[x]); 365 } 366#else 367 printf(" Warning: APIC I/O disabled\n"); 368#endif /* APIC_IO */ 369} 370 371/* 372 * AP cpu's call this to sync up protected mode. 373 */ 374void 375init_secondary(void) 376{ 377 int gsel_tss, slot; 378 379 r_gdt.rd_limit = sizeof(gdt[0]) * (NGDT + NCPU) - 1; 380 r_gdt.rd_base = (int) gdt; 381 lgdt(&r_gdt); /* does magic intra-segment return */ 382 lidt(&r_idt); 383 lldt(_default_ldt); 384 385 slot = NGDT + cpuid; 386 gsel_tss = GSEL(slot, SEL_KPL); 387 gdt[slot].sd.sd_type = SDT_SYS386TSS; 388 common_tss.tss_esp0 = 0; /* not used until after switch */ 389 common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 390 common_tss.tss_ioopt = (sizeof common_tss) << 16; 391 ltr(gsel_tss); 392 393 load_cr0(0x8005003b); /* XXX! */ 394 395 PTD[0] = 0; 396 invltlb(); 397} 398 399 400#if defined(APIC_IO) 401void 402configure_local_apic(void) 403{ 404 u_char byte; 405 u_int32_t temp; 406 407 if (picmode) { 408 outb(0x22, 0x70); /* select IMCR */ 409 byte = inb(0x23); /* current contents */ 410 byte |= 0x01; /* mask external INTR */ 411 outb(0x23, byte); /* disconnect 8259s/NMI */ 412 } 413 414 /* mask lint0 (the 8259 'virtual wire' connection) */ 415 temp = lapic.lvt_lint0; 416 temp |= APIC_LVT_M; 417 lapic.lvt_lint0 = temp; 418 419 /* setup lint1 to handle NMI */ 420#if 1 421 /** XXX FIXME: 422 * should we arrange for ALL CPUs to catch NMI??? 423 * it would probably crash, so for now only the BSP 424 * will catch it 425 */ 426 if (cpuid != 0) 427 return; 428#endif /* 0/1 */ 429 430 temp = lapic.lvt_lint1; 431 432 /* clear fields of interest, preserve undefined fields */ 433 temp &= ~(0x1f000 | APIC_LVT_DM | APIC_LVT_VECTOR); 434 435 /* setup for NMI, edge trigger, active hi */ 436 temp |= (APIC_LVT_DM_NMI | APIC_LVT_IIPP_INTAHI); 437 438 lapic.lvt_lint1 = temp; 439} 440#endif /* APIC_IO */ 441 442 443/******************************************************************* 444 * local functions and data 445 */ 446 447/* 448 * start the SMP system 449 */ 450static void 451mp_enable(u_int boot_addr) 452{ 453 int x; 454#if defined(APIC_IO) 455 int apic; 456 u_int ux; 457#endif /* APIC_IO */ 458 459 POSTCODE(MP_ENABLE_POST); 460 461 /* Turn on 4MB of V == P addressing so we can get to MP table */ 462 *(int *)PTD = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME); 463 invltlb(); 464 465 /* examine the MP table for needed info, uses physical addresses */ 466 x = mptable_pass2(); 467 468 *(int *)PTD = 0; 469 invltlb(); 470 471 /* can't process default configs till the CPU APIC is pmapped */ 472 if (x) 473 default_mp_table(x); 474 475#if defined(APIC_IO) 476 /* fill the LOGICAL io_apic_versions table */ 477 for (apic = 0; apic < mp_napics; ++apic) { 478 ux = io_apic_read(apic, IOAPIC_VER); 479 io_apic_versions[apic] = ux; 480 } 481 482 /* program each IO APIC in the system */ 483 for (apic = 0; apic < mp_napics; ++apic) 484 if (io_apic_setup(apic) < 0) 485 panic("IO APIC setup failure"); 486 487 /* install an inter-CPU IPI for TLB invalidation */ 488 setidt(XINVLTLB_OFFSET, Xinvltlb, 489 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 490 491#if defined(TEST_CPUSTOP) 492 /* install an inter-CPU IPI for CPU stop/restart */ 493 setidt(XCPUSTOP_OFFSET, Xcpustop, 494 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 495#endif /* TEST_CPUSTOP */ 496#endif /* APIC_IO */ 497 498 /* start each Application Processor */ 499 start_all_aps(boot_addr); 500 501 /* 502 * The init process might be started on a different CPU now, 503 * and the boot CPU might not call prepare_usermode to get 504 * cr0 correctly configured. Thus we initialize cr0 here. 505 */ 506 load_cr0(rcr0() | CR0_WP | CR0_AM); 507} 508 509 510/* 511 * look for the MP spec signature 512 */ 513 514/* string defined by the Intel MP Spec as identifying the MP table */ 515#define MP_SIG 0x5f504d5f /* _MP_ */ 516#define NEXT(X) ((X) += 4) 517static int 518search_for_sig(u_int32_t target, int count) 519{ 520 int x; 521 u_int32_t *addr = (u_int32_t *) (KERNBASE + target); 522 523 for (x = 0; x < count; NEXT(x)) 524 if (addr[x] == MP_SIG) 525 /* make array index a byte index */ 526 return (target + (x * sizeof(u_int32_t))); 527 528 return -1; 529} 530 531 532static basetable_entry basetable_entry_types[] = 533{ 534 {0, 20, "Processor"}, 535 {1, 8, "Bus"}, 536 {2, 8, "I/O APIC"}, 537 {3, 8, "I/O INT"}, 538 {4, 8, "Local INT"} 539}; 540 541typedef struct BUSDATA { 542 u_char bus_id; 543 enum busTypes bus_type; 544} bus_datum; 545 546typedef struct INTDATA { 547 u_char int_type; 548 u_short int_flags; 549 u_char src_bus_id; 550 u_char src_bus_irq; 551 u_char dst_apic_id; 552 u_char dst_apic_int; 553} io_int, local_int; 554 555typedef struct BUSTYPENAME { 556 u_char type; 557 char name[7]; 558} bus_type_name; 559 560static bus_type_name bus_type_table[] = 561{ 562 {CBUS, "CBUS"}, 563 {CBUSII, "CBUSII"}, 564 {EISA, "EISA"}, 565 {UNKNOWN_BUSTYPE, "---"}, 566 {UNKNOWN_BUSTYPE, "---"}, 567 {ISA, "ISA"}, 568 {UNKNOWN_BUSTYPE, "---"}, 569 {UNKNOWN_BUSTYPE, "---"}, 570 {UNKNOWN_BUSTYPE, "---"}, 571 {UNKNOWN_BUSTYPE, "---"}, 572 {UNKNOWN_BUSTYPE, "---"}, 573 {UNKNOWN_BUSTYPE, "---"}, 574 {PCI, "PCI"}, 575 {UNKNOWN_BUSTYPE, "---"}, 576 {UNKNOWN_BUSTYPE, "---"}, 577 {UNKNOWN_BUSTYPE, "---"}, 578 {UNKNOWN_BUSTYPE, "---"}, 579 {XPRESS, "XPRESS"}, 580 {UNKNOWN_BUSTYPE, "---"} 581}; 582/* from MP spec v1.4, table 5-1 */ 583static int default_data[7][5] = 584{ 585/* nbus, id0, type0, id1, type1 */ 586 {1, 0, ISA, 255, 255}, 587 {1, 0, EISA, 255, 255}, 588 {1, 0, EISA, 255, 255}, 589 {0, 255, 255, 255, 255},/* MCA not supported */ 590 {2, 0, ISA, 1, PCI}, 591 {2, 0, EISA, 1, PCI}, 592 {0, 255, 255, 255, 255} /* MCA not supported */ 593}; 594 595 596/* the bus data */ 597bus_datum bus_data[NBUS]; 598 599/* the IO INT data, one entry per possible APIC INTerrupt */ 600io_int io_apic_ints[NINTR]; 601 602static int nintrs; 603 604static void fix_mp_table __P((void)); 605static int processor_entry __P((proc_entry_ptr entry, int cpu)); 606static int bus_entry __P((bus_entry_ptr entry, int bus)); 607static int io_apic_entry __P((io_apic_entry_ptr entry, int apic)); 608static int int_entry __P((int_entry_ptr entry, int intr)); 609static int lookup_bus_type __P((char *name)); 610 611 612/* 613 * 1st pass on motherboard's Intel MP specification table. 614 * 615 * initializes: 616 * mp_ncpus = 1 617 * 618 * determines: 619 * cpu_apic_address (common to all CPUs) 620 * io_apic_address[N] 621 * mp_naps 622 * mp_nbusses 623 * mp_napics 624 * nintrs 625 */ 626static int 627mptable_pass1(void) 628{ 629 int x; 630 mpcth_t cth; 631 int totalSize; 632 void* position; 633 int count; 634 int type; 635 int mustpanic; 636 637 POSTCODE(MPTABLE_PASS1_POST); 638 639 mustpanic = 0; 640 641 /* clear various tables */ 642 for (x = 0; x < NAPICID; ++x) { 643 io_apic_address[x] = ~0; /* IO APIC address table */ 644 } 645 646 /* init everything to empty */ 647 mp_naps = 0; 648 mp_nbusses = 0; 649 mp_napics = 0; 650 nintrs = 0; 651 652 /* check for use of 'default' configuration */ 653 if (mpfps->mpfb1 != 0) { 654 /* use default addresses */ 655 cpu_apic_address = DEFAULT_APIC_BASE; 656 io_apic_address[0] = DEFAULT_IO_APIC_BASE; 657 658 /* fill in with defaults */ 659 mp_naps = 2; /* includes BSP */ 660 mp_nbusses = default_data[mpfps->mpfb1 - 1][0]; 661#if defined(APIC_IO) 662 mp_napics = 1; 663 nintrs = 16; 664#endif /* APIC_IO */ 665 } 666 else { 667 if ((cth = mpfps->pap) == 0) 668 panic("MP Configuration Table Header MISSING!"); 669 670 cpu_apic_address = (vm_offset_t) cth->apic_address; 671 672 /* walk the table, recording info of interest */ 673 totalSize = cth->base_table_length - sizeof(struct MPCTH); 674 position = (u_char *) cth + sizeof(struct MPCTH); 675 count = cth->entry_count; 676 677 while (count--) { 678 switch (type = *(u_char *) position) { 679 case 0: /* processor_entry */ 680 if (((proc_entry_ptr)position)->cpu_flags 681 & PROCENTRY_FLAG_EN) 682 ++mp_naps; 683 break; 684 case 1: /* bus_entry */ 685 ++mp_nbusses; 686 break; 687 case 2: /* io_apic_entry */ 688 if (((io_apic_entry_ptr)position)->apic_flags 689 & IOAPICENTRY_FLAG_EN) 690 io_apic_address[mp_napics++] = 691 (vm_offset_t)((io_apic_entry_ptr) 692 position)->apic_address; 693 break; 694 case 3: /* int_entry */ 695 ++nintrs; 696 break; 697 case 4: /* int_entry */ 698 break; 699 default: 700 panic("mpfps Base Table HOSED!"); 701 /* NOTREACHED */ 702 } 703 704 totalSize -= basetable_entry_types[type].length; 705 (u_char*)position += basetable_entry_types[type].length; 706 } 707 } 708 709 /* qualify the numbers */ 710 if (mp_naps > NCPU) 711 printf("Warning: only using %d of %d available CPUs!\n", 712 NCPU, mp_naps); 713#if 0 714 /** XXX we consider this legal now (but should we?) */ 715 mustpanic = 1; 716#endif 717 if (mp_nbusses > NBUS) { 718 printf("found %d busses, increase NBUS\n", mp_nbusses); 719 mustpanic = 1; 720 } 721 if (mp_napics > NAPIC) { 722 printf("found %d apics, increase NAPIC\n", mp_napics); 723 mustpanic = 1; 724 } 725 if (nintrs > NINTR) { 726 printf("found %d intrs, increase NINTR\n", nintrs); 727 mustpanic = 1; 728 } 729 730 /* 731 * Count the BSP. 732 * This is also used as a counter while starting the APs. 733 */ 734 mp_ncpus = 1; 735 736 --mp_naps; /* subtract the BSP */ 737 738 return mustpanic; 739} 740 741 742/* 743 * 2nd pass on motherboard's Intel MP specification table. 744 * 745 * sets: 746 * boot_cpu_id 747 * ID_TO_IO(N), phy APIC ID to log CPU/IO table 748 * CPU_TO_ID(N), logical CPU to APIC ID table 749 * IO_TO_ID(N), logical IO to APIC ID table 750 * bus_data[N] 751 * io_apic_ints[N] 752 */ 753static int 754mptable_pass2(void) 755{ 756 int x; 757 mpcth_t cth; 758 int totalSize; 759 void* position; 760 int count; 761 int type; 762 int apic, bus, cpu, intr; 763 764 POSTCODE(MPTABLE_PASS2_POST); 765 766 /* clear various tables */ 767 for (x = 0; x < NAPICID; ++x) { 768 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */ 769 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */ 770 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */ 771 } 772 773 /* clear bus data table */ 774 for (x = 0; x < NBUS; ++x) 775 bus_data[x].bus_id = 0xff; 776 777 /* clear IO APIC INT table */ 778 for (x = 0; x < NINTR; ++x) 779 io_apic_ints[x].int_type = 0xff; 780 781 /* setup the cpu/apic mapping arrays */ 782 boot_cpu_id = -1; 783 784 /* record whether PIC or virtual-wire mode */ 785 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0; 786 787 /* check for use of 'default' configuration */ 788#if defined(TEST_DEFAULT_CONFIG) 789 return TEST_DEFAULT_CONFIG; 790#else 791 if (mpfps->mpfb1 != 0) 792 return mpfps->mpfb1; /* return default configuration type */ 793#endif /* TEST_DEFAULT_CONFIG */ 794 795 if ((cth = mpfps->pap) == 0) 796 panic("MP Configuration Table Header MISSING!"); 797 798 /* walk the table, recording info of interest */ 799 totalSize = cth->base_table_length - sizeof(struct MPCTH); 800 position = (u_char *) cth + sizeof(struct MPCTH); 801 count = cth->entry_count; 802 apic = bus = intr = 0; 803 cpu = 1; /* pre-count the BSP */ 804 805 while (count--) { 806 switch (type = *(u_char *) position) { 807 case 0: 808 if (processor_entry(position, cpu)) 809 ++cpu; 810 break; 811 case 1: 812 if (bus_entry(position, bus)) 813 ++bus; 814 break; 815 case 2: 816 if (io_apic_entry(position, apic)) 817 ++apic; 818 break; 819 case 3: 820 if (int_entry(position, intr)) 821 ++intr; 822 break; 823 case 4: 824 /* int_entry(position); */ 825 break; 826 default: 827 panic("mpfps Base Table HOSED!"); 828 /* NOTREACHED */ 829 } 830 831 totalSize -= basetable_entry_types[type].length; 832 (u_char *) position += basetable_entry_types[type].length; 833 } 834 835 if (boot_cpu_id == -1) 836 panic("NO BSP found!"); 837 838 /* post scan cleanup */ 839 fix_mp_table(); 840 841 /* report fact that its NOT a default configuration */ 842 return 0; 843} 844 845 846/* 847 * parse an Intel MP specification table 848 */ 849static void 850fix_mp_table(void) 851{ 852 int x; 853 int id; 854 int bus_0; 855 int bus_pci; 856 int num_pci_bus; 857 858 /* 859 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS 860 * did it wrong. The MP spec says that when more than 1 PCI bus 861 * exists the BIOS must begin with bus entries for the PCI bus and use 862 * actual PCI bus numbering. This implies that when only 1 PCI bus 863 * exists the BIOS can choose to ignore this ordering, and indeed many 864 * MP motherboards do ignore it. This causes a problem when the PCI 865 * sub-system makes requests of the MP sub-system based on PCI bus 866 * numbers. So here we look for the situation and renumber the 867 * busses and associated INTs in an effort to "make it right". 868 */ 869 870 /* find bus 0, PCI bus, count the number of PCI busses */ 871 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { 872 if (bus_data[x].bus_id == 0) { 873 bus_0 = x; 874 } 875 if (bus_data[x].bus_type == PCI) { 876 ++num_pci_bus; 877 bus_pci = x; 878 } 879 } 880 /* 881 * bus_0 == slot of bus with ID of 0 882 * bus_pci == slot of last PCI bus encountered 883 */ 884 885 /* check the 1 PCI bus case for sanity */ 886 if (num_pci_bus == 1) { 887 888 /* if it is number 0 all is well */ 889 if (bus_data[bus_pci].bus_id == 0) 890 return; 891 892 /* mis-numbered, swap with whichever bus uses slot 0 */ 893 894 /* swap the bus entry types */ 895 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type; 896 bus_data[bus_0].bus_type = PCI; 897 898 /* swap each relavant INTerrupt entry */ 899 id = bus_data[bus_pci].bus_id; 900 for (x = 0; x < nintrs; ++x) { 901 if (io_apic_ints[x].src_bus_id == id) { 902 io_apic_ints[x].src_bus_id = 0; 903 } 904 else if (io_apic_ints[x].src_bus_id == 0) { 905 io_apic_ints[x].src_bus_id = id; 906 } 907 } 908 } 909 /* sanity check if more than 1 PCI bus */ 910 else if (num_pci_bus > 1) { 911 for (x = 0; x < mp_nbusses; ++x) { 912 if (bus_data[x].bus_type != PCI) 913 continue; 914 if (bus_data[x].bus_id >= num_pci_bus) 915 panic("bad PCI bus numbering"); 916 } 917 } 918} 919 920 921static int 922processor_entry(proc_entry_ptr entry, int cpu) 923{ 924 /* check for usability */ 925 if ((cpu >= NCPU) || !(entry->cpu_flags & PROCENTRY_FLAG_EN)) 926 return 0; 927 928 /* check for BSP flag */ 929 if (entry->cpu_flags & PROCENTRY_FLAG_BP) { 930 boot_cpu_id = entry->apic_id; 931 CPU_TO_ID(0) = entry->apic_id; 932 ID_TO_CPU(entry->apic_id) = 0; 933 return 0; /* its already been counted */ 934 } 935 936 /* add another AP to list, if less than max number of CPUs */ 937 else { 938 CPU_TO_ID(cpu) = entry->apic_id; 939 ID_TO_CPU(entry->apic_id) = cpu; 940 return 1; 941 } 942} 943 944 945static int 946bus_entry(bus_entry_ptr entry, int bus) 947{ 948 int x; 949 char c, name[8]; 950 951 /* encode the name into an index */ 952 for (x = 0; x < 6; ++x) { 953 if ((c = entry->bus_type[x]) == ' ') 954 break; 955 name[x] = c; 956 } 957 name[x] = '\0'; 958 959 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) 960 panic("unknown bus type: '%s'", name); 961 962 bus_data[bus].bus_id = entry->bus_id; 963 bus_data[bus].bus_type = x; 964 965 return 1; 966} 967 968 969static int 970io_apic_entry(io_apic_entry_ptr entry, int apic) 971{ 972 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) 973 return 0; 974 975 IO_TO_ID(apic) = entry->apic_id; 976 ID_TO_IO(entry->apic_id) = apic; 977 978 return 1; 979} 980 981 982static int 983lookup_bus_type(char *name) 984{ 985 int x; 986 987 for (x = 0; x < MAX_BUSTYPE; ++x) 988 if (strcmp(bus_type_table[x].name, name) == 0) 989 return bus_type_table[x].type; 990 991 return UNKNOWN_BUSTYPE; 992} 993 994 995static int 996int_entry(int_entry_ptr entry, int intr) 997{ 998 io_apic_ints[intr].int_type = entry->int_type; 999 io_apic_ints[intr].int_flags = entry->int_flags; 1000 io_apic_ints[intr].src_bus_id = entry->src_bus_id; 1001 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq; 1002 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; 1003 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int; 1004 1005 return 1; 1006} 1007 1008 1009static int 1010apic_int_is_bus_type(int intr, int bus_type) 1011{ 1012 int bus; 1013 1014 for (bus = 0; bus < mp_nbusses; ++bus) 1015 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) 1016 && ((int) bus_data[bus].bus_type == bus_type)) 1017 return 1; 1018 1019 return 0; 1020} 1021 1022 1023/* 1024 * Given a traditional ISA INT mask, return an APIC mask. 1025 */ 1026u_int 1027isa_apic_mask(u_int isa_mask) 1028{ 1029 int isa_irq; 1030 int apic_pin; 1031 1032 isa_irq = ffs(isa_mask); /* find its bit position */ 1033 if (isa_irq == 0) /* doesn't exist */ 1034 return 0; 1035 --isa_irq; /* make it zero based */ 1036 1037 apic_pin = isa_apic_pin(isa_irq); /* look for APIC connection */ 1038 if (apic_pin == -1) 1039 return 0; 1040 1041 return (1 << apic_pin); /* convert pin# to a mask */ 1042} 1043 1044 1045/* 1046 * Determine which APIC pin an ISA/EISA INT is attached to. 1047 */ 1048#define INTTYPE(I) (io_apic_ints[(I)].int_type) 1049#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) 1050 1051#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) 1052int 1053isa_apic_pin(int isa_irq) 1054{ 1055 int intr; 1056 1057#if defined(SMP_TIMER_NC) 1058 if (isa_irq == 0) 1059 return -1; 1060#endif /* SMP_TIMER_NC */ 1061 1062 for (intr = 0; intr < nintrs; ++intr) { /* check each record */ 1063 if (INTTYPE(intr) == 0) { /* standard INT */ 1064 if (SRCBUSIRQ(intr) == isa_irq) { 1065 if (apic_int_is_bus_type(intr, ISA) || 1066 apic_int_is_bus_type(intr, EISA)) 1067 return INTPIN(intr); /* found */ 1068 } 1069 } 1070 } 1071 return -1; /* NOT found */ 1072} 1073#undef SRCBUSIRQ 1074 1075 1076/* 1077 * Determine which APIC pin a PCI INT is attached to. 1078 */ 1079#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) 1080#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) 1081#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) 1082int 1083pci_apic_pin(int pciBus, int pciDevice, int pciInt) 1084{ 1085 int intr; 1086 1087 --pciInt; /* zero based */ 1088 1089 for (intr = 0; intr < nintrs; ++intr) /* check each record */ 1090 if ((INTTYPE(intr) == 0) /* standard INT */ 1091 && (SRCBUSID(intr) == pciBus) 1092 && (SRCBUSDEVICE(intr) == pciDevice) 1093 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ 1094 if (apic_int_is_bus_type(intr, PCI)) 1095 return INTPIN(intr); /* exact match */ 1096 1097 return -1; /* NOT found */ 1098} 1099#undef SRCBUSLINE 1100#undef SRCBUSDEVICE 1101#undef SRCBUSID 1102 1103#undef INTPIN 1104#undef INTTYPE 1105 1106 1107/* 1108 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt. 1109 * 1110 * XXX FIXME: 1111 * Exactly what this means is unclear at this point. It is a solution 1112 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard 1113 * could route any of the ISA INTs to upper (>15) IRQ values. But most would 1114 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an 1115 * option. 1116 */ 1117int 1118undirect_isa_irq(int rirq) 1119{ 1120#if defined(READY) 1121 printf("Freeing redirected ISA irq %d.\n", rirq); 1122 /** FIXME: tickle the MB redirector chip */ 1123 return ???; 1124#else 1125 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq); 1126 return 0; 1127#endif /* READY */ 1128} 1129 1130 1131/* 1132 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt 1133 */ 1134int 1135undirect_pci_irq(int rirq) 1136{ 1137#if defined(READY) 1138 if (bootverbose) 1139 printf("Freeing redirected PCI irq %d.\n", rirq); 1140 1141 /** FIXME: tickle the MB redirector chip */ 1142 return ???; 1143#else 1144 if (bootverbose) 1145 printf("Freeing (NOT implemented) redirected PCI irq %d.\n", 1146 rirq); 1147 return 0; 1148#endif /* READY */ 1149} 1150 1151 1152/* 1153 * given a bus ID, return: 1154 * the bus type if found 1155 * -1 if NOT found 1156 */ 1157int 1158apic_bus_type(int id) 1159{ 1160 int x; 1161 1162 for (x = 0; x < mp_nbusses; ++x) 1163 if (bus_data[x].bus_id == id) 1164 return bus_data[x].bus_type; 1165 1166 return -1; 1167} 1168 1169 1170/* 1171 * given a LOGICAL APIC# and pin#, return: 1172 * the associated src bus ID if found 1173 * -1 if NOT found 1174 */ 1175int 1176apic_src_bus_id(int apic, int pin) 1177{ 1178 int x; 1179 1180 /* search each of the possible INTerrupt sources */ 1181 for (x = 0; x < nintrs; ++x) 1182 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1183 (pin == io_apic_ints[x].dst_apic_int)) 1184 return (io_apic_ints[x].src_bus_id); 1185 1186 return -1; /* NOT found */ 1187} 1188 1189 1190/* 1191 * given a LOGICAL APIC# and pin#, return: 1192 * the associated src bus IRQ if found 1193 * -1 if NOT found 1194 */ 1195int 1196apic_src_bus_irq(int apic, int pin) 1197{ 1198 int x; 1199 1200 for (x = 0; x < nintrs; x++) 1201 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1202 (pin == io_apic_ints[x].dst_apic_int)) 1203 return (io_apic_ints[x].src_bus_irq); 1204 1205 return -1; /* NOT found */ 1206} 1207 1208 1209/* 1210 * given a LOGICAL APIC# and pin#, return: 1211 * the associated INTerrupt type if found 1212 * -1 if NOT found 1213 */ 1214int 1215apic_int_type(int apic, int pin) 1216{ 1217 int x; 1218 1219 /* search each of the possible INTerrupt sources */ 1220 for (x = 0; x < nintrs; ++x) 1221 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1222 (pin == io_apic_ints[x].dst_apic_int)) 1223 return (io_apic_ints[x].int_type); 1224 1225 return -1; /* NOT found */ 1226} 1227 1228 1229/* 1230 * given a LOGICAL APIC# and pin#, return: 1231 * the associated trigger mode if found 1232 * -1 if NOT found 1233 */ 1234int 1235apic_trigger(int apic, int pin) 1236{ 1237 int x; 1238 1239 /* search each of the possible INTerrupt sources */ 1240 for (x = 0; x < nintrs; ++x) 1241 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1242 (pin == io_apic_ints[x].dst_apic_int)) 1243 return ((io_apic_ints[x].int_flags >> 2) & 0x03); 1244 1245 return -1; /* NOT found */ 1246} 1247 1248 1249/* 1250 * given a LOGICAL APIC# and pin#, return: 1251 * the associated 'active' level if found 1252 * -1 if NOT found 1253 */ 1254int 1255apic_polarity(int apic, int pin) 1256{ 1257 int x; 1258 1259 /* search each of the possible INTerrupt sources */ 1260 for (x = 0; x < nintrs; ++x) 1261 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1262 (pin == io_apic_ints[x].dst_apic_int)) 1263 return (io_apic_ints[x].int_flags & 0x03); 1264 1265 return -1; /* NOT found */ 1266} 1267 1268 1269/* 1270 * set data according to MP defaults 1271 * FIXME: probably not complete yet... 1272 */ 1273static void 1274default_mp_table(int type) 1275{ 1276 int ap_cpu_id; 1277#if defined(APIC_IO) 1278 u_int32_t ux; 1279 int io_apic_id; 1280 int pin; 1281#endif /* APIC_IO */ 1282 1283#if 0 1284 printf(" MP default config type: %d\n", type); 1285 switch (type) { 1286 case 1: 1287 printf(" bus: ISA, APIC: 82489DX\n"); 1288 break; 1289 case 2: 1290 printf(" bus: EISA, APIC: 82489DX\n"); 1291 break; 1292 case 3: 1293 printf(" bus: EISA, APIC: 82489DX\n"); 1294 break; 1295 case 4: 1296 printf(" bus: MCA, APIC: 82489DX\n"); 1297 break; 1298 case 5: 1299 printf(" bus: ISA+PCI, APIC: Integrated\n"); 1300 break; 1301 case 6: 1302 printf(" bus: EISA+PCI, APIC: Integrated\n"); 1303 break; 1304 case 7: 1305 printf(" bus: MCA+PCI, APIC: Integrated\n"); 1306 break; 1307 default: 1308 printf(" future type\n"); 1309 break; 1310 /* NOTREACHED */ 1311 } 1312#endif /* 0 */ 1313 1314 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24; 1315 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; 1316 1317 /* BSP */ 1318 CPU_TO_ID(0) = boot_cpu_id; 1319 ID_TO_CPU(boot_cpu_id) = 0; 1320 1321 /* one and only AP */ 1322 CPU_TO_ID(1) = ap_cpu_id; 1323 ID_TO_CPU(ap_cpu_id) = 1; 1324 1325#if defined(APIC_IO) 1326 /* one and only IO APIC */ 1327 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; 1328 1329 /* 1330 * sanity check, refer to MP spec section 3.6.6, last paragraph 1331 * necessary as some hardware isn't properly setting up the IO APIC 1332 */ 1333#if defined(REALLY_ANAL_IOAPICID_VALUE) 1334 if (io_apic_id != 2) { 1335#else 1336 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { 1337#endif /* REALLY_ANAL_IOAPICID_VALUE */ 1338 ux = io_apic_read(0, IOAPIC_ID); /* get current contents */ 1339 ux &= ~APIC_ID_MASK; /* clear the ID field */ 1340 ux |= 0x02000000; /* set it to '2' */ 1341 io_apic_write(0, IOAPIC_ID, ux); /* write new value */ 1342 ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */ 1343 if ((ux & APIC_ID_MASK) != 0x02000000) 1344 panic("can't control IO APIC ID, reg: 0x%08x", ux); 1345 io_apic_id = 2; 1346 } 1347 IO_TO_ID(0) = io_apic_id; 1348 ID_TO_IO(io_apic_id) = 0; 1349#endif /* APIC_IO */ 1350 1351 /* fill out bus entries */ 1352 switch (type) { 1353 case 1: 1354 case 2: 1355 case 3: 1356 case 5: 1357 case 6: 1358 bus_data[0].bus_id = default_data[type - 1][1]; 1359 bus_data[0].bus_type = default_data[type - 1][2]; 1360 bus_data[1].bus_id = default_data[type - 1][3]; 1361 bus_data[1].bus_type = default_data[type - 1][4]; 1362 break; 1363 1364 /* case 4: case 7: MCA NOT supported */ 1365 default: /* illegal/reserved */ 1366 panic("BAD default MP config: %d", type); 1367 /* NOTREACHED */ 1368 } 1369 1370#if defined(APIC_IO) 1371 /* general cases from MP v1.4, table 5-2 */ 1372 for (pin = 0; pin < 16; ++pin) { 1373 io_apic_ints[pin].int_type = 0; 1374 io_apic_ints[pin].int_flags = 0x05; /* edge-triggered/active-hi */ 1375 io_apic_ints[pin].src_bus_id = 0; 1376 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 is caught below */ 1377 io_apic_ints[pin].dst_apic_id = io_apic_id; 1378 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 correspondence */ 1379 } 1380 1381 /* special cases from MP v1.4, table 5-2 */ 1382 if (type == 2) { 1383 io_apic_ints[2].int_type = 0xff; /* N/C */ 1384 io_apic_ints[13].int_type = 0xff; /* N/C */ 1385#if !defined(APIC_MIXED_MODE) 1386 /** FIXME: ??? */ 1387 panic("sorry, can't support type 2 default yet"); 1388#endif /* APIC_MIXED_MODE */ 1389 } 1390 else 1391 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ 1392 1393 if (type == 7) 1394 io_apic_ints[0].int_type = 0xff; /* N/C */ 1395 else 1396 io_apic_ints[0].int_type = 3; /* vectored 8259 */ 1397#endif /* APIC_IO */ 1398} 1399 1400 1401/* 1402 * start each AP in our list 1403 */ 1404static int 1405start_all_aps(u_int boot_addr) 1406{ 1407 int x, i; 1408 u_char mpbiosreason; 1409 u_long mpbioswarmvec; 1410 pd_entry_t newptd; 1411 pt_entry_t newpt; 1412 int *newpp; 1413 1414 POSTCODE(START_ALL_APS_POST); 1415 1416 /** 1417 * NOTE: this needs further thought: 1418 * where does it get released? 1419 * should it be set to empy? 1420 * 1421 * get the initial mp_lock with a count of 1 for the BSP 1422 */ 1423 mp_lock = 1; /* this uses a LOGICAL cpu ID, ie BSP == 0 */ 1424 1425 /* initialize BSP's local APIC */ 1426 apic_initialize(1); 1427 1428 /* install the AP 1st level boot code */ 1429 install_ap_tramp(boot_addr); 1430 1431 1432 /* save the current value of the warm-start vector */ 1433 mpbioswarmvec = *((u_long *) WARMBOOT_OFF); 1434 outb(CMOS_REG, BIOS_RESET); 1435 mpbiosreason = inb(CMOS_DATA); 1436 1437 /* record BSP in CPU map */ 1438 all_cpus = 1; 1439 1440 /* start each AP */ 1441 for (x = 1; x <= mp_naps; ++x) { 1442 1443 /* HACK HACK HACK !!! */ 1444 1445 /* alloc new page table directory */ 1446 newptd = (pd_entry_t)(kmem_alloc(kernel_map, PAGE_SIZE)); 1447 1448 /* clone currently active one (ie: IdlePTD) */ 1449 bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */ 1450 1451 /* set up 0 -> 4MB P==V mapping for AP boot */ 1452 newptd[0] = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME); 1453 1454 /* store PTD for this AP */ 1455 bootPTD = (pd_entry_t)vtophys(newptd); 1456 1457 /* alloc new page table page */ 1458 newpt = (pt_entry_t)(kmem_alloc(kernel_map, PAGE_SIZE)); 1459 1460 /* set the new PTD's private page to point there */ 1461 newptd[MPPTDI] = PG_V | PG_RW | vtophys(newpt); 1462 1463 /* install self referential entry */ 1464 newptd[PTDPTDI] = PG_V | PG_RW | vtophys(newptd); 1465 1466 /* get a new private data page */ 1467 newpp = (int *)kmem_alloc(kernel_map, PAGE_SIZE); 1468 1469 /* wire it into the private page table page */ 1470 newpt[0] = PG_V | PG_RW | vtophys(newpp); 1471 1472 /* wire the ptp into itself for access */ 1473 newpt[1] = PG_V | PG_RW | vtophys(newpt); 1474 1475 /* and the local apic */ 1476 newpt[2] = SMP_prvpt[2]; 1477 1478 /* and the IO apic mapping[s] */ 1479 for (i = 16; i < 32; i++) 1480 newpt[i] = SMP_prvpt[i]; 1481 1482 /* prime data page for it to use */ 1483 newpp[0] = x; /* cpuid */ 1484 newpp[1] = 0; /* curproc */ 1485 newpp[2] = 0; /* curpcb */ 1486 newpp[3] = 0; /* npxproc */ 1487 newpp[4] = 0; /* runtime.tv_sec */ 1488 newpp[5] = 0; /* runtime.tv_usec */ 1489 newpp[6] = x << 24; /* cpu_lockid */ 1490 1491 /* XXX NOTE: ABANDON bootPTD for now!!!! */ 1492 1493 /* END REVOLTING HACKERY */ 1494 1495 /* setup a vector to our boot code */ 1496 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 1497 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); 1498 outb(CMOS_REG, BIOS_RESET); 1499 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 1500 1501 /* attempt to start the Application Processor */ 1502 CHECK_INIT(99); /* setup checkpoints */ 1503 if (!start_ap(x, boot_addr)) { 1504 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); 1505 CHECK_PRINT("trace"); /* show checkpoints */ 1506 /* better panic as the AP may be running loose */ 1507 printf("panic y/n? [y] "); 1508 if (cngetc() != 'n') 1509 panic("bye-bye"); 1510 } 1511 CHECK_PRINT("trace"); /* show checkpoints */ 1512 1513 /* record its version info */ 1514 cpu_apic_versions[x] = cpu_apic_versions[0]; 1515 1516 all_cpus |= (1 << x); /* record AP in CPU map */ 1517 } 1518 1519 /* build our map of 'other' CPUs */ 1520 other_cpus = all_cpus & ~(1 << cpuid); 1521 1522 /* fill in our (BSP) APIC version */ 1523 cpu_apic_versions[0] = lapic.version; 1524 1525 /* restore the warmstart vector */ 1526 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 1527 outb(CMOS_REG, BIOS_RESET); 1528 outb(CMOS_DATA, mpbiosreason); 1529 1530 /* number of APs actually started */ 1531 return mp_ncpus - 1; 1532} 1533 1534 1535/* 1536 * load the 1st level AP boot code into base memory. 1537 */ 1538 1539/* targets for relocation */ 1540extern void bigJump(void); 1541extern void bootCodeSeg(void); 1542extern void bootDataSeg(void); 1543extern void MPentry(void); 1544extern u_int MP_GDT; 1545extern u_int mp_gdtbase; 1546 1547static void 1548install_ap_tramp(u_int boot_addr) 1549{ 1550 int x; 1551 int size = *(int *) ((u_long) & bootMP_size); 1552 u_char *src = (u_char *) ((u_long) bootMP); 1553 u_char *dst = (u_char *) boot_addr + KERNBASE; 1554 u_int boot_base = (u_int) bootMP; 1555 u_int8_t *dst8; 1556 u_int16_t *dst16; 1557 u_int32_t *dst32; 1558 1559 POSTCODE(INSTALL_AP_TRAMP_POST); 1560 1561 for (x = 0; x < size; ++x) 1562 *dst++ = *src++; 1563 1564 /* 1565 * modify addresses in code we just moved to basemem. unfortunately we 1566 * need fairly detailed info about mpboot.s for this to work. changes 1567 * to mpboot.s might require changes here. 1568 */ 1569 1570 /* boot code is located in KERNEL space */ 1571 dst = (u_char *) boot_addr + KERNBASE; 1572 1573 /* modify the lgdt arg */ 1574 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 1575 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); 1576 1577 /* modify the ljmp target for MPentry() */ 1578 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 1579 *dst32 = ((u_int) MPentry - KERNBASE); 1580 1581 /* modify the target for boot code segment */ 1582 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 1583 dst8 = (u_int8_t *) (dst16 + 1); 1584 *dst16 = (u_int) boot_addr & 0xffff; 1585 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1586 1587 /* modify the target for boot data segment */ 1588 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 1589 dst8 = (u_int8_t *) (dst16 + 1); 1590 *dst16 = (u_int) boot_addr & 0xffff; 1591 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1592} 1593 1594 1595/* 1596 * this function starts the AP (application processor) identified 1597 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 1598 * to accomplish this. This is necessary because of the nuances 1599 * of the different hardware we might encounter. It ain't pretty, 1600 * but it seems to work. 1601 */ 1602static int 1603start_ap(int logical_cpu, u_int boot_addr) 1604{ 1605 int physical_cpu; 1606 int vector; 1607 int cpus; 1608 u_long icr_lo, icr_hi; 1609 1610 POSTCODE(START_AP_POST); 1611 1612 /* get the PHYSICAL APIC ID# */ 1613 physical_cpu = CPU_TO_ID(logical_cpu); 1614 1615 /* calculate the vector */ 1616 vector = (boot_addr >> 12) & 0xff; 1617 1618 /* used as a watchpoint to signal AP startup */ 1619 cpus = mp_ncpus; 1620 1621 /* 1622 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 1623 * and running the target CPU. OR this INIT IPI might be latched (P5 1624 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 1625 * ignored. 1626 */ 1627 1628 /* setup the address for the target AP */ 1629 icr_hi = lapic.icr_hi & ~APIC_ID_MASK; 1630 icr_hi |= (physical_cpu << 24); 1631 lapic.icr_hi = icr_hi; 1632 1633 /* do an INIT IPI: assert RESET */ 1634 icr_lo = lapic.icr_lo & 0xfff00000; 1635 lapic.icr_lo = icr_lo | 0x0000c500; 1636 1637 /* wait for pending status end */ 1638 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1639 /* spin */ ; 1640 1641 /* do an INIT IPI: deassert RESET */ 1642 lapic.icr_lo = icr_lo | 0x00008500; 1643 1644 /* wait for pending status end */ 1645 u_sleep(10000); /* wait ~10mS */ 1646 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1647 /* spin */ ; 1648 1649 /* 1650 * next we do a STARTUP IPI: the previous INIT IPI might still be 1651 * latched, (P5 bug) this 1st STARTUP would then terminate 1652 * immediately, and the previously started INIT IPI would continue. OR 1653 * the previous INIT IPI has already run. and this STARTUP IPI will 1654 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 1655 * will run. 1656 */ 1657 1658 /* do a STARTUP IPI */ 1659 lapic.icr_lo = icr_lo | 0x00000600 | vector; 1660 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1661 /* spin */ ; 1662 u_sleep(200); /* wait ~200uS */ 1663 1664 /* 1665 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 1666 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 1667 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 1668 * recognized after hardware RESET or INIT IPI. 1669 */ 1670 1671 lapic.icr_lo = icr_lo | 0x00000600 | vector; 1672 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1673 /* spin */ ; 1674 u_sleep(200); /* wait ~200uS */ 1675 1676 /* wait for it to start */ 1677 set_apic_timer(5000000);/* == 5 seconds */ 1678 while (read_apic_timer()) 1679 if (mp_ncpus > cpus) 1680 return 1; /* return SUCCESS */ 1681 1682 return 0; /* return FAILURE */ 1683} 1684 1685 1686/* 1687 * Flush the TLB on all other CPU's 1688 * 1689 * XXX: Needs to handshake and wait for completion before proceding. 1690 */ 1691void 1692smp_invltlb(void) 1693{ 1694#if defined(APIC_IO) 1695 if (smp_active && invltlb_ok) 1696 all_but_self_ipi(XINVLTLB_OFFSET); 1697#endif /* APIC_IO */ 1698} 1699 1700void 1701invlpg(u_int addr) 1702{ 1703 __asm __volatile("invlpg (%0)"::"r"(addr):"memory"); 1704 1705 /* send a message to the other CPUs */ 1706 smp_invltlb(); 1707} 1708 1709void 1710invltlb(void) 1711{ 1712 u_long temp; 1713 1714 /* 1715 * This should be implemented as load_cr3(rcr3()) when load_cr3() is 1716 * inlined. 1717 */ 1718 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory"); 1719 1720 /* send a message to the other CPUs */ 1721 smp_invltlb(); 1722} 1723 1724 1725#if defined(TEST_CPUSTOP) 1726 1727/* 1728 * When called the executing CPU will send an IPI to all other CPUs 1729 * requesting that they halt execution. 1730 * 1731 * Usually (but not necessarily) called with 'other_cpus' as its arg. 1732 * 1733 * - Signals all CPUs in map to stop. 1734 * - Waits for each to stop. 1735 * 1736 * Returns: 1737 * -1: error 1738 * 0: NA 1739 * 1: ok 1740 * 1741 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs 1742 * from executing at same time. 1743 1744 */ 1745int 1746stop_cpus( u_int map ) 1747{ 1748 if (!smp_active) 1749 return 0; 1750 1751 stopped_cpus = 0; 1752 1753 /* send IPI to all CPUs in map */ 1754#if defined(DEBUG_CPUSTOP) 1755 db_printf("\nCPU%d stopping CPUs: 0x%08x\n", cpuid, map); 1756#endif /* DEBUG_CPUSTOP */ 1757#if 0 1758 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED); 1759#else 1760 all_but_self_ipi(XCPUSTOP_OFFSET); 1761#endif 1762 1763#if defined(DEBUG_CPUSTOP) 1764 db_printf(" stopped_cpus: 0x%08x, map: 0x%08x, spin\n", 1765 stopped_cpus, map); 1766#endif /* DEBUG_CPUSTOP */ 1767 1768 while (stopped_cpus != map) { 1769#if 0 1770 /* spin */ ; 1771#else 1772 POSTCODE(stopped_cpus & 0xff); 1773#endif 1774 } 1775 1776#if defined(DEBUG_CPUSTOP) 1777 db_printf(" spun\nstopped\n"); 1778#endif /* DEBUG_CPUSTOP */ 1779 1780 return 1; 1781} 1782 1783 1784/* 1785 * Called by a CPU to restart stopped CPUs. 1786 * 1787 * Usually (but not necessarily) called with 'stopped_cpus' as its arg. 1788 * 1789 * - Signals all CPUs in map to restart. 1790 * - Waits for each to restart. 1791 * 1792 * Returns: 1793 * -1: error 1794 * 0: NA 1795 * 1: ok 1796 */ 1797int 1798restart_cpus( u_int map ) 1799{ 1800 if (!smp_active) 1801 return 0; 1802 1803 started_cpus = map; /* signal other cpus to restart */ 1804 1805#if defined(DEBUG_CPUSTOP) 1806 db_printf("\nCPU%d restarting CPUs: 0x%08x (0x%08x)\n", 1807 cpuid, started_cpus, stopped_cpus); 1808#endif /* DEBUG_CPUSTOP */ 1809 1810 while (started_cpus) /* wait for each to clear its bit */ 1811 /* spin */ ; 1812 1813#if defined(DEBUG_CPUSTOP) 1814 db_printf(" restarted\n"); 1815#endif /* DEBUG_CPUSTOP */ 1816 1817 return 1; 1818} 1819 1820#endif /* TEST_CPUSTOP */ 1821