mptable.c revision 26950
1/*
2 * Copyright (c) 1996, by Steve Passe
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 *    derived from this software without specific prior written permission.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 *	$Id: mp_machdep.c,v 1.4 1997/06/25 20:44:00 smp Exp smp $
26 */
27
28#include "opt_smp.h"
29
30#include <sys/param.h>		/* for KERNBASE */
31#include <sys/types.h>
32#include <sys/sysproto.h>
33#include <sys/time.h>
34#include <sys/systm.h>
35
36#include <vm/vm.h>		/* for KERNBASE */
37#include <vm/vm_param.h>	/* for KERNBASE */
38#include <vm/pmap.h>		/* for KERNBASE */
39#include <machine/pmap.h>	/* for KERNBASE */
40#include <vm/vm_kern.h>
41#include <vm/vm_extern.h>
42
43#include <machine/smp.h>
44#include <machine/apic.h>
45#include <machine/mpapic.h>
46#include <machine/cpufunc.h>
47#include <machine/segments.h>
48#include <machine/smptests.h>	/** TEST_DEFAULT_CONFIG */
49#include <machine/tss.h>
50#include <machine/specialreg.h>
51
52#include <i386/i386/cons.h>	/* cngetc() */
53
54#if defined(APIC_IO)
55#include <machine/md_var.h>	/* setidt() */
56#include <i386/isa/icu.h>		/* Xinvltlb() */
57#include <i386/isa/intr_machdep.h>	/* Xinvltlb() */
58#endif	/* APIC_IO */
59
60#define WARMBOOT_TARGET	0
61#define WARMBOOT_OFF	(KERNBASE + 0x0467)
62#define WARMBOOT_SEG	(KERNBASE + 0x0469)
63
64#define BIOS_BASE	(0xf0000)
65#define BIOS_SIZE	(0x10000)
66#define BIOS_COUNT	(BIOS_SIZE/4)
67
68#define CMOS_REG	(0x70)
69#define CMOS_DATA	(0x71)
70#define BIOS_RESET	(0x0f)
71#define BIOS_WARM	(0x0a)
72
73#define PROCENTRY_FLAG_EN	0x01
74#define PROCENTRY_FLAG_BP	0x02
75#define IOAPICENTRY_FLAG_EN	0x01
76
77/* MP Floating Pointer Structure */
78typedef struct MPFPS {
79	char    signature[4];
80	void   *pap;
81	u_char  length;
82	u_char  spec_rev;
83	u_char  checksum;
84	u_char  mpfb1;
85	u_char  mpfb2;
86	u_char  mpfb3;
87	u_char  mpfb4;
88	u_char  mpfb5;
89}      *mpfps_t;
90
91/* MP Configuration Table Header */
92typedef struct MPCTH {
93	char    signature[4];
94	u_short base_table_length;
95	u_char  spec_rev;
96	u_char  checksum;
97	u_char  oem_id[8];
98	u_char  product_id[12];
99	void   *oem_table_pointer;
100	u_short oem_table_size;
101	u_short entry_count;
102	void   *apic_address;
103	u_short extended_table_length;
104	u_char  extended_table_checksum;
105	u_char  reserved;
106}      *mpcth_t;
107
108
109typedef struct PROCENTRY {
110	u_char  type;
111	u_char  apic_id;
112	u_char  apic_version;
113	u_char  cpu_flags;
114	u_long  cpu_signature;
115	u_long  feature_flags;
116	u_long  reserved1;
117	u_long  reserved2;
118}      *proc_entry_ptr;
119
120typedef struct BUSENTRY {
121	u_char  type;
122	u_char  bus_id;
123	char    bus_type[6];
124}      *bus_entry_ptr;
125
126typedef struct IOAPICENTRY {
127	u_char  type;
128	u_char  apic_id;
129	u_char  apic_version;
130	u_char  apic_flags;
131	void   *apic_address;
132}      *io_apic_entry_ptr;
133
134typedef struct INTENTRY {
135	u_char  type;
136	u_char  int_type;
137	u_short int_flags;
138	u_char  src_bus_id;
139	u_char  src_bus_irq;
140	u_char  dst_apic_id;
141	u_char  dst_apic_int;
142}      *int_entry_ptr;
143
144/* descriptions of MP basetable entries */
145typedef struct BASETABLE_ENTRY {
146	u_char  type;
147	u_char  length;
148	char    name[16];
149}       basetable_entry;
150
151/*
152 * this code MUST be enabled here and in mpboot.s.
153 * it follows the very early stages of AP boot by placing values in CMOS ram.
154 * it NORMALLY will never be needed and thus the primitive method for enabling.
155 *
156#define CHECK_POINTS
157 */
158
159#if defined(CHECK_POINTS)
160#define CHECK_READ(A)	 (outb(CMOS_REG, (A)), inb(CMOS_DATA))
161#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
162
163#define CHECK_INIT(D);				\
164	CHECK_WRITE(0x34, (D));			\
165	CHECK_WRITE(0x35, (D));			\
166	CHECK_WRITE(0x36, (D));			\
167	CHECK_WRITE(0x37, (D));			\
168	CHECK_WRITE(0x38, (D));			\
169	CHECK_WRITE(0x39, (D));
170
171#define CHECK_PRINT(S);				\
172	printf("%s: %d, %d, %d, %d, %d, %d\n",	\
173	   (S),					\
174	   CHECK_READ(0x34),			\
175	   CHECK_READ(0x35),			\
176	   CHECK_READ(0x36),			\
177	   CHECK_READ(0x37),			\
178	   CHECK_READ(0x38),			\
179	   CHECK_READ(0x39));
180
181#else				/* CHECK_POINTS */
182
183#define CHECK_INIT(D)
184#define CHECK_PRINT(S)
185
186#endif				/* CHECK_POINTS */
187
188
189/** FIXME: what system files declare these??? */
190extern struct region_descriptor r_gdt, r_idt;
191
192int	mp_ncpus;		/* # of CPUs, including BSP */
193int	mp_naps;		/* # of Applications processors */
194int	mp_nbusses;		/* # of busses */
195int	mp_napics;		/* # of IO APICs */
196int	boot_cpu_id;		/* designated BSP */
197vm_offset_t cpu_apic_address;
198vm_offset_t io_apic_address[NAPICID];	/* NAPICID is more than enough */
199
200u_int32_t cpu_apic_versions[NCPU];
201u_int32_t io_apic_versions[NAPIC];
202
203/*
204 * APIC ID logical/physical mapping structures.
205 * We oversize these to simplify boot-time config.
206 */
207int     cpu_num_to_apic_id[NAPICID];
208int     io_num_to_apic_id[NAPICID];
209int     apic_id_to_logical[NAPICID];
210
211/* Boot of AP uses this PTD */
212u_int *bootPTD;
213
214/* Hotwire a 0->4MB V==P mapping */
215extern pt_entry_t KPTphys;
216
217/* virtual address of per-cpu common_tss */
218extern struct i386tss common_tss;
219
220/*
221 * look for MP compliant motherboard.
222 */
223
224static int	mp_capable;
225static u_int	boot_address;
226static u_int	base_memory;
227
228static int	picmode;		/* 0: virtual wire mode, 1: PIC mode */
229static mpfps_t	mpfps;
230static int	search_for_sig(u_int32_t target, int count);
231static void	mp_enable(u_int boot_addr);
232
233static int	mptable_pass1(void);
234static int	mptable_pass2(void);
235static void	default_mp_table(int type);
236static int	start_all_aps(u_int boot_addr);
237static void	install_ap_tramp(u_int boot_addr);
238static int	start_ap(int logicalCpu, u_int boot_addr);
239
240
241/*
242 * calculate usable address in base memory for AP trampoline code
243 */
244u_int
245mp_bootaddress(u_int basemem)
246{
247	base_memory = basemem * 1024;	/* convert to bytes */
248
249	boot_address = base_memory & ~0xfff;	/* round down to 4k boundary */
250	if ((base_memory - boot_address) < bootMP_size)
251		boot_address -= 4096;	/* not enough, lower by 4k */
252
253	return boot_address;
254}
255
256
257int
258mp_probe(void)
259{
260	int     x;
261	u_long  segment;
262	u_int32_t target;
263
264	/* see if EBDA exists */
265	if (segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) {
266		/* search first 1K of EBDA */
267		target = (u_int32_t) (segment << 4);
268		if ((x = search_for_sig(target, 1024 / 4)) >= 0)
269			goto found;
270	} else {
271		/* last 1K of base memory, effective 'top of base' passed in */
272		target = (u_int32_t) (base_memory - 0x400);
273		if ((x = search_for_sig(target, 1024 / 4)) >= 0)
274			goto found;
275	}
276
277	/* search the BIOS */
278	target = (u_int32_t) BIOS_BASE;
279	if ((x = search_for_sig(target, BIOS_COUNT)) >= 0)
280		goto found;
281
282	/* nothing found */
283	mpfps = (mpfps_t)0;
284	mp_capable = 0;
285	return 0;
286
287found:				/* please forgive the 'goto'! */
288	/* calculate needed resources */
289	mpfps = (mpfps_t)x;
290	if (mptable_pass1())
291		panic("you must reconfigure your kernel");
292
293	/* flag fact that we are running multiple processors */
294	mp_capable = 1;
295	return 1;
296}
297
298
299/*
300 * startup the SMP processors
301 */
302void
303mp_start(void)
304{
305	/* look for MP capable motherboard */
306	if (mp_capable)
307		mp_enable(boot_address);
308	else
309		panic("MP hardware not found!");
310}
311
312
313/*
314 * print various information about the SMP system hardware and setup
315 */
316void
317mp_announce(void)
318{
319	int     x;
320
321	printf("FreeBSD/SMP: Multiprocessor motherboard\n");
322	printf(" cpu0 (BSP): apic id: %d", CPU_TO_ID(0));
323	printf(", version: 0x%08x", cpu_apic_versions[0]);
324	printf(", at 0x%08x\n", cpu_apic_address);
325	for (x = 1; x <= mp_naps; ++x) {
326		printf(" cpu%d (AP):  apic id: %d", x, CPU_TO_ID(x));
327		printf(", version: 0x%08x", cpu_apic_versions[x]);
328		printf(", at 0x%08x\n", cpu_apic_address);
329	}
330
331#if defined(APIC_IO)
332	for (x = 0; x < mp_napics; ++x) {
333		printf(" io%d (APIC): apic id: %d", x, IO_TO_ID(x));
334		printf(", version: 0x%08x", io_apic_versions[x]);
335		printf(", at 0x%08x\n", io_apic_address[x]);
336	}
337#else
338	printf(" Warning: APIC I/O disabled\n");
339#endif	/* APIC_IO */
340}
341
342/*
343 * AP cpu's call this to sync up protected mode.
344 */
345void
346init_secondary(void)
347{
348	int     gsel_tss, slot;
349
350	r_gdt.rd_limit = sizeof(gdt[0]) * (NGDT + NCPU) - 1;
351	r_gdt.rd_base = (int) gdt;
352	lgdt(&r_gdt);		/* does magic intra-segment return */
353	lidt(&r_idt);
354	lldt(_default_ldt);
355
356	slot = NGDT + cpuid;
357	gsel_tss = GSEL(slot, SEL_KPL);
358	gdt[slot].sd.sd_type = SDT_SYS386TSS;
359	common_tss.tss_esp0 = 0;	/* not used until after switch */
360	common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
361	common_tss.tss_ioopt = (sizeof common_tss) << 16;
362	ltr(gsel_tss);
363
364	load_cr0(0x8005003b);	/* XXX! */
365
366	PTD[0] = 0;
367	invltlb();
368}
369
370
371#if defined(APIC_IO)
372void
373configure_local_apic(void)
374{
375	u_char  byte;
376	u_int32_t temp;
377
378	if (picmode) {
379		outb(0x22, 0x70);	/* select IMCR */
380		byte = inb(0x23);	/* current contents */
381		byte |= 0x01;	/* mask external INTR */
382		outb(0x23, byte);	/* disconnect 8259s/NMI */
383	}
384	/* mask the LVT1 */
385	temp = lapic.lvt_lint0;
386	temp |= APIC_LVT_M;
387	lapic.lvt_lint0 = temp;
388}
389#endif	/* APIC_IO */
390
391
392/*******************************************************************
393 * local functions and data
394 */
395
396/*
397 * start the SMP system
398 */
399static void
400mp_enable(u_int boot_addr)
401{
402	int     x;
403#if defined(APIC_IO)
404	int     apic;
405	u_int   ux;
406#endif	/* APIC_IO */
407
408	/* Turn on 4MB of V == P addressing so we can get to MP table */
409	*(int *)PTD = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME);
410	invltlb();
411
412	/* examine the MP table for needed info, uses physical addresses */
413	x = mptable_pass2();
414
415	*(int *)PTD = 0;
416	invltlb();
417
418	/* can't process default configs till the CPU APIC is pmapped */
419	if (x)
420		default_mp_table(x);
421
422#if defined(APIC_IO)
423	/* fill the LOGICAL io_apic_versions table */
424	for (apic = 0; apic < mp_napics; ++apic) {
425		ux = io_apic_read(apic, IOAPIC_VER);
426		io_apic_versions[apic] = ux;
427	}
428
429	/* program each IO APIC in the system */
430	for (apic = 0; apic < mp_napics; ++apic)
431		if (io_apic_setup(apic) < 0)
432			panic("IO APIC setup failure");
433
434	/* install an inter-CPU IPI for TLB invalidation */
435	setidt(ICU_OFFSET + XINVLTLB_OFFSET, Xinvltlb,
436	       SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
437#endif	/* APIC_IO */
438
439	/* start each Application Processor */
440	start_all_aps(boot_addr);
441
442	/*
443	 * The init process might be started on a different CPU now,
444	 * and the boot CPU might not call prepare_usermode to get
445	 * cr0 correctly configured. Thus we initialize cr0 here.
446	 */
447	load_cr0(rcr0() | CR0_WP | CR0_AM);
448}
449
450
451/*
452 * look for the MP spec signature
453 */
454
455/* string defined by the Intel MP Spec as identifying the MP table */
456#define MP_SIG		0x5f504d5f	/* _MP_ */
457#define NEXT(X)		((X) += 4)
458static int
459search_for_sig(u_int32_t target, int count)
460{
461	int     x;
462	u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
463
464	for (x = 0; x < count; NEXT(x))
465		if (addr[x] == MP_SIG)
466			/* make array index a byte index */
467			return (target + (x * sizeof(u_int32_t)));
468
469	return -1;
470}
471
472
473static basetable_entry basetable_entry_types[] =
474{
475	{0, 20, "Processor"},
476	{1, 8, "Bus"},
477	{2, 8, "I/O APIC"},
478	{3, 8, "I/O INT"},
479	{4, 8, "Local INT"}
480};
481
482typedef struct BUSDATA {
483	u_char  bus_id;
484	enum busTypes bus_type;
485}       bus_datum;
486
487typedef struct INTDATA {
488	u_char  int_type;
489	u_short int_flags;
490	u_char  src_bus_id;
491	u_char  src_bus_irq;
492	u_char  dst_apic_id;
493	u_char  dst_apic_int;
494}       io_int, local_int;
495
496typedef struct BUSTYPENAME {
497	u_char  type;
498	char    name[7];
499}       bus_type_name;
500
501static bus_type_name bus_type_table[] =
502{
503	{CBUS, "CBUS"},
504	{CBUSII, "CBUSII"},
505	{EISA, "EISA"},
506	{UNKNOWN_BUSTYPE, "---"},
507	{UNKNOWN_BUSTYPE, "---"},
508	{ISA, "ISA"},
509	{UNKNOWN_BUSTYPE, "---"},
510	{UNKNOWN_BUSTYPE, "---"},
511	{UNKNOWN_BUSTYPE, "---"},
512	{UNKNOWN_BUSTYPE, "---"},
513	{UNKNOWN_BUSTYPE, "---"},
514	{UNKNOWN_BUSTYPE, "---"},
515	{PCI, "PCI"},
516	{UNKNOWN_BUSTYPE, "---"},
517	{UNKNOWN_BUSTYPE, "---"},
518	{UNKNOWN_BUSTYPE, "---"},
519	{UNKNOWN_BUSTYPE, "---"},
520	{XPRESS, "XPRESS"},
521	{UNKNOWN_BUSTYPE, "---"}
522};
523/* from MP spec v1.4, table 5-1 */
524static int default_data[7][5] =
525{
526/*   nbus, id0, type0, id1, type1 */
527	{1, 0, ISA, 255, 255},
528	{1, 0, EISA, 255, 255},
529	{1, 0, EISA, 255, 255},
530	{0, 255, 255, 255, 255},/* MCA not supported */
531	{2, 0, ISA, 1, PCI},
532	{2, 0, EISA, 1, PCI},
533	{0, 255, 255, 255, 255}	/* MCA not supported */
534};
535
536
537/* the bus data */
538bus_datum bus_data[NBUS];
539
540/* the IO INT data, one entry per possible APIC INTerrupt */
541io_int  io_apic_ints[NINTR];
542
543static int nintrs;
544
545static void fix_mp_table	__P((void));
546static int processor_entry	__P((proc_entry_ptr entry, int cpu));
547static int bus_entry		__P((bus_entry_ptr entry, int bus));
548static int io_apic_entry	__P((io_apic_entry_ptr entry, int apic));
549static int int_entry		__P((int_entry_ptr entry, int intr));
550static int lookup_bus_type	__P((char *name));
551
552
553/*
554 * 1st pass on motherboard's Intel MP specification table.
555 *
556 * initializes:
557 *	mp_ncpus = 1
558 *
559 * determines:
560 *	cpu_apic_address (common to all CPUs)
561 *	io_apic_address[N]
562 *	mp_naps
563 *	mp_nbusses
564 *	mp_napics
565 *	nintrs
566 */
567static int
568mptable_pass1(void)
569{
570	int	x;
571	mpcth_t	cth;
572	int	totalSize;
573	void*	position;
574	int	count;
575	int	type;
576	int	mustpanic;
577
578	mustpanic = 0;
579
580	/* clear various tables */
581	for (x = 0; x < NAPICID; ++x) {
582		io_apic_address[x] = ~0;	/* IO APIC address table */
583	}
584
585	/* init everything to empty */
586	mp_naps = 0;
587	mp_nbusses = 0;
588	mp_napics = 0;
589	nintrs = 0;
590
591	/* check for use of 'default' configuration */
592	if (mpfps->mpfb1 != 0) {
593		/* use default addresses */
594		cpu_apic_address = DEFAULT_APIC_BASE;
595		io_apic_address[0] = DEFAULT_IO_APIC_BASE;
596
597		/* fill in with defaults */
598		mp_naps = 2;		/* includes BSP */
599		mp_nbusses = default_data[mpfps->mpfb1 - 1][0];
600#if defined(APIC_IO)
601		mp_napics = 1;
602		nintrs = 16;
603#endif	/* APIC_IO */
604	}
605	else {
606		if ((cth = mpfps->pap) == 0)
607			panic("MP Configuration Table Header MISSING!");
608
609		cpu_apic_address = (vm_offset_t) cth->apic_address;
610
611		/* walk the table, recording info of interest */
612		totalSize = cth->base_table_length - sizeof(struct MPCTH);
613		position = (u_char *) cth + sizeof(struct MPCTH);
614		count = cth->entry_count;
615
616		while (count--) {
617			switch (type = *(u_char *) position) {
618			case 0: /* processor_entry */
619				if (((proc_entry_ptr)position)->cpu_flags
620					& PROCENTRY_FLAG_EN)
621					++mp_naps;
622				break;
623			case 1: /* bus_entry */
624				++mp_nbusses;
625				break;
626			case 2: /* io_apic_entry */
627				if (((io_apic_entry_ptr)position)->apic_flags
628					& IOAPICENTRY_FLAG_EN)
629					io_apic_address[mp_napics++] =
630					    (vm_offset_t)((io_apic_entry_ptr)
631						position)->apic_address;
632				break;
633			case 3: /* int_entry */
634				++nintrs;
635				break;
636			case 4:	/* int_entry */
637				break;
638			default:
639				panic("mpfps Base Table HOSED!");
640				/* NOTREACHED */
641			}
642
643			totalSize -= basetable_entry_types[type].length;
644			(u_char*)position += basetable_entry_types[type].length;
645		}
646	}
647
648	/* qualify the numbers */
649	if (mp_naps > NCPU)
650		printf("Warning: only using %d of %d available CPUs!\n",
651			NCPU, mp_naps);
652#if 0
653		/** XXX we consider this legal now (but should we?) */
654		mustpanic = 1;
655#endif
656	if (mp_nbusses > NBUS) {
657		printf("found %d busses, increase NBUS\n", mp_nbusses);
658		mustpanic = 1;
659	}
660	if (mp_napics > NAPIC) {
661		printf("found %d apics, increase NAPIC\n", mp_napics);
662		mustpanic = 1;
663	}
664	if (nintrs > NINTR) {
665		printf("found %d intrs, increase NINTR\n", nintrs);
666		mustpanic = 1;
667	}
668
669	/*
670	 * Count the BSP.
671	 * This is also used as a counter while starting the APs.
672	 */
673	mp_ncpus = 1;
674
675	--mp_naps;	/* subtract the BSP */
676
677	return mustpanic;
678}
679
680
681/*
682 * 2nd pass on motherboard's Intel MP specification table.
683 *
684 * sets:
685 *	boot_cpu_id
686 *	ID_TO_IO(N), phy APIC ID to log CPU/IO table
687 *	CPU_TO_ID(N), logical CPU to APIC ID table
688 *	IO_TO_ID(N), logical IO to APIC ID table
689 *	bus_data[N]
690 *	io_apic_ints[N]
691 */
692static int
693mptable_pass2(void)
694{
695	int     x;
696	mpcth_t cth;
697	int     totalSize;
698	void*   position;
699	int     count;
700	int     type;
701	int     apic, bus, cpu, intr;
702
703	/* clear various tables */
704	for (x = 0; x < NAPICID; ++x) {
705		ID_TO_IO(x) = -1;	/* phy APIC ID to log CPU/IO table */
706		CPU_TO_ID(x) = -1;	/* logical CPU to APIC ID table */
707		IO_TO_ID(x) = -1;	/* logical IO to APIC ID table */
708	}
709
710	/* clear bus data table */
711	for (x = 0; x < NBUS; ++x)
712		bus_data[x].bus_id = 0xff;
713
714	/* clear IO APIC INT table */
715	for (x = 0; x < NINTR; ++x)
716		io_apic_ints[x].int_type = 0xff;
717
718	/* setup the cpu/apic mapping arrays */
719	boot_cpu_id = -1;
720
721	/* record whether PIC or virtual-wire mode */
722	picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0;
723
724	/* check for use of 'default' configuration */
725#if defined(TEST_DEFAULT_CONFIG)
726	return TEST_DEFAULT_CONFIG;
727#else
728	if (mpfps->mpfb1 != 0)
729		return mpfps->mpfb1;	/* return default configuration type */
730#endif	/* TEST_DEFAULT_CONFIG */
731
732	if ((cth = mpfps->pap) == 0)
733		panic("MP Configuration Table Header MISSING!");
734
735	/* walk the table, recording info of interest */
736	totalSize = cth->base_table_length - sizeof(struct MPCTH);
737	position = (u_char *) cth + sizeof(struct MPCTH);
738	count = cth->entry_count;
739	apic = bus = intr = 0;
740	cpu = 1;				/* pre-count the BSP */
741
742	while (count--) {
743		switch (type = *(u_char *) position) {
744		case 0:
745			if (processor_entry(position, cpu))
746				++cpu;
747			break;
748		case 1:
749			if (bus_entry(position, bus))
750				++bus;
751			break;
752		case 2:
753			if (io_apic_entry(position, apic))
754				++apic;
755			break;
756		case 3:
757			if (int_entry(position, intr))
758				++intr;
759			break;
760		case 4:
761			/* int_entry(position); */
762			break;
763		default:
764			panic("mpfps Base Table HOSED!");
765			/* NOTREACHED */
766		}
767
768		totalSize -= basetable_entry_types[type].length;
769		(u_char *) position += basetable_entry_types[type].length;
770	}
771
772	if (boot_cpu_id == -1)
773		panic("NO BSP found!");
774
775	/* post scan cleanup */
776	fix_mp_table();
777
778	/* report fact that its NOT a default configuration */
779	return 0;
780}
781
782
783/*
784 * parse an Intel MP specification table
785 */
786static void
787fix_mp_table(void)
788{
789	int	x;
790	int	id;
791	int	bus_0;
792	int	bus_pci;
793	int	num_pci_bus;
794
795	/*
796	 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
797	 * did it wrong.  The MP spec says that when more than 1 PCI bus
798	 * exists the BIOS must begin with bus entries for the PCI bus and use
799	 * actual PCI bus numbering.  This implies that when only 1 PCI bus
800	 * exists the BIOS can choose to ignore this ordering, and indeed many
801	 * MP motherboards do ignore it.  This causes a problem when the PCI
802	 * sub-system makes requests of the MP sub-system based on PCI bus
803	 * numbers.	So here we look for the situation and renumber the
804	 * busses and associated INTs in an effort to "make it right".
805	 */
806
807	/* find bus 0, PCI bus, count the number of PCI busses */
808	for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
809		if (bus_data[x].bus_id == 0) {
810			bus_0 = x;
811		}
812		if (bus_data[x].bus_type == PCI) {
813			++num_pci_bus;
814			bus_pci = x;
815		}
816	}
817	/*
818	 * bus_0 == slot of bus with ID of 0
819	 * bus_pci == slot of last PCI bus encountered
820	 */
821
822	/* check the 1 PCI bus case for sanity */
823	if (num_pci_bus == 1) {
824
825		/* if it is number 0 all is well */
826		if (bus_data[bus_pci].bus_id == 0)
827			return;
828
829		/* mis-numbered, swap with whichever bus uses slot 0 */
830
831		/* swap the bus entry types */
832		bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
833		bus_data[bus_0].bus_type = PCI;
834
835		/* swap each relavant INTerrupt entry */
836		id = bus_data[bus_pci].bus_id;
837		for (x = 0; x < nintrs; ++x) {
838			if (io_apic_ints[x].src_bus_id == id) {
839				io_apic_ints[x].src_bus_id = 0;
840			}
841			else if (io_apic_ints[x].src_bus_id == 0) {
842				io_apic_ints[x].src_bus_id = id;
843			}
844		}
845	}
846	/* sanity check if more than 1 PCI bus */
847	else if (num_pci_bus > 1) {
848		for (x = 0; x < mp_nbusses; ++x) {
849			if (bus_data[x].bus_type != PCI)
850				continue;
851			if (bus_data[x].bus_id >= num_pci_bus)
852				panic("bad PCI bus numbering");
853		}
854	}
855}
856
857
858static int
859processor_entry(proc_entry_ptr entry, int cpu)
860{
861	/* check for usability */
862	if ((cpu >= NCPU) || !(entry->cpu_flags & PROCENTRY_FLAG_EN))
863		return 0;
864
865	/* check for BSP flag */
866	if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
867		boot_cpu_id = entry->apic_id;
868		CPU_TO_ID(0) = entry->apic_id;
869		ID_TO_CPU(entry->apic_id) = 0;
870		return 0;	/* its already been counted */
871	}
872
873	/* add another AP to list, if less than max number of CPUs */
874	else {
875		CPU_TO_ID(cpu) = entry->apic_id;
876		ID_TO_CPU(entry->apic_id) = cpu;
877		return 1;
878	}
879}
880
881
882static int
883bus_entry(bus_entry_ptr entry, int bus)
884{
885	int     x;
886	char    c, name[8];
887
888	/* encode the name into an index */
889	for (x = 0; x < 6; ++x) {
890		if ((c = entry->bus_type[x]) == ' ')
891			break;
892		name[x] = c;
893	}
894	name[x] = '\0';
895
896	if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
897		panic("unknown bus type: '%s'", name);
898
899	bus_data[bus].bus_id = entry->bus_id;
900	bus_data[bus].bus_type = x;
901
902	return 1;
903}
904
905
906static int
907io_apic_entry(io_apic_entry_ptr entry, int apic)
908{
909	if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
910		return 0;
911
912	IO_TO_ID(apic) = entry->apic_id;
913	ID_TO_IO(entry->apic_id) = apic;
914
915	return 1;
916}
917
918
919static int
920lookup_bus_type(char *name)
921{
922	int     x;
923
924	for (x = 0; x < MAX_BUSTYPE; ++x)
925		if (strcmp(bus_type_table[x].name, name) == 0)
926			return bus_type_table[x].type;
927
928	return UNKNOWN_BUSTYPE;
929}
930
931
932static int
933int_entry(int_entry_ptr entry, int intr)
934{
935	io_apic_ints[intr].int_type = entry->int_type;
936	io_apic_ints[intr].int_flags = entry->int_flags;
937	io_apic_ints[intr].src_bus_id = entry->src_bus_id;
938	io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
939	io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
940	io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
941
942	return 1;
943}
944
945
946static int
947apic_int_is_bus_type(int intr, int bus_type)
948{
949	int     bus;
950
951	for (bus = 0; bus < mp_nbusses; ++bus)
952		if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
953		    && ((int) bus_data[bus].bus_type == bus_type))
954			return 1;
955
956	return 0;
957}
958
959
960/*
961 * Given a traditional ISA INT mask, return an APIC mask.
962 */
963u_int
964isa_apic_mask(u_int isa_mask)
965{
966	int isa_irq;
967	int apic_pin;
968
969	isa_irq = ffs(isa_mask);		/* find its bit position */
970	if (isa_irq == 0)			/* doesn't exist */
971		return 0;
972	--isa_irq;				/* make it zero based */
973
974	apic_pin = isa_apic_pin(isa_irq);	/* look for APIC connection */
975	if (apic_pin == -1)
976		return 0;
977
978	return (1 << apic_pin);			/* convert pin# to a mask */
979}
980
981
982/*
983 * Determine which APIC pin an ISA/EISA INT is attached to.
984 */
985#define INTTYPE(I)	(io_apic_ints[(I)].int_type)
986#define INTPIN(I)	(io_apic_ints[(I)].dst_apic_int)
987
988#define SRCBUSIRQ(I)	(io_apic_ints[(I)].src_bus_irq)
989int
990isa_apic_pin(int isa_irq)
991{
992	int     intr;
993
994#if defined(SMP_TIMER_NC)
995	if (isa_irq == 0)
996		return -1;
997#endif	/* SMP_TIMER_NC */
998
999	for (intr = 0; intr < nintrs; ++intr) {		/* check each record */
1000		if (INTTYPE(intr) == 0) {		/* standard INT */
1001			if (SRCBUSIRQ(intr) == isa_irq) {
1002				if (apic_int_is_bus_type(intr, ISA) ||
1003			            apic_int_is_bus_type(intr, EISA))
1004					return INTPIN(intr);	/* found */
1005			}
1006		}
1007	}
1008	return -1;					/* NOT found */
1009}
1010#undef SRCBUSIRQ
1011
1012
1013/*
1014 * Determine which APIC pin a PCI INT is attached to.
1015 */
1016#define SRCBUSID(I)	(io_apic_ints[(I)].src_bus_id)
1017#define SRCBUSDEVICE(I)	((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1018#define SRCBUSLINE(I)	(io_apic_ints[(I)].src_bus_irq & 0x03)
1019int
1020pci_apic_pin(int pciBus, int pciDevice, int pciInt)
1021{
1022	int     intr;
1023
1024	--pciInt;					/* zero based */
1025
1026	for (intr = 0; intr < nintrs; ++intr)		/* check each record */
1027		if ((INTTYPE(intr) == 0)		/* standard INT */
1028		    && (SRCBUSID(intr) == pciBus)
1029		    && (SRCBUSDEVICE(intr) == pciDevice)
1030		    && (SRCBUSLINE(intr) == pciInt))	/* a candidate IRQ */
1031			if (apic_int_is_bus_type(intr, PCI))
1032				return INTPIN(intr);	/* exact match */
1033
1034	return -1;					/* NOT found */
1035}
1036#undef SRCBUSLINE
1037#undef SRCBUSDEVICE
1038#undef SRCBUSID
1039
1040#undef INTPIN
1041#undef INTTYPE
1042
1043
1044/*
1045 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1046 *
1047 * XXX FIXME:
1048 *  Exactly what this means is unclear at this point.  It is a solution
1049 *  for motherboards that redirect the MBIRQ0 pin.  Generically a motherboard
1050 *  could route any of the ISA INTs to upper (>15) IRQ values.  But most would
1051 *  NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1052 *  option.
1053 */
1054int
1055undirect_isa_irq(int rirq)
1056{
1057#if defined(READY)
1058	printf("Freeing redirected ISA irq %d.\n", rirq);
1059	/** FIXME: tickle the MB redirector chip */
1060	return ???;
1061#else
1062	printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1063	return 0;
1064#endif  /* READY */
1065}
1066
1067
1068/*
1069 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1070 */
1071int
1072undirect_pci_irq(int rirq)
1073{
1074#if defined(READY)
1075	if (bootverbose)
1076		printf("Freeing redirected PCI irq %d.\n", rirq);
1077
1078	/** FIXME: tickle the MB redirector chip */
1079	return ???;
1080#else
1081	if (bootverbose)
1082		printf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1083		       rirq);
1084	return 0;
1085#endif  /* READY */
1086}
1087
1088
1089/*
1090 * given a bus ID, return:
1091 *  the bus type if found
1092 *  -1 if NOT found
1093 */
1094int
1095apic_bus_type(int id)
1096{
1097	int     x;
1098
1099	for (x = 0; x < mp_nbusses; ++x)
1100		if (bus_data[x].bus_id == id)
1101			return bus_data[x].bus_type;
1102
1103	return -1;
1104}
1105
1106
1107/*
1108 * given a LOGICAL APIC# and pin#, return:
1109 *  the associated src bus ID if found
1110 *  -1 if NOT found
1111 */
1112int
1113apic_src_bus_id(int apic, int pin)
1114{
1115	int     x;
1116
1117	/* search each of the possible INTerrupt sources */
1118	for (x = 0; x < nintrs; ++x)
1119		if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1120		    (pin == io_apic_ints[x].dst_apic_int))
1121			return (io_apic_ints[x].src_bus_id);
1122
1123	return -1;		/* NOT found */
1124}
1125
1126
1127/*
1128 * given a LOGICAL APIC# and pin#, return:
1129 *  the associated src bus IRQ if found
1130 *  -1 if NOT found
1131 */
1132int
1133apic_src_bus_irq(int apic, int pin)
1134{
1135	int     x;
1136
1137	for (x = 0; x < nintrs; x++)
1138		if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1139		    (pin == io_apic_ints[x].dst_apic_int))
1140			return (io_apic_ints[x].src_bus_irq);
1141
1142	return -1;		/* NOT found */
1143}
1144
1145
1146/*
1147 * given a LOGICAL APIC# and pin#, return:
1148 *  the associated INTerrupt type if found
1149 *  -1 if NOT found
1150 */
1151int
1152apic_int_type(int apic, int pin)
1153{
1154	int     x;
1155
1156	/* search each of the possible INTerrupt sources */
1157	for (x = 0; x < nintrs; ++x)
1158		if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1159		    (pin == io_apic_ints[x].dst_apic_int))
1160			return (io_apic_ints[x].int_type);
1161
1162	return -1;		/* NOT found */
1163}
1164
1165
1166/*
1167 * given a LOGICAL APIC# and pin#, return:
1168 *  the associated trigger mode if found
1169 *  -1 if NOT found
1170 */
1171int
1172apic_trigger(int apic, int pin)
1173{
1174	int     x;
1175
1176	/* search each of the possible INTerrupt sources */
1177	for (x = 0; x < nintrs; ++x)
1178		if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1179		    (pin == io_apic_ints[x].dst_apic_int))
1180			return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1181
1182	return -1;		/* NOT found */
1183}
1184
1185
1186/*
1187 * given a LOGICAL APIC# and pin#, return:
1188 *  the associated 'active' level if found
1189 *  -1 if NOT found
1190 */
1191int
1192apic_polarity(int apic, int pin)
1193{
1194	int     x;
1195
1196	/* search each of the possible INTerrupt sources */
1197	for (x = 0; x < nintrs; ++x)
1198		if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1199		    (pin == io_apic_ints[x].dst_apic_int))
1200			return (io_apic_ints[x].int_flags & 0x03);
1201
1202	return -1;		/* NOT found */
1203}
1204
1205
1206/*
1207 * set data according to MP defaults
1208 * FIXME: probably not complete yet...
1209 */
1210static void
1211default_mp_table(int type)
1212{
1213	int     ap_cpu_id;
1214#if defined(APIC_IO)
1215	u_int32_t ux;
1216	int     io_apic_id;
1217	int     pin;
1218#endif	/* APIC_IO */
1219
1220#if 0
1221	printf("  MP default config type: %d\n", type);
1222	switch (type) {
1223	case 1:
1224		printf("   bus: ISA, APIC: 82489DX\n");
1225		break;
1226	case 2:
1227		printf("   bus: EISA, APIC: 82489DX\n");
1228		break;
1229	case 3:
1230		printf("   bus: EISA, APIC: 82489DX\n");
1231		break;
1232	case 4:
1233		printf("   bus: MCA, APIC: 82489DX\n");
1234		break;
1235	case 5:
1236		printf("   bus: ISA+PCI, APIC: Integrated\n");
1237		break;
1238	case 6:
1239		printf("   bus: EISA+PCI, APIC: Integrated\n");
1240		break;
1241	case 7:
1242		printf("   bus: MCA+PCI, APIC: Integrated\n");
1243		break;
1244	default:
1245		printf("   future type\n");
1246		break;
1247		/* NOTREACHED */
1248	}
1249#endif	/* 0 */
1250
1251	boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24;
1252	ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1253
1254	/* BSP */
1255	CPU_TO_ID(0) = boot_cpu_id;
1256	ID_TO_CPU(boot_cpu_id) = 0;
1257
1258	/* one and only AP */
1259	CPU_TO_ID(1) = ap_cpu_id;
1260	ID_TO_CPU(ap_cpu_id) = 1;
1261
1262#if defined(APIC_IO)
1263	/* one and only IO APIC */
1264	io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1265
1266	/*
1267	 * sanity check, refer to MP spec section 3.6.6, last paragraph
1268	 * necessary as some hardware isn't properly setting up the IO APIC
1269	 */
1270#if defined(REALLY_ANAL_IOAPICID_VALUE)
1271	if (io_apic_id != 2) {
1272#else
1273	if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1274#endif	/* REALLY_ANAL_IOAPICID_VALUE */
1275		ux = io_apic_read(0, IOAPIC_ID);	/* get current contents */
1276		ux &= ~APIC_ID_MASK;	/* clear the ID field */
1277		ux |= 0x02000000;	/* set it to '2' */
1278		io_apic_write(0, IOAPIC_ID, ux);	/* write new value */
1279		ux = io_apic_read(0, IOAPIC_ID);	/* re-read && test */
1280		if ((ux & APIC_ID_MASK) != 0x02000000)
1281			panic("can't control IO APIC ID, reg: 0x%08x", ux);
1282		io_apic_id = 2;
1283	}
1284	IO_TO_ID(0) = io_apic_id;
1285	ID_TO_IO(io_apic_id) = 0;
1286#endif	/* APIC_IO */
1287
1288	/* fill out bus entries */
1289	switch (type) {
1290	case 1:
1291	case 2:
1292	case 3:
1293	case 5:
1294	case 6:
1295		bus_data[0].bus_id = default_data[type - 1][1];
1296		bus_data[0].bus_type = default_data[type - 1][2];
1297		bus_data[1].bus_id = default_data[type - 1][3];
1298		bus_data[1].bus_type = default_data[type - 1][4];
1299		break;
1300
1301	/* case 4: case 7:		   MCA NOT supported */
1302	default:		/* illegal/reserved */
1303		panic("BAD default MP config: %d", type);
1304		/* NOTREACHED */
1305	}
1306
1307#if defined(APIC_IO)
1308	/* general cases from MP v1.4, table 5-2 */
1309	for (pin = 0; pin < 16; ++pin) {
1310		io_apic_ints[pin].int_type = 0;
1311		io_apic_ints[pin].int_flags = 0x05;	/* edge-triggered/active-hi */
1312		io_apic_ints[pin].src_bus_id = 0;
1313		io_apic_ints[pin].src_bus_irq = pin;	/* IRQ2 is caught below */
1314		io_apic_ints[pin].dst_apic_id = io_apic_id;
1315		io_apic_ints[pin].dst_apic_int = pin;	/* 1-to-1 correspondence */
1316	}
1317
1318	/* special cases from MP v1.4, table 5-2 */
1319	if (type == 2) {
1320		io_apic_ints[2].int_type = 0xff;	/* N/C */
1321		io_apic_ints[13].int_type = 0xff;	/* N/C */
1322#if !defined(APIC_MIXED_MODE)
1323		/** FIXME: ??? */
1324		panic("sorry, can't support type 2 default yet");
1325#endif	/* APIC_MIXED_MODE */
1326	}
1327	else
1328		io_apic_ints[2].src_bus_irq = 0;	/* ISA IRQ0 is on APIC INT 2 */
1329
1330	if (type == 7)
1331		io_apic_ints[0].int_type = 0xff;	/* N/C */
1332	else
1333		io_apic_ints[0].int_type = 3;	/* vectored 8259 */
1334#endif	/* APIC_IO */
1335}
1336
1337
1338/*
1339 * start each AP in our list
1340 */
1341static int
1342start_all_aps(u_int boot_addr)
1343{
1344	int     x, i;
1345	u_char  mpbiosreason;
1346	u_long  mpbioswarmvec;
1347	pd_entry_t newptd;
1348	pt_entry_t newpt;
1349	int *newpp;
1350
1351	/**
1352         * NOTE: this needs further thought:
1353         *        where does it get released?
1354         *        should it be set to empy?
1355         *
1356         * get the initial mp_lock with a count of 1 for the BSP
1357         */
1358	mp_lock = 1;	/* this uses a LOGICAL cpu ID, ie BSP == 0 */
1359
1360	/* initialize BSP's local APIC */
1361	apic_initialize(1);
1362
1363	/* install the AP 1st level boot code */
1364	install_ap_tramp(boot_addr);
1365
1366
1367	/* save the current value of the warm-start vector */
1368	mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
1369	outb(CMOS_REG, BIOS_RESET);
1370	mpbiosreason = inb(CMOS_DATA);
1371
1372	/* start each AP */
1373	for (x = 1; x <= mp_naps; ++x) {
1374
1375		/* HACK HACK HACK !!! */
1376
1377		/* alloc new page table directory */
1378		newptd = (pd_entry_t)(kmem_alloc(kernel_map, PAGE_SIZE));
1379
1380		/* clone currently active one (ie: IdlePTD) */
1381		bcopy(PTD, newptd, PAGE_SIZE);	/* inc prv page pde */
1382
1383		/* set up 0 -> 4MB P==V mapping for AP boot */
1384		newptd[0] = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME);
1385
1386		/* store PTD for this AP */
1387		bootPTD = (pd_entry_t)vtophys(newptd);
1388
1389		/* alloc new page table page */
1390		newpt = (pt_entry_t)(kmem_alloc(kernel_map, PAGE_SIZE));
1391
1392		/* set the new PTD's private page to point there */
1393		newptd[MPPTDI] = PG_V | PG_RW | vtophys(newpt);
1394
1395		/* install self referential entry */
1396		newptd[PTDPTDI] = PG_V | PG_RW | vtophys(newptd);
1397
1398		/* get a new private data page */
1399		newpp = (int *)kmem_alloc(kernel_map, PAGE_SIZE);
1400
1401		/* wire it into the private page table page */
1402		newpt[0] = PG_V | PG_RW | vtophys(newpp);
1403
1404		/* wire the ptp into itself for access */
1405		newpt[1] = PG_V | PG_RW | vtophys(newpt);
1406
1407		/* and the local apic */
1408		newpt[2] = SMP_prvpt[2];
1409
1410		/* and the IO apic mapping[s] */
1411		for (i = 16; i < 32; i++)
1412			newpt[i] = SMP_prvpt[i];
1413
1414		/* prime data page for it to use */
1415		newpp[0] = x;		/* cpuid */
1416		newpp[1] = 0;		/* curproc */
1417		newpp[2] = 0;		/* curpcb */
1418		newpp[3] = 0;		/* npxproc */
1419		newpp[4] = 0;		/* runtime.tv_sec */
1420		newpp[5] = 0;		/* runtime.tv_usec */
1421		newpp[6] = x << 24;	/* cpu_lockid */
1422
1423		/* XXX NOTE: ABANDON bootPTD for now!!!! */
1424
1425		/* END REVOLTING HACKERY */
1426
1427		/* setup a vector to our boot code */
1428		*((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
1429		*((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
1430		outb(CMOS_REG, BIOS_RESET);
1431		outb(CMOS_DATA, BIOS_WARM);	/* 'warm-start' */
1432
1433		/* attempt to start the Application Processor */
1434		CHECK_INIT(99);	/* setup checkpoints */
1435		if (!start_ap(x, boot_addr)) {
1436			printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
1437			CHECK_PRINT("trace");	/* show checkpoints */
1438			/* better panic as the AP may be running loose */
1439			printf("panic y/n? [y] ");
1440			if (cngetc() != 'n')
1441				panic("bye-bye");
1442		}
1443		CHECK_PRINT("trace");	/* show checkpoints */
1444
1445		/* record its version info */
1446		cpu_apic_versions[x] = cpu_apic_versions[0];
1447	}
1448
1449	/* fill in our (BSP) APIC version */
1450	cpu_apic_versions[0] = lapic.version;
1451
1452	/* restore the warmstart vector */
1453	*(u_long *) WARMBOOT_OFF = mpbioswarmvec;
1454	outb(CMOS_REG, BIOS_RESET);
1455	outb(CMOS_DATA, mpbiosreason);
1456
1457	/* number of APs actually started */
1458	return mp_ncpus - 1;
1459}
1460
1461
1462/*
1463 * load the 1st level AP boot code into base memory.
1464 */
1465
1466/* targets for relocation */
1467extern void bigJump(void);
1468extern void bootCodeSeg(void);
1469extern void bootDataSeg(void);
1470extern void MPentry(void);
1471extern u_int MP_GDT;
1472extern u_int mp_gdtbase;
1473
1474static void
1475install_ap_tramp(u_int boot_addr)
1476{
1477	int     x;
1478	int     size = *(int *) ((u_long) & bootMP_size);
1479	u_char *src = (u_char *) ((u_long) bootMP);
1480	u_char *dst = (u_char *) boot_addr + KERNBASE;
1481	u_int   boot_base = (u_int) bootMP;
1482	u_int8_t *dst8;
1483	u_int16_t *dst16;
1484	u_int32_t *dst32;
1485
1486	for (x = 0; x < size; ++x)
1487		*dst++ = *src++;
1488
1489	/*
1490	 * modify addresses in code we just moved to basemem. unfortunately we
1491	 * need fairly detailed info about mpboot.s for this to work.  changes
1492	 * to mpboot.s might require changes here.
1493	 */
1494
1495	/* boot code is located in KERNEL space */
1496	dst = (u_char *) boot_addr + KERNBASE;
1497
1498	/* modify the lgdt arg */
1499	dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
1500	*dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
1501
1502	/* modify the ljmp target for MPentry() */
1503	dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
1504	*dst32 = ((u_int) MPentry - KERNBASE);
1505
1506	/* modify the target for boot code segment */
1507	dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
1508	dst8 = (u_int8_t *) (dst16 + 1);
1509	*dst16 = (u_int) boot_addr & 0xffff;
1510	*dst8 = ((u_int) boot_addr >> 16) & 0xff;
1511
1512	/* modify the target for boot data segment */
1513	dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
1514	dst8 = (u_int8_t *) (dst16 + 1);
1515	*dst16 = (u_int) boot_addr & 0xffff;
1516	*dst8 = ((u_int) boot_addr >> 16) & 0xff;
1517}
1518
1519
1520/*
1521 * this function starts the AP (application processor) identified
1522 * by the APIC ID 'physicalCpu'.  It does quite a "song and dance"
1523 * to accomplish this.  This is necessary because of the nuances
1524 * of the different hardware we might encounter.  It ain't pretty,
1525 * but it seems to work.
1526 */
1527static int
1528start_ap(int logical_cpu, u_int boot_addr)
1529{
1530	int     physical_cpu;
1531	int     vector;
1532	int     cpus;
1533	u_long  icr_lo, icr_hi;
1534
1535	/* get the PHYSICAL APIC ID# */
1536	physical_cpu = CPU_TO_ID(logical_cpu);
1537
1538	/* calculate the vector */
1539	vector = (boot_addr >> 12) & 0xff;
1540
1541	/* used as a watchpoint to signal AP startup */
1542	cpus = mp_ncpus;
1543
1544	/*
1545	 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
1546	 * and running the target CPU. OR this INIT IPI might be latched (P5
1547	 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
1548	 * ignored.
1549	 */
1550
1551	/* setup the address for the target AP */
1552	icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
1553	icr_hi |= (physical_cpu << 24);
1554	lapic.icr_hi = icr_hi;
1555
1556	/* do an INIT IPI: assert RESET */
1557	icr_lo = lapic.icr_lo & 0xfff00000;
1558	lapic.icr_lo = icr_lo | 0x0000c500;
1559
1560	/* wait for pending status end */
1561	while (lapic.icr_lo & APIC_DELSTAT_MASK)
1562		 /* spin */ ;
1563
1564	/* do an INIT IPI: deassert RESET */
1565	lapic.icr_lo = icr_lo | 0x00008500;
1566
1567	/* wait for pending status end */
1568	u_sleep(10000);		/* wait ~10mS */
1569	while (lapic.icr_lo & APIC_DELSTAT_MASK)
1570		 /* spin */ ;
1571
1572	/*
1573	 * next we do a STARTUP IPI: the previous INIT IPI might still be
1574	 * latched, (P5 bug) this 1st STARTUP would then terminate
1575	 * immediately, and the previously started INIT IPI would continue. OR
1576	 * the previous INIT IPI has already run. and this STARTUP IPI will
1577	 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
1578	 * will run.
1579	 */
1580
1581	/* do a STARTUP IPI */
1582	lapic.icr_lo = icr_lo | 0x00000600 | vector;
1583	while (lapic.icr_lo & APIC_DELSTAT_MASK)
1584		 /* spin */ ;
1585	u_sleep(200);		/* wait ~200uS */
1586
1587	/*
1588	 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
1589	 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
1590	 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
1591	 * recognized after hardware RESET or INIT IPI.
1592	 */
1593
1594	lapic.icr_lo = icr_lo | 0x00000600 | vector;
1595	while (lapic.icr_lo & APIC_DELSTAT_MASK)
1596		 /* spin */ ;
1597	u_sleep(200);		/* wait ~200uS */
1598
1599	/* wait for it to start */
1600	set_apic_timer(5000000);/* == 5 seconds */
1601	while (read_apic_timer())
1602		if (mp_ncpus > cpus)
1603			return 1;	/* return SUCCESS */
1604
1605	return 0;		/* return FAILURE */
1606}
1607
1608
1609/*
1610 * Flush the TLB on all other CPU's
1611 *
1612 * XXX: Needs to handshake and wait for completion before proceding.
1613 */
1614void
1615smp_invltlb(void)
1616{
1617#if defined(APIC_IO)
1618	if (smp_active && invltlb_ok)
1619		all_but_self_ipi(ICU_OFFSET + XINVLTLB_OFFSET);
1620#endif  /* APIC_IO */
1621}
1622
1623void
1624invlpg(u_int addr)
1625{
1626	__asm   __volatile("invlpg (%0)"::"r"(addr):"memory");
1627
1628	/* send a message to the other CPUs */
1629	smp_invltlb();
1630}
1631
1632void
1633invltlb(void)
1634{
1635	u_long  temp;
1636
1637	/*
1638	 * This should be implemented as load_cr3(rcr3()) when load_cr3() is
1639	 * inlined.
1640	 */
1641	__asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory");
1642
1643	/* send a message to the other CPUs */
1644	smp_invltlb();
1645}
1646