mptable.c revision 26812
1/* 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $Id: mp_machdep.c,v 1.17 1997/06/02 10:44:08 dfr Exp $ 26 */ 27 28#include "opt_smp.h" 29 30#include <sys/param.h> /* for KERNBASE */ 31#include <sys/types.h> 32#include <sys/sysproto.h> 33#include <sys/time.h> 34#include <sys/systm.h> 35 36#include <vm/vm.h> /* for KERNBASE */ 37#include <vm/vm_param.h> /* for KERNBASE */ 38#include <vm/pmap.h> /* for KERNBASE */ 39#include <machine/pmap.h> /* for KERNBASE */ 40#include <vm/vm_kern.h> 41#include <vm/vm_extern.h> 42 43#include <machine/smp.h> 44#include <machine/apic.h> 45#include <machine/mpapic.h> 46#include <machine/cpufunc.h> 47#include <machine/segments.h> 48#include <machine/smptests.h> /** TEST_DEFAULT_CONFIG */ 49#include <machine/tss.h> 50 51#include <i386/i386/cons.h> /* cngetc() */ 52 53#if defined(APIC_IO) 54#include <machine/md_var.h> /* setidt() */ 55#include <i386/isa/icu.h> /* Xinvltlb() */ 56#include <i386/isa/intr_machdep.h> /* Xinvltlb() */ 57#endif /* APIC_IO */ 58 59#define WARMBOOT_TARGET 0 60#define WARMBOOT_OFF (KERNBASE + 0x0467) 61#define WARMBOOT_SEG (KERNBASE + 0x0469) 62 63#define BIOS_BASE (0xf0000) 64#define BIOS_SIZE (0x10000) 65#define BIOS_COUNT (BIOS_SIZE/4) 66 67#define CMOS_REG (0x70) 68#define CMOS_DATA (0x71) 69#define BIOS_RESET (0x0f) 70#define BIOS_WARM (0x0a) 71 72#define PROCENTRY_FLAG_EN 0x01 73#define PROCENTRY_FLAG_BP 0x02 74#define IOAPICENTRY_FLAG_EN 0x01 75 76/* MP Floating Pointer Structure */ 77typedef struct MPFPS { 78 char signature[4]; 79 void *pap; 80 u_char length; 81 u_char spec_rev; 82 u_char checksum; 83 u_char mpfb1; 84 u_char mpfb2; 85 u_char mpfb3; 86 u_char mpfb4; 87 u_char mpfb5; 88} *mpfps_t; 89 90/* MP Configuration Table Header */ 91typedef struct MPCTH { 92 char signature[4]; 93 u_short base_table_length; 94 u_char spec_rev; 95 u_char checksum; 96 u_char oem_id[8]; 97 u_char product_id[12]; 98 void *oem_table_pointer; 99 u_short oem_table_size; 100 u_short entry_count; 101 void *apic_address; 102 u_short extended_table_length; 103 u_char extended_table_checksum; 104 u_char reserved; 105} *mpcth_t; 106 107 108typedef struct PROCENTRY { 109 u_char type; 110 u_char apic_id; 111 u_char apic_version; 112 u_char cpu_flags; 113 u_long cpu_signature; 114 u_long feature_flags; 115 u_long reserved1; 116 u_long reserved2; 117} *proc_entry_ptr; 118 119typedef struct BUSENTRY { 120 u_char type; 121 u_char bus_id; 122 char bus_type[6]; 123} *bus_entry_ptr; 124 125typedef struct IOAPICENTRY { 126 u_char type; 127 u_char apic_id; 128 u_char apic_version; 129 u_char apic_flags; 130 void *apic_address; 131} *io_apic_entry_ptr; 132 133typedef struct INTENTRY { 134 u_char type; 135 u_char int_type; 136 u_short int_flags; 137 u_char src_bus_id; 138 u_char src_bus_irq; 139 u_char dst_apic_id; 140 u_char dst_apic_int; 141} *int_entry_ptr; 142 143/* descriptions of MP basetable entries */ 144typedef struct BASETABLE_ENTRY { 145 u_char type; 146 u_char length; 147 char name[16]; 148} basetable_entry; 149 150/* 151 * this code MUST be enabled here and in mpboot.s. 152 * it follows the very early stages of AP boot by placing values in CMOS ram. 153 * it NORMALLY will never be needed and thus the primitive method for enabling. 154 * 155#define CHECK_POINTS 156 */ 157 158#if defined(CHECK_POINTS) 159#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 160#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 161 162#define CHECK_INIT(D); \ 163 CHECK_WRITE(0x34, (D)); \ 164 CHECK_WRITE(0x35, (D)); \ 165 CHECK_WRITE(0x36, (D)); \ 166 CHECK_WRITE(0x37, (D)); \ 167 CHECK_WRITE(0x38, (D)); \ 168 CHECK_WRITE(0x39, (D)); 169 170#define CHECK_PRINT(S); \ 171 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 172 (S), \ 173 CHECK_READ(0x34), \ 174 CHECK_READ(0x35), \ 175 CHECK_READ(0x36), \ 176 CHECK_READ(0x37), \ 177 CHECK_READ(0x38), \ 178 CHECK_READ(0x39)); 179 180#else /* CHECK_POINTS */ 181 182#define CHECK_INIT(D) 183#define CHECK_PRINT(S) 184 185#endif /* CHECK_POINTS */ 186 187 188/** FIXME: what system files declare these??? */ 189extern struct region_descriptor r_gdt, r_idt; 190 191int mp_ncpus; /* # of CPUs, including BSP */ 192int mp_naps; /* # of Applications processors */ 193int mp_nbusses; /* # of busses */ 194int mp_napics; /* # of IO APICs */ 195int boot_cpu_id; /* designated BSP */ 196vm_offset_t cpu_apic_address; 197vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */ 198 199u_int32_t cpu_apic_versions[NCPU]; 200u_int32_t io_apic_versions[NAPIC]; 201 202/* 203 * APIC ID logical/physical mapping structures. 204 * We oversize these to simplify boot-time config. 205 */ 206int cpu_num_to_apic_id[NAPICID]; 207int io_num_to_apic_id[NAPICID]; 208int apic_id_to_logical[NAPICID]; 209 210/* Boot of AP uses this PTD */ 211u_int *bootPTD; 212 213/* Hotwire a 0->4MB V==P mapping */ 214extern pt_entry_t KPTphys; 215 216/* virtual address of per-cpu common_tss */ 217extern struct i386tss common_tss; 218 219/* 220 * look for MP compliant motherboard. 221 */ 222 223static int mp_capable; 224static u_int boot_address; 225static u_int base_memory; 226 227static int picmode; /* 0: virtual wire mode, 1: PIC mode */ 228static mpfps_t mpfps; 229static int search_for_sig(u_int32_t target, int count); 230static void mp_enable(u_int boot_addr); 231 232static int mptable_pass1(void); 233static int mptable_pass2(void); 234static void default_mp_table(int type); 235static int start_all_aps(u_int boot_addr); 236static void install_ap_tramp(u_int boot_addr); 237static int start_ap(int logicalCpu, u_int boot_addr); 238 239 240/* 241 * calculate usable address in base memory for AP trampoline code 242 */ 243u_int 244mp_bootaddress(u_int basemem) 245{ 246 base_memory = basemem * 1024; /* convert to bytes */ 247 248 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ 249 if ((base_memory - boot_address) < bootMP_size) 250 boot_address -= 4096; /* not enough, lower by 4k */ 251 252 return boot_address; 253} 254 255 256int 257mp_probe(void) 258{ 259 int x; 260 u_long segment; 261 u_int32_t target; 262 263 /* see if EBDA exists */ 264 if (segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) { 265 /* search first 1K of EBDA */ 266 target = (u_int32_t) (segment << 4); 267 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 268 goto found; 269 } else { 270 /* last 1K of base memory, effective 'top of base' passed in */ 271 target = (u_int32_t) (base_memory - 0x400); 272 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 273 goto found; 274 } 275 276 /* search the BIOS */ 277 target = (u_int32_t) BIOS_BASE; 278 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) 279 goto found; 280 281 /* nothing found */ 282 mpfps = (mpfps_t)0; 283 mp_capable = 0; 284 return 0; 285 286found: /* please forgive the 'goto'! */ 287 /* calculate needed resources */ 288 mpfps = (mpfps_t)x; 289 if (mptable_pass1()) 290 panic("you must reconfigure your kernel"); 291 292 /* flag fact that we are running multiple processors */ 293 mp_capable = 1; 294 return 1; 295} 296 297 298/* 299 * startup the SMP processors 300 */ 301void 302mp_start(void) 303{ 304 /* look for MP capable motherboard */ 305 if (mp_capable) 306 mp_enable(boot_address); 307 else 308 panic("MP hardware not found!"); 309} 310 311 312/* 313 * print various information about the SMP system hardware and setup 314 */ 315void 316mp_announce(void) 317{ 318 int x; 319 320 printf("FreeBSD/SMP: Multiprocessor motherboard\n"); 321 printf(" cpu0 (BSP): apic id: %d", CPU_TO_ID(0)); 322 printf(", version: 0x%08x", cpu_apic_versions[0]); 323 printf(", at 0x%08x\n", cpu_apic_address); 324 for (x = 1; x <= mp_naps; ++x) { 325 printf(" cpu%d (AP): apic id: %d", x, CPU_TO_ID(x)); 326 printf(", version: 0x%08x", cpu_apic_versions[x]); 327 printf(", at 0x%08x\n", cpu_apic_address); 328 } 329 330#if defined(APIC_IO) 331 for (x = 0; x < mp_napics; ++x) { 332 printf(" io%d (APIC): apic id: %d", x, IO_TO_ID(x)); 333 printf(", version: 0x%08x", io_apic_versions[x]); 334 printf(", at 0x%08x\n", io_apic_address[x]); 335 } 336#else 337 printf(" Warning: APIC I/O disabled\n"); 338#endif /* APIC_IO */ 339} 340 341/* 342 * AP cpu's call this to sync up protected mode. 343 */ 344void 345init_secondary(void) 346{ 347 int gsel_tss, slot; 348 349 r_gdt.rd_limit = sizeof(gdt[0]) * (NGDT + NCPU) - 1; 350 r_gdt.rd_base = (int) gdt; 351 lgdt(&r_gdt); /* does magic intra-segment return */ 352 lidt(&r_idt); 353 lldt(_default_ldt); 354 355 slot = NGDT + cpuid; 356 gsel_tss = GSEL(slot, SEL_KPL); 357 gdt[slot].sd.sd_type = SDT_SYS386TSS; 358 common_tss.tss_esp0 = 0; /* not used until after switch */ 359 common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 360 common_tss.tss_ioopt = (sizeof common_tss) << 16; 361 ltr(gsel_tss); 362 363 load_cr0(0x8005003b); /* XXX! */ 364 365 PTD[0] = 0; 366 invltlb(); 367} 368 369 370#if defined(APIC_IO) 371void 372configure_local_apic(void) 373{ 374 u_char byte; 375 u_int32_t temp; 376 377 if (picmode) { 378 outb(0x22, 0x70); /* select IMCR */ 379 byte = inb(0x23); /* current contents */ 380 byte |= 0x01; /* mask external INTR */ 381 outb(0x23, byte); /* disconnect 8259s/NMI */ 382 } 383 /* mask the LVT1 */ 384 temp = lapic.lvt_lint0; 385 temp |= APIC_LVT_M; 386 lapic.lvt_lint0 = temp; 387} 388#endif /* APIC_IO */ 389 390 391/******************************************************************* 392 * local functions and data 393 */ 394 395/* 396 * start the SMP system 397 */ 398static void 399mp_enable(u_int boot_addr) 400{ 401 int x; 402#if defined(APIC_IO) 403 int apic; 404 u_int ux; 405#endif /* APIC_IO */ 406 407 /* Turn on 4MB of V == P addressing so we can get to MP table */ 408 *(int *)PTD = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME); 409 invltlb(); 410 411 /* examine the MP table for needed info, uses physical addresses */ 412 x = mptable_pass2(); 413 414 *(int *)PTD = 0; 415 invltlb(); 416 417 /* can't process default configs till the CPU APIC is pmapped */ 418 if (x) 419 default_mp_table(x); 420 421#if defined(APIC_IO) 422 /* fill the LOGICAL io_apic_versions table */ 423 for (apic = 0; apic < mp_napics; ++apic) { 424 ux = io_apic_read(apic, IOAPIC_VER); 425 io_apic_versions[apic] = ux; 426 } 427 428 /* program each IO APIC in the system */ 429 for (apic = 0; apic < mp_napics; ++apic) 430 if (io_apic_setup(apic) < 0) 431 panic("IO APIC setup failure"); 432 433 /* install an inter-CPU IPI for TLB invalidation */ 434 setidt(ICU_OFFSET + XINVLTLB_OFFSET, Xinvltlb, 435 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 436#endif /* APIC_IO */ 437 438 /* start each Application Processor */ 439 start_all_aps(boot_addr); 440} 441 442 443/* 444 * look for the MP spec signature 445 */ 446 447/* string defined by the Intel MP Spec as identifying the MP table */ 448#define MP_SIG 0x5f504d5f /* _MP_ */ 449#define NEXT(X) ((X) += 4) 450static int 451search_for_sig(u_int32_t target, int count) 452{ 453 int x; 454 u_int32_t *addr = (u_int32_t *) (KERNBASE + target); 455 456 for (x = 0; x < count; NEXT(x)) 457 if (addr[x] == MP_SIG) 458 /* make array index a byte index */ 459 return (target + (x * sizeof(u_int32_t))); 460 461 return -1; 462} 463 464 465static basetable_entry basetable_entry_types[] = 466{ 467 {0, 20, "Processor"}, 468 {1, 8, "Bus"}, 469 {2, 8, "I/O APIC"}, 470 {3, 8, "I/O INT"}, 471 {4, 8, "Local INT"} 472}; 473 474typedef struct BUSDATA { 475 u_char bus_id; 476 enum busTypes bus_type; 477} bus_datum; 478 479typedef struct INTDATA { 480 u_char int_type; 481 u_short int_flags; 482 u_char src_bus_id; 483 u_char src_bus_irq; 484 u_char dst_apic_id; 485 u_char dst_apic_int; 486} io_int, local_int; 487 488typedef struct BUSTYPENAME { 489 u_char type; 490 char name[7]; 491} bus_type_name; 492 493static bus_type_name bus_type_table[] = 494{ 495 {CBUS, "CBUS"}, 496 {CBUSII, "CBUSII"}, 497 {EISA, "EISA"}, 498 {UNKNOWN_BUSTYPE, "---"}, 499 {UNKNOWN_BUSTYPE, "---"}, 500 {ISA, "ISA"}, 501 {UNKNOWN_BUSTYPE, "---"}, 502 {UNKNOWN_BUSTYPE, "---"}, 503 {UNKNOWN_BUSTYPE, "---"}, 504 {UNKNOWN_BUSTYPE, "---"}, 505 {UNKNOWN_BUSTYPE, "---"}, 506 {UNKNOWN_BUSTYPE, "---"}, 507 {PCI, "PCI"}, 508 {UNKNOWN_BUSTYPE, "---"}, 509 {UNKNOWN_BUSTYPE, "---"}, 510 {UNKNOWN_BUSTYPE, "---"}, 511 {UNKNOWN_BUSTYPE, "---"}, 512 {XPRESS, "XPRESS"}, 513 {UNKNOWN_BUSTYPE, "---"} 514}; 515/* from MP spec v1.4, table 5-1 */ 516static int default_data[7][5] = 517{ 518/* nbus, id0, type0, id1, type1 */ 519 {1, 0, ISA, 255, 255}, 520 {1, 0, EISA, 255, 255}, 521 {1, 0, EISA, 255, 255}, 522 {0, 255, 255, 255, 255},/* MCA not supported */ 523 {2, 0, ISA, 1, PCI}, 524 {2, 0, EISA, 1, PCI}, 525 {0, 255, 255, 255, 255} /* MCA not supported */ 526}; 527 528 529/* the bus data */ 530bus_datum bus_data[NBUS]; 531 532/* the IO INT data, one entry per possible APIC INTerrupt */ 533io_int io_apic_ints[NINTR]; 534 535static int nintrs; 536 537static void fix_mp_table __P((void)); 538static int processor_entry __P((proc_entry_ptr entry, int cpu)); 539static int bus_entry __P((bus_entry_ptr entry, int bus)); 540static int io_apic_entry __P((io_apic_entry_ptr entry, int apic)); 541static int int_entry __P((int_entry_ptr entry, int intr)); 542static int lookup_bus_type __P((char *name)); 543 544 545/* 546 * 1st pass on motherboard's Intel MP specification table. 547 * 548 * initializes: 549 * mp_ncpus = 1 550 * 551 * determines: 552 * cpu_apic_address (common to all CPUs) 553 * io_apic_address[N] 554 * mp_naps 555 * mp_nbusses 556 * mp_napics 557 * nintrs 558 */ 559static int 560mptable_pass1(void) 561{ 562 int x; 563 mpcth_t cth; 564 int totalSize; 565 void* position; 566 int count; 567 int type; 568 int mustpanic; 569 570 mustpanic = 0; 571 572 /* clear various tables */ 573 for (x = 0; x < NAPICID; ++x) { 574 io_apic_address[x] = ~0; /* IO APIC address table */ 575 } 576 577 /* init everything to empty */ 578 mp_naps = 0; 579 mp_nbusses = 0; 580 mp_napics = 0; 581 nintrs = 0; 582 583 /* check for use of 'default' configuration */ 584 if (mpfps->mpfb1 != 0) { 585 /* use default addresses */ 586 cpu_apic_address = DEFAULT_APIC_BASE; 587 io_apic_address[0] = DEFAULT_IO_APIC_BASE; 588 589 /* fill in with defaults */ 590 mp_naps = 1; 591 mp_nbusses = default_data[mpfps->mpfb1 - 1][0]; 592#if defined(APIC_IO) 593 mp_napics = 1; 594 nintrs = 16; 595#endif /* APIC_IO */ 596 } 597 else { 598 if ((cth = mpfps->pap) == 0) 599 panic("MP Configuration Table Header MISSING!"); 600 601 cpu_apic_address = (vm_offset_t) cth->apic_address; 602 603 /* walk the table, recording info of interest */ 604 totalSize = cth->base_table_length - sizeof(struct MPCTH); 605 position = (u_char *) cth + sizeof(struct MPCTH); 606 count = cth->entry_count; 607 608 while (count--) { 609 switch (type = *(u_char *) position) { 610 case 0: /* processor_entry */ 611 if (((proc_entry_ptr)position)->cpu_flags 612 & PROCENTRY_FLAG_EN) 613 ++mp_naps; 614 break; 615 case 1: /* bus_entry */ 616 ++mp_nbusses; 617 break; 618 case 2: /* io_apic_entry */ 619 if (((io_apic_entry_ptr)position)->apic_flags 620 & IOAPICENTRY_FLAG_EN) 621 io_apic_address[mp_napics++] = 622 (vm_offset_t)((io_apic_entry_ptr) 623 position)->apic_address; 624 break; 625 case 3: /* int_entry */ 626 ++nintrs; 627 break; 628 case 4: /* int_entry */ 629 break; 630 default: 631 panic("mpfps Base Table HOSED!"); 632 /* NOTREACHED */ 633 } 634 635 totalSize -= basetable_entry_types[type].length; 636 (u_char*)position += basetable_entry_types[type].length; 637 } 638 } 639 640 /* qualify the numbers */ 641 if (mp_naps > NCPU) 642 printf("Warning: only using %d of %d available CPUs!\n", 643 NCPU, mp_naps); 644#if 0 645 /** XXX we consider this legal now (but should we?) */ 646 mustpanic = 1; 647#endif 648 if (mp_nbusses > NBUS) { 649 printf("found %d busses, increase NBUS\n", mp_nbusses); 650 mustpanic = 1; 651 } 652 if (mp_napics > NAPIC) { 653 printf("found %d apics, increase NAPIC\n", mp_napics); 654 mustpanic = 1; 655 } 656 if (nintrs > NINTR) { 657 printf("found %d intrs, increase NINTR\n", nintrs); 658 mustpanic = 1; 659 } 660 661 /* 662 * Count the BSP. 663 * This is also used as a counter while starting the APs. 664 */ 665 mp_ncpus = 1; 666 667 --mp_naps; /* subtract the BSP */ 668 669 return mustpanic; 670} 671 672 673/* 674 * 2nd pass on motherboard's Intel MP specification table. 675 * 676 * sets: 677 * boot_cpu_id 678 * ID_TO_IO(N), phy APIC ID to log CPU/IO table 679 * CPU_TO_ID(N), logical CPU to APIC ID table 680 * IO_TO_ID(N), logical IO to APIC ID table 681 * bus_data[N] 682 * io_apic_ints[N] 683 */ 684static int 685mptable_pass2(void) 686{ 687 int x; 688 mpcth_t cth; 689 int totalSize; 690 void* position; 691 int count; 692 int type; 693 int apic, bus, cpu, intr; 694 695 /* clear various tables */ 696 for (x = 0; x < NAPICID; ++x) { 697 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */ 698 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */ 699 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */ 700 } 701 702 /* clear bus data table */ 703 for (x = 0; x < NBUS; ++x) 704 bus_data[x].bus_id = 0xff; 705 706 /* clear IO APIC INT table */ 707 for (x = 0; x < NINTR; ++x) 708 io_apic_ints[x].int_type = 0xff; 709 710 /* setup the cpu/apic mapping arrays */ 711 boot_cpu_id = -1; 712 713 /* record whether PIC or virtual-wire mode */ 714 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0; 715 716 /* check for use of 'default' configuration */ 717#if defined(TEST_DEFAULT_CONFIG) 718 return TEST_DEFAULT_CONFIG; 719#else 720 if (mpfps->mpfb1 != 0) 721 return mpfps->mpfb1; /* return default configuration type */ 722#endif /* TEST_DEFAULT_CONFIG */ 723 724 if ((cth = mpfps->pap) == 0) 725 panic("MP Configuration Table Header MISSING!"); 726 727 /* walk the table, recording info of interest */ 728 totalSize = cth->base_table_length - sizeof(struct MPCTH); 729 position = (u_char *) cth + sizeof(struct MPCTH); 730 count = cth->entry_count; 731 apic = bus = intr = 0; 732 cpu = 1; /* pre-count the BSP */ 733 734 while (count--) { 735 switch (type = *(u_char *) position) { 736 case 0: 737 if (processor_entry(position, cpu)) 738 ++cpu; 739 break; 740 case 1: 741 if (bus_entry(position, bus)) 742 ++bus; 743 break; 744 case 2: 745 if (io_apic_entry(position, apic)) 746 ++apic; 747 break; 748 case 3: 749 if (int_entry(position, intr)) 750 ++intr; 751 break; 752 case 4: 753 /* int_entry(position); */ 754 break; 755 default: 756 panic("mpfps Base Table HOSED!"); 757 /* NOTREACHED */ 758 } 759 760 totalSize -= basetable_entry_types[type].length; 761 (u_char *) position += basetable_entry_types[type].length; 762 } 763 764 if (boot_cpu_id == -1) 765 panic("NO BSP found!"); 766 767 /* post scan cleanup */ 768 fix_mp_table(); 769 770 /* report fact that its NOT a default configuration */ 771 return 0; 772} 773 774 775/* 776 * parse an Intel MP specification table 777 */ 778static void 779fix_mp_table(void) 780{ 781 int x; 782 int id; 783 int bus_0; 784 int bus_pci; 785 int num_pci_bus; 786 787 /* 788 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS 789 * did it wrong. The MP spec says that when more than 1 PCI bus 790 * exists the BIOS must begin with bus entries for the PCI bus and use 791 * actual PCI bus numbering. This implies that when only 1 PCI bus 792 * exists the BIOS can choose to ignore this ordering, and indeed many 793 * MP motherboards do ignore it. This causes a problem when the PCI 794 * sub-system makes requests of the MP sub-system based on PCI bus 795 * numbers. So here we look for the situation and renumber the 796 * busses and associated INTs in an effort to "make it right". 797 */ 798 799 /* find bus 0, PCI bus, count the number of PCI busses */ 800 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { 801 if (bus_data[x].bus_id == 0) { 802 bus_0 = x; 803 } 804 if (bus_data[x].bus_type == PCI) { 805 ++num_pci_bus; 806 bus_pci = x; 807 } 808 } 809 /* 810 * bus_0 == slot of bus with ID of 0 811 * bus_pci == slot of last PCI bus encountered 812 */ 813 814 /* check the 1 PCI bus case for sanity */ 815 if (num_pci_bus == 1) { 816 817 /* if it is number 0 all is well */ 818 if (bus_data[bus_pci].bus_id == 0) 819 return; 820 821 /* mis-numbered, swap with whichever bus uses slot 0 */ 822 823 /* swap the bus entry types */ 824 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type; 825 bus_data[bus_0].bus_type = PCI; 826 827 /* swap each relavant INTerrupt entry */ 828 id = bus_data[bus_pci].bus_id; 829 for (x = 0; x < nintrs; ++x) { 830 if (io_apic_ints[x].src_bus_id == id) { 831 io_apic_ints[x].src_bus_id = 0; 832 } 833 else if (io_apic_ints[x].src_bus_id == 0) { 834 io_apic_ints[x].src_bus_id = id; 835 } 836 } 837 } 838 /* sanity check if more than 1 PCI bus */ 839 else if (num_pci_bus > 1) { 840 for (x = 0; x < mp_nbusses; ++x) { 841 if (bus_data[x].bus_type != PCI) 842 continue; 843 if (bus_data[x].bus_id >= num_pci_bus) 844 panic("bad PCI bus numbering"); 845 } 846 } 847} 848 849 850static int 851processor_entry(proc_entry_ptr entry, int cpu) 852{ 853 /* check for usability */ 854 if ((cpu >= NCPU) || !(entry->cpu_flags & PROCENTRY_FLAG_EN)) 855 return 0; 856 857 /* check for BSP flag */ 858 if (entry->cpu_flags & PROCENTRY_FLAG_BP) { 859 boot_cpu_id = entry->apic_id; 860 CPU_TO_ID(0) = entry->apic_id; 861 ID_TO_CPU(entry->apic_id) = 0; 862 return 0; /* its already been counted */ 863 } 864 865 /* add another AP to list, if less than max number of CPUs */ 866 else { 867 CPU_TO_ID(cpu) = entry->apic_id; 868 ID_TO_CPU(entry->apic_id) = cpu; 869 return 1; 870 } 871} 872 873 874static int 875bus_entry(bus_entry_ptr entry, int bus) 876{ 877 int x; 878 char c, name[8]; 879 880 /* encode the name into an index */ 881 for (x = 0; x < 6; ++x) { 882 if ((c = entry->bus_type[x]) == ' ') 883 break; 884 name[x] = c; 885 } 886 name[x] = '\0'; 887 888 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) 889 panic("unknown bus type: '%s'", name); 890 891 bus_data[bus].bus_id = entry->bus_id; 892 bus_data[bus].bus_type = x; 893 894 return 1; 895} 896 897 898static int 899io_apic_entry(io_apic_entry_ptr entry, int apic) 900{ 901 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) 902 return 0; 903 904 IO_TO_ID(apic) = entry->apic_id; 905 ID_TO_IO(entry->apic_id) = apic; 906 907 return 1; 908} 909 910 911static int 912lookup_bus_type(char *name) 913{ 914 int x; 915 916 for (x = 0; x < MAX_BUSTYPE; ++x) 917 if (strcmp(bus_type_table[x].name, name) == 0) 918 return bus_type_table[x].type; 919 920 return UNKNOWN_BUSTYPE; 921} 922 923 924static int 925int_entry(int_entry_ptr entry, int intr) 926{ 927 io_apic_ints[intr].int_type = entry->int_type; 928 io_apic_ints[intr].int_flags = entry->int_flags; 929 io_apic_ints[intr].src_bus_id = entry->src_bus_id; 930 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq; 931 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; 932 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int; 933 934 return 1; 935} 936 937 938static int 939apic_int_is_bus_type(int intr, int bus_type) 940{ 941 int bus; 942 943 for (bus = 0; bus < mp_nbusses; ++bus) 944 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) 945 && ((int) bus_data[bus].bus_type == bus_type)) 946 return 1; 947 948 return 0; 949} 950 951 952/* 953 * determine which APIC pin an ISA INT is attached to. 954 */ 955#define INTTYPE(I) (io_apic_ints[(I)].int_type) 956#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) 957 958#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) 959int 960get_isa_apic_irq(int isaIRQ) 961{ 962 int intr; 963 964#if defined(SMP_TIMER_NC) 965 if (isaIRQ == 0) 966 return -1; 967#endif /* SMP_TIMER_NC */ 968 969 for (intr = 0; intr < nintrs; ++intr) /* search each INT record */ 970 if ((INTTYPE(intr) == 0) 971 && (SRCBUSIRQ(intr) == isaIRQ)) /* a candidate IRQ */ 972 if (apic_int_is_bus_type(intr, ISA)) /* check bus match */ 973 return INTPIN(intr); /* exact match */ 974 975 return -1; /* NOT found */ 976} 977#undef SRCBUSIRQ 978 979 980/* 981 * 982 */ 983u_int 984get_isa_apic_mask(u_int isaMASK) 985{ 986 int apicpin, isairq; 987 988 isairq = ffs(isaMASK); 989 if (isairq == 0) { 990 return 0; 991 } 992 --isairq; 993 994 apicpin = get_isa_apic_irq(isairq); 995 if (apicpin == -1) { 996 apicpin = get_eisa_apic_irq(isairq); 997 if (apicpin == -1) { 998 return 0; 999 } 1000 } 1001 1002 return (1 << apicpin); 1003} 1004 1005 1006/* 1007 * determine which APIC pin an EISA INT is attached to. 1008 */ 1009#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) 1010int 1011get_eisa_apic_irq(int eisaIRQ) 1012{ 1013 int intr; 1014 1015#if defined(SMP_TIMER_NC) 1016 if (eisaIRQ == 0) 1017 return -1; 1018#endif /* SMP_TIMER_NC */ 1019 1020 for (intr = 0; intr < nintrs; ++intr) /* search each INT record */ 1021 if ((INTTYPE(intr) == 0) 1022 && (SRCBUSIRQ(intr) == eisaIRQ)) /* a candidate IRQ */ 1023 if (apic_int_is_bus_type(intr, EISA)) /* check bus match */ 1024 return INTPIN(intr); /* exact match */ 1025 1026 return -1; /* NOT found */ 1027} 1028#undef SRCBUSIRQ 1029 1030 1031/* 1032 * determine which APIC pin a PCI INT is attached to. 1033 */ 1034#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) 1035#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) 1036#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) 1037int 1038get_pci_apic_irq(int pciBus, int pciDevice, int pciInt) 1039{ 1040 int intr; 1041 1042 --pciInt; /* zero based */ 1043 1044 for (intr = 0; intr < nintrs; ++intr) /* search each record */ 1045 if ((INTTYPE(intr) == 0) 1046 && (SRCBUSID(intr) == pciBus) 1047 && (SRCBUSDEVICE(intr) == pciDevice) 1048 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ 1049 if (apic_int_is_bus_type(intr, PCI)) /* check bus match */ 1050 return INTPIN(intr); /* exact match */ 1051 1052 return -1; /* NOT found */ 1053} 1054#undef SRCBUSLINE 1055#undef SRCBUSDEVICE 1056#undef SRCBUSID 1057 1058#undef INTPIN 1059#undef INTTYPE 1060 1061 1062/* 1063 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt 1064 */ 1065int 1066undirect_pci_irq(int rirq) 1067{ 1068#if defined(READY) 1069 if (bootverbose) 1070 printf("Freeing redirected PCI irq %d.\n", rirq); 1071 1072 /** FIXME: tickle the MB redirector chip */ 1073 return ???; 1074#else 1075 if (bootverbose) 1076 printf("Freeing (NOT implemented) redirected PCI irq %d.\n", 1077 rirq); 1078 return 0; 1079#endif /* READY */ 1080} 1081 1082 1083/* 1084 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt. 1085 * 1086 * XXX FIXME: 1087 * Exactly what this means is unclear at this point. It is a solution 1088 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard 1089 * could route any of the ISA INTs to upper (>15) IRQ values. But most would 1090 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an 1091 * option. 1092 */ 1093int 1094undirect_isa_irq(int rirq) 1095{ 1096#if defined(READY) 1097 printf("Freeing redirected ISA irq %d.\n", rirq); 1098 /** FIXME: tickle the MB redirector chip */ 1099 return ???; 1100#else 1101 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq); 1102 return 0; 1103#endif /* READY */ 1104} 1105 1106 1107/* 1108 * given a bus ID, return: 1109 * the bus type if found 1110 * -1 if NOT found 1111 */ 1112int 1113apic_bus_type(int id) 1114{ 1115 int x; 1116 1117 for (x = 0; x < mp_nbusses; ++x) 1118 if (bus_data[x].bus_id == id) 1119 return bus_data[x].bus_type; 1120 1121 return -1; 1122} 1123 1124 1125/* 1126 * given a LOGICAL APIC# and pin#, return: 1127 * the associated src bus ID if found 1128 * -1 if NOT found 1129 */ 1130int 1131apic_src_bus_id(int apic, int pin) 1132{ 1133 int x; 1134 1135 /* search each of the possible INTerrupt sources */ 1136 for (x = 0; x < nintrs; ++x) 1137 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1138 (pin == io_apic_ints[x].dst_apic_int)) 1139 return (io_apic_ints[x].src_bus_id); 1140 1141 return -1; /* NOT found */ 1142} 1143 1144 1145/* 1146 * given a LOGICAL APIC# and pin#, return: 1147 * the associated src bus IRQ if found 1148 * -1 if NOT found 1149 */ 1150int 1151apic_src_bus_irq(int apic, int pin) 1152{ 1153 int x; 1154 1155 for (x = 0; x < nintrs; x++) 1156 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1157 (pin == io_apic_ints[x].dst_apic_int)) 1158 return (io_apic_ints[x].src_bus_irq); 1159 1160 return -1; /* NOT found */ 1161} 1162 1163 1164/* 1165 * given a LOGICAL APIC# and pin#, return: 1166 * the associated INTerrupt type if found 1167 * -1 if NOT found 1168 */ 1169int 1170apic_int_type(int apic, int pin) 1171{ 1172 int x; 1173 1174 /* search each of the possible INTerrupt sources */ 1175 for (x = 0; x < nintrs; ++x) 1176 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1177 (pin == io_apic_ints[x].dst_apic_int)) 1178 return (io_apic_ints[x].int_type); 1179 1180 return -1; /* NOT found */ 1181} 1182 1183 1184/* 1185 * given a LOGICAL APIC# and pin#, return: 1186 * the associated trigger mode if found 1187 * -1 if NOT found 1188 */ 1189int 1190apic_trigger(int apic, int pin) 1191{ 1192 int x; 1193 1194 /* search each of the possible INTerrupt sources */ 1195 for (x = 0; x < nintrs; ++x) 1196 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1197 (pin == io_apic_ints[x].dst_apic_int)) 1198 return ((io_apic_ints[x].int_flags >> 2) & 0x03); 1199 1200 return -1; /* NOT found */ 1201} 1202 1203 1204/* 1205 * given a LOGICAL APIC# and pin#, return: 1206 * the associated 'active' level if found 1207 * -1 if NOT found 1208 */ 1209int 1210apic_polarity(int apic, int pin) 1211{ 1212 int x; 1213 1214 /* search each of the possible INTerrupt sources */ 1215 for (x = 0; x < nintrs; ++x) 1216 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1217 (pin == io_apic_ints[x].dst_apic_int)) 1218 return (io_apic_ints[x].int_flags & 0x03); 1219 1220 return -1; /* NOT found */ 1221} 1222 1223 1224/* 1225 * set data according to MP defaults 1226 * FIXME: probably not complete yet... 1227 */ 1228static void 1229default_mp_table(int type) 1230{ 1231 int ap_cpu_id; 1232#if defined(APIC_IO) 1233 u_int32_t ux; 1234 int io_apic_id; 1235 int pin; 1236#endif /* APIC_IO */ 1237 1238#if 0 1239 printf(" MP default config type: %d\n", type); 1240 switch (type) { 1241 case 1: 1242 printf(" bus: ISA, APIC: 82489DX\n"); 1243 break; 1244 case 2: 1245 printf(" bus: EISA, APIC: 82489DX\n"); 1246 break; 1247 case 3: 1248 printf(" bus: EISA, APIC: 82489DX\n"); 1249 break; 1250 case 4: 1251 printf(" bus: MCA, APIC: 82489DX\n"); 1252 break; 1253 case 5: 1254 printf(" bus: ISA+PCI, APIC: Integrated\n"); 1255 break; 1256 case 6: 1257 printf(" bus: EISA+PCI, APIC: Integrated\n"); 1258 break; 1259 case 7: 1260 printf(" bus: MCA+PCI, APIC: Integrated\n"); 1261 break; 1262 default: 1263 printf(" future type\n"); 1264 break; 1265 /* NOTREACHED */ 1266 } 1267#endif /* 0 */ 1268 1269 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24; 1270 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; 1271 1272 /* BSP */ 1273 CPU_TO_ID(0) = boot_cpu_id; 1274 ID_TO_CPU(boot_cpu_id) = 0; 1275 1276 /* one and only AP */ 1277 CPU_TO_ID(1) = ap_cpu_id; 1278 ID_TO_CPU(ap_cpu_id) = 1; 1279 1280#if defined(APIC_IO) 1281 /* one and only IO APIC */ 1282 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; 1283 1284 /* 1285 * sanity check, refer to MP spec section 3.6.6, last paragraph 1286 * necessary as some hardware isn't properly setting up the IO APIC 1287 */ 1288#if defined(REALLY_ANAL_IOAPICID_VALUE) 1289 if (io_apic_id != 2) { 1290#else 1291 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { 1292#endif /* REALLY_ANAL_IOAPICID_VALUE */ 1293 ux = io_apic_read(0, IOAPIC_ID); /* get current contents */ 1294 ux &= ~APIC_ID_MASK; /* clear the ID field */ 1295 ux |= 0x02000000; /* set it to '2' */ 1296 io_apic_write(0, IOAPIC_ID, ux); /* write new value */ 1297 ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */ 1298 if ((ux & APIC_ID_MASK) != 0x02000000) 1299 panic("can't control IO APIC ID, reg: 0x%08x", ux); 1300 io_apic_id = 2; 1301 } 1302 IO_TO_ID(0) = io_apic_id; 1303 ID_TO_IO(io_apic_id) = 0; 1304#endif /* APIC_IO */ 1305 1306 /* fill out bus entries */ 1307 switch (type) { 1308 case 1: 1309 case 2: 1310 case 3: 1311 case 5: 1312 case 6: 1313 bus_data[0].bus_id = default_data[type - 1][1]; 1314 bus_data[0].bus_type = default_data[type - 1][2]; 1315 bus_data[1].bus_id = default_data[type - 1][3]; 1316 bus_data[1].bus_type = default_data[type - 1][4]; 1317 break; 1318 1319 /* case 4: case 7: MCA NOT supported */ 1320 default: /* illegal/reserved */ 1321 panic("BAD default MP config: %d", type); 1322 /* NOTREACHED */ 1323 } 1324 1325#if defined(APIC_IO) 1326 /* general cases from MP v1.4, table 5-2 */ 1327 for (pin = 0; pin < 16; ++pin) { 1328 io_apic_ints[pin].int_type = 0; 1329 io_apic_ints[pin].int_flags = 0x05; /* edge-triggered/active-hi */ 1330 io_apic_ints[pin].src_bus_id = 0; 1331 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 is caught below */ 1332 io_apic_ints[pin].dst_apic_id = io_apic_id; 1333 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 correspondence */ 1334 } 1335 1336 /* special cases from MP v1.4, table 5-2 */ 1337 if (type == 2) { 1338 io_apic_ints[2].int_type = 0xff; /* N/C */ 1339 io_apic_ints[13].int_type = 0xff; /* N/C */ 1340#if !defined(APIC_MIXED_MODE) 1341 /** FIXME: ??? */ 1342 panic("sorry, can't support type 2 default yet"); 1343#endif /* APIC_MIXED_MODE */ 1344 } 1345 else 1346 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ 1347 1348 if (type == 7) 1349 io_apic_ints[0].int_type = 0xff; /* N/C */ 1350 else 1351 io_apic_ints[0].int_type = 3; /* vectored 8259 */ 1352#endif /* APIC_IO */ 1353} 1354 1355 1356/* 1357 * start each AP in our list 1358 */ 1359static int 1360start_all_aps(u_int boot_addr) 1361{ 1362 int x, i; 1363 u_char mpbiosreason; 1364 u_long mpbioswarmvec; 1365 pd_entry_t newptd; 1366 pt_entry_t newpt; 1367 int *newpp; 1368 1369 /** 1370 * NOTE: this needs further thought: 1371 * where does it get released? 1372 * should it be set to empy? 1373 * 1374 * get the initial mp_lock with a count of 1 for the BSP 1375 */ 1376 mp_lock = (lapic.id & APIC_ID_MASK) + 1; 1377 1378 /* initialize BSP's local APIC */ 1379 apic_initialize(1); 1380 1381 /* install the AP 1st level boot code */ 1382 install_ap_tramp(boot_addr); 1383 1384 1385 /* save the current value of the warm-start vector */ 1386 mpbioswarmvec = *((u_long *) WARMBOOT_OFF); 1387 outb(CMOS_REG, BIOS_RESET); 1388 mpbiosreason = inb(CMOS_DATA); 1389 1390 /* start each AP */ 1391 for (x = 1; x <= mp_naps; ++x) { 1392 1393 /* HACK HACK HACK !!! */ 1394 1395 /* alloc new page table directory */ 1396 newptd = (pd_entry_t)(kmem_alloc(kernel_map, PAGE_SIZE)); 1397 1398 /* clone currently active one (ie: IdlePTD) */ 1399 bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */ 1400 1401 /* set up 0 -> 4MB P==V mapping for AP boot */ 1402 newptd[0] = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME); 1403 1404 /* store PTD for this AP */ 1405 bootPTD = (pd_entry_t)vtophys(newptd); 1406 1407 /* alloc new page table page */ 1408 newpt = (pt_entry_t)(kmem_alloc(kernel_map, PAGE_SIZE)); 1409 1410 /* set the new PTD's private page to point there */ 1411 newptd[MPPTDI] = PG_V | PG_RW | vtophys(newpt); 1412 1413 /* install self referential entry */ 1414 newptd[PTDPTDI] = PG_V | PG_RW | vtophys(newptd); 1415 1416 /* get a new private data page */ 1417 newpp = (int *)kmem_alloc(kernel_map, PAGE_SIZE); 1418 1419 /* wire it into the private page table page */ 1420 newpt[0] = PG_V | PG_RW | vtophys(newpp); 1421 1422 /* wire the ptp into itself for access */ 1423 newpt[1] = PG_V | PG_RW | vtophys(newpt); 1424 1425 /* and the local apic */ 1426 newpt[2] = SMP_prvpt[2]; 1427 1428 /* and the IO apic mapping[s] */ 1429 for (i = 16; i < 32; i++) 1430 newpt[i] = SMP_prvpt[i]; 1431 1432 /* prime data page for it to use */ 1433 newpp[0] = x; /* cpuid */ 1434 newpp[1] = 0; /* curproc */ 1435 newpp[2] = 0; /* curpcb */ 1436 newpp[3] = 0; /* npxproc */ 1437 newpp[4] = 0; /* runtime.tv_sec */ 1438 newpp[5] = 0; /* runtime.tv_usec */ 1439 newpp[6] = x << 24; /* cpu_lockid */ 1440 1441 /* XXX NOTE: ABANDON bootPTD for now!!!! */ 1442 1443 /* END REVOLTING HACKERY */ 1444 1445 /* setup a vector to our boot code */ 1446 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 1447 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); 1448 outb(CMOS_REG, BIOS_RESET); 1449 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 1450 1451 /* attempt to start the Application Processor */ 1452 CHECK_INIT(99); /* setup checkpoints */ 1453 if (!start_ap(x, boot_addr)) { 1454 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); 1455 CHECK_PRINT("trace"); /* show checkpoints */ 1456 /* better panic as the AP may be running loose */ 1457 printf("panic y/n? [y] "); 1458 if (cngetc() != 'n') 1459 panic("bye-bye"); 1460 } 1461 CHECK_PRINT("trace"); /* show checkpoints */ 1462 1463 /* record its version info */ 1464 cpu_apic_versions[x] = cpu_apic_versions[0]; 1465 } 1466 1467 /* fill in our (BSP) APIC version */ 1468 cpu_apic_versions[0] = lapic.version; 1469 1470 /* restore the warmstart vector */ 1471 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 1472 outb(CMOS_REG, BIOS_RESET); 1473 outb(CMOS_DATA, mpbiosreason); 1474 1475 /* number of APs actually started */ 1476 return mp_ncpus - 1; 1477} 1478 1479 1480/* 1481 * load the 1st level AP boot code into base memory. 1482 */ 1483 1484/* targets for relocation */ 1485extern void bigJump(void); 1486extern void bootCodeSeg(void); 1487extern void bootDataSeg(void); 1488extern void MPentry(void); 1489extern u_int MP_GDT; 1490extern u_int mp_gdtbase; 1491 1492static void 1493install_ap_tramp(u_int boot_addr) 1494{ 1495 int x; 1496 int size = *(int *) ((u_long) & bootMP_size); 1497 u_char *src = (u_char *) ((u_long) bootMP); 1498 u_char *dst = (u_char *) boot_addr + KERNBASE; 1499 u_int boot_base = (u_int) bootMP; 1500 u_int8_t *dst8; 1501 u_int16_t *dst16; 1502 u_int32_t *dst32; 1503 1504 for (x = 0; x < size; ++x) 1505 *dst++ = *src++; 1506 1507 /* 1508 * modify addresses in code we just moved to basemem. unfortunately we 1509 * need fairly detailed info about mpboot.s for this to work. changes 1510 * to mpboot.s might require changes here. 1511 */ 1512 1513 /* boot code is located in KERNEL space */ 1514 dst = (u_char *) boot_addr + KERNBASE; 1515 1516 /* modify the lgdt arg */ 1517 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 1518 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); 1519 1520 /* modify the ljmp target for MPentry() */ 1521 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 1522 *dst32 = ((u_int) MPentry - KERNBASE); 1523 1524 /* modify the target for boot code segment */ 1525 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 1526 dst8 = (u_int8_t *) (dst16 + 1); 1527 *dst16 = (u_int) boot_addr & 0xffff; 1528 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1529 1530 /* modify the target for boot data segment */ 1531 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 1532 dst8 = (u_int8_t *) (dst16 + 1); 1533 *dst16 = (u_int) boot_addr & 0xffff; 1534 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1535} 1536 1537 1538/* 1539 * this function starts the AP (application processor) identified 1540 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 1541 * to accomplish this. This is necessary because of the nuances 1542 * of the different hardware we might encounter. It ain't pretty, 1543 * but it seems to work. 1544 */ 1545static int 1546start_ap(int logical_cpu, u_int boot_addr) 1547{ 1548 int physical_cpu; 1549 int vector; 1550 int cpus; 1551 u_long icr_lo, icr_hi; 1552 1553 /* get the PHYSICAL APIC ID# */ 1554 physical_cpu = CPU_TO_ID(logical_cpu); 1555 1556 /* calculate the vector */ 1557 vector = (boot_addr >> 12) & 0xff; 1558 1559 /* used as a watchpoint to signal AP startup */ 1560 cpus = mp_ncpus; 1561 1562 /* 1563 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 1564 * and running the target CPU. OR this INIT IPI might be latched (P5 1565 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 1566 * ignored. 1567 */ 1568 1569 /* setup the address for the target AP */ 1570 icr_hi = lapic.icr_hi & ~APIC_ID_MASK; 1571 icr_hi |= (physical_cpu << 24); 1572 lapic.icr_hi = icr_hi; 1573 1574 /* do an INIT IPI: assert RESET */ 1575 icr_lo = lapic.icr_lo & 0xfff00000; 1576 lapic.icr_lo = icr_lo | 0x0000c500; 1577 1578 /* wait for pending status end */ 1579 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1580 /* spin */ ; 1581 1582 /* do an INIT IPI: deassert RESET */ 1583 lapic.icr_lo = icr_lo | 0x00008500; 1584 1585 /* wait for pending status end */ 1586 u_sleep(10000); /* wait ~10mS */ 1587 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1588 /* spin */ ; 1589 1590 /* 1591 * next we do a STARTUP IPI: the previous INIT IPI might still be 1592 * latched, (P5 bug) this 1st STARTUP would then terminate 1593 * immediately, and the previously started INIT IPI would continue. OR 1594 * the previous INIT IPI has already run. and this STARTUP IPI will 1595 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 1596 * will run. 1597 */ 1598 1599 /* do a STARTUP IPI */ 1600 lapic.icr_lo = icr_lo | 0x00000600 | vector; 1601 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1602 /* spin */ ; 1603 u_sleep(200); /* wait ~200uS */ 1604 1605 /* 1606 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 1607 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 1608 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 1609 * recognized after hardware RESET or INIT IPI. 1610 */ 1611 1612 lapic.icr_lo = icr_lo | 0x00000600 | vector; 1613 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1614 /* spin */ ; 1615 u_sleep(200); /* wait ~200uS */ 1616 1617 /* wait for it to start */ 1618 set_apic_timer(5000000);/* == 5 seconds */ 1619 while (read_apic_timer()) 1620 if (mp_ncpus > cpus) 1621 return 1; /* return SUCCESS */ 1622 1623 return 0; /* return FAILURE */ 1624} 1625 1626 1627/* 1628 * Flush the TLB on all other CPU's 1629 * 1630 * XXX: Needs to handshake and wait for completion before proceding. 1631 */ 1632void 1633smp_invltlb(void) 1634{ 1635#if defined(APIC_IO) 1636 if (smp_active && invltlb_ok) 1637 all_but_self_ipi(ICU_OFFSET + XINVLTLB_OFFSET); 1638#endif /* APIC_IO */ 1639} 1640 1641void 1642invlpg(u_int addr) 1643{ 1644 __asm __volatile("invlpg (%0)"::"r"(addr):"memory"); 1645 1646 /* send a message to the other CPUs */ 1647 smp_invltlb(); 1648} 1649 1650void 1651invltlb(void) 1652{ 1653 u_long temp; 1654 1655 /* 1656 * This should be implemented as load_cr3(rcr3()) when load_cr3() is 1657 * inlined. 1658 */ 1659 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory"); 1660 1661 /* send a message to the other CPUs */ 1662 smp_invltlb(); 1663} 1664