mptable.c revision 26101
1/* 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $Id: mp_machdep.c,v 1.10 1997/05/22 22:35:42 fsmp Exp $ 26 */ 27 28#include "opt_smp.h" 29 30#define FIX_MP_TABLE_WORKS 31 32#include "opt_serial.h" 33 34#include <sys/param.h> /* for KERNBASE */ 35#include <sys/types.h> 36#include <sys/sysproto.h> 37#include <sys/time.h> 38#include <sys/systm.h> 39 40#include <vm/vm.h> /* for KERNBASE */ 41#include <vm/vm_param.h> /* for KERNBASE */ 42#include <vm/pmap.h> /* for KERNBASE */ 43#include <machine/pmap.h> /* for KERNBASE */ 44 45#include <machine/smp.h> 46#include <machine/apic.h> 47#include <machine/mpapic.h> 48#include <machine/cpufunc.h> 49#include <machine/segments.h> 50#include <machine/smptests.h> /** TEST_DEFAULT_CONFIG */ 51 52#include <i386/i386/cons.h> /* cngetc() */ 53 54#if defined(APIC_IO) 55#include <i386/include/md_var.h> /* setidt() */ 56#include <i386/isa/icu.h> /* Xinvltlb() */ 57#include <i386/isa/isa_device.h> /* Xinvltlb() */ 58#endif /* APIC_IO */ 59 60#define WARMBOOT_TARGET 0 61#define WARMBOOT_OFF (KERNBASE + 0x0467) 62#define WARMBOOT_SEG (KERNBASE + 0x0469) 63 64#define BIOS_BASE (0xf0000) 65#define BIOS_SIZE (0x10000) 66#define BIOS_COUNT (BIOS_SIZE/4) 67 68#define CMOS_REG (0x70) 69#define CMOS_DATA (0x71) 70#define BIOS_RESET (0x0f) 71#define BIOS_WARM (0x0a) 72 73/* 74 * this code MUST be enabled here and in mpboot.s. 75 * it follows the very early stages of AP boot by placing values in CMOS ram. 76 * it NORMALLY will never be needed and thus the primitive method for enabling. 77 * 78#define CHECK_POINTS 79 */ 80 81#if defined(CHECK_POINTS) 82#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 83#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 84 85#define CHECK_INIT(D); \ 86 CHECK_WRITE(0x34, (D)); \ 87 CHECK_WRITE(0x35, (D)); \ 88 CHECK_WRITE(0x36, (D)); \ 89 CHECK_WRITE(0x37, (D)); \ 90 CHECK_WRITE(0x38, (D)); \ 91 CHECK_WRITE(0x39, (D)); 92 93#define CHECK_PRINT(S); \ 94 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 95 (S), \ 96 CHECK_READ(0x34), \ 97 CHECK_READ(0x35), \ 98 CHECK_READ(0x36), \ 99 CHECK_READ(0x37), \ 100 CHECK_READ(0x38), \ 101 CHECK_READ(0x39)); 102 103#else /* CHECK_POINTS */ 104 105#define CHECK_INIT(D) 106#define CHECK_PRINT(S) 107 108#endif /* CHECK_POINTS */ 109 110 111/** FIXME: what system files declare these??? */ 112extern struct region_descriptor r_gdt, r_idt; 113 114/* global data */ 115struct proc *SMPcurproc[NCPU]; 116struct pcb *SMPcurpcb[NCPU]; 117struct timeval SMPruntime[NCPU]; 118 119int mp_ncpus; /* # of CPUs, including BSP */ 120int mp_naps; /* # of Applications processors */ 121int mp_nbusses; /* # of busses */ 122int mp_napics; /* # of IO APICs */ 123int mpenabled; 124int boot_cpu_id; /* designated BSP */ 125vm_offset_t cpu_apic_address; 126vm_offset_t io_apic_address[NAPIC]; 127 128u_int32_t cpu_apic_versions[NCPU]; 129u_int32_t io_apic_versions[NAPIC]; 130 131/* 132 * APIC ID logical/physical mapping structures 133 */ 134int cpu_num_to_apic_id[NCPU]; 135int io_num_to_apic_id[NAPIC]; 136int apic_id_to_logical[NAPICID]; 137 138/* 139 * look for MP compliant motherboard. 140 */ 141 142static u_int boot_address; 143static u_int base_memory; 144 145static int picmode; /* 0: virtual wire mode, 1: PIC mode */ 146static u_int mpfps; 147static int search_for_sig(u_int32_t target, int count); 148static int mp_probe(u_int base_top); 149static void mp_enable(u_int boot_addr); 150 151 152/* 153 * calculate usable address in base memory for AP trampoline code 154 */ 155u_int 156mp_bootaddress(u_int basemem) 157{ 158 base_memory = basemem * 1024; /* convert to bytes */ 159 160 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ 161 if ((base_memory - boot_address) < bootMP_size) 162 boot_address -= 4096; /* not enough, lower by 4k */ 163 164 return boot_address; 165} 166 167 168/* 169 * startup the SMP processors 170 */ 171void 172mp_start(void) 173{ 174 /* look for MP capable motherboard */ 175 if (mp_probe(base_memory)) 176 mp_enable(boot_address); 177 else 178 panic( "MP FPS not found, can't continue!" ); 179 180 /* finish pmap initialization - turn off V==P mapping at zero */ 181 pmap_bootstrap2(); 182} 183 184 185/* 186 * print various information about the SMP system hardware and setup 187 */ 188void 189mp_announce(void) 190{ 191 int x; 192 193 printf("FreeBSD/SMP: Multiprocessor motherboard\n"); 194 printf(" cpu0 (BSP): apic id: %d", CPU_TO_ID(0)); 195 printf(", version: 0x%08x\n", cpu_apic_versions[0]); 196 for (x = 1; x <= mp_naps; ++x) { 197 printf(" cpu%d (AP): apic id: %d", x, CPU_TO_ID(x)); 198 printf(", version: 0x%08x\n", cpu_apic_versions[x]); 199 } 200 201#if defined(APIC_IO) 202 for (x = 0; x < mp_napics; ++x) { 203 printf(" io%d (APIC): apic id: %d", x, IO_TO_ID(x)); 204 printf(", version: 0x%08x\n", io_apic_versions[x]); 205 } 206#else 207 printf(" Warning: APIC I/O disabled\n"); 208#endif /* APIC_IO */ 209} 210 211 212/* 213 * AP cpu's call this to sync up protected mode. 214 */ 215void 216init_secondary(void) 217{ 218 int gsel_tss, slot; 219 220 r_gdt.rd_limit = sizeof(gdt[0]) * (NGDT + NCPU) - 1; 221 r_gdt.rd_base = (int) gdt; 222 lgdt(&r_gdt); /* does magic intra-segment return */ 223 lidt(&r_idt); 224 lldt(_default_ldt); 225 226 slot = NGDT + cpunumber(); 227 gsel_tss = GSEL(slot, SEL_KPL); 228 gdt[slot].sd.sd_type = SDT_SYS386TSS; 229 ltr(gsel_tss); 230 231 load_cr0(0x8005003b); /* XXX! */ 232} 233 234 235#if defined(APIC_IO) 236void 237configure_local_apic(void) 238{ 239 u_char byte; 240 u_int32_t temp; 241 242 if (picmode) { 243 outb(0x22, 0x70); /* select IMCR */ 244 byte = inb(0x23); /* current contents */ 245 byte |= 0x01; /* mask external INTR */ 246 outb(0x23, byte); /* disconnect 8259s/NMI */ 247 } 248 /* mask the LVT1 */ 249 temp = apic_base[APIC_LVT1]; 250 temp |= APIC_LVT_M; 251 apic_base[APIC_LVT1] = temp; 252} 253#endif /* APIC_IO */ 254 255 256/******************************************************************* 257 * local functions and data 258 */ 259 260static int 261mp_probe(u_int base_top) 262{ 263 int x; 264 u_long segment; 265 u_int32_t target; 266 267 /* see if EBDA exists */ 268 if (segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) { 269 /* search first 1K of EBDA */ 270 target = (u_int32_t) (segment << 4); 271 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 272 goto found; 273 } else { 274 /*last 1K of base memory, effective 'top of base' is passed in*/ 275 target = (u_int32_t) (base_top - 0x400); 276 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 277 goto found; 278 } 279 280 /* search the BIOS */ 281 target = (u_int32_t) BIOS_BASE; 282 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) 283 goto found; 284 285 /* nothing found */ 286 mpfps = mpenabled = 0; 287 return 0; 288 289found: /* please forgive the 'goto'! */ 290 /* flag fact that we are running multiple processors */ 291 mpfps = x; 292 mpenabled = 1; 293 return 1; 294} 295 296 297/* 298 * start the SMP system 299 */ 300static int parse_mp_table(void); 301static void default_mp_table(int type); 302static int start_all_aps(u_int boot_addr); 303 304static void 305mp_enable(u_int boot_addr) 306{ 307 int x; 308#if defined(APIC_IO) 309 int apic; 310 u_int ux; 311#endif /* APIC_IO */ 312 313 /* examine the MP table for needed info */ 314 x = parse_mp_table(); 315 316 /* create pages for (address common) cpu APIC and each IO APIC */ 317 pmap_bootstrap_apics(); 318 319 /* can't process default configs till the CPU APIC is pmapped */ 320 if (x) 321 default_mp_table(x); 322 323#if defined(APIC_IO) 324 /* fill the LOGICAL io_apic_versions table */ 325 for (apic = 0; apic < mp_napics; ++apic) { 326 ux = io_apic_read(apic, IOAPIC_VER); 327 io_apic_versions[apic] = ux; 328 } 329 330 /* program each IO APIC in the system */ 331 for (apic = 0; apic < mp_napics; ++apic) 332 if (io_apic_setup(apic) < 0) 333 panic( "IO APIC setup failure" ); 334 335 /* install an inter-CPU IPI for TLB invalidation */ 336 setidt(ICU_OFFSET + XINVLTLB_OFFSET, Xinvltlb, 337 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 338#endif /* APIC_IO */ 339 340 /* start each Application Processor */ 341 start_all_aps(boot_addr); 342} 343 344 345/* 346 * look for the MP spec signature 347 */ 348 349/* string defined by the Intel MP Spec as identifying the MP table */ 350#define MP_SIG 0x5f504d5f /* _MP_ */ 351#define NEXT(X) ((X) += 4) 352static int 353search_for_sig(u_int32_t target, int count) 354{ 355 int x; 356 u_int32_t *addr = (u_int32_t *) (KERNBASE + target); 357 358 for (x = 0; x < count; NEXT(x)) 359 if (addr[x] == MP_SIG) 360 /* make array index a byte index */ 361 return (target + (x * sizeof(u_int32_t))); 362 363 return -1; 364} 365 366 367#define PROCENTRY_FLAG_EN 0x01 368#define PROCENTRY_FLAG_BP 0x02 369#define IOAPICENTRY_FLAG_EN 0x01 370 371/* MP Floating Pointer Structure */ 372typedef struct MPFPS { 373 char signature[4]; 374 void *pap; 375 u_char length; 376 u_char spec_rev; 377 u_char checksum; 378 u_char mpfb1; 379 u_char mpfb2; 380 u_char mpfb3; 381 u_char mpfb4; 382 u_char mpfb5; 383} *mpfps_t; 384/* MP Configuration Table Header */ 385typedef struct MPCTH { 386 char signature[4]; 387 u_short base_table_length; 388 u_char spec_rev; 389 u_char checksum; 390 u_char oem_id[8]; 391 u_char product_id[12]; 392 void *oem_table_pointer; 393 u_short oem_table_size; 394 u_short entry_count; 395 void *apic_address; 396 u_short extended_table_length; 397 u_char extended_table_checksum; 398 u_char reserved; 399} *mpcth_t; 400 401 402typedef struct PROCENTRY { 403 u_char type; 404 u_char apic_id; 405 u_char apic_version; 406 u_char cpu_flags; 407 u_long cpu_signature; 408 u_long feature_flags; 409 u_long reserved1; 410 u_long reserved2; 411} *proc_entry_ptr; 412 413typedef struct BUSENTRY { 414 u_char type; 415 u_char bus_id; 416 char bus_type[6]; 417} *bus_entry_ptr; 418 419typedef struct IOAPICENTRY { 420 u_char type; 421 u_char apic_id; 422 u_char apic_version; 423 u_char apic_flags; 424 void *apic_address; 425} *io_apic_entry_ptr; 426 427typedef struct INTENTRY { 428 u_char type; 429 u_char int_type; 430 u_short int_flags; 431 u_char src_bus_id; 432 u_char src_bus_irq; 433 u_char dst_apic_id; 434 u_char dst_apic_int; 435} *int_entry_ptr; 436/* descriptions of MP basetable entries */ 437typedef struct BASETABLE_ENTRY { 438 u_char type; 439 u_char length; 440 char name[16]; 441} basetable_entry; 442 443static basetable_entry basetable_entry_types[] = 444{ 445 {0, 20, "Processor"}, 446 {1, 8, "Bus"}, 447 {2, 8, "I/O APIC"}, 448 {3, 8, "I/O INT"}, 449 {4, 8, "Local INT"} 450}; 451 452typedef struct BUSDATA { 453 u_char bus_id; 454 enum busTypes bus_type; 455} bus_datum; 456 457typedef struct INTDATA { 458 u_char int_type; 459 u_short int_flags; 460 u_char src_bus_id; 461 u_char src_bus_irq; 462 u_char dst_apic_id; 463 u_char dst_apic_int; 464} io_int, local_int; 465 466typedef struct BUSTYPENAME { 467 u_char type; 468 char name[7]; 469} bus_type_name; 470 471static bus_type_name bus_type_table[] = 472{ 473 {CBUS, "CBUS"}, 474 {CBUSII, "CBUSII"}, 475 {EISA, "EISA"}, 476 {UNKNOWN_BUSTYPE, "---"}, 477 {UNKNOWN_BUSTYPE, "---"}, 478 {ISA, "ISA"}, 479 {UNKNOWN_BUSTYPE, "---"}, 480 {UNKNOWN_BUSTYPE, "---"}, 481 {UNKNOWN_BUSTYPE, "---"}, 482 {UNKNOWN_BUSTYPE, "---"}, 483 {UNKNOWN_BUSTYPE, "---"}, 484 {UNKNOWN_BUSTYPE, "---"}, 485 {PCI, "PCI"}, 486 {UNKNOWN_BUSTYPE, "---"}, 487 {UNKNOWN_BUSTYPE, "---"}, 488 {UNKNOWN_BUSTYPE, "---"}, 489 {UNKNOWN_BUSTYPE, "---"}, 490 {XPRESS, "XPRESS"}, 491 {UNKNOWN_BUSTYPE, "---"} 492}; 493/* from MP spec v1.4, table 5-1 */ 494static int default_data[7][5] = 495{ 496/* nbus, id0, type0, id1, type1 */ 497 {1, 0, ISA, 255, 255}, 498 {1, 0, EISA, 255, 255}, 499 {1, 0, EISA, 255, 255}, 500 {0, 255, 255, 255, 255},/* MCA not supported */ 501 {2, 0, ISA, 1, PCI}, 502 {2, 0, EISA, 1, PCI}, 503 {0, 255, 255, 255, 255} /* MCA not supported */ 504}; 505 506 507/* the bus data */ 508bus_datum bus_data[NBUS]; 509 510/* the IO INT data, one entry per possible APIC INTerrupt */ 511io_int io_apic_ints[NINTR]; 512 513static int nintrs; 514 515#if defined(FIX_MP_TABLE_WORKS) 516static void fix_mp_table __P((void)); 517#endif /* FIX_MP_TABLE_WORKS */ 518 519static void processor_entry __P((proc_entry_ptr entry, int *cpu)); 520static void io_apic_entry __P((io_apic_entry_ptr entry, int *apic)); 521static void bus_entry __P((bus_entry_ptr entry, int *bus)); 522static void int_entry __P((int_entry_ptr entry, int *intr)); 523static int lookup_bus_type __P((char *name)); 524 525 526/* 527 * parse an Intel MP specification table 528 */ 529static int 530parse_mp_table(void) 531{ 532 int x; 533 mpfps_t fps; 534 mpcth_t cth; 535 int totalSize; 536 void *position; 537 int count; 538 int type; 539 int apic, bus, cpu, intr; 540 541 /* clear physical APIC ID to logical CPU/IO table */ 542 for (x = 0; x < NAPICID; ++x) 543 ID_TO_IO(x) = -1; 544 545 /* clear logical CPU to APIC ID table */ 546 for (x = 0; x < NCPU; ++x) 547 CPU_TO_ID(x) = -1; 548 549 /* clear logical IO to APIC ID table */ 550 for (x = 0; x < NAPIC; ++x) 551 IO_TO_ID(x) = -1; 552 553 /* clear IO APIC address table */ 554 for (x = 0; x < NAPIC; ++x) 555 io_apic_address[x] = ~0; 556 557 /* clear bus data table */ 558 for (x = 0; x < NBUS; ++x) 559 bus_data[x].bus_id = 0xff; 560 561 /* clear IO APIC INT table */ 562 for (x = 0; x < NINTR; ++x) 563 io_apic_ints[x].int_type = 0xff; 564 nintrs = 0; 565 566 /* count the BSP */ 567 mp_ncpus = 1; 568 569 /* setup the cpu/apic mapping arrays */ 570 boot_cpu_id = -1; 571 572 /* local pointer */ 573 fps = (mpfps_t) mpfps; 574 575 /* record whether PIC or virtual-wire mode */ 576 picmode = (fps->mpfb2 & 0x80) ? 1 : 0; 577 578 /* check for use of 'default' configuration */ 579#if defined(TEST_DEFAULT_CONFIG) 580 /* use default addresses */ 581 cpu_apic_address = DEFAULT_APIC_BASE; 582 io_apic_address[0] = DEFAULT_IO_APIC_BASE; 583 584 /* return default configuration type */ 585 return TEST_DEFAULT_CONFIG; 586#else 587 if (fps->mpfb1 != 0) { 588 /* use default addresses */ 589 cpu_apic_address = DEFAULT_APIC_BASE; 590 io_apic_address[0] = DEFAULT_IO_APIC_BASE; 591 592 /* return default configuration type */ 593 return fps->mpfb1; 594 } 595#endif /* TEST_DEFAULT_CONFIG */ 596 597 if ((cth = fps->pap) == 0) 598 panic( "MP Configuration Table Header MISSING!" ); 599 600 cpu_apic_address = (vm_offset_t) cth->apic_address; 601 602 totalSize = cth->base_table_length - sizeof(struct MPCTH); 603 position = (u_char *) cth + sizeof(struct MPCTH); 604 count = cth->entry_count; 605 606 apic = 0; /* logical apic# start @ 0 */ 607 bus = 0; /* logical bus# start @ 0 */ 608 cpu = 1; /* logical cpu# start @ 0, BUT reserve 0 for */ 609 /* BSP */ 610 intr = 0; /* unknown */ 611 612 /* walk the table, recording info of interest */ 613 while (count--) { 614 switch (type = *(u_char *) position) { 615 case 0: 616 processor_entry(position, &cpu); 617 break; 618 case 1: 619 bus_entry(position, &bus); 620 break; 621 case 2: 622 io_apic_entry(position, &apic); 623 break; 624 case 3: 625 int_entry(position, &intr); 626 break; 627 case 4: 628 /* int_entry(position); */ 629 break; 630 default: 631 panic( "mpfps Base Table HOSED!" ); 632 /* NOTREACHED */ 633 } 634 635 totalSize -= basetable_entry_types[type].length; 636 (u_char *) position += basetable_entry_types[type].length; 637 } 638 639 if (boot_cpu_id == -1) 640 panic( "NO BSP found!" ); 641 642 /* record # of APs found */ 643 mp_naps = (cpu - 1); 644 645 /* record # of busses found */ 646 mp_nbusses = bus; 647 648 /* record # of IO APICs found */ 649 mp_napics = apic; 650 651 /* record # of IO APICs found */ 652 nintrs = intr; 653 654#if defined(FIX_MP_TABLE_WORKS) 655 /* post scan cleanup */ 656 fix_mp_table(); 657#endif /* FIX_MP_TABLE_WORKS */ 658 659 /* report fact that its NOT a default configuration */ 660 return 0; 661} 662 663 664/* 665 * parse an Intel MP specification table 666 */ 667#if defined(FIX_MP_TABLE_WORKS) 668static void 669fix_mp_table(void) 670{ 671 int x; 672 int id; 673 int bus_0; 674 int bus_pci; 675 int num_pci_bus; 676 677 /* 678 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS 679 * did it wrong. The MP spec says that when more than 1 PCI bus 680 * exists the BIOS must begin with bus entries for the PCI bus and use 681 * actual PCI bus numbering. This implies that when only 1 PCI bus 682 * exists the BIOS can choose to ignore this ordering, and indeed many 683 * MP motherboards do ignore it. This causes a problem when the PCI 684 * sub-system makes requests of the MP sub-system based on PCI bus 685 * numbers. So here we look for the situation and renumber the 686 * busses and associated INTs in an effort to "make it right". 687 */ 688 689 /* find bus 0, PCI bus, count the number of PCI busses */ 690 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { 691 if (bus_data[x].bus_id == 0) { 692 bus_0 = x; 693 } 694 if (bus_data[x].bus_type == PCI) { 695 ++num_pci_bus; 696 bus_pci = x; 697 } 698 } 699 /* 700 * bus_0 == slot of bus with ID of 0 701 * bus_pci == slot of last PCI bus encountered 702 */ 703 704 /* check the 1 PCI bus case for sanity */ 705 if (num_pci_bus == 1) { 706 707 /* if it is number 0 all is well */ 708 if (bus_data[bus_pci].bus_id == 0) 709 return; 710 711 /* mis-numbered, swap with whichever bus uses slot 0 */ 712 713 /* swap the bus entry types */ 714 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type; 715 bus_data[bus_0].bus_type = PCI; 716 717 /* swap each relavant INTerrupt entry */ 718 id = bus_data[bus_pci].bus_id; 719 for (x = 0; x < nintrs; ++x) { 720 if (io_apic_ints[x].src_bus_id == id) { 721 io_apic_ints[x].src_bus_id = 0; 722 } 723 else if (io_apic_ints[x].src_bus_id == 0) { 724 io_apic_ints[x].src_bus_id = id; 725 } 726 } 727 } 728 /* sanity check if more than 1 PCI bus */ 729 else if (num_pci_bus > 1) { 730 for (x = 0; x < mp_nbusses; ++x) { 731 if (bus_data[x].bus_type != PCI) 732 continue; 733 if (bus_data[x].bus_id >= num_pci_bus ) 734 panic( "bad PCI bus numbering" ); 735 } 736 } 737} 738#endif /* FIX_MP_TABLE_WORKS */ 739 740 741static void 742processor_entry(proc_entry_ptr entry, int *cpu) 743{ 744 int x = *cpu; 745 746 /* check for usability */ 747 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN)) 748 return; 749 750 /* check for BSP flag */ 751 if (entry->cpu_flags & PROCENTRY_FLAG_BP) { 752 /* always give boot CPU the logical value of 0 */ 753 x = 0; 754 boot_cpu_id = entry->apic_id; 755 } else { 756 /* add another AP to list, if less than max number of CPUs */ 757 if (x == NCPU) { 758 printf("Warning: only using %d of the available CPUs!\n", x); 759 return; 760 } 761 ++(*cpu); 762 } 763 764 CPU_TO_ID(x) = entry->apic_id; 765 ID_TO_CPU(entry->apic_id) = x; 766} 767 768 769static void 770bus_entry(bus_entry_ptr entry, int *bus) 771{ 772 int x, y; 773 char name[8]; 774 char c; 775 776 if ((x = (*bus)++) == NBUS) 777 panic( "too many busses, increase 'NBUS'" ); 778 779 /* encode the name into an index */ 780 for (y = 0; y < 6; ++y) { 781 if ((c = entry->bus_type[y]) == ' ') 782 break; 783 name[y] = c; 784 } 785 name[y] = '\0'; 786 787 if ((y = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) 788 panic( "unknown bus type: '%s'", name ); 789 790 bus_data[x].bus_id = entry->bus_id; 791 bus_data[x].bus_type = y; 792} 793 794 795static void 796io_apic_entry(io_apic_entry_ptr entry, int *apic) 797{ 798 int x; 799 800 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) 801 return; 802 803 if ((x = (*apic)++) == NAPIC) 804 panic( "too many APICs, increase 'NAPIC'" ); 805 806 IO_TO_ID(x) = entry->apic_id; 807 ID_TO_IO(entry->apic_id) = x; 808 809 io_apic_address[x] = (vm_offset_t) entry->apic_address; 810} 811 812 813static int 814lookup_bus_type(char *name) 815{ 816 int x; 817 818 for (x = 0; x < MAX_BUSTYPE; ++x) 819 if (strcmp(bus_type_table[x].name, name) == 0) 820 return bus_type_table[x].type; 821 822 return UNKNOWN_BUSTYPE; 823} 824 825 826static void 827int_entry(int_entry_ptr entry, int *intr) 828{ 829 int x; 830 831 if ((x = (*intr)++) == NINTR) 832 panic( "too many INTs, increase 'NINTR'" ); 833 834 io_apic_ints[x].int_type = entry->int_type; 835 io_apic_ints[x].int_flags = entry->int_flags; 836 io_apic_ints[x].src_bus_id = entry->src_bus_id; 837 io_apic_ints[x].src_bus_irq = entry->src_bus_irq; 838 io_apic_ints[x].dst_apic_id = entry->dst_apic_id; 839 io_apic_ints[x].dst_apic_int = entry->dst_apic_int; 840} 841 842 843static int 844apic_int_is_bus_type(int intr, int bus_type) 845{ 846 int bus; 847 848 for (bus = 0; bus < mp_nbusses; ++bus) 849 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) 850 && ((int) bus_data[bus].bus_type == bus_type)) 851 return 1; 852 853 return 0; 854} 855 856 857/* 858 * determine which APIC pin an ISA INT is attached to. 859 */ 860#define INTTYPE(I) (io_apic_ints[(I)].int_type) 861#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) 862 863#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) 864int 865get_isa_apic_irq(int isaIRQ) 866{ 867 int intr; 868 869#if defined(SMP_TIMER_NC) 870 if (isaIRQ == 0) 871 return -1; 872#endif /* SMP_TIMER_NC */ 873 874 for (intr = 0; intr < nintrs; ++intr) /* search each INT record */ 875 if ((INTTYPE(intr) == 0) 876 && (SRCBUSIRQ(intr) == isaIRQ)) /* a candidate IRQ */ 877 if (apic_int_is_bus_type(intr, ISA)) /* check bus match */ 878 return INTPIN(intr); /* exact match */ 879 880 return -1; /* NOT found */ 881} 882#undef SRCBUSIRQ 883 884 885/* 886 * 887 */ 888u_int 889get_isa_apic_mask(u_int isaMASK) 890{ 891 int apicpin, isairq; 892 893 isairq = ffs(isaMASK); 894 if (isairq == 0) { 895 return 0; 896 } 897 --isairq; 898 899 apicpin = get_isa_apic_irq( isairq ); 900 if (apicpin == -1) { 901 apicpin = get_eisa_apic_irq( isairq ); 902 if (apicpin == -1) { 903 return 0; 904 } 905 } 906 907 return (1 << apicpin); 908} 909 910 911/* 912 * determine which APIC pin an EISA INT is attached to. 913 */ 914#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) 915int 916get_eisa_apic_irq(int eisaIRQ) 917{ 918 int intr; 919 920#if defined(SMP_TIMER_NC) 921 if (eisaIRQ == 0) 922 return -1; 923#endif /* SMP_TIMER_NC */ 924 925 for (intr = 0; intr < nintrs; ++intr) /* search each INT record */ 926 if ((INTTYPE(intr) == 0) 927 && (SRCBUSIRQ(intr) == eisaIRQ)) /* a candidate IRQ */ 928 if (apic_int_is_bus_type(intr, EISA)) /* check bus match */ 929 return INTPIN(intr); /* exact match */ 930 931 return -1; /* NOT found */ 932} 933#undef SRCBUSIRQ 934 935 936/* 937 * determine which APIC pin a PCI INT is attached to. 938 */ 939#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) 940#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) 941#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) 942int 943get_pci_apic_irq(int pciBus, int pciDevice, int pciInt) 944{ 945 int intr; 946 947 --pciInt; /* zero based */ 948 949 for (intr = 0; intr < nintrs; ++intr) /* search each record */ 950 if ((INTTYPE(intr) == 0) 951#if defined(FIX_MP_TABLE_WORKS) 952 && (SRCBUSID(intr) == pciBus) 953#endif /* FIX_MP_TABLE_WORKS */ 954 && (SRCBUSDEVICE(intr) == pciDevice) 955 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ 956 if (apic_int_is_bus_type(intr, PCI)) /* check bus match */ 957 return INTPIN(intr); /* exact match */ 958 959 return -1; /* NOT found */ 960} 961#undef SRCBUSLINE 962#undef SRCBUSDEVICE 963#undef SRCBUSID 964 965#undef INTPIN 966#undef INTTYPE 967 968 969/* 970 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt 971 */ 972int 973undirect_pci_irq(int rirq) 974{ 975#if defined(READY) 976 printf("Freeing redirected PCI irq %d.\n", rirq); 977 /** FIXME: tickle the MB redirector chip */ 978 return ???; 979#else 980 printf("Freeing (NOT implemented) redirected PCI irq %d.\n", rirq); 981 return 0; 982#endif /* READY */ 983} 984 985 986/* 987 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt. 988 * 989 * XXX FIXME: 990 * Exactly what this means is unclear at this point. It is a solution 991 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard 992 * could route any of the ISA INTs to upper (>15) IRQ values. But most would 993 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an 994 * option. 995 */ 996int 997undirect_isa_irq(int rirq) 998{ 999#if defined(READY) 1000 printf("Freeing redirected ISA irq %d.\n", rirq); 1001 /** FIXME: tickle the MB redirector chip */ 1002 return ???; 1003#else 1004 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq); 1005 return 0; 1006#endif /* READY */ 1007} 1008 1009 1010/* 1011 * given a bus ID, return: 1012 * the bus type if found 1013 * -1 if NOT found 1014 */ 1015int 1016apic_bus_type(int id) 1017{ 1018 int x; 1019 1020 for (x = 0; x < mp_nbusses; ++x) 1021 if (bus_data[x].bus_id == id) 1022 return bus_data[x].bus_type; 1023 1024 return -1; 1025} 1026 1027 1028/* 1029 * given a LOGICAL APIC# and pin#, return: 1030 * the associated src bus ID if found 1031 * -1 if NOT found 1032 */ 1033int 1034apic_src_bus_id(int apic, int pin) 1035{ 1036 int x; 1037 1038 /* search each of the possible INTerrupt sources */ 1039 for (x = 0; x < nintrs; ++x) 1040 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1041 (pin == io_apic_ints[x].dst_apic_int)) 1042 return (io_apic_ints[x].src_bus_id); 1043 1044 return -1; /* NOT found */ 1045} 1046 1047 1048/* 1049 * given a LOGICAL APIC# and pin#, return: 1050 * the associated src bus IRQ if found 1051 * -1 if NOT found 1052 */ 1053int 1054apic_src_bus_irq(int apic, int pin) 1055{ 1056 int x; 1057 1058 for (x = 0; x < nintrs; x++) 1059 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1060 (pin == io_apic_ints[x].dst_apic_int)) 1061 return (io_apic_ints[x].src_bus_irq); 1062 1063 return -1; /* NOT found */ 1064} 1065 1066 1067/* 1068 * given a LOGICAL APIC# and pin#, return: 1069 * the associated INTerrupt type if found 1070 * -1 if NOT found 1071 */ 1072int 1073apic_int_type(int apic, int pin) 1074{ 1075 int x; 1076 1077 /* search each of the possible INTerrupt sources */ 1078 for (x = 0; x < nintrs; ++x) 1079 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1080 (pin == io_apic_ints[x].dst_apic_int)) 1081 return (io_apic_ints[x].int_type); 1082 1083 return -1; /* NOT found */ 1084} 1085 1086 1087/* 1088 * given a LOGICAL APIC# and pin#, return: 1089 * the associated trigger mode if found 1090 * -1 if NOT found 1091 */ 1092int 1093apic_trigger(int apic, int pin) 1094{ 1095 int x; 1096 1097 /* search each of the possible INTerrupt sources */ 1098 for (x = 0; x < nintrs; ++x) 1099 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1100 (pin == io_apic_ints[x].dst_apic_int)) 1101 return ((io_apic_ints[x].int_flags >> 2) & 0x03); 1102 1103 return -1; /* NOT found */ 1104} 1105 1106 1107/* 1108 * given a LOGICAL APIC# and pin#, return: 1109 * the associated 'active' level if found 1110 * -1 if NOT found 1111 */ 1112int 1113apic_polarity(int apic, int pin) 1114{ 1115 int x; 1116 1117 /* search each of the possible INTerrupt sources */ 1118 for (x = 0; x < nintrs; ++x) 1119 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1120 (pin == io_apic_ints[x].dst_apic_int)) 1121 return (io_apic_ints[x].int_flags & 0x03); 1122 1123 return -1; /* NOT found */ 1124} 1125 1126 1127/* 1128 * set data according to MP defaults 1129 * FIXME: probably not complete yet... 1130 */ 1131static void 1132default_mp_table(int type) 1133{ 1134 int ap_cpu_id; 1135#if defined(APIC_IO) 1136 u_int32_t ux; 1137 int io_apic_id; 1138 int pin; 1139#endif /* APIC_IO */ 1140 1141#if 0 1142 printf(" MP default config type: %d\n", type); 1143 switch (type) { 1144 case 1: 1145 printf(" bus: ISA, APIC: 82489DX\n"); 1146 break; 1147 case 2: 1148 printf(" bus: EISA, APIC: 82489DX\n"); 1149 break; 1150 case 3: 1151 printf(" bus: EISA, APIC: 82489DX\n"); 1152 break; 1153 case 4: 1154 printf(" bus: MCA, APIC: 82489DX\n"); 1155 break; 1156 case 5: 1157 printf(" bus: ISA+PCI, APIC: Integrated\n"); 1158 break; 1159 case 6: 1160 printf(" bus: EISA+PCI, APIC: Integrated\n"); 1161 break; 1162 case 7: 1163 printf(" bus: MCA+PCI, APIC: Integrated\n"); 1164 break; 1165 default: 1166 printf(" future type\n"); 1167 break; 1168 /* NOTREACHED */ 1169 } 1170#endif /* 0 */ 1171 1172 boot_cpu_id = (apic_base[APIC_ID] & APIC_ID_MASK) >> 24; 1173 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; 1174 1175 /* BSP */ 1176 CPU_TO_ID(0) = boot_cpu_id; 1177 ID_TO_CPU(boot_cpu_id) = 0; 1178 1179 /* one and only AP */ 1180 CPU_TO_ID(1) = ap_cpu_id; 1181 ID_TO_CPU(ap_cpu_id) = 1; 1182 mp_naps = 1; 1183 1184 /* one and only IO APIC */ 1185#if defined(APIC_IO) 1186 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; 1187 1188 /* 1189 * sanity check, refer to MP spec section 3.6.6, last paragraph 1190 * necessary as some hardware isn't properly setting up the IO APIC 1191 */ 1192#if defined(REALLY_ANAL_IOAPICID_VALUE) 1193 if (io_apic_id != 2) { 1194#else 1195 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { 1196#endif /* REALLY_ANAL_IOAPICID_VALUE */ 1197 ux = io_apic_read(0, IOAPIC_ID); /* get current contents */ 1198 ux &= ~APIC_ID_MASK; /* clear the ID field */ 1199 ux |= 0x02000000; /* set it to '2' */ 1200 io_apic_write(0, IOAPIC_ID, ux); /* write new value */ 1201 ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */ 1202 if ((ux & APIC_ID_MASK) != 0x02000000) 1203 panic( "can't control IO APIC ID, reg: 0x%08x", ux ); 1204 io_apic_id = 2; 1205 } 1206 IO_TO_ID(0) = io_apic_id; 1207 ID_TO_IO(io_apic_id) = 0; 1208 mp_napics = 1; 1209#else 1210 mp_napics = 0; 1211#endif /* APIC_IO */ 1212 1213 /* fill out bus entries */ 1214 switch (type) { 1215 case 1: 1216 case 2: 1217 case 3: 1218 case 5: 1219 case 6: 1220 mp_nbusses = default_data[type - 1][0]; 1221 bus_data[0].bus_id = default_data[type - 1][1]; 1222 bus_data[0].bus_type = default_data[type - 1][2]; 1223 bus_data[1].bus_id = default_data[type - 1][3]; 1224 bus_data[1].bus_type = default_data[type - 1][4]; 1225 break; 1226 1227 /* case 4: case 7: MCA NOT supported */ 1228 default: /* illegal/reserved */ 1229 panic( "BAD default MP config: %d", type ); 1230 /* NOTREACHED */ 1231 } 1232 1233#if defined(APIC_IO) 1234 /* general cases from MP v1.4, table 5-2 */ 1235 for (pin = 0; pin < 16; ++pin) { 1236 io_apic_ints[pin].int_type = 0; 1237 io_apic_ints[pin].int_flags = 0x05; /* edge-triggered/active-hi */ 1238 io_apic_ints[pin].src_bus_id = 0; 1239 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 is caught below */ 1240 io_apic_ints[pin].dst_apic_id = io_apic_id; 1241 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 correspondence */ 1242 } 1243 1244 /* special cases from MP v1.4, table 5-2 */ 1245 if (type == 2) { 1246 io_apic_ints[2].int_type = 0xff; /* N/C */ 1247 io_apic_ints[13].int_type = 0xff; /* N/C */ 1248#if !defined(APIC_MIXED_MODE) 1249 /** FIXME: ??? */ 1250 panic( "sorry, can't support type 2 default yet" ); 1251#endif /* APIC_MIXED_MODE */ 1252 } 1253 else 1254 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ 1255 1256 if (type == 7) 1257 io_apic_ints[0].int_type = 0xff; /* N/C */ 1258 else 1259 io_apic_ints[0].int_type = 3; /* vectored 8259 */ 1260 1261 nintrs = 16; 1262#endif /* APIC_IO */ 1263} 1264 1265 1266static void install_ap_tramp(u_int boot_addr); 1267static int start_ap(int logicalCpu, u_int boot_addr); 1268 1269/* 1270 * start each AP in our list 1271 */ 1272static int 1273start_all_aps(u_int boot_addr) 1274{ 1275 int x; 1276 u_char mpbiosreason; 1277 u_long mpbioswarmvec; 1278 1279 /** 1280 * NOTE: this needs further thought: 1281 * where does it get released? 1282 * should it be set to empy? 1283 * 1284 * get the initial mp_lock with a count of 1 for the BSP 1285 */ 1286 mp_lock = (apic_base[APIC_ID] & APIC_ID_MASK) + 1; 1287 1288 /* initialize BSP's local APIC */ 1289 apic_initialize(1); 1290 1291 /* install the AP 1st level boot code */ 1292 install_ap_tramp(boot_addr); 1293 1294 /* save the current value of the warm-start vector */ 1295 mpbioswarmvec = *((u_long *) WARMBOOT_OFF); 1296 outb(CMOS_REG, BIOS_RESET); 1297 mpbiosreason = inb(CMOS_DATA); 1298 1299 /* start each AP */ 1300 for (x = 1; x <= mp_naps; ++x) { 1301 1302 /* setup a vector to our boot code */ 1303 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 1304 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); 1305 outb(CMOS_REG, BIOS_RESET); 1306 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 1307 1308 /* attempt to start the Application Processor */ 1309 CHECK_INIT(99); /* setup checkpoints */ 1310 if (!start_ap(x, boot_addr)) { 1311 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); 1312 CHECK_PRINT("trace"); /* show checkpoints */ 1313 /* 1314 * better panic as the AP may be running loose 1315 * somewhere 1316 */ 1317 printf("panic y/n? [n] "); 1318 if (cngetc() != 'n') 1319 panic( "bye-bye" ); 1320 } 1321 CHECK_PRINT("trace"); /* show checkpoints */ 1322 1323 /* record its version info */ 1324 cpu_apic_versions[x] = cpu_apic_versions[0]; 1325 } 1326 1327 /* fill in our (BSP) APIC version */ 1328 cpu_apic_versions[0] = apic_base[APIC_VER]; 1329 1330 /* restore the warmstart vector */ 1331 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 1332 outb(CMOS_REG, BIOS_RESET); 1333 outb(CMOS_DATA, mpbiosreason); 1334 1335 /* number of APs actually started */ 1336 return mp_ncpus - 1; 1337} 1338 1339 1340/* 1341 * load the 1st level AP boot code into base memory. 1342 */ 1343 1344/* targets for relocation */ 1345extern void bigJump(void); 1346extern void bootCodeSeg(void); 1347extern void bootDataSeg(void); 1348extern void MPentry(void); 1349extern u_int MP_GDT; 1350extern u_int mp_gdtbase; 1351 1352static void 1353install_ap_tramp(u_int boot_addr) 1354{ 1355 int x; 1356 int size = *(int *) ((u_long) & bootMP_size); 1357 u_char *src = (u_char *) ((u_long) bootMP); 1358 u_char *dst = (u_char *) boot_addr + KERNBASE; 1359 u_int boot_base = (u_int) bootMP; 1360 u_int8_t *dst8; 1361 u_int16_t *dst16; 1362 u_int32_t *dst32; 1363 1364 for (x = 0; x < size; ++x) 1365 *dst++ = *src++; 1366 1367 /* 1368 * modify addresses in code we just moved to basemem. unfortunately we 1369 * need fairly detailed info about mpboot.s for this to work. changes 1370 * to mpboot.s might require changes here. 1371 */ 1372 1373 /* boot code is located in KERNEL space */ 1374 dst = (u_char *) boot_addr + KERNBASE; 1375 1376 /* modify the lgdt arg */ 1377 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 1378 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); 1379 1380 /* modify the ljmp target for MPentry() */ 1381 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 1382 *dst32 = ((u_int) MPentry - KERNBASE); 1383 1384 /* modify the target for boot code segment */ 1385 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 1386 dst8 = (u_int8_t *) (dst16 + 1); 1387 *dst16 = (u_int) boot_addr & 0xffff; 1388 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1389 1390 /* modify the target for boot data segment */ 1391 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 1392 dst8 = (u_int8_t *) (dst16 + 1); 1393 *dst16 = (u_int) boot_addr & 0xffff; 1394 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1395} 1396 1397 1398/* 1399 * this function starts the AP (application processor) identified 1400 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 1401 * to accomplish this. This is necessary because of the nuances 1402 * of the different hardware we might encounter. It ain't pretty, 1403 * but it seems to work. 1404 */ 1405static int 1406start_ap(int logical_cpu, u_int boot_addr) 1407{ 1408 int physical_cpu; 1409 int vector; 1410 int cpus; 1411 u_long icr_lo, icr_hi; 1412 1413 /* get the PHYSICAL APIC ID# */ 1414 physical_cpu = CPU_TO_ID(logical_cpu); 1415 1416 /* calculate the vector */ 1417 vector = (boot_addr >> 12) & 0xff; 1418 1419 /* used as a watchpoint to signal AP startup */ 1420 cpus = mp_ncpus; 1421 1422 /* 1423 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 1424 * and running the target CPU. OR this INIT IPI might be latched (P5 1425 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 1426 * ignored. 1427 */ 1428 1429 /* setup the address for the target AP */ 1430 icr_hi = apic_base[APIC_ICR_HI] & ~APIC_ID_MASK; 1431 icr_hi |= (physical_cpu << 24); 1432 apic_base[APIC_ICR_HI] = icr_hi; 1433 1434 /* do an INIT IPI: assert RESET */ 1435 icr_lo = apic_base[APIC_ICR_LOW] & 0xfff00000; 1436 apic_base[APIC_ICR_LOW] = icr_lo | 0x0000c500; 1437 1438 /* wait for pending status end */ 1439 while (apic_base[APIC_ICR_LOW] & APIC_DELSTAT_MASK) 1440 /* spin */ ; 1441 1442 /* do an INIT IPI: deassert RESET */ 1443 apic_base[APIC_ICR_LOW] = icr_lo | 0x00008500; 1444 1445 /* wait for pending status end */ 1446 u_sleep(10000); /* wait ~10mS */ 1447 while (apic_base[APIC_ICR_LOW] & APIC_DELSTAT_MASK) 1448 /* spin */ ; 1449 1450 /* 1451 * next we do a STARTUP IPI: the previous INIT IPI might still be 1452 * latched, (P5 bug) this 1st STARTUP would then terminate 1453 * immediately, and the previously started INIT IPI would continue. OR 1454 * the previous INIT IPI has already run. and this STARTUP IPI will 1455 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 1456 * will run. 1457 */ 1458 1459 /* do a STARTUP IPI */ 1460 apic_base[APIC_ICR_LOW] = icr_lo | 0x00000600 | vector; 1461 while (apic_base[APIC_ICR_LOW] & APIC_DELSTAT_MASK) 1462 /* spin */ ; 1463 u_sleep(200); /* wait ~200uS */ 1464 1465 /* 1466 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 1467 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 1468 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 1469 * recognized after hardware RESET or INIT IPI. 1470 */ 1471 1472 apic_base[APIC_ICR_LOW] = icr_lo | 0x00000600 | vector; 1473 while (apic_base[APIC_ICR_LOW] & APIC_DELSTAT_MASK) 1474 /* spin */ ; 1475 u_sleep(200); /* wait ~200uS */ 1476 1477 /* wait for it to start */ 1478 set_apic_timer(5000000);/* == 5 seconds */ 1479 while (read_apic_timer()) 1480 if (mp_ncpus > cpus) 1481 return 1; /* return SUCCESS */ 1482 1483 return 0; /* return FAILURE */ 1484} 1485 1486 1487/* 1488 * Flush the TLB on all other CPU's 1489 * 1490 * XXX: Needs to handshake and wait for completion before proceding. 1491 */ 1492void 1493smp_invltlb(void) 1494{ 1495#if defined(APIC_IO) 1496 if (smp_active && invltlb_ok) 1497 all_but_self_ipi(ICU_OFFSET + XINVLTLB_OFFSET); 1498#endif /* APIC_IO */ 1499} 1500 1501void 1502invlpg(u_int addr) 1503{ 1504 __asm __volatile("invlpg (%0)"::"r"(addr):"memory"); 1505 1506 /* send a message to the other CPUs */ 1507 smp_invltlb(); 1508} 1509 1510void 1511invltlb(void) 1512{ 1513 u_long temp; 1514 1515 /* 1516 * This should be implemented as load_cr3(rcr3()) when load_cr3() is 1517 * inlined. 1518 */ 1519 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory"); 1520 1521 /* send a message to the other CPUs */ 1522 smp_invltlb(); 1523} 1524