mptable.c revision 25216
1/* 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $Id: mp_machdep.c,v 1.3 1997/04/28 00:24:47 fsmp Exp $ 26 */ 27 28#include "opt_smp.h" 29 30#define FIX_MP_TABLE_WORKS_NOT 31 32#include "opt_serial.h" 33 34#include <sys/param.h> /* for KERNBASE */ 35#include <sys/types.h> 36#include <sys/sysproto.h> 37#include <sys/time.h> 38#include <sys/systm.h> 39 40#include <vm/vm.h> /* for KERNBASE */ 41#include <vm/vm_param.h> /* for KERNBASE */ 42#include <vm/pmap.h> /* for KERNBASE */ 43#include <machine/pmap.h> /* for KERNBASE */ 44 45#include <machine/smp.h> 46#include <machine/apic.h> 47#include <machine/mpapic.h> 48#include <machine/cpufunc.h> 49#include <machine/segments.h> 50#include <machine/smptests.h> /** TEST_DEFAULT_CONFIG */ 51 52#include <i386/i386/cons.h> /* cngetc() */ 53 54#if defined(APIC_IO) 55#include <i386/include/md_var.h> /* setidt() */ 56#include <i386/isa/icu.h> /* Xinvltlb() */ 57#include <i386/isa/isa_device.h> /* Xinvltlb() */ 58#endif /* APIC_IO */ 59 60#define WARMBOOT_TARGET 0 61#define WARMBOOT_OFF (KERNBASE + 0x0467) 62#define WARMBOOT_SEG (KERNBASE + 0x0469) 63 64#define BIOS_BASE (0xf0000) 65#define BIOS_SIZE (0x10000) 66#define BIOS_COUNT (BIOS_SIZE/4) 67 68#define CMOS_REG (0x70) 69#define CMOS_DATA (0x71) 70#define BIOS_RESET (0x0f) 71#define BIOS_WARM (0x0a) 72 73/* 74 * this code MUST be enabled here and in mpboot.s. 75 * it follows the very early stages of AP boot by placing values in CMOS ram. 76 * it NORMALLY will never be needed and thus the primitive method for enabling. 77 * 78#define CHECK_POINTS 79 */ 80 81#if defined(CHECK_POINTS) 82#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 83#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 84 85#define CHECK_INIT(D); \ 86 CHECK_WRITE(0x34, (D)); \ 87 CHECK_WRITE(0x35, (D)); \ 88 CHECK_WRITE(0x36, (D)); \ 89 CHECK_WRITE(0x37, (D)); \ 90 CHECK_WRITE(0x38, (D)); \ 91 CHECK_WRITE(0x39, (D)); 92 93#define CHECK_PRINT(S); \ 94 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 95 (S), \ 96 CHECK_READ(0x34), \ 97 CHECK_READ(0x35), \ 98 CHECK_READ(0x36), \ 99 CHECK_READ(0x37), \ 100 CHECK_READ(0x38), \ 101 CHECK_READ(0x39)); 102 103#else /* CHECK_POINTS */ 104 105#define CHECK_INIT(D) 106#define CHECK_PRINT(S) 107 108#endif /* CHECK_POINTS */ 109 110 111/** FIXME: what system files declare these??? */ 112extern struct region_descriptor r_gdt, r_idt; 113 114/* global data */ 115struct proc *SMPcurproc[NCPU]; 116struct pcb *SMPcurpcb[NCPU]; 117struct timeval SMPruntime[NCPU]; 118 119int mp_ncpus; /* # of CPUs, including BSP */ 120int mp_naps; /* # of Applications processors */ 121int mp_nbusses; /* # of busses */ 122int mp_napics; /* # of IO APICs */ 123int mpenabled; 124int boot_cpu_id; /* designated BSP */ 125vm_offset_t cpu_apic_address; 126vm_offset_t io_apic_address[NAPIC]; 127 128u_int32_t cpu_apic_versions[NCPU]; 129u_int32_t io_apic_versions[NAPIC]; 130 131/* 132 * APIC ID logical/physical mapping structures 133 */ 134int cpu_num_to_apic_id[NCPU]; 135int io_num_to_apic_id[NAPIC]; 136int apic_id_to_logical[NAPICID]; 137 138/* 139 * look for MP compliant motherboard. 140 */ 141 142static u_int boot_address; 143static u_int base_memory; 144 145static int picmode; /* 0: virtual wire mode, 1: PIC mode */ 146static u_int mpfps; 147static int search_for_sig(u_int32_t target, int count); 148static int mp_probe(u_int base_top); 149static void mp_enable(u_int boot_addr); 150 151 152/* 153 * calculate usable address in base memory for AP trampoline code 154 */ 155u_int 156mp_bootaddress(u_int basemem) 157{ 158 base_memory = basemem * 1024; /* convert to bytes */ 159 160 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ 161 if ((base_memory - boot_address) < bootMP_size) 162 boot_address -= 4096; /* not enough, lower by 4k */ 163 164 return boot_address; 165} 166 167 168/* 169 * startup the SMP processors 170 */ 171void 172mp_start(void) 173{ 174 /* look for MP capable motherboard */ 175 if (mp_probe(base_memory)) 176 mp_enable(boot_address); 177 else { 178 printf("MP FPS NOT FOUND, suggest use of 'mptable' program\n"); 179 panic("can't continue!\n"); 180 } 181 182 /* finish pmap initialization - turn off V==P mapping at zero */ 183 pmap_bootstrap2(); 184} 185 186 187/* 188 * print various information about the SMP system hardware and setup 189 */ 190void 191mp_announce(void) 192{ 193 int x; 194 195 printf("FreeBSD/SMP: Multiprocessor motherboard\n"); 196 printf(" cpu0 (BSP): apic id: %d", CPU_TO_ID(0)); 197 printf(", version: 0x%08x\n", cpu_apic_versions[0]); 198 for (x = 1; x <= mp_naps; ++x) { 199 printf(" cpu%d (AP): apic id: %d", x, CPU_TO_ID(x)); 200 printf(", version: 0x%08x\n", cpu_apic_versions[x]); 201 } 202 203#if defined(APIC_IO) 204 for (x = 0; x < mp_napics; ++x) { 205 printf(" io%d (APIC): apic id: %d", x, IO_TO_ID(x)); 206 printf(", version: 0x%08x\n", io_apic_versions[x]); 207 } 208#else 209 printf(" Warning: APIC I/O disabled\n"); 210#endif /* APIC_IO */ 211} 212 213 214/* 215 * AP cpu's call this to sync up protected mode. 216 */ 217void 218init_secondary(void) 219{ 220 int gsel_tss, slot; 221 222 r_gdt.rd_limit = sizeof(gdt[0]) * (NGDT + NCPU) - 1; 223 r_gdt.rd_base = (int) gdt; 224 lgdt(&r_gdt); /* does magic intra-segment return */ 225 lidt(&r_idt); 226 lldt(_default_ldt); 227 228 slot = NGDT + cpunumber(); 229 gsel_tss = GSEL(slot, SEL_KPL); 230 gdt[slot].sd.sd_type = SDT_SYS386TSS; 231 ltr(gsel_tss); 232 233 load_cr0(0x8005003b); /* XXX! */ 234} 235 236 237#if defined(APIC_IO) 238void 239configure_local_apic(void) 240{ 241 u_char byte; 242 u_int32_t temp; 243 244 if (picmode) { 245 outb(0x22, 0x70); /* select IMCR */ 246 byte = inb(0x23); /* current contents */ 247 byte |= 0x01; /* mask external INTR */ 248 outb(0x23, byte); /* disconnect 8259s/NMI */ 249 } 250 /* mask the LVT1 */ 251 temp = apic_base[APIC_LVT1]; 252 temp |= APIC_LVT_M; 253 apic_base[APIC_LVT1] = temp; 254} 255#endif /* APIC_IO */ 256 257 258/******************************************************************* 259 * local functions and data 260 */ 261 262static int 263mp_probe(u_int base_top) 264{ 265 int x; 266 u_long segment; 267 u_int32_t target; 268 269 /* see if EBDA exists */ 270 if (segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) { 271 /* search first 1K of EBDA */ 272 target = (u_int32_t) (segment << 4); 273 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 274 goto found; 275 } else { 276 /*last 1K of base memory, effective 'top of base' is passed in*/ 277 target = (u_int32_t) (base_top - 0x400); 278 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 279 goto found; 280 } 281 282 /* search the BIOS */ 283 target = (u_int32_t) BIOS_BASE; 284 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) 285 goto found; 286 287 /* nothing found */ 288 mpfps = mpenabled = 0; 289 return 0; 290 291found: /* please forgive the 'goto'! */ 292 /* flag fact that we are running multiple processors */ 293 mpfps = x; 294 mpenabled = 1; 295 return 1; 296} 297 298 299/* 300 * start the SMP system 301 */ 302static int parse_mp_table(void); 303static void default_mp_table(int type); 304static int start_all_aps(u_int boot_addr); 305 306static void 307mp_enable(u_int boot_addr) 308{ 309 int x; 310#if defined(APIC_IO) 311 int apic; 312 u_int ux; 313#endif /* APIC_IO */ 314 315 /* examine the MP table for needed info */ 316 x = parse_mp_table(); 317 318 /* create pages for (address common) cpu APIC and each IO APIC */ 319 pmap_bootstrap_apics(); 320 321 /* can't process default configs till the CPU APIC is pmapped */ 322 if (x) 323 default_mp_table(x); 324 325#if defined(APIC_IO) 326 /* fill the LOGICAL io_apic_versions table */ 327 for (apic = 0; apic < mp_napics; ++apic) { 328 ux = io_apic_read(apic, IOAPIC_VER); 329 io_apic_versions[apic] = ux; 330 } 331 332 /* program each IO APIC in the system */ 333 for (apic = 0; apic < mp_napics; ++apic) 334 if (io_apic_setup(apic) < 0) 335 panic("IO APIC setup failure\n"); 336 337 /* install an inter-CPU IPI for TLB invalidation */ 338 setidt(ICU_OFFSET + XINVLTLB_OFFSET, Xinvltlb, 339 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 340#endif /* APIC_IO */ 341 342 /* start each Application Processor */ 343 start_all_aps(boot_addr); 344} 345 346 347/* 348 * look for the MP spec signature 349 */ 350 351/* string defined by the Intel MP Spec as identifying the MP table */ 352#define MP_SIG 0x5f504d5f /* _MP_ */ 353#define NEXT(X) ((X) += 4) 354static int 355search_for_sig(u_int32_t target, int count) 356{ 357 int x; 358 u_int32_t *addr = (u_int32_t *) (KERNBASE + target); 359 360 for (x = 0; x < count; NEXT(x)) 361 if (addr[x] == MP_SIG) 362 /* make array index a byte index */ 363 return (target + (x * sizeof(u_int32_t))); 364 365 return -1; 366} 367 368 369#define PROCENTRY_FLAG_EN 0x01 370#define PROCENTRY_FLAG_BP 0x02 371#define IOAPICENTRY_FLAG_EN 0x01 372 373/* MP Floating Pointer Structure */ 374typedef struct MPFPS { 375 char signature[4]; 376 void *pap; 377 u_char length; 378 u_char spec_rev; 379 u_char checksum; 380 u_char mpfb1; 381 u_char mpfb2; 382 u_char mpfb3; 383 u_char mpfb4; 384 u_char mpfb5; 385} *mpfps_t; 386/* MP Configuration Table Header */ 387typedef struct MPCTH { 388 char signature[4]; 389 u_short base_table_length; 390 u_char spec_rev; 391 u_char checksum; 392 u_char oem_id[8]; 393 u_char product_id[12]; 394 void *oem_table_pointer; 395 u_short oem_table_size; 396 u_short entry_count; 397 void *apic_address; 398 u_short extended_table_length; 399 u_char extended_table_checksum; 400 u_char reserved; 401} *mpcth_t; 402 403 404typedef struct PROCENTRY { 405 u_char type; 406 u_char apic_id; 407 u_char apic_version; 408 u_char cpu_flags; 409 u_long cpu_signature; 410 u_long feature_flags; 411 u_long reserved1; 412 u_long reserved2; 413} *proc_entry_ptr; 414 415typedef struct BUSENTRY { 416 u_char type; 417 u_char bus_id; 418 char bus_type[6]; 419} *bus_entry_ptr; 420 421typedef struct IOAPICENTRY { 422 u_char type; 423 u_char apic_id; 424 u_char apic_version; 425 u_char apic_flags; 426 void *apic_address; 427} *io_apic_entry_ptr; 428 429typedef struct INTENTRY { 430 u_char type; 431 u_char int_type; 432 u_short int_flags; 433 u_char src_bus_id; 434 u_char src_bus_irq; 435 u_char dst_apic_id; 436 u_char dst_apic_int; 437} *int_entry_ptr; 438/* descriptions of MP basetable entries */ 439typedef struct BASETABLE_ENTRY { 440 u_char type; 441 u_char length; 442 char name[16]; 443} basetable_entry; 444 445static basetable_entry basetable_entry_types[] = 446{ 447 {0, 20, "Processor"}, 448 {1, 8, "Bus"}, 449 {2, 8, "I/O APIC"}, 450 {3, 8, "I/O INT"}, 451 {4, 8, "Local INT"} 452}; 453 454typedef struct BUSDATA { 455 u_char bus_id; 456 enum busTypes bus_type; 457} bus_datum; 458 459typedef struct INTDATA { 460 u_char int_type; 461 u_short int_flags; 462 u_char src_bus_id; 463 u_char src_bus_irq; 464 u_char dst_apic_id; 465 u_char dst_apic_int; 466} io_int, local_int; 467 468typedef struct BUSTYPENAME { 469 u_char type; 470 char name[7]; 471} bus_type_name; 472 473static bus_type_name bus_type_table[] = 474{ 475 {CBUS, "CBUS"}, 476 {CBUSII, "CBUSII"}, 477 {EISA, "EISA"}, 478 {UNKNOWN_BUSTYPE, "---"}, 479 {UNKNOWN_BUSTYPE, "---"}, 480 {ISA, "ISA"}, 481 {UNKNOWN_BUSTYPE, "---"}, 482 {UNKNOWN_BUSTYPE, "---"}, 483 {UNKNOWN_BUSTYPE, "---"}, 484 {UNKNOWN_BUSTYPE, "---"}, 485 {UNKNOWN_BUSTYPE, "---"}, 486 {UNKNOWN_BUSTYPE, "---"}, 487 {PCI, "PCI"}, 488 {UNKNOWN_BUSTYPE, "---"}, 489 {UNKNOWN_BUSTYPE, "---"}, 490 {UNKNOWN_BUSTYPE, "---"}, 491 {UNKNOWN_BUSTYPE, "---"}, 492 {XPRESS, "XPRESS"}, 493 {UNKNOWN_BUSTYPE, "---"} 494}; 495/* from MP spec v1.4, table 5-1 */ 496static int default_data[7][5] = 497{ 498/* nbus, id0, type0, id1, type1 */ 499 {1, 0, ISA, 255, 255}, 500 {1, 0, EISA, 255, 255}, 501 {1, 0, EISA, 255, 255}, 502 {0, 255, 255, 255, 255},/* MCA not supported */ 503 {2, 0, ISA, 1, PCI}, 504 {2, 0, EISA, 1, PCI}, 505 {0, 255, 255, 255, 255} /* MCA not supported */ 506}; 507 508 509/* the bus data */ 510bus_datum bus_data[NBUS]; 511 512/* the IO INT data, one entry per possible APIC INTerrupt */ 513io_int io_apic_ints[NINTR]; 514 515static int nintrs; 516 517#if defined(FIX_MP_TABLE_WORKS) 518static void fix_mp_table __P((void)); 519#endif /* FIX_MP_TABLE_WORKS */ 520 521static void processor_entry __P((proc_entry_ptr entry, int *cpu)); 522static void io_apic_entry __P((io_apic_entry_ptr entry, int *apic)); 523static void bus_entry __P((bus_entry_ptr entry, int *bus)); 524static void int_entry __P((int_entry_ptr entry, int *intr)); 525static int lookup_bus_type __P((char *name)); 526 527 528/* 529 * parse an Intel MP specification table 530 */ 531static int 532parse_mp_table(void) 533{ 534 int x; 535 mpfps_t fps; 536 mpcth_t cth; 537 int totalSize; 538 void *position; 539 int count; 540 int type; 541 int apic, bus, cpu, intr; 542 543 /* clear physical APIC ID to logical CPU/IO table */ 544 for (x = 0; x < NAPICID; ++x) 545 ID_TO_IO(x) = -1; 546 547 /* clear logical CPU to APIC ID table */ 548 for (x = 0; x < NCPU; ++x) 549 CPU_TO_ID(x) = -1; 550 551 /* clear logical IO to APIC ID table */ 552 for (x = 0; x < NAPIC; ++x) 553 IO_TO_ID(x) = -1; 554 555 /* clear IO APIC address table */ 556 for (x = 0; x < NAPIC; ++x) 557 io_apic_address[x] = ~0; 558 559 /* clear bus data table */ 560 for (x = 0; x < NBUS; ++x) 561 bus_data[x].bus_id = 0xff; 562 563 /* clear IO APIC INT table */ 564 for (x = 0; x < NINTR; ++x) 565 io_apic_ints[x].int_type = 0xff; 566 nintrs = 0; 567 568 /* count the BSP */ 569 mp_ncpus = 1; 570 571 /* setup the cpu/apic mapping arrays */ 572 boot_cpu_id = -1; 573 574 /* local pointer */ 575 fps = (mpfps_t) mpfps; 576 577 /* record whether PIC or virtual-wire mode */ 578 picmode = (fps->mpfb2 & 0x80) ? 1 : 0; 579 580 /* check for use of 'default' configuration */ 581#if defined(TEST_DEFAULT_CONFIG) 582 /* use default addresses */ 583 cpu_apic_address = DEFAULT_APIC_BASE; 584 io_apic_address[0] = DEFAULT_IO_APIC_BASE; 585 586 /* return default configuration type */ 587 return TEST_DEFAULT_CONFIG; 588#else 589 if (fps->mpfb1 != 0) { 590 /* use default addresses */ 591 cpu_apic_address = DEFAULT_APIC_BASE; 592 io_apic_address[0] = DEFAULT_IO_APIC_BASE; 593 594 /* return default configuration type */ 595 return fps->mpfb1; 596 } 597#endif /* TEST_DEFAULT_CONFIG */ 598 599 if ((cth = fps->pap) == 0) 600 panic("MP Configuration Table Header MISSING!\n"); 601 602 cpu_apic_address = (vm_offset_t) cth->apic_address; 603 604 totalSize = cth->base_table_length - sizeof(struct MPCTH); 605 position = (u_char *) cth + sizeof(struct MPCTH); 606 count = cth->entry_count; 607 608 apic = 0; /* logical apic# start @ 0 */ 609 bus = 0; /* logical bus# start @ 0 */ 610 cpu = 1; /* logical cpu# start @ 0, BUT reserve 0 for */ 611 /* BSP */ 612 intr = 0; /* unknown */ 613 614 /* walk the table, recording info of interest */ 615 while (count--) { 616 switch (type = *(u_char *) position) { 617 case 0: 618 processor_entry(position, &cpu); 619 break; 620 case 1: 621 bus_entry(position, &bus); 622 break; 623 case 2: 624 io_apic_entry(position, &apic); 625 break; 626 case 3: 627 int_entry(position, &intr); 628 break; 629 case 4: 630 /* int_entry(position); */ 631 break; 632 default: 633 panic("mpfps Base Table HOSED!\n"); 634 /* NOTREACHED */ 635 } 636 637 totalSize -= basetable_entry_types[type].length; 638 (u_char *) position += basetable_entry_types[type].length; 639 } 640 641 if (boot_cpu_id == -1) 642 panic("NO BSP found!\n"); 643 644 /* record # of APs found */ 645 mp_naps = (cpu - 1); 646 647 /* record # of busses found */ 648 mp_nbusses = bus; 649 650 /* record # of IO APICs found */ 651 mp_napics = apic; 652 653 /* record # of IO APICs found */ 654 nintrs = intr; 655 656#if defined(FIX_MP_TABLE_WORKS) 657 /* post scan cleanup */ 658 fix_mp_table(); 659#endif /* FIX_MP_TABLE_WORKS */ 660 661 /* report fact that its NOT a default configuration */ 662 return 0; 663} 664 665 666/* 667 * parse an Intel MP specification table 668 */ 669#if defined(FIX_MP_TABLE_WORKS) 670static void 671fix_mp_table(void) 672{ 673 int x; 674 int y; 675 int num_pci_bus; 676 bus_datum bus_record; 677 678 /* 679 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS 680 * did it wrong. The MP spec says that when more than 1 PCI bus 681 * exists the BIOS must begin with bus entries for the PCI bus and use 682 * actual PCI bus numbering. This implies that when only 1 PCI bus 683 * exists the BIOS can choose to ignore this ordering, and indeed many 684 * MP motherboards do ignore it. This causes a problem when the PCI 685 * sub-system makes requests of the MP sub-system based on PCI bus 686 * numbers. So here we look for the situation and renumber the 687 * busses and associated INTs in an effort to "make it right". 688 */ 689 690 /* count the number of PCI busses */ 691 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { 692 if (bus_data[x].bus_type == PCI) 693 ++num_pci_bus; 694 } 695 696 /* check the 1 PCI bus case for sanity */ 697 if (num_pci_bus == 1) { 698 699 /* if its in the first slot all is well */ 700 if (bus_data[0].bus_type == PCI) 701 return; 702 703 /* mis-numbered, swap with whichever bus uses slot 0 */ 704 705 /* locate the entry holding the PCI bus */ 706 for (x = 1; x < mp_nbusses; ++x) { 707 if (bus_data[x].bus_type == PCI) 708 break; 709 } 710 711 /* swap the bus entry records */ 712 bus_record = bus_data[0]; 713 bus_data[0] = bus_data[x]; 714 bus_data[x] = bus_record; 715 716 /* swap each relavant INTerrupt entry */ 717 for (y = 0; y < nintrs; ++y) { 718 if (io_apic_ints[y].src_bus_id == x) 719 io_apic_ints[y].src_bus_id = 0; 720 else 721 if (io_apic_ints[y].src_bus_id == 0) 722 io_apic_ints[y].src_bus_id = x; 723 } 724 } 725 /* sanity check if more than 1 PCI bus */ 726 else 727 if (num_pci_bus > 1) { 728 for (x = 0; x < num_pci_bus; ++x) { 729 if (bus_data[x].bus_type != PCI) { 730 printf("bad PCI bus numbering\n"); 731 panic("\n"); 732 } 733 } 734 } 735} 736#endif /* FIX_MP_TABLE_WORKS */ 737 738 739static void 740processor_entry(proc_entry_ptr entry, int *cpu) 741{ 742 int x = *cpu; 743 744 /* check for usability */ 745 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN)) 746 return; 747 748 /* check for BSP flag */ 749 if (entry->cpu_flags & PROCENTRY_FLAG_BP) { 750 /* always give boot CPU the logical value of 0 */ 751 x = 0; 752 boot_cpu_id = entry->apic_id; 753 } else { 754 /* add another AP to list, if less than max number of CPUs */ 755 if (x == NCPU) { 756 printf("Warning: only using %d of the available CPUs!\n", x); 757 return; 758 } 759 ++(*cpu); 760 } 761 762 CPU_TO_ID(x) = entry->apic_id; 763 ID_TO_CPU(entry->apic_id) = x; 764} 765 766 767static void 768bus_entry(bus_entry_ptr entry, int *bus) 769{ 770 int x, y; 771 char name[8]; 772 char c; 773 774 if ((x = (*bus)++) == NBUS) 775 panic("too many busses, increase 'NBUS'\n"); 776 777 /* encode the name into an index */ 778 for (y = 0; y < 6; ++y) { 779 if ((c = entry->bus_type[y]) == ' ') 780 break; 781 name[y] = c; 782 } 783 name[y] = '\0'; 784 785 if ((y = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) 786 panic("unknown bus type: '%s'\n", name); 787 788 bus_data[x].bus_id = entry->bus_id; 789 bus_data[x].bus_type = y; 790} 791 792 793static void 794io_apic_entry(io_apic_entry_ptr entry, int *apic) 795{ 796 int x; 797 798 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) 799 return; 800 801 if ((x = (*apic)++) == NAPIC) 802 panic("too many APICs, increase 'NAPIC'\n"); 803 804 IO_TO_ID(x) = entry->apic_id; 805 ID_TO_IO(entry->apic_id) = x; 806 807 io_apic_address[x] = (vm_offset_t) entry->apic_address; 808} 809 810 811static int 812lookup_bus_type(char *name) 813{ 814 int x; 815 816 for (x = 0; x < MAX_BUSTYPE; ++x) 817 if (strcmp(bus_type_table[x].name, name) == 0) 818 return bus_type_table[x].type; 819 820 return UNKNOWN_BUSTYPE; 821} 822 823 824static void 825int_entry(int_entry_ptr entry, int *intr) 826{ 827 int x; 828 829 if ((x = (*intr)++) == NINTR) 830 panic("too many INTs, increase 'NINTR'\n"); 831 832 io_apic_ints[x].int_type = entry->int_type; 833 io_apic_ints[x].int_flags = entry->int_flags; 834 io_apic_ints[x].src_bus_id = entry->src_bus_id; 835 io_apic_ints[x].src_bus_irq = entry->src_bus_irq; 836 io_apic_ints[x].dst_apic_id = entry->dst_apic_id; 837 io_apic_ints[x].dst_apic_int = entry->dst_apic_int; 838} 839 840 841static int 842apic_int_is_bus_type(int intr, int bus_type) 843{ 844 int bus; 845 846 for (bus = 0; bus < mp_nbusses; ++bus) 847 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) 848 && ((int) bus_data[bus].bus_type == bus_type)) 849 return 1; 850 851 return 0; 852} 853 854 855/* 856 * determine which APIC pin an ISA INT is attached to. 857 */ 858#define INTTYPE(I) (io_apic_ints[(I)].int_type) 859#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) 860 861#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) 862int 863get_isa_apic_irq(int isaIRQ) 864{ 865 int intr; 866 867#if defined(SMP_TIMER_NC) 868 if (isaIRQ == 0) 869 return -1; 870#endif /* SMP_TIMER_NC */ 871 872 for (intr = 0; intr < nintrs; ++intr) /* search each INT record */ 873 if ((INTTYPE(intr) == 0) 874 && (SRCBUSIRQ(intr) == isaIRQ)) /* a candidate IRQ */ 875 if (apic_int_is_bus_type(intr, ISA)) /* check bus match */ 876 return INTPIN(intr); /* exact match */ 877 878 return -1; /* NOT found */ 879} 880#undef SRCBUSIRQ 881 882 883/* 884 * determine which APIC pin an EISA INT is attached to. 885 */ 886#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) 887int 888get_eisa_apic_irq(int eisaIRQ) 889{ 890 int intr; 891 892#if defined(SMP_TIMER_NC) 893 if (eisaIRQ == 0) 894 return -1; 895#endif /* SMP_TIMER_NC */ 896 897 for (intr = 0; intr < nintrs; ++intr) /* search each INT record */ 898 if ((INTTYPE(intr) == 0) 899 && (SRCBUSIRQ(intr) == eisaIRQ)) /* a candidate IRQ */ 900 if (apic_int_is_bus_type(intr, EISA)) /* check bus match */ 901 return INTPIN(intr); /* exact match */ 902 903 return -1; /* NOT found */ 904} 905#undef SRCBUSIRQ 906 907 908/* 909 * determine which APIC pin a PCI INT is attached to. 910 */ 911#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) 912#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) 913#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) 914int 915get_pci_apic_irq(int pciBus, int pciDevice, int pciInt) 916{ 917 int intr; 918 919 --pciInt; /* zero based */ 920 921 for (intr = 0; intr < nintrs; ++intr) /* search each record */ 922 if ((INTTYPE(intr) == 0) 923#if defined(FIX_MP_TABLE_WORKS) 924 && (SRCBUSID(intr) == pciBus) 925#endif /* FIX_MP_TABLE_WORKS */ 926 && (SRCBUSDEVICE(intr) == pciDevice) 927 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ 928 if (apic_int_is_bus_type(intr, PCI)) /* check bus match */ 929 return INTPIN(intr); /* exact match */ 930 931 return -1; /* NOT found */ 932} 933#undef SRCBUSLINE 934#undef SRCBUSDEVICE 935#undef SRCBUSID 936 937#undef INTPIN 938#undef INTTYPE 939 940 941int 942undirect_pci_irq(int rirq) 943{ 944#if defined(READY) 945 printf("Freeing irq %d for ISA cards.\n", rirq); 946 /** FIXME: tickle the MB redirector chip */ 947 return ???; 948#else 949 printf("Freeing (NOT implimented) irq %d for ISA cards.\n", rirq); 950 return 0; 951#endif /* READY */ 952} 953 954 955/* 956 * given a bus ID, return: 957 * the bus type if found 958 * -1 if NOT found 959 */ 960int 961apic_bus_type(int id) 962{ 963 int x; 964 965 for (x = 0; x < mp_nbusses; ++x) 966 if (bus_data[x].bus_id == id) 967 return bus_data[x].bus_type; 968 969 return -1; 970} 971 972 973/* 974 * given a LOGICAL APIC# and pin#, return: 975 * the associated src bus ID if found 976 * -1 if NOT found 977 */ 978int 979apic_src_bus_id(int apic, int pin) 980{ 981 int x; 982 983 /* search each of the possible INTerrupt sources */ 984 for (x = 0; x < nintrs; ++x) 985 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 986 (pin == io_apic_ints[x].dst_apic_int)) 987 return (io_apic_ints[x].src_bus_id); 988 989 return -1; /* NOT found */ 990} 991 992 993/* 994 * given a LOGICAL APIC# and pin#, return: 995 * the associated src bus IRQ if found 996 * -1 if NOT found 997 */ 998int 999apic_src_bus_irq(int apic, int pin) 1000{ 1001 int x; 1002 1003 for (x = 0; x < nintrs; x++) 1004 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1005 (pin == io_apic_ints[x].dst_apic_int)) 1006 return (io_apic_ints[x].src_bus_irq); 1007 1008 return -1; /* NOT found */ 1009} 1010 1011 1012/* 1013 * given a LOGICAL APIC# and pin#, return: 1014 * the associated INTerrupt type if found 1015 * -1 if NOT found 1016 */ 1017int 1018apic_int_type(int apic, int pin) 1019{ 1020 int x; 1021 1022 /* search each of the possible INTerrupt sources */ 1023 for (x = 0; x < nintrs; ++x) 1024 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1025 (pin == io_apic_ints[x].dst_apic_int)) 1026 return (io_apic_ints[x].int_type); 1027 1028 return -1; /* NOT found */ 1029} 1030 1031 1032/* 1033 * given a LOGICAL APIC# and pin#, return: 1034 * the associated trigger mode if found 1035 * -1 if NOT found 1036 */ 1037int 1038apic_trigger(int apic, int pin) 1039{ 1040 int x; 1041 1042 /* search each of the possible INTerrupt sources */ 1043 for (x = 0; x < nintrs; ++x) 1044 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1045 (pin == io_apic_ints[x].dst_apic_int)) 1046 return ((io_apic_ints[x].int_flags >> 2) & 0x03); 1047 1048 return -1; /* NOT found */ 1049} 1050 1051 1052/* 1053 * given a LOGICAL APIC# and pin#, return: 1054 * the associated 'active' level if found 1055 * -1 if NOT found 1056 */ 1057int 1058apic_polarity(int apic, int pin) 1059{ 1060 int x; 1061 1062 /* search each of the possible INTerrupt sources */ 1063 for (x = 0; x < nintrs; ++x) 1064 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1065 (pin == io_apic_ints[x].dst_apic_int)) 1066 return (io_apic_ints[x].int_flags & 0x03); 1067 1068 return -1; /* NOT found */ 1069} 1070 1071 1072/* 1073 * set data according to MP defaults 1074 * FIXME: probably not complete yet... 1075 */ 1076static void 1077default_mp_table(int type) 1078{ 1079 int ap_cpu_id; 1080#if defined(APIC_IO) 1081 u_int32_t ux; 1082 int io_apic_id; 1083 int pin; 1084#endif /* APIC_IO */ 1085 1086#if 0 1087 printf(" MP default config type: %d\n", type); 1088 switch (type) { 1089 case 1: 1090 printf(" bus: ISA, APIC: 82489DX\n"); 1091 break; 1092 case 2: 1093 printf(" bus: EISA, APIC: 82489DX\n"); 1094 break; 1095 case 3: 1096 printf(" bus: EISA, APIC: 82489DX\n"); 1097 break; 1098 case 4: 1099 printf(" bus: MCA, APIC: 82489DX\n"); 1100 break; 1101 case 5: 1102 printf(" bus: ISA+PCI, APIC: Integrated\n"); 1103 break; 1104 case 6: 1105 printf(" bus: EISA+PCI, APIC: Integrated\n"); 1106 break; 1107 case 7: 1108 printf(" bus: MCA+PCI, APIC: Integrated\n"); 1109 break; 1110 default: 1111 printf(" future type\n"); 1112 break; 1113 /* NOTREACHED */ 1114 } 1115#endif /* 0 */ 1116 1117 boot_cpu_id = (apic_base[APIC_ID] & APIC_ID_MASK) >> 24; 1118 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; 1119 1120 /* BSP */ 1121 CPU_TO_ID(0) = boot_cpu_id; 1122 ID_TO_CPU(boot_cpu_id) = 0; 1123 1124 /* one and only AP */ 1125 CPU_TO_ID(1) = ap_cpu_id; 1126 ID_TO_CPU(ap_cpu_id) = 1; 1127 mp_naps = 1; 1128 1129 /* one and only IO APIC */ 1130#if defined(APIC_IO) 1131 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; 1132 1133 /* 1134 * sanity check, refer to MP spec section 3.6.6, last paragraph 1135 * necessary as some hardware isn't properly setting up the IO APIC 1136 */ 1137#if defined(REALLY_ANAL_IOAPICID_VALUE) 1138 if (io_apic_id != 2) { 1139#else 1140 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { 1141#endif /* REALLY_ANAL_IOAPICID_VALUE */ 1142 ux = io_apic_read(0, IOAPIC_ID); /* get current contents */ 1143 ux &= ~APIC_ID_MASK; /* clear the ID field */ 1144 ux |= 0x02000000; /* set it to '2' */ 1145 io_apic_write(0, IOAPIC_ID, ux); /* write new value */ 1146 ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */ 1147 if ((ux & APIC_ID_MASK) != 0x02000000) 1148 panic("Problem: can't control IO APIC ID, reg: 0x%08x\n", ux); 1149 io_apic_id = 2; 1150 } 1151 IO_TO_ID(0) = io_apic_id; 1152 ID_TO_IO(io_apic_id) = 0; 1153 mp_napics = 1; 1154#else 1155 mp_napics = 0; 1156#endif /* APIC_IO */ 1157 1158 /* fill out bus entries */ 1159 switch (type) { 1160 case 1: 1161 case 2: 1162 case 3: 1163 case 5: 1164 case 6: 1165 mp_nbusses = default_data[type - 1][0]; 1166 bus_data[0].bus_id = default_data[type - 1][1]; 1167 bus_data[0].bus_type = default_data[type - 1][2]; 1168 bus_data[1].bus_id = default_data[type - 1][3]; 1169 bus_data[1].bus_type = default_data[type - 1][4]; 1170 break; 1171 1172 /* case 4: case 7: MCA NOT supported */ 1173 default: /* illegal/reserved */ 1174 panic("BAD default MP config: %d\n", type); 1175 } 1176 1177#if defined(APIC_IO) 1178 /* general cases from MP v1.4, table 5-2 */ 1179 for (pin = 0; pin < 16; ++pin) { 1180 io_apic_ints[pin].int_type = 0; 1181 io_apic_ints[pin].int_flags = 0x05; /* edge-triggered/active-hi */ 1182 io_apic_ints[pin].src_bus_id = 0; 1183 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 is caught below */ 1184 io_apic_ints[pin].dst_apic_id = io_apic_id; 1185 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 correspondence */ 1186 } 1187 1188 /* special cases from MP v1.4, table 5-2 */ 1189 if (type == 2) { 1190 io_apic_ints[2].int_type = 0xff; /* N/C */ 1191 io_apic_ints[13].int_type = 0xff; /* N/C */ 1192#if !defined(APIC_MIXED_MODE) 1193 /** FIXME: ??? */ 1194 panic("sorry, can't support type 2 default yet\n"); 1195#endif /* APIC_MIXED_MODE */ 1196 } else 1197 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ 1198 1199 if (type == 7) 1200 io_apic_ints[0].int_type = 0xff; /* N/C */ 1201 else 1202 io_apic_ints[0].int_type = 3; /* vectored 8259 */ 1203 1204 nintrs = 16; 1205#endif /* APIC_IO */ 1206} 1207 1208 1209static void install_ap_tramp(u_int boot_addr); 1210static int start_ap(int logicalCpu, u_int boot_addr); 1211 1212/* 1213 * start each AP in our list 1214 */ 1215static int 1216start_all_aps(u_int boot_addr) 1217{ 1218 int x; 1219 u_char mpbiosreason; 1220 u_long mpbioswarmvec; 1221 1222 /** 1223 * NOTE: this needs further thought: 1224 * where does it get released? 1225 * should it be set to empy? 1226 * 1227 * get the initial mp_lock with a count of 1 for the BSP 1228 */ 1229 mp_lock = (apic_base[APIC_ID] & APIC_ID_MASK) + 1; 1230 1231 /* initialize BSP's local APIC */ 1232 apic_initialize(1); 1233 1234 /* install the AP 1st level boot code */ 1235 install_ap_tramp(boot_addr); 1236 1237 /* save the current value of the warm-start vector */ 1238 mpbioswarmvec = *((u_long *) WARMBOOT_OFF); 1239 outb(CMOS_REG, BIOS_RESET); 1240 mpbiosreason = inb(CMOS_DATA); 1241 1242 /* start each AP */ 1243 for (x = 1; x <= mp_naps; ++x) { 1244 1245 /* setup a vector to our boot code */ 1246 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 1247 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); 1248 outb(CMOS_REG, BIOS_RESET); 1249 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 1250 1251 /* attempt to start the Application Processor */ 1252 CHECK_INIT(99); /* setup checkpoints */ 1253 if (!start_ap(x, boot_addr)) { 1254 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); 1255 CHECK_PRINT("trace"); /* show checkpoints */ 1256 /* 1257 * better panic as the AP may be running loose 1258 * somewhere 1259 */ 1260 printf("panic y/n? [n] "); 1261 if (cngetc() != 'n') 1262 panic("bye-bye\n"); 1263 } 1264 CHECK_PRINT("trace"); /* show checkpoints */ 1265 1266 /* record its version info */ 1267 cpu_apic_versions[x] = cpu_apic_versions[0]; 1268 } 1269 1270 /* fill in our (BSP) APIC version */ 1271 cpu_apic_versions[0] = apic_base[APIC_VER]; 1272 1273 /* restore the warmstart vector */ 1274 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 1275 outb(CMOS_REG, BIOS_RESET); 1276 outb(CMOS_DATA, mpbiosreason); 1277 1278 /* number of APs actually started */ 1279 return mp_ncpus - 1; 1280} 1281 1282 1283/* 1284 * load the 1st level AP boot code into base memory. 1285 */ 1286 1287/* targets for relocation */ 1288extern void bigJump(void); 1289extern void bootCodeSeg(void); 1290extern void bootDataSeg(void); 1291extern void MPentry(void); 1292extern u_int MP_GDT; 1293extern u_int mp_gdtbase; 1294 1295static void 1296install_ap_tramp(u_int boot_addr) 1297{ 1298 int x; 1299 int size = *(int *) ((u_long) & bootMP_size); 1300 u_char *src = (u_char *) ((u_long) bootMP); 1301 u_char *dst = (u_char *) boot_addr + KERNBASE; 1302 u_int boot_base = (u_int) bootMP; 1303 u_int8_t *dst8; 1304 u_int16_t *dst16; 1305 u_int32_t *dst32; 1306 1307 for (x = 0; x < size; ++x) 1308 *dst++ = *src++; 1309 1310 /* 1311 * modify addresses in code we just moved to basemem. unfortunately we 1312 * need fairly detailed info about mpboot.s for this to work. changes 1313 * to mpboot.s might require changes here. 1314 */ 1315 1316 /* boot code is located in KERNEL space */ 1317 dst = (u_char *) boot_addr + KERNBASE; 1318 1319 /* modify the lgdt arg */ 1320 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 1321 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); 1322 1323 /* modify the ljmp target for MPentry() */ 1324 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 1325 *dst32 = ((u_int) MPentry - KERNBASE); 1326 1327 /* modify the target for boot code segment */ 1328 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 1329 dst8 = (u_int8_t *) (dst16 + 1); 1330 *dst16 = (u_int) boot_addr & 0xffff; 1331 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1332 1333 /* modify the target for boot data segment */ 1334 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 1335 dst8 = (u_int8_t *) (dst16 + 1); 1336 *dst16 = (u_int) boot_addr & 0xffff; 1337 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1338} 1339 1340 1341/* 1342 * this function starts the AP (application processor) identified 1343 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 1344 * to accomplish this. This is necessary because of the nuances 1345 * of the different hardware we might encounter. It ain't pretty, 1346 * but it seems to work. 1347 */ 1348static int 1349start_ap(int logical_cpu, u_int boot_addr) 1350{ 1351 int physical_cpu; 1352 int vector; 1353 int cpus; 1354 u_long icr_lo, icr_hi; 1355 1356 /* get the PHYSICAL APIC ID# */ 1357 physical_cpu = CPU_TO_ID(logical_cpu); 1358 1359 /* calculate the vector */ 1360 vector = (boot_addr >> 12) & 0xff; 1361 1362 /* used as a watchpoint to signal AP startup */ 1363 cpus = mp_ncpus; 1364 1365 /* 1366 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 1367 * and running the target CPU. OR this INIT IPI might be latched (P5 1368 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 1369 * ignored. 1370 */ 1371 1372 /* setup the address for the target AP */ 1373 icr_hi = apic_base[APIC_ICR_HI] & ~APIC_ID_MASK; 1374 icr_hi |= (physical_cpu << 24); 1375 apic_base[APIC_ICR_HI] = icr_hi; 1376 1377 /* do an INIT IPI: assert RESET */ 1378 icr_lo = apic_base[APIC_ICR_LOW] & 0xfff00000; 1379 apic_base[APIC_ICR_LOW] = icr_lo | 0x0000c500; 1380 1381 /* wait for pending status end */ 1382 while (apic_base[APIC_ICR_LOW] & APIC_DELSTAT_MASK) 1383 /* spin */ ; 1384 1385 /* do an INIT IPI: deassert RESET */ 1386 apic_base[APIC_ICR_LOW] = icr_lo | 0x00008500; 1387 1388 /* wait for pending status end */ 1389 u_sleep(10000); /* wait ~10mS */ 1390 while (apic_base[APIC_ICR_LOW] & APIC_DELSTAT_MASK) 1391 /* spin */ ; 1392 1393 /* 1394 * next we do a STARTUP IPI: the previous INIT IPI might still be 1395 * latched, (P5 bug) this 1st STARTUP would then terminate 1396 * immediately, and the previously started INIT IPI would continue. OR 1397 * the previous INIT IPI has already run. and this STARTUP IPI will 1398 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 1399 * will run. 1400 */ 1401 1402 /* do a STARTUP IPI */ 1403 apic_base[APIC_ICR_LOW] = icr_lo | 0x00000600 | vector; 1404 while (apic_base[APIC_ICR_LOW] & APIC_DELSTAT_MASK) 1405 /* spin */ ; 1406 u_sleep(200); /* wait ~200uS */ 1407 1408 /* 1409 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 1410 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 1411 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 1412 * recognized after hardware RESET or INIT IPI. 1413 */ 1414 1415 apic_base[APIC_ICR_LOW] = icr_lo | 0x00000600 | vector; 1416 while (apic_base[APIC_ICR_LOW] & APIC_DELSTAT_MASK) 1417 /* spin */ ; 1418 u_sleep(200); /* wait ~200uS */ 1419 1420 /* wait for it to start */ 1421 set_apic_timer(5000000);/* == 5 seconds */ 1422 while (read_apic_timer()) 1423 if (mp_ncpus > cpus) 1424 return 1; /* return SUCCESS */ 1425 1426 return 0; /* return FAILURE */ 1427} 1428 1429 1430/* 1431 * Flush the TLB on all other CPU's 1432 * 1433 * XXX: Needs to handshake and wait for completion before proceding. 1434 */ 1435void 1436smp_invltlb(void) 1437{ 1438 if (smp_active && invltlb_ok) 1439 all_but_self_ipi(ICU_OFFSET + XINVLTLB_OFFSET); 1440} 1441 1442void 1443invlpg(u_int addr) 1444{ 1445 __asm __volatile("invlpg (%0)"::"r"(addr):"memory"); 1446 1447 /* send a message to the other CPUs */ 1448 smp_invltlb(); 1449} 1450 1451void 1452invltlb(void) 1453{ 1454 u_long temp; 1455 1456 /* 1457 * This should be implemented as load_cr3(rcr3()) when load_cr3() is 1458 * inlined. 1459 */ 1460 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory"); 1461 1462 /* send a message to the other CPUs */ 1463 smp_invltlb(); 1464} 1465