mptable.c revision 25215
1/* 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $Id: mp_machdep.c,v 1.2 1997/04/27 21:17:24 fsmp Exp $ 26 */ 27 28#include "opt_smp.h" 29 30#define FIX_MP_TABLE_WORKS_NOT 31 32#include "opt_serial.h" 33 34#include <sys/param.h> /* for KERNBASE */ 35#include <sys/types.h> 36#include <sys/sysproto.h> 37#include <sys/time.h> 38#include <sys/systm.h> 39 40#include <vm/vm.h> /* for KERNBASE */ 41#include <vm/vm_param.h> /* for KERNBASE */ 42#include <vm/pmap.h> /* for KERNBASE */ 43#include <machine/pmap.h> /* for KERNBASE */ 44 45#include <machine/smp.h> 46#include <machine/apic.h> 47#include <machine/mpapic.h> 48#include <machine/cpufunc.h> 49#include <machine/segments.h> 50#include <machine/smptests.h> /** TEST_UPPERPRIO, TEST_DEFAULT_CONFIG */ 51 52#include <i386/i386/cons.h> /* cngetc() */ 53 54#if defined(APIC_IO) 55#include <i386/include/md_var.h> /* setidt() */ 56#include <i386/isa/icu.h> /* Xinvltlb() */ 57#include <i386/isa/isa_device.h> /* Xinvltlb() */ 58#endif /* APIC_IO */ 59 60#define WARMBOOT_TARGET 0 61#define WARMBOOT_OFF (KERNBASE + 0x0467) 62#define WARMBOOT_SEG (KERNBASE + 0x0469) 63 64#define BIOS_BASE (0xf0000) 65#define BIOS_SIZE (0x10000) 66#define BIOS_COUNT (BIOS_SIZE/4) 67 68#define CMOS_REG (0x70) 69#define CMOS_DATA (0x71) 70#define BIOS_RESET (0x0f) 71#define BIOS_WARM (0x0a) 72 73/* 74 * this code MUST be enabled here and in mpboot.s. 75 * it follows the very early stages of AP boot by placing values in CMOS ram. 76 * it NORMALLY will never be needed and thus the primitive method for enabling. 77 * 78#define CHECK_POINTS 79 */ 80 81#if defined(CHECK_POINTS) 82#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 83#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 84 85#define CHECK_INIT(D); \ 86 CHECK_WRITE(0x34, (D)); \ 87 CHECK_WRITE(0x35, (D)); \ 88 CHECK_WRITE(0x36, (D)); \ 89 CHECK_WRITE(0x37, (D)); \ 90 CHECK_WRITE(0x38, (D)); \ 91 CHECK_WRITE(0x39, (D)); 92 93#define CHECK_PRINT(S); \ 94 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 95 (S), \ 96 CHECK_READ(0x34), \ 97 CHECK_READ(0x35), \ 98 CHECK_READ(0x36), \ 99 CHECK_READ(0x37), \ 100 CHECK_READ(0x38), \ 101 CHECK_READ(0x39)); 102 103#else /* CHECK_POINTS */ 104 105#define CHECK_INIT(D) 106#define CHECK_PRINT(S) 107 108#endif /* CHECK_POINTS */ 109 110 111/** FIXME: what system files declare these??? */ 112extern struct region_descriptor r_gdt, r_idt; 113 114/* global data */ 115struct proc *SMPcurproc[NCPU]; 116struct pcb *SMPcurpcb[NCPU]; 117struct timeval SMPruntime[NCPU]; 118 119int mp_ncpus; /* # of CPUs, including BSP */ 120int mp_naps; /* # of Applications processors */ 121int mp_nbusses; /* # of busses */ 122int mp_napics; /* # of IO APICs */ 123int mpenabled; 124int boot_cpu_id; /* designated BSP */ 125vm_offset_t cpu_apic_address; 126vm_offset_t io_apic_address[NAPIC]; 127 128u_int32_t cpu_apic_versions[NCPU]; 129u_int32_t io_apic_versions[NAPIC]; 130 131/* 132 * APIC ID logical/physical mapping structures 133 */ 134int cpu_num_to_apic_id[NCPU]; 135int io_num_to_apic_id[NAPIC]; 136int apic_id_to_logical[NAPICID]; 137 138/* 139 * look for MP compliant motherboard. 140 */ 141 142static u_int boot_address; 143static u_int base_memory; 144 145static int picmode; /* 0: virtual wire mode, 1: PIC mode */ 146static u_int mpfps; 147static int search_for_sig(u_int32_t target, int count); 148static int mp_probe(u_int base_top); 149static void mp_enable(u_int boot_addr); 150 151 152/* 153 * calculate usable address in base memory for AP trampoline code 154 */ 155u_int 156mp_bootaddress(u_int basemem) 157{ 158 base_memory = basemem * 1024; /* convert to bytes */ 159 160 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ 161 if ((base_memory - boot_address) < bootMP_size) 162 boot_address -= 4096; /* not enough, lower by 4k */ 163 164 return boot_address; 165} 166 167 168/* 169 * startup the SMP processors 170 */ 171void 172mp_start(void) 173{ 174 /* look for MP capable motherboard */ 175 if (mp_probe(base_memory)) 176 mp_enable(boot_address); 177 else { 178 printf("MP FPS NOT FOUND, suggest use of 'mptable' program\n"); 179 panic("can't continue!\n"); 180 } 181 182 /* finish pmap initialization - turn off V==P mapping at zero */ 183 pmap_bootstrap2(); 184} 185 186 187/* 188 * print various information about the SMP system hardware and setup 189 */ 190void 191mp_announce(void) 192{ 193 int x; 194 195 printf("FreeBSD/SMP: Multiprocessor motherboard\n"); 196 printf(" cpu0 (BSP): apic id: %d", CPU_TO_ID(0)); 197 printf(", version: 0x%08x\n", cpu_apic_versions[0]); 198 for (x = 1; x <= mp_naps; ++x) { 199 printf(" cpu%d (AP): apic id: %d", x, CPU_TO_ID(x)); 200 printf(", version: 0x%08x\n", cpu_apic_versions[x]); 201 } 202 203#if defined(APIC_IO) 204 for (x = 0; x < mp_napics; ++x) { 205 printf(" io%d (APIC): apic id: %d", x, IO_TO_ID(x)); 206 printf(", version: 0x%08x\n", io_apic_versions[x]); 207 } 208#else 209 printf(" Warning: APIC I/O disabled\n"); 210#endif /* APIC_IO */ 211} 212 213 214/* 215 * AP cpu's call this to sync up protected mode. 216 */ 217void 218init_secondary(void) 219{ 220 int gsel_tss, slot; 221 222 r_gdt.rd_limit = sizeof(gdt[0]) * (NGDT + NCPU) - 1; 223 r_gdt.rd_base = (int) gdt; 224 lgdt(&r_gdt); /* does magic intra-segment return */ 225 lidt(&r_idt); 226 lldt(_default_ldt); 227 228 slot = NGDT + cpunumber(); 229 gsel_tss = GSEL(slot, SEL_KPL); 230 gdt[slot].sd.sd_type = SDT_SYS386TSS; 231 ltr(gsel_tss); 232 233 load_cr0(0x8005003b); /* XXX! */ 234} 235 236 237#if defined(APIC_IO) 238void 239configure_local_apic(void) 240{ 241 u_char byte; 242 u_int32_t temp; 243 244 if (picmode) { 245 outb(0x22, 0x70); /* select IMCR */ 246 byte = inb(0x23); /* current contents */ 247 byte |= 0x01; /* mask external INTR */ 248 outb(0x23, byte); /* disconnect 8259s/NMI */ 249 } 250 /* mask the LVT1 */ 251 temp = apic_base[APIC_LVT1]; 252 temp |= APIC_LVT_M; 253 apic_base[APIC_LVT1] = temp; 254} 255#endif /* APIC_IO */ 256 257 258/******************************************************************* 259 * local functions and data 260 */ 261 262static int 263mp_probe(u_int base_top) 264{ 265 int x; 266 u_long segment; 267 u_int32_t target; 268 269 /* see if EBDA exists */ 270 if (segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) { 271 /* search first 1K of EBDA */ 272 target = (u_int32_t) (segment << 4); 273 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 274 goto found; 275 } else { 276 /*last 1K of base memory, effective 'top of base' is passed in*/ 277 target = (u_int32_t) (base_top - 0x400); 278 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 279 goto found; 280 } 281 282 /* search the BIOS */ 283 target = (u_int32_t) BIOS_BASE; 284 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) 285 goto found; 286 287 /* nothing found */ 288 mpfps = mpenabled = 0; 289 return 0; 290 291found: /* please forgive the 'goto'! */ 292 /* flag fact that we are running multiple processors */ 293 mpfps = x; 294 mpenabled = 1; 295 return 1; 296} 297 298 299/* 300 * start the SMP system 301 */ 302static int parse_mp_table(void); 303static void default_mp_table(int type); 304static int start_all_aps(u_int boot_addr); 305 306static void 307mp_enable(u_int boot_addr) 308{ 309 int x; 310#if defined(APIC_IO) 311 int apic; 312 u_int ux; 313#if defined(TEST_UPPERPRIO) 314 u_char select; /* the select register is 8 bits */ 315 u_int32_t flags; /* the window register is 32 bits */ 316#endif /* TEST_UPPERPRIO */ 317#endif /* APIC_IO */ 318 319 /* examine the MP table for needed info */ 320 x = parse_mp_table(); 321 322 /* create pages for (address common) cpu APIC and each IO APIC */ 323 pmap_bootstrap_apics(); 324 325 /* can't process default configs till the CPU APIC is pmapped */ 326 if (x) 327 default_mp_table(x); 328 329#if defined(APIC_IO) 330 /* fill the LOGICAL io_apic_versions table */ 331 for (apic = 0; apic < mp_napics; ++apic) { 332 ux = io_apic_read(apic, IOAPIC_VER); 333 io_apic_versions[apic] = ux; 334 } 335 336 /* 337 */ 338 for (apic = 0; apic < mp_napics; ++apic) 339 if (io_apic_setup(apic) < 0) 340 panic("IO APIC setup failure\n"); 341 342 /* install an inter-CPU IPI for TLB invalidation */ 343 setidt(ICU_OFFSET + XINVLTLB_OFFSET, Xinvltlb, 344 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 345 346#if defined(TEST_UPPERPRIO) 347 348#if 1 349 printf("special IRQ10\n"); 350 select = IOAPIC_REDTBL10; /** HARD_VECTORXXX: */ 351 flags = io_apic_read(0, select); 352 flags &= ~0xff; /** clear vector */ 353 flags |= 64; 354 io_apic_write(0, select, flags); 355#else 356 printf("special IRQ10\n"); 357 cngetc(); 358 select = IOAPIC_REDTBL10; /** HARD_VECTORXXX: */ 359 flags = io_apic_read(0, select); 360 flags &= ~IOART_DELMOD; /* FIXED mode */ 361 io_apic_write(0, select, flags); 362 io_apic_write(0, select + 1, boot_cpu_id << 24); 363#endif /** 0/1 */ 364 365#endif /* TEST_UPPERPRIO */ 366 367#endif /* APIC_IO */ 368 369 /* start each Application Processor */ 370 start_all_aps(boot_addr); 371} 372 373 374/* 375 * look for the MP spec signature 376 */ 377 378/* string defined by the Intel MP Spec as identifying the MP table */ 379#define MP_SIG 0x5f504d5f /* _MP_ */ 380#define NEXT(X) ((X) += 4) 381static int 382search_for_sig(u_int32_t target, int count) 383{ 384 int x; 385 u_int32_t *addr = (u_int32_t *) (KERNBASE + target); 386 387 for (x = 0; x < count; NEXT(x)) 388 if (addr[x] == MP_SIG) 389 /* make array index a byte index */ 390 return (target + (x * sizeof(u_int32_t))); 391 392 return -1; 393} 394 395 396#define PROCENTRY_FLAG_EN 0x01 397#define PROCENTRY_FLAG_BP 0x02 398#define IOAPICENTRY_FLAG_EN 0x01 399 400/* MP Floating Pointer Structure */ 401typedef struct MPFPS { 402 char signature[4]; 403 void *pap; 404 u_char length; 405 u_char spec_rev; 406 u_char checksum; 407 u_char mpfb1; 408 u_char mpfb2; 409 u_char mpfb3; 410 u_char mpfb4; 411 u_char mpfb5; 412} *mpfps_t; 413/* MP Configuration Table Header */ 414typedef struct MPCTH { 415 char signature[4]; 416 u_short base_table_length; 417 u_char spec_rev; 418 u_char checksum; 419 u_char oem_id[8]; 420 u_char product_id[12]; 421 void *oem_table_pointer; 422 u_short oem_table_size; 423 u_short entry_count; 424 void *apic_address; 425 u_short extended_table_length; 426 u_char extended_table_checksum; 427 u_char reserved; 428} *mpcth_t; 429 430 431typedef struct PROCENTRY { 432 u_char type; 433 u_char apic_id; 434 u_char apic_version; 435 u_char cpu_flags; 436 u_long cpu_signature; 437 u_long feature_flags; 438 u_long reserved1; 439 u_long reserved2; 440} *proc_entry_ptr; 441 442typedef struct BUSENTRY { 443 u_char type; 444 u_char bus_id; 445 char bus_type[6]; 446} *bus_entry_ptr; 447 448typedef struct IOAPICENTRY { 449 u_char type; 450 u_char apic_id; 451 u_char apic_version; 452 u_char apic_flags; 453 void *apic_address; 454} *io_apic_entry_ptr; 455 456typedef struct INTENTRY { 457 u_char type; 458 u_char int_type; 459 u_short int_flags; 460 u_char src_bus_id; 461 u_char src_bus_irq; 462 u_char dst_apic_id; 463 u_char dst_apic_int; 464} *int_entry_ptr; 465/* descriptions of MP basetable entries */ 466typedef struct BASETABLE_ENTRY { 467 u_char type; 468 u_char length; 469 char name[16]; 470} basetable_entry; 471 472static basetable_entry basetable_entry_types[] = 473{ 474 {0, 20, "Processor"}, 475 {1, 8, "Bus"}, 476 {2, 8, "I/O APIC"}, 477 {3, 8, "I/O INT"}, 478 {4, 8, "Local INT"} 479}; 480 481typedef struct BUSDATA { 482 u_char bus_id; 483 enum busTypes bus_type; 484} bus_datum; 485 486typedef struct INTDATA { 487 u_char int_type; 488 u_short int_flags; 489 u_char src_bus_id; 490 u_char src_bus_irq; 491 u_char dst_apic_id; 492 u_char dst_apic_int; 493} io_int, local_int; 494 495typedef struct BUSTYPENAME { 496 u_char type; 497 char name[7]; 498} bus_type_name; 499 500static bus_type_name bus_type_table[] = 501{ 502 {CBUS, "CBUS"}, 503 {CBUSII, "CBUSII"}, 504 {EISA, "EISA"}, 505 {UNKNOWN_BUSTYPE, "---"}, 506 {UNKNOWN_BUSTYPE, "---"}, 507 {ISA, "ISA"}, 508 {UNKNOWN_BUSTYPE, "---"}, 509 {UNKNOWN_BUSTYPE, "---"}, 510 {UNKNOWN_BUSTYPE, "---"}, 511 {UNKNOWN_BUSTYPE, "---"}, 512 {UNKNOWN_BUSTYPE, "---"}, 513 {UNKNOWN_BUSTYPE, "---"}, 514 {PCI, "PCI"}, 515 {UNKNOWN_BUSTYPE, "---"}, 516 {UNKNOWN_BUSTYPE, "---"}, 517 {UNKNOWN_BUSTYPE, "---"}, 518 {UNKNOWN_BUSTYPE, "---"}, 519 {XPRESS, "XPRESS"}, 520 {UNKNOWN_BUSTYPE, "---"} 521}; 522/* from MP spec v1.4, table 5-1 */ 523static int default_data[7][5] = 524{ 525/* nbus, id0, type0, id1, type1 */ 526 {1, 0, ISA, 255, 255}, 527 {1, 0, EISA, 255, 255}, 528 {1, 0, EISA, 255, 255}, 529 {0, 255, 255, 255, 255},/* MCA not supported */ 530 {2, 0, ISA, 1, PCI}, 531 {2, 0, EISA, 1, PCI}, 532 {0, 255, 255, 255, 255} /* MCA not supported */ 533}; 534 535 536/* the bus data */ 537bus_datum bus_data[NBUS]; 538 539/* the IO INT data, one entry per possible APIC INTerrupt */ 540io_int io_apic_ints[NINTR]; 541 542static int nintrs; 543 544#if defined(FIX_MP_TABLE_WORKS) 545static void fix_mp_table __P((void)); 546#endif /* FIX_MP_TABLE_WORKS */ 547 548static void processor_entry __P((proc_entry_ptr entry, int *cpu)); 549static void io_apic_entry __P((io_apic_entry_ptr entry, int *apic)); 550static void bus_entry __P((bus_entry_ptr entry, int *bus)); 551static void int_entry __P((int_entry_ptr entry, int *intr)); 552static int lookup_bus_type __P((char *name)); 553 554 555/* 556 * parse an Intel MP specification table 557 */ 558static int 559parse_mp_table(void) 560{ 561 int x; 562 mpfps_t fps; 563 mpcth_t cth; 564 int totalSize; 565 void *position; 566 int count; 567 int type; 568 int apic, bus, cpu, intr; 569 570 /* clear physical APIC ID to logical CPU/IO table */ 571 for (x = 0; x < NAPICID; ++x) 572 ID_TO_IO(x) = -1; 573 574 /* clear logical CPU to APIC ID table */ 575 for (x = 0; x < NCPU; ++x) 576 CPU_TO_ID(x) = -1; 577 578 /* clear logical IO to APIC ID table */ 579 for (x = 0; x < NAPIC; ++x) 580 IO_TO_ID(x) = -1; 581 582 /* clear IO APIC address table */ 583 for (x = 0; x < NAPIC; ++x) 584 io_apic_address[x] = ~0; 585 586 /* clear bus data table */ 587 for (x = 0; x < NBUS; ++x) 588 bus_data[x].bus_id = 0xff; 589 590 /* clear IO APIC INT table */ 591 for (x = 0; x < NINTR; ++x) 592 io_apic_ints[x].int_type = 0xff; 593 nintrs = 0; 594 595 /* count the BSP */ 596 mp_ncpus = 1; 597 598 /* setup the cpu/apic mapping arrays */ 599 boot_cpu_id = -1; 600 601 /* local pointer */ 602 fps = (mpfps_t) mpfps; 603 604 /* record whether PIC or virtual-wire mode */ 605 picmode = (fps->mpfb2 & 0x80) ? 1 : 0; 606 607 /* check for use of 'default' configuration */ 608#if defined(TEST_DEFAULT_CONFIG) 609 /* use default addresses */ 610 cpu_apic_address = DEFAULT_APIC_BASE; 611 io_apic_address[0] = DEFAULT_IO_APIC_BASE; 612 613 /* return default configuration type */ 614 return TEST_DEFAULT_CONFIG; 615#else 616 if (fps->mpfb1 != 0) { 617 /* use default addresses */ 618 cpu_apic_address = DEFAULT_APIC_BASE; 619 io_apic_address[0] = DEFAULT_IO_APIC_BASE; 620 621 /* return default configuration type */ 622 return fps->mpfb1; 623 } 624#endif /* TEST_DEFAULT_CONFIG */ 625 626 if ((cth = fps->pap) == 0) 627 panic("MP Configuration Table Header MISSING!\n"); 628 629 cpu_apic_address = (vm_offset_t) cth->apic_address; 630 631 totalSize = cth->base_table_length - sizeof(struct MPCTH); 632 position = (u_char *) cth + sizeof(struct MPCTH); 633 count = cth->entry_count; 634 635 apic = 0; /* logical apic# start @ 0 */ 636 bus = 0; /* logical bus# start @ 0 */ 637 cpu = 1; /* logical cpu# start @ 0, BUT reserve 0 for */ 638 /* BSP */ 639 intr = 0; /* unknown */ 640 641 /* walk the table, recording info of interest */ 642 while (count--) { 643 switch (type = *(u_char *) position) { 644 case 0: 645 processor_entry(position, &cpu); 646 break; 647 case 1: 648 bus_entry(position, &bus); 649 break; 650 case 2: 651 io_apic_entry(position, &apic); 652 break; 653 case 3: 654 int_entry(position, &intr); 655 break; 656 case 4: 657 /* int_entry(position); */ 658 break; 659 default: 660 panic("mpfps Base Table HOSED!\n"); 661 /* NOTREACHED */ 662 } 663 664 totalSize -= basetable_entry_types[type].length; 665 (u_char *) position += basetable_entry_types[type].length; 666 } 667 668 if (boot_cpu_id == -1) 669 panic("NO BSP found!\n"); 670 671 /* record # of APs found */ 672 mp_naps = (cpu - 1); 673 674 /* record # of busses found */ 675 mp_nbusses = bus; 676 677 /* record # of IO APICs found */ 678 mp_napics = apic; 679 680 /* record # of IO APICs found */ 681 nintrs = intr; 682 683#if defined(FIX_MP_TABLE_WORKS) 684 /* post scan cleanup */ 685 fix_mp_table(); 686#endif /* FIX_MP_TABLE_WORKS */ 687 688 /* report fact that its NOT a default configuration */ 689 return 0; 690} 691 692 693/* 694 * parse an Intel MP specification table 695 */ 696#if defined(FIX_MP_TABLE_WORKS) 697static void 698fix_mp_table(void) 699{ 700 int x; 701 int y; 702 int num_pci_bus; 703 bus_datum bus_record; 704 705 /* 706 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS 707 * did it wrong. The MP spec says that when more than 1 PCI bus 708 * exists the BIOS must begin with bus entries for the PCI bus and use 709 * actual PCI bus numbering. This implies that when only 1 PCI bus 710 * exists the BIOS can choose to ignore this ordering, and indeed many 711 * MP motherboards do ignore it. This causes a problem when the PCI 712 * sub-system makes requests of the MP sub-system based on PCI bus 713 * numbers. So here we look for the situation and renumber the 714 * busses and associated INTs in an effort to "make it right". 715 */ 716 717 /* count the number of PCI busses */ 718 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { 719 if (bus_data[x].bus_type == PCI) 720 ++num_pci_bus; 721 } 722 723 /* check the 1 PCI bus case for sanity */ 724 if (num_pci_bus == 1) { 725 726 /* if its in the first slot all is well */ 727 if (bus_data[0].bus_type == PCI) 728 return; 729 730 /* mis-numbered, swap with whichever bus uses slot 0 */ 731 732 /* locate the entry holding the PCI bus */ 733 for (x = 1; x < mp_nbusses; ++x) { 734 if (bus_data[x].bus_type == PCI) 735 break; 736 } 737 738 /* swap the bus entry records */ 739 bus_record = bus_data[0]; 740 bus_data[0] = bus_data[x]; 741 bus_data[x] = bus_record; 742 743 /* swap each relavant INTerrupt entry */ 744 for (y = 0; y < nintrs; ++y) { 745 if (io_apic_ints[y].src_bus_id == x) 746 io_apic_ints[y].src_bus_id = 0; 747 else 748 if (io_apic_ints[y].src_bus_id == 0) 749 io_apic_ints[y].src_bus_id = x; 750 } 751 } 752 /* sanity check if more than 1 PCI bus */ 753 else 754 if (num_pci_bus > 1) { 755 for (x = 0; x < num_pci_bus; ++x) { 756 if (bus_data[x].bus_type != PCI) { 757 printf("bad PCI bus numbering\n"); 758 panic("\n"); 759 } 760 } 761 } 762} 763#endif /* FIX_MP_TABLE_WORKS */ 764 765 766static void 767processor_entry(proc_entry_ptr entry, int *cpu) 768{ 769 int x = *cpu; 770 771 /* check for usability */ 772 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN)) 773 return; 774 775 /* check for BSP flag */ 776 if (entry->cpu_flags & PROCENTRY_FLAG_BP) { 777 /* always give boot CPU the logical value of 0 */ 778 x = 0; 779 boot_cpu_id = entry->apic_id; 780 } else { 781 /* add another AP to list, if less than max number of CPUs */ 782 if (x == NCPU) { 783 printf("Warning: only using %d of the available CPUs!\n", x); 784 return; 785 } 786 ++(*cpu); 787 } 788 789 CPU_TO_ID(x) = entry->apic_id; 790 ID_TO_CPU(entry->apic_id) = x; 791} 792 793 794static void 795bus_entry(bus_entry_ptr entry, int *bus) 796{ 797 int x, y; 798 char name[8]; 799 char c; 800 801 if ((x = (*bus)++) == NBUS) 802 panic("too many busses, increase 'NBUS'\n"); 803 804 /* encode the name into an index */ 805 for (y = 0; y < 6; ++y) { 806 if ((c = entry->bus_type[y]) == ' ') 807 break; 808 name[y] = c; 809 } 810 name[y] = '\0'; 811 812 if ((y = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) 813 panic("unknown bus type: '%s'\n", name); 814 815 bus_data[x].bus_id = entry->bus_id; 816 bus_data[x].bus_type = y; 817} 818 819 820static void 821io_apic_entry(io_apic_entry_ptr entry, int *apic) 822{ 823 int x; 824 825 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) 826 return; 827 828 if ((x = (*apic)++) == NAPIC) 829 panic("too many APICs, increase 'NAPIC'\n"); 830 831 IO_TO_ID(x) = entry->apic_id; 832 ID_TO_IO(entry->apic_id) = x; 833 834 io_apic_address[x] = (vm_offset_t) entry->apic_address; 835} 836 837 838static int 839lookup_bus_type(char *name) 840{ 841 int x; 842 843 for (x = 0; x < MAX_BUSTYPE; ++x) 844 if (strcmp(bus_type_table[x].name, name) == 0) 845 return bus_type_table[x].type; 846 847 return UNKNOWN_BUSTYPE; 848} 849 850 851static void 852int_entry(int_entry_ptr entry, int *intr) 853{ 854 int x; 855 856 if ((x = (*intr)++) == NINTR) 857 panic("too many INTs, increase 'NINTR'\n"); 858 859 io_apic_ints[x].int_type = entry->int_type; 860 io_apic_ints[x].int_flags = entry->int_flags; 861 io_apic_ints[x].src_bus_id = entry->src_bus_id; 862 io_apic_ints[x].src_bus_irq = entry->src_bus_irq; 863 io_apic_ints[x].dst_apic_id = entry->dst_apic_id; 864 io_apic_ints[x].dst_apic_int = entry->dst_apic_int; 865} 866 867 868static int 869apic_int_is_bus_type(int intr, int bus_type) 870{ 871 int bus; 872 873 for (bus = 0; bus < mp_nbusses; ++bus) 874 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) 875 && ((int) bus_data[bus].bus_type == bus_type)) 876 return 1; 877 878 return 0; 879} 880 881 882/* 883 * determine which APIC pin an ISA INT is attached to. 884 */ 885#define INTTYPE(I) (io_apic_ints[(I)].int_type) 886#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) 887 888#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) 889int 890get_isa_apic_irq(int isaIRQ) 891{ 892 int intr; 893 894#if defined(SMP_TIMER_NC) 895 if (isaIRQ == 0) 896 return -1; 897#endif /* SMP_TIMER_NC */ 898 899 for (intr = 0; intr < nintrs; ++intr) /* search each INT record */ 900 if ((INTTYPE(intr) == 0) 901 && (SRCBUSIRQ(intr) == isaIRQ)) /* a candidate IRQ */ 902 if (apic_int_is_bus_type(intr, ISA)) /* check bus match */ 903 return INTPIN(intr); /* exact match */ 904 905 return -1; /* NOT found */ 906} 907#undef SRCBUSIRQ 908 909 910/* 911 * determine which APIC pin an EISA INT is attached to. 912 */ 913#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) 914int 915get_eisa_apic_irq(int eisaIRQ) 916{ 917 int intr; 918 919#if defined(SMP_TIMER_NC) 920 if (eisaIRQ == 0) 921 return -1; 922#endif /* SMP_TIMER_NC */ 923 924 for (intr = 0; intr < nintrs; ++intr) /* search each INT record */ 925 if ((INTTYPE(intr) == 0) 926 && (SRCBUSIRQ(intr) == eisaIRQ)) /* a candidate IRQ */ 927 if (apic_int_is_bus_type(intr, EISA)) /* check bus match */ 928 return INTPIN(intr); /* exact match */ 929 930 return -1; /* NOT found */ 931} 932#undef SRCBUSIRQ 933 934 935/* 936 * determine which APIC pin a PCI INT is attached to. 937 */ 938#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) 939#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) 940#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) 941int 942get_pci_apic_irq(int pciBus, int pciDevice, int pciInt) 943{ 944 int intr; 945 946 --pciInt; /* zero based */ 947 948 for (intr = 0; intr < nintrs; ++intr) /* search each record */ 949 if ((INTTYPE(intr) == 0) 950#if defined(FIX_MP_TABLE_WORKS) 951 && (SRCBUSID(intr) == pciBus) 952#endif /* FIX_MP_TABLE_WORKS */ 953 && (SRCBUSDEVICE(intr) == pciDevice) 954 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ 955 if (apic_int_is_bus_type(intr, PCI)) /* check bus match */ 956 return INTPIN(intr); /* exact match */ 957 958 return -1; /* NOT found */ 959} 960#undef SRCBUSLINE 961#undef SRCBUSDEVICE 962#undef SRCBUSID 963 964#undef INTPIN 965#undef INTTYPE 966 967 968int 969undirect_pci_irq(int rirq) 970{ 971#if defined(READY) 972 printf("Freeing irq %d for ISA cards.\n", rirq); 973 /** FIXME: tickle the MB redirector chip */ 974 return ???; 975#else 976 printf("Freeing (NOT implimented) irq %d for ISA cards.\n", rirq); 977 return 0; 978#endif /* READY */ 979} 980 981 982/* 983 * given a bus ID, return: 984 * the bus type if found 985 * -1 if NOT found 986 */ 987int 988apic_bus_type(int id) 989{ 990 int x; 991 992 for (x = 0; x < mp_nbusses; ++x) 993 if (bus_data[x].bus_id == id) 994 return bus_data[x].bus_type; 995 996 return -1; 997} 998 999 1000/* 1001 * given a LOGICAL APIC# and pin#, return: 1002 * the associated src bus ID if found 1003 * -1 if NOT found 1004 */ 1005int 1006apic_src_bus_id(int apic, int pin) 1007{ 1008 int x; 1009 1010 /* search each of the possible INTerrupt sources */ 1011 for (x = 0; x < nintrs; ++x) 1012 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1013 (pin == io_apic_ints[x].dst_apic_int)) 1014 return (io_apic_ints[x].src_bus_id); 1015 1016 return -1; /* NOT found */ 1017} 1018 1019 1020/* 1021 * given a LOGICAL APIC# and pin#, return: 1022 * the associated src bus IRQ if found 1023 * -1 if NOT found 1024 */ 1025int 1026apic_src_bus_irq(int apic, int pin) 1027{ 1028 int x; 1029 1030 for (x = 0; x < nintrs; x++) 1031 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1032 (pin == io_apic_ints[x].dst_apic_int)) 1033 return (io_apic_ints[x].src_bus_irq); 1034 1035 return -1; /* NOT found */ 1036} 1037 1038 1039/* 1040 * given a LOGICAL APIC# and pin#, return: 1041 * the associated INTerrupt type if found 1042 * -1 if NOT found 1043 */ 1044int 1045apic_int_type(int apic, int pin) 1046{ 1047 int x; 1048 1049 /* search each of the possible INTerrupt sources */ 1050 for (x = 0; x < nintrs; ++x) 1051 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1052 (pin == io_apic_ints[x].dst_apic_int)) 1053 return (io_apic_ints[x].int_type); 1054 1055 return -1; /* NOT found */ 1056} 1057 1058 1059/* 1060 * given a LOGICAL APIC# and pin#, return: 1061 * the associated trigger mode if found 1062 * -1 if NOT found 1063 */ 1064int 1065apic_trigger(int apic, int pin) 1066{ 1067 int x; 1068 1069 /* search each of the possible INTerrupt sources */ 1070 for (x = 0; x < nintrs; ++x) 1071 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1072 (pin == io_apic_ints[x].dst_apic_int)) 1073 return ((io_apic_ints[x].int_flags >> 2) & 0x03); 1074 1075 return -1; /* NOT found */ 1076} 1077 1078 1079/* 1080 * given a LOGICAL APIC# and pin#, return: 1081 * the associated 'active' level if found 1082 * -1 if NOT found 1083 */ 1084int 1085apic_polarity(int apic, int pin) 1086{ 1087 int x; 1088 1089 /* search each of the possible INTerrupt sources */ 1090 for (x = 0; x < nintrs; ++x) 1091 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1092 (pin == io_apic_ints[x].dst_apic_int)) 1093 return (io_apic_ints[x].int_flags & 0x03); 1094 1095 return -1; /* NOT found */ 1096} 1097 1098 1099/* 1100 * set data according to MP defaults 1101 * FIXME: probably not complete yet... 1102 */ 1103static void 1104default_mp_table(int type) 1105{ 1106 int ap_cpu_id; 1107#if defined(APIC_IO) 1108 u_int32_t ux; 1109 int io_apic_id; 1110 int pin; 1111#endif /* APIC_IO */ 1112 1113#if 0 1114 printf(" MP default config type: %d\n", type); 1115 switch (type) { 1116 case 1: 1117 printf(" bus: ISA, APIC: 82489DX\n"); 1118 break; 1119 case 2: 1120 printf(" bus: EISA, APIC: 82489DX\n"); 1121 break; 1122 case 3: 1123 printf(" bus: EISA, APIC: 82489DX\n"); 1124 break; 1125 case 4: 1126 printf(" bus: MCA, APIC: 82489DX\n"); 1127 break; 1128 case 5: 1129 printf(" bus: ISA+PCI, APIC: Integrated\n"); 1130 break; 1131 case 6: 1132 printf(" bus: EISA+PCI, APIC: Integrated\n"); 1133 break; 1134 case 7: 1135 printf(" bus: MCA+PCI, APIC: Integrated\n"); 1136 break; 1137 default: 1138 printf(" future type\n"); 1139 break; 1140 /* NOTREACHED */ 1141 } 1142#endif /* 0 */ 1143 1144 boot_cpu_id = (apic_base[APIC_ID] & APIC_ID_MASK) >> 24; 1145 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; 1146 1147 /* BSP */ 1148 CPU_TO_ID(0) = boot_cpu_id; 1149 ID_TO_CPU(boot_cpu_id) = 0; 1150 1151 /* one and only AP */ 1152 CPU_TO_ID(1) = ap_cpu_id; 1153 ID_TO_CPU(ap_cpu_id) = 1; 1154 mp_naps = 1; 1155 1156 /* one and only IO APIC */ 1157#if defined(APIC_IO) 1158 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; 1159 1160 /* 1161 * sanity check, refer to MP spec section 3.6.6, last paragraph 1162 * necessary as some hardware isn't properly setting up the IO APIC 1163 */ 1164#if defined(REALLY_ANAL_IOAPICID_VALUE) 1165 if (io_apic_id != 2) { 1166#else 1167 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { 1168#endif /* REALLY_ANAL_IOAPICID_VALUE */ 1169 ux = io_apic_read(0, IOAPIC_ID); /* get current contents */ 1170 ux &= ~APIC_ID_MASK; /* clear the ID field */ 1171 ux |= 0x02000000; /* set it to '2' */ 1172 io_apic_write(0, IOAPIC_ID, ux); /* write new value */ 1173 ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */ 1174 if ((ux & APIC_ID_MASK) != 0x02000000) 1175 panic("Problem: can't control IO APIC ID, reg: 0x%08x\n", ux); 1176 io_apic_id = 2; 1177 } 1178 IO_TO_ID(0) = io_apic_id; 1179 ID_TO_IO(io_apic_id) = 0; 1180 mp_napics = 1; 1181#else 1182 mp_napics = 0; 1183#endif /* APIC_IO */ 1184 1185 /* fill out bus entries */ 1186 switch (type) { 1187 case 1: 1188 case 2: 1189 case 3: 1190 case 5: 1191 case 6: 1192 mp_nbusses = default_data[type - 1][0]; 1193 bus_data[0].bus_id = default_data[type - 1][1]; 1194 bus_data[0].bus_type = default_data[type - 1][2]; 1195 bus_data[1].bus_id = default_data[type - 1][3]; 1196 bus_data[1].bus_type = default_data[type - 1][4]; 1197 break; 1198 1199 /* case 4: case 7: MCA NOT supported */ 1200 default: /* illegal/reserved */ 1201 panic("BAD default MP config: %d\n", type); 1202 } 1203 1204#if defined(APIC_IO) 1205 /* general cases from MP v1.4, table 5-2 */ 1206 for (pin = 0; pin < 16; ++pin) { 1207 io_apic_ints[pin].int_type = 0; 1208 io_apic_ints[pin].int_flags = 0x05; /* edge-triggered/active-hi */ 1209 io_apic_ints[pin].src_bus_id = 0; 1210 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 is caught below */ 1211 io_apic_ints[pin].dst_apic_id = io_apic_id; 1212 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 correspondence */ 1213 } 1214 1215 /* special cases from MP v1.4, table 5-2 */ 1216 if (type == 2) { 1217 io_apic_ints[2].int_type = 0xff; /* N/C */ 1218 io_apic_ints[13].int_type = 0xff; /* N/C */ 1219#if !defined(APIC_MIXED_MODE) 1220 /** FIXME: ??? */ 1221 panic("sorry, can't support type 2 default yet\n"); 1222#endif /* APIC_MIXED_MODE */ 1223 } else 1224 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ 1225 1226 if (type == 7) 1227 io_apic_ints[0].int_type = 0xff; /* N/C */ 1228 else 1229 io_apic_ints[0].int_type = 3; /* vectored 8259 */ 1230 1231 nintrs = 16; 1232#endif /* APIC_IO */ 1233} 1234 1235 1236static void install_ap_tramp(u_int boot_addr); 1237static int start_ap(int logicalCpu, u_int boot_addr); 1238 1239/* 1240 * start each AP in our list 1241 */ 1242static int 1243start_all_aps(u_int boot_addr) 1244{ 1245 int x; 1246 u_char mpbiosreason; 1247 u_long mpbioswarmvec; 1248 1249 /** 1250 * NOTE: this needs further thought: 1251 * where does it get released? 1252 * should it be set to empy? 1253 * 1254 * get the initial mp_lock with a count of 1 for the BSP 1255 */ 1256 mp_lock = (apic_base[APIC_ID] & APIC_ID_MASK) + 1; 1257 1258 /* initialize BSP's local APIC */ 1259 apic_initialize(1); 1260 1261 /* install the AP 1st level boot code */ 1262 install_ap_tramp(boot_addr); 1263 1264 /* save the current value of the warm-start vector */ 1265 mpbioswarmvec = *((u_long *) WARMBOOT_OFF); 1266 outb(CMOS_REG, BIOS_RESET); 1267 mpbiosreason = inb(CMOS_DATA); 1268 1269 /* start each AP */ 1270 for (x = 1; x <= mp_naps; ++x) { 1271 1272 /* setup a vector to our boot code */ 1273 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 1274 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); 1275 outb(CMOS_REG, BIOS_RESET); 1276 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 1277 1278 /* attempt to start the Application Processor */ 1279 CHECK_INIT(99); /* setup checkpoints */ 1280 if (!start_ap(x, boot_addr)) { 1281 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); 1282 CHECK_PRINT("trace"); /* show checkpoints */ 1283 /* 1284 * better panic as the AP may be running loose 1285 * somewhere 1286 */ 1287 printf("panic y/n? [n] "); 1288 if (cngetc() != 'n') 1289 panic("bye-bye\n"); 1290 } 1291 CHECK_PRINT("trace"); /* show checkpoints */ 1292 1293 /* record its version info */ 1294 cpu_apic_versions[x] = cpu_apic_versions[0]; 1295 } 1296 1297 /* fill in our (BSP) APIC version */ 1298 cpu_apic_versions[0] = apic_base[APIC_VER]; 1299 1300 /* restore the warmstart vector */ 1301 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 1302 outb(CMOS_REG, BIOS_RESET); 1303 outb(CMOS_DATA, mpbiosreason); 1304 1305 /* number of APs actually started */ 1306 return mp_ncpus - 1; 1307} 1308 1309 1310/* 1311 * load the 1st level AP boot code into base memory. 1312 */ 1313 1314/* targets for relocation */ 1315extern void bigJump(void); 1316extern void bootCodeSeg(void); 1317extern void bootDataSeg(void); 1318extern void MPentry(void); 1319extern u_int MP_GDT; 1320extern u_int mp_gdtbase; 1321 1322static void 1323install_ap_tramp(u_int boot_addr) 1324{ 1325 int x; 1326 int size = *(int *) ((u_long) & bootMP_size); 1327 u_char *src = (u_char *) ((u_long) bootMP); 1328 u_char *dst = (u_char *) boot_addr + KERNBASE; 1329 u_int boot_base = (u_int) bootMP; 1330 u_int8_t *dst8; 1331 u_int16_t *dst16; 1332 u_int32_t *dst32; 1333 1334 for (x = 0; x < size; ++x) 1335 *dst++ = *src++; 1336 1337 /* 1338 * modify addresses in code we just moved to basemem. unfortunately we 1339 * need fairly detailed info about mpboot.s for this to work. changes 1340 * to mpboot.s might require changes here. 1341 */ 1342 1343 /* boot code is located in KERNEL space */ 1344 dst = (u_char *) boot_addr + KERNBASE; 1345 1346 /* modify the lgdt arg */ 1347 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 1348 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); 1349 1350 /* modify the ljmp target for MPentry() */ 1351 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 1352 *dst32 = ((u_int) MPentry - KERNBASE); 1353 1354 /* modify the target for boot code segment */ 1355 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 1356 dst8 = (u_int8_t *) (dst16 + 1); 1357 *dst16 = (u_int) boot_addr & 0xffff; 1358 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1359 1360 /* modify the target for boot data segment */ 1361 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 1362 dst8 = (u_int8_t *) (dst16 + 1); 1363 *dst16 = (u_int) boot_addr & 0xffff; 1364 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1365} 1366 1367 1368/* 1369 * this function starts the AP (application processor) identified 1370 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 1371 * to accomplish this. This is necessary because of the nuances 1372 * of the different hardware we might encounter. It ain't pretty, 1373 * but it seems to work. 1374 */ 1375static int 1376start_ap(int logical_cpu, u_int boot_addr) 1377{ 1378 int physical_cpu; 1379 int vector; 1380 int cpus; 1381 u_long icr_lo, icr_hi; 1382 1383 /* get the PHYSICAL APIC ID# */ 1384 physical_cpu = CPU_TO_ID(logical_cpu); 1385 1386 /* calculate the vector */ 1387 vector = (boot_addr >> 12) & 0xff; 1388 1389 /* used as a watchpoint to signal AP startup */ 1390 cpus = mp_ncpus; 1391 1392 /* 1393 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 1394 * and running the target CPU. OR this INIT IPI might be latched (P5 1395 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 1396 * ignored. 1397 */ 1398 1399 /* setup the address for the target AP */ 1400 icr_hi = apic_base[APIC_ICR_HI] & ~APIC_ID_MASK; 1401 icr_hi |= (physical_cpu << 24); 1402 apic_base[APIC_ICR_HI] = icr_hi; 1403 1404 /* do an INIT IPI: assert RESET */ 1405 icr_lo = apic_base[APIC_ICR_LOW] & 0xfff00000; 1406 apic_base[APIC_ICR_LOW] = icr_lo | 0x0000c500; 1407 1408 /* wait for pending status end */ 1409 while (apic_base[APIC_ICR_LOW] & APIC_DELSTAT_MASK) 1410 /* spin */ ; 1411 1412 /* do an INIT IPI: deassert RESET */ 1413 apic_base[APIC_ICR_LOW] = icr_lo | 0x00008500; 1414 1415 /* wait for pending status end */ 1416 u_sleep(10000); /* wait ~10mS */ 1417 while (apic_base[APIC_ICR_LOW] & APIC_DELSTAT_MASK) 1418 /* spin */ ; 1419 1420 /* 1421 * next we do a STARTUP IPI: the previous INIT IPI might still be 1422 * latched, (P5 bug) this 1st STARTUP would then terminate 1423 * immediately, and the previously started INIT IPI would continue. OR 1424 * the previous INIT IPI has already run. and this STARTUP IPI will 1425 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 1426 * will run. 1427 */ 1428 1429 /* do a STARTUP IPI */ 1430 apic_base[APIC_ICR_LOW] = icr_lo | 0x00000600 | vector; 1431 while (apic_base[APIC_ICR_LOW] & APIC_DELSTAT_MASK) 1432 /* spin */ ; 1433 u_sleep(200); /* wait ~200uS */ 1434 1435 /* 1436 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 1437 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 1438 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 1439 * recognized after hardware RESET or INIT IPI. 1440 */ 1441 1442 apic_base[APIC_ICR_LOW] = icr_lo | 0x00000600 | vector; 1443 while (apic_base[APIC_ICR_LOW] & APIC_DELSTAT_MASK) 1444 /* spin */ ; 1445 u_sleep(200); /* wait ~200uS */ 1446 1447 /* wait for it to start */ 1448 set_apic_timer(5000000);/* == 5 seconds */ 1449 while (read_apic_timer()) 1450 if (mp_ncpus > cpus) 1451 return 1; /* return SUCCESS */ 1452 1453 return 0; /* return FAILURE */ 1454} 1455 1456 1457/* 1458 * Flush the TLB on all other CPU's 1459 * 1460 * XXX: Needs to handshake and wait for completion before proceding. 1461 */ 1462void 1463smp_invltlb(void) 1464{ 1465 if (smp_active && invltlb_ok) 1466 all_but_self_ipi(ICU_OFFSET + XINVLTLB_OFFSET); 1467} 1468 1469void 1470invlpg(u_int addr) 1471{ 1472 __asm __volatile("invlpg (%0)"::"r"(addr):"memory"); 1473 1474 /* send a message to the other CPUs */ 1475 smp_invltlb(); 1476} 1477 1478void 1479invltlb(void) 1480{ 1481 u_long temp; 1482 1483 /* 1484 * This should be implemented as load_cr3(rcr3()) when load_cr3() is 1485 * inlined. 1486 */ 1487 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory"); 1488 1489 /* send a message to the other CPUs */ 1490 smp_invltlb(); 1491} 1492