mptable.c revision 122434
1/*- 2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3 * Copyright (c) 1996, by Steve Passe 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. The name of the developer may NOT be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/i386/i386/mptable.c 122434 2003-11-10 19:52:58Z jhb $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/kernel.h> 34#include <sys/malloc.h> 35 36#include <vm/vm.h> 37#include <vm/vm_param.h> 38#include <vm/pmap.h> 39 40#include <machine/apicreg.h> 41#include <machine/frame.h> 42#include <machine/intr_machdep.h> 43#include <machine/apicvar.h> 44#include <machine/md_var.h> 45#include <machine/mptable.h> 46#include <machine/specialreg.h> 47 48#include <dev/pci/pcivar.h> 49 50/* EISA Edge/Level trigger control registers */ 51#define ELCR0 0x4d0 /* eisa irq 0-7 */ 52#define ELCR1 0x4d1 /* eisa irq 8-15 */ 53 54/* string defined by the Intel MP Spec as identifying the MP table */ 55#define MP_SIG 0x5f504d5f /* _MP_ */ 56 57#define NAPICID 32 /* Max number of I/O APIC's */ 58 59#ifdef PC98 60#define BIOS_BASE (0xe8000) 61#define BIOS_SIZE (0x18000) 62#else 63#define BIOS_BASE (0xf0000) 64#define BIOS_SIZE (0x10000) 65#endif 66#define BIOS_COUNT (BIOS_SIZE/4) 67 68typedef void mptable_entry_handler(u_char *entry, void *arg); 69 70static basetable_entry basetable_entry_types[] = 71{ 72 {0, 20, "Processor"}, 73 {1, 8, "Bus"}, 74 {2, 8, "I/O APIC"}, 75 {3, 8, "I/O INT"}, 76 {4, 8, "Local INT"} 77}; 78 79typedef struct BUSDATA { 80 u_char bus_id; 81 enum busTypes bus_type; 82} bus_datum; 83 84typedef struct INTDATA { 85 u_char int_type; 86 u_short int_flags; 87 u_char src_bus_id; 88 u_char src_bus_irq; 89 u_char dst_apic_id; 90 u_char dst_apic_int; 91 u_char int_vector; 92} io_int, local_int; 93 94typedef struct BUSTYPENAME { 95 u_char type; 96 char name[7]; 97} bus_type_name; 98 99/* From MP spec v1.4, table 4-8. */ 100static bus_type_name bus_type_table[] = 101{ 102 {UNKNOWN_BUSTYPE, "CBUS "}, 103 {UNKNOWN_BUSTYPE, "CBUSII"}, 104 {EISA, "EISA "}, 105 {UNKNOWN_BUSTYPE, "FUTURE"}, 106 {UNKNOWN_BUSTYPE, "INTERN"}, 107 {ISA, "ISA "}, 108 {UNKNOWN_BUSTYPE, "MBI "}, 109 {UNKNOWN_BUSTYPE, "MBII "}, 110 {MCA, "MCA "}, 111 {UNKNOWN_BUSTYPE, "MPI "}, 112 {UNKNOWN_BUSTYPE, "MPSA "}, 113 {UNKNOWN_BUSTYPE, "NUBUS "}, 114 {PCI, "PCI "}, 115 {UNKNOWN_BUSTYPE, "PCMCIA"}, 116 {UNKNOWN_BUSTYPE, "TC "}, 117 {UNKNOWN_BUSTYPE, "VL "}, 118 {UNKNOWN_BUSTYPE, "VME "}, 119 {UNKNOWN_BUSTYPE, "XPRESS"} 120}; 121 122/* From MP spec v1.4, table 5-1. */ 123static int default_data[7][5] = 124{ 125/* nbus, id0, type0, id1, type1 */ 126 {1, 0, ISA, 255, NOBUS}, 127 {1, 0, EISA, 255, NOBUS}, 128 {1, 0, EISA, 255, NOBUS}, 129 {1, 0, MCA, 255, NOBUS}, 130 {2, 0, ISA, 1, PCI}, 131 {2, 0, EISA, 1, PCI}, 132 {2, 0, MCA, 1, PCI} 133}; 134 135struct pci_probe_table_args { 136 u_char bus; 137 u_char found; 138}; 139 140struct pci_route_interrupt_args { 141 u_char bus; /* Source bus. */ 142 u_char irq; /* Source slot:pin. */ 143 int vector; /* Return value. */ 144}; 145 146static mpfps_t mpfps; 147static mpcth_t mpct; 148static void *ioapics[NAPICID]; 149static bus_datum *busses; 150static int mptable_nioapics, mptable_nbusses, mptable_maxbusid; 151static int pci0 = -1; 152 153MALLOC_DEFINE(M_MPTABLE, "MP Table", "MP Table Items"); 154 155static u_char conforming_polarity(u_char src_bus); 156static u_char conforming_trigger(u_char src_bus, u_char src_bus_irq); 157static u_char intentry_polarity(int_entry_ptr intr); 158static u_char intentry_trigger(int_entry_ptr intr); 159static int lookup_bus_type(char *name); 160static void mptable_count_items(void); 161static void mptable_count_items_handler(u_char *entry, void *arg); 162static void mptable_hyperthread_fixup(u_int id_mask); 163static void mptable_parse_apics_and_busses(void); 164static void mptable_parse_apics_and_busses_handler(u_char *entry, 165 void *arg); 166static void mptable_parse_ints(void); 167static void mptable_parse_ints_handler(u_char *entry, void *arg); 168static void mptable_parse_io_int(int_entry_ptr intr); 169static void mptable_parse_local_int(int_entry_ptr intr); 170static void mptable_pci_probe_table_handler(u_char *entry, void *arg); 171static void mptable_pci_route_interrupt_handler(u_char *entry, void *arg); 172static void mptable_pci_setup(void); 173static int mptable_probe(void); 174static int mptable_probe_cpus(void); 175static void mptable_probe_cpus_handler(u_char *entry, void *arg __unused); 176static void mptable_register(void *dummy); 177static int mptable_setup_local(void); 178static int mptable_setup_io(void); 179static void mptable_walk_table(mptable_entry_handler *handler, void *arg); 180static int search_for_sig(u_int32_t target, int count); 181 182static struct apic_enumerator mptable_enumerator = { 183 "MPTable", 184 mptable_probe, 185 mptable_probe_cpus, 186 mptable_setup_local, 187 mptable_setup_io 188}; 189 190/* 191 * look for the MP spec signature 192 */ 193 194static int 195search_for_sig(u_int32_t target, int count) 196{ 197 int x; 198 u_int32_t *addr = (u_int32_t *) (KERNBASE + target); 199 200 for (x = 0; x < count; x += 4) 201 if (addr[x] == MP_SIG) 202 /* make array index a byte index */ 203 return (target + (x * sizeof(u_int32_t))); 204 return (-1); 205} 206 207static int 208lookup_bus_type(char *name) 209{ 210 int x; 211 212 for (x = 0; x < MAX_BUSTYPE; ++x) 213 if (strncmp(bus_type_table[x].name, name, 6) == 0) 214 return (bus_type_table[x].type); 215 216 return (UNKNOWN_BUSTYPE); 217} 218 219/* 220 * Look for an Intel MP spec table (ie, SMP capable hardware). 221 */ 222static int 223mptable_probe(void) 224{ 225 int x; 226 u_long segment; 227 u_int32_t target; 228 229 /* see if EBDA exists */ 230 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) { 231 /* search first 1K of EBDA */ 232 target = (u_int32_t) (segment << 4); 233 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 234 goto found; 235 } else { 236 /* last 1K of base memory, effective 'top of base' passed in */ 237 target = (u_int32_t) (basemem - 0x400); 238 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 239 goto found; 240 } 241 242 /* search the BIOS */ 243 target = (u_int32_t) BIOS_BASE; 244 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) 245 goto found; 246 247 /* nothing found */ 248 return (ENXIO); 249 250found: 251 mpfps = (mpfps_t)(KERNBASE + x); 252 253 /* Map in the configuration table if it exists. */ 254 if (mpfps->config_type != 0) 255 mpct = NULL; 256 else { 257 if ((uintptr_t)mpfps->pap >= 1024 * 1024) { 258 printf("%s: Unable to map MP Configuration Table\n", 259 __func__); 260 return (ENXIO); 261 } 262 mpct = (mpcth_t)(KERNBASE + (uintptr_t)mpfps->pap); 263 if (mpct->base_table_length + (uintptr_t)mpfps->pap >= 264 1024 * 1024) { 265 printf("%s: Unable to map end of MP Config Table\n", 266 __func__); 267 return (ENXIO); 268 } 269 if (mpct->signature[0] != 'P' || mpct->signature[1] != 'C' || 270 mpct->signature[2] != 'M' || mpct->signature[3] != 'P') { 271 printf("%s: MP Config Table has bad signature: %c%c%c%c\n", 272 __func__, mpct->signature[0], mpct->signature[1], 273 mpct->signature[2], mpct->signature[3]); 274 return (ENXIO); 275 } 276 if (bootverbose) 277 printf( 278 "MP Configuration Table version 1.%d found at %p\n", 279 mpct->spec_rev, mpct); 280 } 281 282 return (-100); 283} 284 285/* 286 * Run through the MP table enumerating CPUs. 287 */ 288static int 289mptable_probe_cpus(void) 290{ 291 u_int cpu_mask; 292 293 /* Is this a pre-defined config? */ 294 if (mpfps->config_type != 0) { 295 lapic_create(0, 1); 296 lapic_create(1, 0); 297 } else { 298 cpu_mask = 0; 299 mptable_walk_table(mptable_probe_cpus_handler, &cpu_mask); 300 mptable_hyperthread_fixup(cpu_mask); 301 } 302 return (0); 303} 304 305/* 306 * Initialize the local APIC on the BSP. 307 */ 308static int 309mptable_setup_local(void) 310{ 311 312 /* Is this a pre-defined config? */ 313 printf("MPTable: <"); 314 if (mpfps->config_type != 0) { 315 lapic_init(DEFAULT_APIC_BASE); 316 printf("Preset Config %d", mpfps->config_type); 317 } else { 318 lapic_init((uintptr_t)mpct->apic_address); 319 printf("%.*s %.*s", sizeof(mpct->oem_id), mpct->oem_id, 320 sizeof(mpct->product_id), mpct->product_id); 321 } 322 printf(">\n"); 323 return (0); 324} 325 326/* 327 * Run through the MP table enumerating I/O APICs. 328 */ 329static int 330mptable_setup_io(void) 331{ 332 int i; 333 u_char byte; 334 335 /* First, we count individual items and allocate arrays. */ 336 mptable_count_items(); 337 busses = malloc((mptable_maxbusid + 1) * sizeof(bus_datum), M_MPTABLE, 338 M_WAITOK); 339 for (i = 0; i <= mptable_maxbusid; i++) 340 busses[i].bus_type = NOBUS; 341 342 /* Second, we run through adding I/O APIC's and busses. */ 343 mptable_parse_apics_and_busses(); 344 345 /* Third, we run through the table tweaking interrupt sources. */ 346 mptable_parse_ints(); 347 348 /* Fourth, we register all the I/O APIC's. */ 349 for (i = 0; i < NAPICID; i++) 350 if (ioapics[i] != NULL) 351 ioapic_register(ioapics[i]); 352 353 /* Fifth, we setup data structures to handle PCI interrupt routing. */ 354 mptable_pci_setup(); 355 356 /* Finally, we throw the switch to enable the I/O APIC's. */ 357 if (mpfps->mpfb2 & MPFB2_IMCR_PRESENT) { 358 outb(0x22, 0x70); /* select IMCR */ 359 byte = inb(0x23); /* current contents */ 360 byte |= 0x01; /* mask external INTR */ 361 outb(0x23, byte); /* disconnect 8259s/NMI */ 362 } 363 364 return (0); 365} 366 367static void 368mptable_register(void *dummy __unused) 369{ 370 371 apic_register_enumerator(&mptable_enumerator); 372} 373SYSINIT(mptable_register, SI_SUB_TUNABLES - 1, SI_ORDER_FIRST, 374 mptable_register, NULL) 375 376/* 377 * Call the handler routine for each entry in the MP config table. 378 */ 379static void 380mptable_walk_table(mptable_entry_handler *handler, void *arg) 381{ 382 u_int i; 383 u_char *entry; 384 385 entry = (u_char *)(mpct + 1); 386 for (i = 0; i < mpct->entry_count; i++) { 387 switch (*entry) { 388 case MPCT_ENTRY_PROCESSOR: 389 case MPCT_ENTRY_IOAPIC: 390 case MPCT_ENTRY_BUS: 391 case MPCT_ENTRY_INT: 392 case MPCT_ENTRY_LOCAL_INT: 393 break; 394 default: 395 panic("%s: Unknown MP Config Entry %d\n", __func__, 396 (int)*entry); 397 } 398 handler(entry, arg); 399 entry += basetable_entry_types[*entry].length; 400 } 401} 402 403static void 404mptable_probe_cpus_handler(u_char *entry, void *arg) 405{ 406 proc_entry_ptr proc; 407 u_int *cpu_mask; 408 409 switch (*entry) { 410 case MPCT_ENTRY_PROCESSOR: 411 proc = (proc_entry_ptr)entry; 412 if (proc->cpu_flags & PROCENTRY_FLAG_EN) { 413 lapic_create(proc->apic_id, proc->cpu_flags & 414 PROCENTRY_FLAG_BP); 415 cpu_mask = (u_int *)arg; 416 *cpu_mask |= (1 << proc->apic_id); 417 } 418 break; 419 } 420} 421 422static void 423mptable_count_items_handler(u_char *entry, void *arg __unused) 424{ 425 io_apic_entry_ptr apic; 426 bus_entry_ptr bus; 427 428 switch (*entry) { 429 case MPCT_ENTRY_BUS: 430 bus = (bus_entry_ptr)entry; 431 mptable_nbusses++; 432 if (bus->bus_id > mptable_maxbusid) 433 mptable_maxbusid = bus->bus_id; 434 break; 435 case MPCT_ENTRY_IOAPIC: 436 apic = (io_apic_entry_ptr)entry; 437 if (apic->apic_flags & IOAPICENTRY_FLAG_EN) 438 mptable_nioapics++; 439 break; 440 } 441} 442 443/* 444 * Count items in the table. 445 */ 446static void 447mptable_count_items(void) 448{ 449 450 /* Is this a pre-defined config? */ 451 if (mpfps->config_type != 0) { 452 mptable_nioapics = 1; 453 switch (mpfps->config_type) { 454 case 1: 455 case 2: 456 case 3: 457 case 4: 458 mptable_nbusses = 1; 459 break; 460 case 5: 461 case 6: 462 case 7: 463 mptable_nbusses = 2; 464 break; 465 default: 466 panic("Unknown pre-defined MP Table config type %d", 467 mpfps->config_type); 468 } 469 mptable_maxbusid = mptable_nbusses - 1; 470 } else 471 mptable_walk_table(mptable_count_items_handler, NULL); 472} 473 474/* 475 * Add a bus or I/O APIC from an entry in the table. 476 */ 477static void 478mptable_parse_apics_and_busses_handler(u_char *entry, void *arg __unused) 479{ 480 io_apic_entry_ptr apic; 481 bus_entry_ptr bus; 482 enum busTypes bus_type; 483 int i; 484 485 486 switch (*entry) { 487 case MPCT_ENTRY_BUS: 488 bus = (bus_entry_ptr)entry; 489 bus_type = lookup_bus_type(bus->bus_type); 490 if (bus_type == UNKNOWN_BUSTYPE) { 491 printf("MPTable: Unknown bus %d type \"", bus->bus_id); 492 for (i = 0; i < 6; i++) 493 printf("%c", bus->bus_type[i]); 494 printf("\"\n"); 495 } 496 busses[bus->bus_id].bus_id = bus->bus_id; 497 busses[bus->bus_id].bus_type = bus_type; 498 break; 499 case MPCT_ENTRY_IOAPIC: 500 apic = (io_apic_entry_ptr)entry; 501 if (!(apic->apic_flags & IOAPICENTRY_FLAG_EN)) 502 break; 503 if (apic->apic_id >= NAPICID) 504 panic("%s: I/O APIC ID %d too high", __func__, 505 apic->apic_id); 506 if (ioapics[apic->apic_id] != NULL) 507 panic("%s: Double APIC ID %d", __func__, 508 apic->apic_id); 509 ioapics[apic->apic_id] = ioapic_create( 510 (uintptr_t)apic->apic_address, apic->apic_id, -1); 511 break; 512 default: 513 break; 514 } 515} 516 517/* 518 * Enumerate I/O APIC's and busses. 519 */ 520static void 521mptable_parse_apics_and_busses(void) 522{ 523 524 /* Is this a pre-defined config? */ 525 if (mpfps->config_type != 0) { 526 ioapics[0] = ioapic_create(DEFAULT_IO_APIC_BASE, 2, 0); 527 busses[0].bus_id = 0; 528 busses[0].bus_type = default_data[mpfps->config_type][2]; 529 if (mptable_nbusses > 1) { 530 busses[1].bus_id = 1; 531 busses[1].bus_type = 532 default_data[mpfps->config_type][4]; 533 } 534 } else 535 mptable_walk_table(mptable_parse_apics_and_busses_handler, 536 NULL); 537} 538 539/* 540 * Determine conforming polarity for a given bus type. 541 */ 542static u_char 543conforming_polarity(u_char src_bus) 544{ 545 546 KASSERT(src_bus <= mptable_maxbusid, ("bus id %d too large", src_bus)); 547 switch (busses[src_bus].bus_type) { 548 case ISA: 549 case EISA: 550 /* Active Hi */ 551 return (1); 552 case PCI: 553 /* Active Lo */ 554 return (0); 555 default: 556 panic("%s: unknown bus type %d", __func__, 557 busses[src_bus].bus_type); 558 } 559} 560 561/* 562 * Determine conforming trigger for a given bus type. 563 */ 564static u_char 565conforming_trigger(u_char src_bus, u_char src_bus_irq) 566{ 567 static int eisa_int_control = -1; 568 569 KASSERT(src_bus <= mptable_maxbusid, ("bus id %d too large", src_bus)); 570 switch (busses[src_bus].bus_type) { 571 case ISA: 572 /* Edge Triggered */ 573 return (1); 574 case PCI: 575 /* Level Triggered */ 576 return (0); 577 case EISA: 578 KASSERT(src_bus_irq < 16, ("Invalid EISA IRQ %d", src_bus_irq)); 579 if (eisa_int_control == -1) 580 eisa_int_control = inb(ELCR1) << 8 | inb(ELCR0); 581 if (eisa_int_control & (1 << src_bus_irq)) 582 /* Level Triggered */ 583 return (0); 584 else 585 /* Edge Triggered */ 586 return (1); 587 default: 588 panic("%s: unknown bus type %d", __func__, 589 busses[src_bus].bus_type); 590 } 591} 592 593static u_char 594intentry_polarity(int_entry_ptr intr) 595{ 596 597 switch (intr->int_flags & INTENTRY_FLAGS_POLARITY) { 598 case INTENTRY_FLAGS_POLARITY_CONFORM: 599 return (conforming_polarity(intr->src_bus_id)); 600 case INTENTRY_FLAGS_POLARITY_ACTIVEHI: 601 return (1); 602 case INTENTRY_FLAGS_POLARITY_ACTIVELO: 603 return (0); 604 default: 605 panic("Bogus interrupt flags"); 606 } 607} 608 609static u_char 610intentry_trigger(int_entry_ptr intr) 611{ 612 613 switch (intr->int_flags & INTENTRY_FLAGS_TRIGGER) { 614 case INTENTRY_FLAGS_TRIGGER_CONFORM: 615 return (conforming_trigger(intr->src_bus_id, 616 intr->src_bus_irq)); 617 case INTENTRY_FLAGS_TRIGGER_EDGE: 618 return (1); 619 case INTENTRY_FLAGS_TRIGGER_LEVEL: 620 return (0); 621 default: 622 panic("Bogus interrupt flags"); 623 } 624} 625 626/* 627 * Parse an interrupt entry for an I/O interrupt routed to a pin on an I/O APIC. 628 */ 629static void 630mptable_parse_io_int(int_entry_ptr intr) 631{ 632 void *ioapic; 633 u_int pin; 634 635 if (intr->dst_apic_id == 0xff) { 636 printf("MPTable: Ignoring global interrupt entry for pin %d\n", 637 intr->dst_apic_int); 638 return; 639 } 640 if (intr->dst_apic_id >= NAPICID) { 641 printf("MPTable: Ignoring interrupt entry for ioapic%d\n", 642 intr->dst_apic_id); 643 return; 644 } 645 ioapic = ioapics[intr->dst_apic_id]; 646 if (ioapic == NULL) { 647 printf( 648 "MPTable: Ignoring interrupt entry for missing ioapic%d\n", 649 intr->dst_apic_id); 650 return; 651 } 652 pin = intr->dst_apic_int; 653 switch (intr->int_type) { 654 case INTENTRY_TYPE_INT: 655 if (busses[intr->src_bus_id].bus_type == NOBUS) 656 panic("interrupt from missing bus"); 657 if (busses[intr->src_bus_id].bus_type == ISA && 658 intr->src_bus_irq != pin) { 659 ioapic_remap_vector(ioapic, pin, intr->src_bus_irq); 660 if (ioapic_get_vector(ioapic, intr->src_bus_irq) == 661 intr->src_bus_irq) 662 ioapic_disable_pin(ioapic, intr->src_bus_irq); 663 } 664 break; 665 case INTENTRY_TYPE_NMI: 666 ioapic_set_nmi(ioapic, pin); 667 break; 668 case INTENTRY_TYPE_SMI: 669 ioapic_set_smi(ioapic, pin); 670 break; 671 case INTENTRY_TYPE_EXTINT: 672 ioapic_set_extint(ioapic, pin); 673 break; 674 default: 675 panic("%s: invalid interrupt entry type %d\n", __func__, 676 intr->int_type); 677 } 678 if (intr->int_type == INTENTRY_TYPE_INT || 679 (intr->int_flags & INTENTRY_FLAGS_TRIGGER) != 680 INTENTRY_FLAGS_TRIGGER_CONFORM) 681 ioapic_set_triggermode(ioapic, pin, intentry_trigger(intr)); 682 if (intr->int_type == INTENTRY_TYPE_INT || 683 (intr->int_flags & INTENTRY_FLAGS_POLARITY) != 684 INTENTRY_FLAGS_POLARITY_CONFORM) 685 ioapic_set_polarity(ioapic, pin, intentry_polarity(intr)); 686} 687 688/* 689 * Parse an interrupt entry for a local APIC LVT pin. 690 */ 691static void 692mptable_parse_local_int(int_entry_ptr intr) 693{ 694 u_int apic_id, pin; 695 696 if (intr->dst_apic_id == 0xff) 697 apic_id = APIC_ID_ALL; 698 else 699 apic_id = intr->dst_apic_id; 700 if (intr->dst_apic_int == 0) 701 pin = LVT_LINT0; 702 else 703 pin = LVT_LINT1; 704 switch (intr->int_type) { 705 case INTENTRY_TYPE_INT: 706#if 1 707 printf( 708 "MPTable: Ignoring vectored local interrupt for LINTIN%d vector %d\n", 709 intr->dst_apic_int, intr->src_bus_irq); 710 return; 711#else 712 lapic_set_lvt_mode(apic_id, pin, APIC_LVT_DM_FIXED); 713 break; 714#endif 715 case INTENTRY_TYPE_NMI: 716 lapic_set_lvt_mode(apic_id, pin, APIC_LVT_DM_NMI); 717 break; 718 case INTENTRY_TYPE_SMI: 719 lapic_set_lvt_mode(apic_id, pin, APIC_LVT_DM_SMI); 720 break; 721 case INTENTRY_TYPE_EXTINT: 722 lapic_set_lvt_mode(apic_id, pin, APIC_LVT_DM_EXTINT); 723 break; 724 default: 725 panic("%s: invalid interrupt entry type %d\n", __func__, 726 intr->int_type); 727 } 728 if ((intr->int_flags & INTENTRY_FLAGS_TRIGGER) != 729 INTENTRY_FLAGS_TRIGGER_CONFORM) 730 lapic_set_lvt_triggermode(apic_id, pin, 731 intentry_trigger(intr)); 732 if ((intr->int_flags & INTENTRY_FLAGS_POLARITY) != 733 INTENTRY_FLAGS_POLARITY_CONFORM) 734 lapic_set_lvt_polarity(apic_id, pin, intentry_polarity(intr)); 735} 736 737/* 738 * Parse interrupt entries. 739 */ 740static void 741mptable_parse_ints_handler(u_char *entry, void *arg __unused) 742{ 743 int_entry_ptr intr; 744 745 intr = (int_entry_ptr)entry; 746 switch (*entry) { 747 case MPCT_ENTRY_INT: 748 mptable_parse_io_int(intr); 749 break; 750 case MPCT_ENTRY_LOCAL_INT: 751 mptable_parse_local_int(intr); 752 break; 753 } 754} 755 756/* 757 * Configure the interrupt pins 758 */ 759static void 760mptable_parse_ints(void) 761{ 762 763 /* Is this a pre-defined config? */ 764 if (mpfps->config_type != 0) { 765 /* Configure LINT pins. */ 766 lapic_set_lvt_mode(APIC_ID_ALL, LVT_LINT0, APIC_LVT_DM_EXTINT); 767 lapic_set_lvt_mode(APIC_ID_ALL, LVT_LINT1, APIC_LVT_DM_NMI); 768 769 /* Configure I/O APIC pins. */ 770 if (mpfps->config_type != 7) 771 ioapic_set_extint(ioapics[0], 0); 772 else 773 ioapic_disable_pin(ioapics[0], 0); 774 if (mpfps->config_type != 2) 775 ioapic_remap_vector(ioapics[0], 2, 0); 776 else 777 ioapic_disable_pin(ioapics[0], 2); 778 if (mpfps->config_type == 2) 779 ioapic_disable_pin(ioapics[0], 13); 780 } else 781 mptable_walk_table(mptable_parse_ints_handler, NULL); 782} 783 784/* 785 * Perform a hyperthreading "fix-up" to enumerate any logical CPU's 786 * that aren't already listed in the table. 787 * 788 * XXX: We assume that all of the physical CPUs in the 789 * system have the same number of logical CPUs. 790 * 791 * XXX: We assume that APIC ID's are allocated such that 792 * the APIC ID's for a physical processor are aligned 793 * with the number of logical CPU's in the processor. 794 */ 795static void 796mptable_hyperthread_fixup(u_int id_mask) 797{ 798 u_int i, id, logical_cpus; 799 800 /* Nothing to do if there is no HTT support. */ 801 if ((cpu_feature & CPUID_HTT) == 0) 802 return; 803 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 804 if (logical_cpus <= 1) 805 return; 806 807 /* 808 * For each APIC ID of a CPU that is set in the mask, 809 * scan the other candidate APIC ID's for this 810 * physical processor. If any of those ID's are 811 * already in the table, then kill the fixup. 812 */ 813 for (id = 0; id <= MAXCPU; id++) { 814 if ((id_mask & 1 << id) == 0) 815 continue; 816 /* First, make sure we are on a logical_cpus boundary. */ 817 if (id % logical_cpus != 0) 818 return; 819 for (i = id + 1; i < id + logical_cpus; i++) 820 if ((id_mask & 1 << i) != 0) 821 return; 822 } 823 824 /* 825 * Ok, the ID's checked out, so perform the fixup by 826 * adding the logical CPUs. 827 */ 828 while ((id = ffs(id_mask)) != 0) { 829 id--; 830 for (i = id + 1; i < id + logical_cpus; i++) { 831 if (bootverbose) 832 printf( 833 "MPTable: Adding logical CPU %d from main CPU %d\n", 834 i, id); 835 lapic_create(i, 0); 836 } 837 id_mask &= ~(1 << id); 838 } 839} 840 841/* 842 * Support code for routing PCI interrupts using the MP Table. 843 */ 844static void 845mptable_pci_setup(void) 846{ 847 int i; 848 849 /* 850 * Find the first pci bus and call it 0. Panic if pci0 is not 851 * bus zero and there are multiple PCI busses. 852 */ 853 for (i = 0; i <= mptable_maxbusid; i++) 854 if (busses[i].bus_type == PCI) { 855 if (pci0 == -1) 856 pci0 = i; 857 else if (pci0 != 0) 858 panic( 859 "MPTable contains multiple PCI busses but no PCI bus 0"); 860 } 861} 862 863static void 864mptable_pci_probe_table_handler(u_char *entry, void *arg) 865{ 866 struct pci_probe_table_args *args; 867 int_entry_ptr intr; 868 869 if (*entry != MPCT_ENTRY_INT) 870 return; 871 intr = (int_entry_ptr)entry; 872 args = (struct pci_probe_table_args *)arg; 873 KASSERT(args->bus <= mptable_maxbusid, 874 ("bus %d is too big", args->bus)); 875 KASSERT(busses[args->bus].bus_type == PCI, ("probing for non-PCI bus")); 876 if (intr->src_bus_id == args->bus) 877 args->found = 1; 878} 879 880int 881mptable_pci_probe_table(int bus) 882{ 883 struct pci_probe_table_args args; 884 885 if (bus < 0) 886 return (EINVAL); 887 if (pci0 == -1 || pci0 + bus > mptable_maxbusid) 888 return (ENXIO); 889 args.bus = pci0 + bus; 890 args.found = 0; 891 mptable_walk_table(mptable_pci_probe_table_handler, &args); 892 if (args.found == 0) 893 return (ENXIO); 894 return (0); 895} 896 897static void 898mptable_pci_route_interrupt_handler(u_char *entry, void *arg) 899{ 900 struct pci_route_interrupt_args *args; 901 int_entry_ptr intr; 902 int vector; 903 904 if (*entry != MPCT_ENTRY_INT) 905 return; 906 intr = (int_entry_ptr)entry; 907 args = (struct pci_route_interrupt_args *)arg; 908 if (intr->src_bus_id != args->bus || intr->src_bus_irq != args->irq) 909 return; 910 911 /* Make sure the APIC maps to a known APIC. */ 912 KASSERT(ioapics[intr->dst_apic_id] != NULL, 913 ("No I/O APIC %d to route interrupt to", intr->dst_apic_id)); 914 915 /* 916 * Look up the vector for this APIC / pin combination. If we 917 * have previously matched an entry for this PCI IRQ but it 918 * has the same vector as this entry, just return. Otherwise, 919 * we use the vector for this APIC / pin combination. 920 */ 921 vector = ioapic_get_vector(ioapics[intr->dst_apic_id], 922 intr->dst_apic_int); 923 if (args->vector == vector) 924 return; 925 KASSERT(args->vector == -1, 926 ("Multiple entries for PCI IRQ %d", args->vector)); 927 args->vector = vector; 928} 929 930int 931mptable_pci_route_interrupt(device_t pcib, device_t dev, int pin) 932{ 933 struct pci_route_interrupt_args args; 934 int slot; 935 936 /* Like ACPI, pin numbers are 0-3, not 1-4. */ 937 pin--; 938 KASSERT(pci0 != -1, ("do not know how to route PCI interrupts")); 939 args.bus = pci_get_bus(dev) + pci0; 940 slot = pci_get_slot(dev); 941 942 /* 943 * PCI interrupt entries in the MP Table encode both the slot and 944 * pin into the IRQ with the pin being the two least significant 945 * bits, the slot being the next five bits, and the most significant 946 * bit being reserved. 947 */ 948 args.irq = slot << 2 | pin; 949 args.vector = -1; 950 mptable_walk_table(mptable_pci_route_interrupt_handler, &args); 951 if (args.vector < 0) { 952 device_printf(pcib, "unable to route slot %d INT%c\n", slot, 953 'A' + pin); 954 return (PCI_INVALID_IRQ); 955 } 956 device_printf(pcib, "slot %d INT%c routed to irq %d\n", slot, 'A' + pin, 957 args.vector); 958 return (args.vector); 959} 960