mptable.c revision 119941
1/*- 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26#include <sys/cdefs.h> 27__FBSDID("$FreeBSD: head/sys/i386/i386/mptable.c 119941 2003-09-10 01:36:48Z jhb $"); 28 29#include "opt_cpu.h" 30#include "opt_kstack_pages.h" 31 32#ifdef SMP 33#include <machine/smptests.h> 34#else 35#if !defined(lint) 36#error 37#endif 38#endif 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/bus.h> 43#include <sys/cons.h> /* cngetc() */ 44#ifdef GPROF 45#include <sys/gmon.h> 46#endif 47#include <sys/kernel.h> 48#include <sys/ktr.h> 49#include <sys/lock.h> 50#include <sys/malloc.h> 51#include <sys/memrange.h> 52#include <sys/mutex.h> 53#include <sys/pcpu.h> 54#include <sys/proc.h> 55#include <sys/smp.h> 56#include <sys/sysctl.h> 57#include <sys/user.h> 58 59#include <vm/vm.h> 60#include <vm/vm_param.h> 61#include <vm/pmap.h> 62#include <vm/vm_kern.h> 63#include <vm/vm_extern.h> 64#include <vm/vm_map.h> 65 66#include <machine/apic.h> 67#include <machine/atomic.h> 68#include <machine/clock.h> 69#include <machine/cpu.h> 70#include <machine/cpufunc.h> 71#include <machine/mpapic.h> 72#include <machine/psl.h> 73#include <machine/segments.h> 74#include <machine/smp.h> 75#include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */ 76#include <machine/tss.h> 77#include <machine/specialreg.h> 78#include <machine/privatespace.h> 79 80#if defined(APIC_IO) 81#include <machine/md_var.h> /* setidt() */ 82#include <i386/isa/icu.h> /* IPIs */ 83#include <i386/isa/intr_machdep.h> /* IPIs */ 84#endif /* APIC_IO */ 85 86#if defined(TEST_DEFAULT_CONFIG) 87#define MPFPS_MPFB1 TEST_DEFAULT_CONFIG 88#else 89#define MPFPS_MPFB1 mpfps->mpfb1 90#endif /* TEST_DEFAULT_CONFIG */ 91 92#define WARMBOOT_TARGET 0 93#define WARMBOOT_OFF (KERNBASE + 0x0467) 94#define WARMBOOT_SEG (KERNBASE + 0x0469) 95 96#ifdef PC98 97#define BIOS_BASE (0xe8000) 98#define BIOS_SIZE (0x18000) 99#else 100#define BIOS_BASE (0xf0000) 101#define BIOS_SIZE (0x10000) 102#endif 103#define BIOS_COUNT (BIOS_SIZE/4) 104 105#define CMOS_REG (0x70) 106#define CMOS_DATA (0x71) 107#define BIOS_RESET (0x0f) 108#define BIOS_WARM (0x0a) 109 110#define PROCENTRY_FLAG_EN 0x01 111#define PROCENTRY_FLAG_BP 0x02 112#define IOAPICENTRY_FLAG_EN 0x01 113 114 115/* MP Floating Pointer Structure */ 116typedef struct MPFPS { 117 char signature[4]; 118 void *pap; 119 u_char length; 120 u_char spec_rev; 121 u_char checksum; 122 u_char mpfb1; 123 u_char mpfb2; 124 u_char mpfb3; 125 u_char mpfb4; 126 u_char mpfb5; 127} *mpfps_t; 128 129/* MP Configuration Table Header */ 130typedef struct MPCTH { 131 char signature[4]; 132 u_short base_table_length; 133 u_char spec_rev; 134 u_char checksum; 135 u_char oem_id[8]; 136 u_char product_id[12]; 137 void *oem_table_pointer; 138 u_short oem_table_size; 139 u_short entry_count; 140 void *apic_address; 141 u_short extended_table_length; 142 u_char extended_table_checksum; 143 u_char reserved; 144} *mpcth_t; 145 146 147typedef struct PROCENTRY { 148 u_char type; 149 u_char apic_id; 150 u_char apic_version; 151 u_char cpu_flags; 152 u_long cpu_signature; 153 u_long feature_flags; 154 u_long reserved1; 155 u_long reserved2; 156} *proc_entry_ptr; 157 158typedef struct BUSENTRY { 159 u_char type; 160 u_char bus_id; 161 char bus_type[6]; 162} *bus_entry_ptr; 163 164typedef struct IOAPICENTRY { 165 u_char type; 166 u_char apic_id; 167 u_char apic_version; 168 u_char apic_flags; 169 void *apic_address; 170} *io_apic_entry_ptr; 171 172typedef struct INTENTRY { 173 u_char type; 174 u_char int_type; 175 u_short int_flags; 176 u_char src_bus_id; 177 u_char src_bus_irq; 178 u_char dst_apic_id; 179 u_char dst_apic_int; 180} *int_entry_ptr; 181 182/* descriptions of MP basetable entries */ 183typedef struct BASETABLE_ENTRY { 184 u_char type; 185 u_char length; 186 char name[16]; 187} basetable_entry; 188 189/* 190 * this code MUST be enabled here and in mpboot.s. 191 * it follows the very early stages of AP boot by placing values in CMOS ram. 192 * it NORMALLY will never be needed and thus the primitive method for enabling. 193 * 194#define CHECK_POINTS 195 */ 196 197#if defined(CHECK_POINTS) && !defined(PC98) 198#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 199#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 200 201#define CHECK_INIT(D); \ 202 CHECK_WRITE(0x34, (D)); \ 203 CHECK_WRITE(0x35, (D)); \ 204 CHECK_WRITE(0x36, (D)); \ 205 CHECK_WRITE(0x37, (D)); \ 206 CHECK_WRITE(0x38, (D)); \ 207 CHECK_WRITE(0x39, (D)); 208 209#define CHECK_PRINT(S); \ 210 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 211 (S), \ 212 CHECK_READ(0x34), \ 213 CHECK_READ(0x35), \ 214 CHECK_READ(0x36), \ 215 CHECK_READ(0x37), \ 216 CHECK_READ(0x38), \ 217 CHECK_READ(0x39)); 218 219#else /* CHECK_POINTS */ 220 221#define CHECK_INIT(D) 222#define CHECK_PRINT(S) 223 224#endif /* CHECK_POINTS */ 225 226/* 227 * Values to send to the POST hardware. 228 */ 229#define MP_BOOTADDRESS_POST 0x10 230#define MP_PROBE_POST 0x11 231#define MPTABLE_PASS1_POST 0x12 232 233#define MP_START_POST 0x13 234#define MP_ENABLE_POST 0x14 235#define MPTABLE_PASS2_POST 0x15 236 237#define START_ALL_APS_POST 0x16 238#define INSTALL_AP_TRAMP_POST 0x17 239#define START_AP_POST 0x18 240 241#define MP_ANNOUNCE_POST 0x19 242 243static int need_hyperthreading_fixup; 244static u_int logical_cpus; 245static u_int logical_cpus_mask; 246 247/* used to hold the AP's until we are ready to release them */ 248static struct mtx ap_boot_mtx; 249 250/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ 251int current_postcode; 252 253/** XXX FIXME: what system files declare these??? */ 254extern struct region_descriptor r_gdt, r_idt; 255 256int bsp_apic_ready = 0; /* flags useability of BSP apic */ 257int mp_naps; /* # of Applications processors */ 258int mp_nbusses; /* # of busses */ 259int mp_napics; /* # of IO APICs */ 260int boot_cpu_id; /* designated BSP */ 261vm_offset_t cpu_apic_address; 262vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */ 263extern int nkpt; 264 265u_int32_t cpu_apic_versions[MAXCPU]; 266u_int32_t *io_apic_versions; 267 268#ifdef APIC_INTR_REORDER 269struct { 270 volatile int *location; 271 int bit; 272} apic_isrbit_location[32]; 273#endif 274 275struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE]; 276 277/* 278 * APIC ID logical/physical mapping structures. 279 * We oversize these to simplify boot-time config. 280 */ 281int cpu_num_to_apic_id[NAPICID]; 282int io_num_to_apic_id[NAPICID]; 283int apic_id_to_logical[NAPICID]; 284 285/* 286 * CPU topology map datastructures for HTT. 287 */ 288struct cpu_group mp_groups[NAPICID]; 289struct cpu_top mp_top; 290struct cpu_top *smp_topology; 291 292 293/* AP uses this during bootstrap. Do not staticize. */ 294char *bootSTK; 295static int bootAP; 296 297/* Hotwire a 0->4MB V==P mapping */ 298extern pt_entry_t *KPTphys; 299 300/* SMP page table page */ 301extern pt_entry_t *SMPpt; 302 303struct pcb stoppcbs[MAXCPU]; 304 305#ifdef APIC_IO 306/* Variables needed for SMP tlb shootdown. */ 307vm_offset_t smp_tlb_addr1; 308vm_offset_t smp_tlb_addr2; 309volatile int smp_tlb_wait; 310static struct mtx smp_tlb_mtx; 311#endif 312 313/* 314 * Local data and functions. 315 */ 316 317/* Set to 1 once we're ready to let the APs out of the pen. */ 318static volatile int aps_ready = 0; 319 320static int mp_capable; 321static u_int boot_address; 322static u_int base_memory; 323 324static int picmode; /* 0: virtual wire mode, 1: PIC mode */ 325static mpfps_t mpfps; 326static int search_for_sig(u_int32_t target, int count); 327static void mp_enable(u_int boot_addr); 328 329static void mptable_hyperthread_fixup(u_int id_mask); 330static void mptable_pass1(void); 331static int mptable_pass2(void); 332static void default_mp_table(int type); 333static void fix_mp_table(void); 334static void setup_apic_irq_mapping(void); 335static void init_locks(void); 336static int start_all_aps(u_int boot_addr); 337static void install_ap_tramp(u_int boot_addr); 338static int start_ap(int logicalCpu, u_int boot_addr); 339void ap_init(void); 340static int apic_int_is_bus_type(int intr, int bus_type); 341static void release_aps(void *dummy); 342 343static int hlt_cpus_mask; 344static int hlt_logical_cpus = 1; 345static struct sysctl_ctx_list logical_cpu_clist; 346 347/* 348 * initialize all the SMP locks 349 */ 350 351/* lock region used by kernel profiling */ 352int mcount_lock; 353 354#ifdef USE_COMLOCK 355/* locks com (tty) data/hardware accesses: a FASTINTR() */ 356struct mtx com_mtx; 357#endif /* USE_COMLOCK */ 358 359static void 360init_locks(void) 361{ 362 363#ifdef USE_COMLOCK 364 mtx_init(&com_mtx, "com", NULL, MTX_SPIN); 365#endif /* USE_COMLOCK */ 366#ifdef APIC_IO 367 mtx_init(&smp_tlb_mtx, "tlb", NULL, MTX_SPIN); 368#endif 369} 370 371/* 372 * Calculate usable address in base memory for AP trampoline code. 373 */ 374u_int 375mp_bootaddress(u_int basemem) 376{ 377 POSTCODE(MP_BOOTADDRESS_POST); 378 379 base_memory = basemem * 1024; /* convert to bytes */ 380 381 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ 382 if ((base_memory - boot_address) < bootMP_size) 383 boot_address -= 4096; /* not enough, lower by 4k */ 384 385 return boot_address; 386} 387 388 389/* 390 * Look for an Intel MP spec table (ie, SMP capable hardware). 391 */ 392void 393i386_mp_probe(void) 394{ 395 int x; 396 u_long segment; 397 u_int32_t target; 398 399 POSTCODE(MP_PROBE_POST); 400 401 /* see if EBDA exists */ 402 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) { 403 /* search first 1K of EBDA */ 404 target = (u_int32_t) (segment << 4); 405 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 406 goto found; 407 } else { 408 /* last 1K of base memory, effective 'top of base' passed in */ 409 target = (u_int32_t) (base_memory - 0x400); 410 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 411 goto found; 412 } 413 414 /* search the BIOS */ 415 target = (u_int32_t) BIOS_BASE; 416 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) 417 goto found; 418 419 /* nothing found */ 420 mpfps = (mpfps_t)0; 421 mp_capable = 0; 422 return; 423 424found: 425 /* calculate needed resources */ 426 mpfps = (mpfps_t)x; 427 mptable_pass1(); 428 429 /* flag fact that we are running multiple processors */ 430 mp_capable = 1; 431} 432 433int 434cpu_mp_probe(void) 435{ 436 /* 437 * Record BSP in CPU map 438 * This is done here so that MBUF init code works correctly. 439 */ 440 all_cpus = 1; 441 442 return (mp_capable); 443} 444 445/* 446 * Initialize the SMP hardware and the APIC and start up the AP's. 447 */ 448void 449cpu_mp_start(void) 450{ 451 POSTCODE(MP_START_POST); 452 453 /* look for MP capable motherboard */ 454 if (mp_capable) 455 mp_enable(boot_address); 456 else 457 panic("MP hardware not found!"); 458 459 cpu_setregs(); 460} 461 462 463/* 464 * Print various information about the SMP system hardware and setup. 465 */ 466void 467cpu_mp_announce(void) 468{ 469 int x; 470 471 POSTCODE(MP_ANNOUNCE_POST); 472 473 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0)); 474 printf(", version: 0x%08x", cpu_apic_versions[0]); 475 printf(", at 0x%08x\n", cpu_apic_address); 476 for (x = 1; x <= mp_naps; ++x) { 477 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x)); 478 printf(", version: 0x%08x", cpu_apic_versions[x]); 479 printf(", at 0x%08x\n", cpu_apic_address); 480 } 481 482#if defined(APIC_IO) 483 for (x = 0; x < mp_napics; ++x) { 484 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x)); 485 printf(", version: 0x%08x", io_apic_versions[x]); 486 printf(", at 0x%08x\n", io_apic_address[x]); 487 } 488#else 489 printf(" Warning: APIC I/O disabled\n"); 490#endif /* APIC_IO */ 491} 492 493/* 494 * AP cpu's call this to sync up protected mode. 495 */ 496void 497init_secondary(void) 498{ 499 int gsel_tss; 500 int x, myid = bootAP; 501 u_int cr0; 502 503 gdt_segs[GPRIV_SEL].ssd_base = (int) &SMP_prvspace[myid]; 504 gdt_segs[GPROC0_SEL].ssd_base = 505 (int) &SMP_prvspace[myid].pcpu.pc_common_tss; 506 SMP_prvspace[myid].pcpu.pc_prvspace = 507 &SMP_prvspace[myid].pcpu; 508 509 for (x = 0; x < NGDT; x++) { 510 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd); 511 } 512 513 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 514 r_gdt.rd_base = (int) &gdt[myid * NGDT]; 515 lgdt(&r_gdt); /* does magic intra-segment return */ 516 517 lidt(&r_idt); 518 519 lldt(_default_ldt); 520 PCPU_SET(currentldt, _default_ldt); 521 522 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 523 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS; 524 PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */ 525 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL)); 526 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16); 527 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd); 528 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt)); 529 ltr(gsel_tss); 530 531 /* 532 * Set to a known state: 533 * Set by mpboot.s: CR0_PG, CR0_PE 534 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM 535 */ 536 cr0 = rcr0(); 537 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM); 538 load_cr0(cr0); 539 540 pmap_set_opt(); 541} 542 543 544#if defined(APIC_IO) 545/* 546 * Final configuration of the BSP's local APIC: 547 * - disable 'pic mode'. 548 * - disable 'virtual wire mode'. 549 * - enable NMI. 550 */ 551void 552bsp_apic_configure(void) 553{ 554 u_char byte; 555 u_int32_t temp; 556 557 /* leave 'pic mode' if necessary */ 558 if (picmode) { 559 outb(0x22, 0x70); /* select IMCR */ 560 byte = inb(0x23); /* current contents */ 561 byte |= 0x01; /* mask external INTR */ 562 outb(0x23, byte); /* disconnect 8259s/NMI */ 563 } 564 565 /* mask lint0 (the 8259 'virtual wire' connection) */ 566 temp = lapic.lvt_lint0; 567 temp |= APIC_LVT_M; /* set the mask */ 568 lapic.lvt_lint0 = temp; 569 570 /* setup lint1 to handle NMI */ 571 temp = lapic.lvt_lint1; 572 temp &= ~APIC_LVT_M; /* clear the mask */ 573 lapic.lvt_lint1 = temp; 574 575 if (bootverbose) 576 apic_dump("bsp_apic_configure()"); 577} 578#endif /* APIC_IO */ 579 580 581/******************************************************************* 582 * local functions and data 583 */ 584 585/* 586 * start the SMP system 587 */ 588static void 589mp_enable(u_int boot_addr) 590{ 591 int x; 592#if defined(APIC_IO) 593 int apic; 594 u_int ux; 595#endif /* APIC_IO */ 596 597 POSTCODE(MP_ENABLE_POST); 598 599 /* turn on 4MB of V == P addressing so we can get to MP table */ 600 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME); 601 invltlb(); 602 603 /* examine the MP table for needed info, uses physical addresses */ 604 x = mptable_pass2(); 605 606 *(int *)PTD = 0; 607 invltlb(); 608 609 /* can't process default configs till the CPU APIC is pmapped */ 610 if (x) 611 default_mp_table(x); 612 613 /* post scan cleanup */ 614 fix_mp_table(); 615 setup_apic_irq_mapping(); 616 617#if defined(APIC_IO) 618 619 /* fill the LOGICAL io_apic_versions table */ 620 for (apic = 0; apic < mp_napics; ++apic) { 621 ux = io_apic_read(apic, IOAPIC_VER); 622 io_apic_versions[apic] = ux; 623 io_apic_set_id(apic, IO_TO_ID(apic)); 624 } 625 626 /* program each IO APIC in the system */ 627 for (apic = 0; apic < mp_napics; ++apic) 628 if (io_apic_setup(apic) < 0) 629 panic("IO APIC setup failure"); 630 631 /* install a 'Spurious INTerrupt' vector */ 632 setidt(XSPURIOUSINT_OFFSET, Xspuriousint, 633 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 634 635 /* install an inter-CPU IPI for TLB invalidation */ 636 setidt(XINVLTLB_OFFSET, Xinvltlb, 637 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 638 setidt(XINVLPG_OFFSET, Xinvlpg, 639 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 640 setidt(XINVLRNG_OFFSET, Xinvlrng, 641 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 642 643 /* install an inter-CPU IPI for forwarding hardclock() */ 644 setidt(XHARDCLOCK_OFFSET, Xhardclock, 645 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 646 647 /* install an inter-CPU IPI for forwarding statclock() */ 648 setidt(XSTATCLOCK_OFFSET, Xstatclock, 649 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 650 651 /* install an inter-CPU IPI for lazy pmap release */ 652 setidt(XLAZYPMAP_OFFSET, Xlazypmap, 653 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 654 655 /* install an inter-CPU IPI for all-CPU rendezvous */ 656 setidt(XRENDEZVOUS_OFFSET, Xrendezvous, 657 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 658 659 /* install an inter-CPU IPI for forcing an additional software trap */ 660 setidt(XCPUAST_OFFSET, Xcpuast, 661 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 662 663 /* install an inter-CPU IPI for CPU stop/restart */ 664 setidt(XCPUSTOP_OFFSET, Xcpustop, 665 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 666 667#if defined(TEST_TEST1) 668 /* install a "fake hardware INTerrupt" vector */ 669 setidt(XTEST1_OFFSET, Xtest1, 670 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 671#endif /** TEST_TEST1 */ 672 673#endif /* APIC_IO */ 674 675 /* initialize all SMP locks */ 676 init_locks(); 677 678 /* start each Application Processor */ 679 start_all_aps(boot_addr); 680} 681 682 683/* 684 * look for the MP spec signature 685 */ 686 687/* string defined by the Intel MP Spec as identifying the MP table */ 688#define MP_SIG 0x5f504d5f /* _MP_ */ 689#define NEXT(X) ((X) += 4) 690static int 691search_for_sig(u_int32_t target, int count) 692{ 693 int x; 694 u_int32_t *addr = (u_int32_t *) (KERNBASE + target); 695 696 for (x = 0; x < count; NEXT(x)) 697 if (addr[x] == MP_SIG) 698 /* make array index a byte index */ 699 return (target + (x * sizeof(u_int32_t))); 700 701 return -1; 702} 703 704 705static basetable_entry basetable_entry_types[] = 706{ 707 {0, 20, "Processor"}, 708 {1, 8, "Bus"}, 709 {2, 8, "I/O APIC"}, 710 {3, 8, "I/O INT"}, 711 {4, 8, "Local INT"} 712}; 713 714typedef struct BUSDATA { 715 u_char bus_id; 716 enum busTypes bus_type; 717} bus_datum; 718 719typedef struct INTDATA { 720 u_char int_type; 721 u_short int_flags; 722 u_char src_bus_id; 723 u_char src_bus_irq; 724 u_char dst_apic_id; 725 u_char dst_apic_int; 726 u_char int_vector; 727} io_int, local_int; 728 729typedef struct BUSTYPENAME { 730 u_char type; 731 char name[7]; 732} bus_type_name; 733 734static bus_type_name bus_type_table[] = 735{ 736 {CBUS, "CBUS"}, 737 {CBUSII, "CBUSII"}, 738 {EISA, "EISA"}, 739 {MCA, "MCA"}, 740 {UNKNOWN_BUSTYPE, "---"}, 741 {ISA, "ISA"}, 742 {MCA, "MCA"}, 743 {UNKNOWN_BUSTYPE, "---"}, 744 {UNKNOWN_BUSTYPE, "---"}, 745 {UNKNOWN_BUSTYPE, "---"}, 746 {UNKNOWN_BUSTYPE, "---"}, 747 {UNKNOWN_BUSTYPE, "---"}, 748 {PCI, "PCI"}, 749 {UNKNOWN_BUSTYPE, "---"}, 750 {UNKNOWN_BUSTYPE, "---"}, 751 {UNKNOWN_BUSTYPE, "---"}, 752 {UNKNOWN_BUSTYPE, "---"}, 753 {XPRESS, "XPRESS"}, 754 {UNKNOWN_BUSTYPE, "---"} 755}; 756/* from MP spec v1.4, table 5-1 */ 757static int default_data[7][5] = 758{ 759/* nbus, id0, type0, id1, type1 */ 760 {1, 0, ISA, 255, 255}, 761 {1, 0, EISA, 255, 255}, 762 {1, 0, EISA, 255, 255}, 763 {1, 0, MCA, 255, 255}, 764 {2, 0, ISA, 1, PCI}, 765 {2, 0, EISA, 1, PCI}, 766 {2, 0, MCA, 1, PCI} 767}; 768 769 770/* the bus data */ 771static bus_datum *bus_data; 772 773/* the IO INT data, one entry per possible APIC INTerrupt */ 774static io_int *io_apic_ints; 775 776static int nintrs; 777 778static int processor_entry(proc_entry_ptr entry, int cpu); 779static int bus_entry(bus_entry_ptr entry, int bus); 780static int io_apic_entry(io_apic_entry_ptr entry, int apic); 781static int int_entry(int_entry_ptr entry, int intr); 782static int lookup_bus_type(char *name); 783 784 785/* 786 * 1st pass on motherboard's Intel MP specification table. 787 * 788 * initializes: 789 * mp_ncpus = 1 790 * 791 * determines: 792 * cpu_apic_address (common to all CPUs) 793 * io_apic_address[N] 794 * mp_naps 795 * mp_nbusses 796 * mp_napics 797 * nintrs 798 */ 799static void 800mptable_pass1(void) 801{ 802 int x; 803 mpcth_t cth; 804 int totalSize; 805 void* position; 806 int count; 807 int type; 808 u_int id_mask; 809 810 POSTCODE(MPTABLE_PASS1_POST); 811 812 /* clear various tables */ 813 for (x = 0; x < NAPICID; ++x) { 814 io_apic_address[x] = ~0; /* IO APIC address table */ 815 } 816 817 /* init everything to empty */ 818 mp_naps = 0; 819 mp_nbusses = 0; 820 mp_napics = 0; 821 nintrs = 0; 822 id_mask = 0; 823 824 /* check for use of 'default' configuration */ 825 if (MPFPS_MPFB1 != 0) { 826 /* use default addresses */ 827 cpu_apic_address = DEFAULT_APIC_BASE; 828 io_apic_address[0] = DEFAULT_IO_APIC_BASE; 829 830 /* fill in with defaults */ 831 mp_naps = 2; /* includes BSP */ 832 mp_maxid = 1; 833 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0]; 834#if defined(APIC_IO) 835 mp_napics = 1; 836 nintrs = 16; 837#endif /* APIC_IO */ 838 } 839 else { 840 if ((cth = mpfps->pap) == 0) 841 panic("MP Configuration Table Header MISSING!"); 842 843 cpu_apic_address = (vm_offset_t) cth->apic_address; 844 845 /* walk the table, recording info of interest */ 846 totalSize = cth->base_table_length - sizeof(struct MPCTH); 847 position = (u_char *) cth + sizeof(struct MPCTH); 848 count = cth->entry_count; 849 850 while (count--) { 851 switch (type = *(u_char *) position) { 852 case 0: /* processor_entry */ 853 if (((proc_entry_ptr)position)->cpu_flags 854 & PROCENTRY_FLAG_EN) { 855 ++mp_naps; 856 mp_maxid++; 857 id_mask |= 1 << 858 ((proc_entry_ptr)position)->apic_id; 859 } 860 break; 861 case 1: /* bus_entry */ 862 ++mp_nbusses; 863 break; 864 case 2: /* io_apic_entry */ 865 if (((io_apic_entry_ptr)position)->apic_flags 866 & IOAPICENTRY_FLAG_EN) 867 io_apic_address[mp_napics++] = 868 (vm_offset_t)((io_apic_entry_ptr) 869 position)->apic_address; 870 break; 871 case 3: /* int_entry */ 872 ++nintrs; 873 break; 874 case 4: /* int_entry */ 875 break; 876 default: 877 panic("mpfps Base Table HOSED!"); 878 /* NOTREACHED */ 879 } 880 881 totalSize -= basetable_entry_types[type].length; 882 (u_char*)position += basetable_entry_types[type].length; 883 } 884 } 885 886 /* qualify the numbers */ 887 if (mp_naps > MAXCPU) { 888 printf("Warning: only using %d of %d available CPUs!\n", 889 MAXCPU, mp_naps); 890 mp_naps = MAXCPU; 891 } 892 893 /* See if we need to fixup HT logical CPUs. */ 894 mptable_hyperthread_fixup(id_mask); 895 896 /* 897 * Count the BSP. 898 * This is also used as a counter while starting the APs. 899 */ 900 mp_ncpus = 1; 901 902 --mp_naps; /* subtract the BSP */ 903} 904 905 906/* 907 * 2nd pass on motherboard's Intel MP specification table. 908 * 909 * sets: 910 * boot_cpu_id 911 * ID_TO_IO(N), phy APIC ID to log CPU/IO table 912 * CPU_TO_ID(N), logical CPU to APIC ID table 913 * IO_TO_ID(N), logical IO to APIC ID table 914 * bus_data[N] 915 * io_apic_ints[N] 916 */ 917static int 918mptable_pass2(void) 919{ 920 struct PROCENTRY proc; 921 int x; 922 mpcth_t cth; 923 int totalSize; 924 void* position; 925 int count; 926 int type; 927 int apic, bus, cpu, intr; 928 int i, j; 929 int pgeflag; 930 931 POSTCODE(MPTABLE_PASS2_POST); 932 933 /* Initialize fake proc entry for use with HT fixup. */ 934 bzero(&proc, sizeof(proc)); 935 proc.type = 0; 936 proc.cpu_flags = PROCENTRY_FLAG_EN; 937 938 pgeflag = 0; /* XXX - Not used under SMP yet. */ 939 940 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics, 941 M_DEVBUF, M_WAITOK); 942 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics, 943 M_DEVBUF, M_WAITOK); 944 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + 1), 945 M_DEVBUF, M_WAITOK); 946 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses, 947 M_DEVBUF, M_WAITOK); 948 949 bzero(ioapic, sizeof(ioapic_t *) * mp_napics); 950 951 for (i = 0; i < mp_napics; i++) { 952 for (j = 0; j < mp_napics; j++) { 953 /* same page frame as a previous IO apic? */ 954 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) == 955 (io_apic_address[i] & PG_FRAME)) { 956 ioapic[i] = (ioapic_t *)((u_int)SMP_prvspace 957 + (NPTEPG-2-j) * PAGE_SIZE 958 + (io_apic_address[i] & PAGE_MASK)); 959 break; 960 } 961 /* use this slot if available */ 962 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) == 0) { 963 SMPpt[NPTEPG-2-j] = (pt_entry_t)(PG_V | PG_RW | 964 pgeflag | (io_apic_address[i] & PG_FRAME)); 965 ioapic[i] = (ioapic_t *)((u_int)SMP_prvspace 966 + (NPTEPG-2-j) * PAGE_SIZE 967 + (io_apic_address[i] & PAGE_MASK)); 968 break; 969 } 970 } 971 } 972 973 /* clear various tables */ 974 for (x = 0; x < NAPICID; ++x) { 975 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */ 976 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */ 977 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */ 978 } 979 980 /* clear bus data table */ 981 for (x = 0; x < mp_nbusses; ++x) 982 bus_data[x].bus_id = 0xff; 983 984 /* clear IO APIC INT table */ 985 for (x = 0; x < (nintrs + 1); ++x) { 986 io_apic_ints[x].int_type = 0xff; 987 io_apic_ints[x].int_vector = 0xff; 988 } 989 990 /* setup the cpu/apic mapping arrays */ 991 boot_cpu_id = -1; 992 993 /* record whether PIC or virtual-wire mode */ 994 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0; 995 996 /* check for use of 'default' configuration */ 997 if (MPFPS_MPFB1 != 0) 998 return MPFPS_MPFB1; /* return default configuration type */ 999 1000 if ((cth = mpfps->pap) == 0) 1001 panic("MP Configuration Table Header MISSING!"); 1002 1003 /* walk the table, recording info of interest */ 1004 totalSize = cth->base_table_length - sizeof(struct MPCTH); 1005 position = (u_char *) cth + sizeof(struct MPCTH); 1006 count = cth->entry_count; 1007 apic = bus = intr = 0; 1008 cpu = 1; /* pre-count the BSP */ 1009 1010 while (count--) { 1011 switch (type = *(u_char *) position) { 1012 case 0: 1013 if (processor_entry(position, cpu)) { 1014 if (logical_cpus != 0 && 1015 cpu % logical_cpus != 0) 1016 logical_cpus_mask |= (1 << cpu); 1017 ++cpu; 1018 } 1019 if (need_hyperthreading_fixup) { 1020 /* 1021 * Create fake mptable processor entries 1022 * and feed them to processor_entry() to 1023 * enumerate the logical CPUs. 1024 */ 1025 proc.apic_id = ((proc_entry_ptr)position)->apic_id; 1026 for (i = 1; i < logical_cpus; i++) { 1027 proc.apic_id++; 1028 (void)processor_entry(&proc, cpu); 1029 logical_cpus_mask |= (1 << cpu); 1030 cpu++; 1031 } 1032 } 1033 break; 1034 case 1: 1035 if (bus_entry(position, bus)) 1036 ++bus; 1037 break; 1038 case 2: 1039 if (io_apic_entry(position, apic)) 1040 ++apic; 1041 break; 1042 case 3: 1043 if (int_entry(position, intr)) 1044 ++intr; 1045 break; 1046 case 4: 1047 /* int_entry(position); */ 1048 break; 1049 default: 1050 panic("mpfps Base Table HOSED!"); 1051 /* NOTREACHED */ 1052 } 1053 1054 totalSize -= basetable_entry_types[type].length; 1055 (u_char *) position += basetable_entry_types[type].length; 1056 } 1057 1058 if (boot_cpu_id == -1) 1059 panic("NO BSP found!"); 1060 1061 /* report fact that its NOT a default configuration */ 1062 return 0; 1063} 1064 1065/* 1066 * Check if we should perform a hyperthreading "fix-up" to 1067 * enumerate any logical CPU's that aren't already listed 1068 * in the table. 1069 * 1070 * XXX: We assume that all of the physical CPUs in the 1071 * system have the same number of logical CPUs. 1072 * 1073 * XXX: We assume that APIC ID's are allocated such that 1074 * the APIC ID's for a physical processor are aligned 1075 * with the number of logical CPU's in the processor. 1076 */ 1077static void 1078mptable_hyperthread_fixup(u_int id_mask) 1079{ 1080 u_int i, id; 1081 int logical; 1082 1083 /* Nothing to do if there is no HTT support. */ 1084 if ((cpu_feature & CPUID_HTT) == 0) 1085 return; 1086 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 1087 if (logical_cpus <= 1) 1088 return; 1089 1090 /* 1091 * For each APIC ID of a CPU that is set in the mask, 1092 * scan the other candidate APIC ID's for this 1093 * physical processor. If any of those ID's are 1094 * already in the table, then kill the fixup. 1095 */ 1096 for (id = 0; id <= MAXCPU; id++) { 1097 if ((id_mask & 1 << id) == 0) 1098 continue; 1099 /* First, make sure we are on a logical_cpus boundary. */ 1100 if (id % logical_cpus != 0) 1101 return; 1102 for (i = id + 1; i < id + logical_cpus; i++) 1103 if ((id_mask & 1 << i) != 0) 1104 return; 1105 } 1106 1107 /* 1108 * Ok, the ID's checked out, so enable the fixup. We have to fixup 1109 * mp_naps and mp_maxid right now. 1110 */ 1111 need_hyperthreading_fixup = 1; 1112 mp_maxid *= logical_cpus; 1113 mp_naps *= logical_cpus; 1114 1115 /* 1116 * Now setup the cpu topology map. 1117 */ 1118 mp_top.ct_count = mp_naps / logical_cpus; 1119 mp_top.ct_group = mp_groups; 1120 1121 /* 1122 * The first logical id is directly after the last valid physical id. 1123 */ 1124 logical = mp_top.ct_count + 1; 1125 1126 for (i = 0; i < mp_top.ct_count; i++) { 1127 int j; 1128 1129 mp_groups[i].cg_mask = (1 << i); 1130 for (j = 1; j < logical_cpus; j++) 1131 mp_groups[i].cg_mask |= (1 << logical++); 1132 mp_groups[i].cg_count = logical_cpus; 1133 mp_groups[i].cg_children = 0; 1134 } 1135 1136 smp_topology = &mp_top; 1137} 1138 1139void 1140assign_apic_irq(int apic, int intpin, int irq) 1141{ 1142 int x; 1143 1144 if (int_to_apicintpin[irq].ioapic != -1) 1145 panic("assign_apic_irq: inconsistent table"); 1146 1147 int_to_apicintpin[irq].ioapic = apic; 1148 int_to_apicintpin[irq].int_pin = intpin; 1149 int_to_apicintpin[irq].apic_address = ioapic[apic]; 1150 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin; 1151 1152 for (x = 0; x < nintrs; x++) { 1153 if ((io_apic_ints[x].int_type == 0 || 1154 io_apic_ints[x].int_type == 3) && 1155 io_apic_ints[x].int_vector == 0xff && 1156 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) && 1157 io_apic_ints[x].dst_apic_int == intpin) 1158 io_apic_ints[x].int_vector = irq; 1159 } 1160} 1161 1162void 1163revoke_apic_irq(int irq) 1164{ 1165 int x; 1166 int oldapic; 1167 int oldintpin; 1168 1169 if (int_to_apicintpin[irq].ioapic == -1) 1170 panic("revoke_apic_irq: inconsistent table"); 1171 1172 oldapic = int_to_apicintpin[irq].ioapic; 1173 oldintpin = int_to_apicintpin[irq].int_pin; 1174 1175 int_to_apicintpin[irq].ioapic = -1; 1176 int_to_apicintpin[irq].int_pin = 0; 1177 int_to_apicintpin[irq].apic_address = NULL; 1178 int_to_apicintpin[irq].redirindex = 0; 1179 1180 for (x = 0; x < nintrs; x++) { 1181 if ((io_apic_ints[x].int_type == 0 || 1182 io_apic_ints[x].int_type == 3) && 1183 io_apic_ints[x].int_vector != 0xff && 1184 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) && 1185 io_apic_ints[x].dst_apic_int == oldintpin) 1186 io_apic_ints[x].int_vector = 0xff; 1187 } 1188} 1189 1190 1191static void 1192allocate_apic_irq(int intr) 1193{ 1194 int apic; 1195 int intpin; 1196 int irq; 1197 1198 if (io_apic_ints[intr].int_vector != 0xff) 1199 return; /* Interrupt handler already assigned */ 1200 1201 if (io_apic_ints[intr].int_type != 0 && 1202 (io_apic_ints[intr].int_type != 3 || 1203 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) && 1204 io_apic_ints[intr].dst_apic_int == 0))) 1205 return; /* Not INT or ExtInt on != (0, 0) */ 1206 1207 irq = 0; 1208 while (irq < APIC_INTMAPSIZE && 1209 int_to_apicintpin[irq].ioapic != -1) 1210 irq++; 1211 1212 if (irq >= APIC_INTMAPSIZE) 1213 return; /* No free interrupt handlers */ 1214 1215 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id); 1216 intpin = io_apic_ints[intr].dst_apic_int; 1217 1218 assign_apic_irq(apic, intpin, irq); 1219 io_apic_setup_intpin(apic, intpin); 1220} 1221 1222 1223static void 1224swap_apic_id(int apic, int oldid, int newid) 1225{ 1226 int x; 1227 int oapic; 1228 1229 1230 if (oldid == newid) 1231 return; /* Nothing to do */ 1232 1233 printf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n", 1234 apic, oldid, newid); 1235 1236 /* Swap physical APIC IDs in interrupt entries */ 1237 for (x = 0; x < nintrs; x++) { 1238 if (io_apic_ints[x].dst_apic_id == oldid) 1239 io_apic_ints[x].dst_apic_id = newid; 1240 else if (io_apic_ints[x].dst_apic_id == newid) 1241 io_apic_ints[x].dst_apic_id = oldid; 1242 } 1243 1244 /* Swap physical APIC IDs in IO_TO_ID mappings */ 1245 for (oapic = 0; oapic < mp_napics; oapic++) 1246 if (IO_TO_ID(oapic) == newid) 1247 break; 1248 1249 if (oapic < mp_napics) { 1250 printf("Changing APIC ID for IO APIC #%d from " 1251 "%d to %d in MP table\n", 1252 oapic, newid, oldid); 1253 IO_TO_ID(oapic) = oldid; 1254 } 1255 IO_TO_ID(apic) = newid; 1256} 1257 1258 1259static void 1260fix_id_to_io_mapping(void) 1261{ 1262 int x; 1263 1264 for (x = 0; x < NAPICID; x++) 1265 ID_TO_IO(x) = -1; 1266 1267 for (x = 0; x <= mp_naps; x++) 1268 if (CPU_TO_ID(x) < NAPICID) 1269 ID_TO_IO(CPU_TO_ID(x)) = x; 1270 1271 for (x = 0; x < mp_napics; x++) 1272 if (IO_TO_ID(x) < NAPICID) 1273 ID_TO_IO(IO_TO_ID(x)) = x; 1274} 1275 1276 1277static int 1278first_free_apic_id(void) 1279{ 1280 int freeid, x; 1281 1282 for (freeid = 0; freeid < NAPICID; freeid++) { 1283 for (x = 0; x <= mp_naps; x++) 1284 if (CPU_TO_ID(x) == freeid) 1285 break; 1286 if (x <= mp_naps) 1287 continue; 1288 for (x = 0; x < mp_napics; x++) 1289 if (IO_TO_ID(x) == freeid) 1290 break; 1291 if (x < mp_napics) 1292 continue; 1293 return freeid; 1294 } 1295 return freeid; 1296} 1297 1298 1299static int 1300io_apic_id_acceptable(int apic, int id) 1301{ 1302 int cpu; /* Logical CPU number */ 1303 int oapic; /* Logical IO APIC number for other IO APIC */ 1304 1305 if (id >= NAPICID) 1306 return 0; /* Out of range */ 1307 1308 for (cpu = 0; cpu <= mp_naps; cpu++) 1309 if (CPU_TO_ID(cpu) == id) 1310 return 0; /* Conflict with CPU */ 1311 1312 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++) 1313 if (IO_TO_ID(oapic) == id) 1314 return 0; /* Conflict with other APIC */ 1315 1316 return 1; /* ID is acceptable for IO APIC */ 1317} 1318 1319 1320/* 1321 * parse an Intel MP specification table 1322 */ 1323static void 1324fix_mp_table(void) 1325{ 1326 int x; 1327 int id; 1328 int bus_0 = 0; /* Stop GCC warning */ 1329 int bus_pci = 0; /* Stop GCC warning */ 1330 int num_pci_bus; 1331 int apic; /* IO APIC unit number */ 1332 int freeid; /* Free physical APIC ID */ 1333 int physid; /* Current physical IO APIC ID */ 1334 1335 /* 1336 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS 1337 * did it wrong. The MP spec says that when more than 1 PCI bus 1338 * exists the BIOS must begin with bus entries for the PCI bus and use 1339 * actual PCI bus numbering. This implies that when only 1 PCI bus 1340 * exists the BIOS can choose to ignore this ordering, and indeed many 1341 * MP motherboards do ignore it. This causes a problem when the PCI 1342 * sub-system makes requests of the MP sub-system based on PCI bus 1343 * numbers. So here we look for the situation and renumber the 1344 * busses and associated INTs in an effort to "make it right". 1345 */ 1346 1347 /* find bus 0, PCI bus, count the number of PCI busses */ 1348 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { 1349 if (bus_data[x].bus_id == 0) { 1350 bus_0 = x; 1351 } 1352 if (bus_data[x].bus_type == PCI) { 1353 ++num_pci_bus; 1354 bus_pci = x; 1355 } 1356 } 1357 /* 1358 * bus_0 == slot of bus with ID of 0 1359 * bus_pci == slot of last PCI bus encountered 1360 */ 1361 1362 /* check the 1 PCI bus case for sanity */ 1363 /* if it is number 0 all is well */ 1364 if (num_pci_bus == 1 && 1365 bus_data[bus_pci].bus_id != 0) { 1366 1367 /* mis-numbered, swap with whichever bus uses slot 0 */ 1368 1369 /* swap the bus entry types */ 1370 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type; 1371 bus_data[bus_0].bus_type = PCI; 1372 1373 /* swap each relavant INTerrupt entry */ 1374 id = bus_data[bus_pci].bus_id; 1375 for (x = 0; x < nintrs; ++x) { 1376 if (io_apic_ints[x].src_bus_id == id) { 1377 io_apic_ints[x].src_bus_id = 0; 1378 } 1379 else if (io_apic_ints[x].src_bus_id == 0) { 1380 io_apic_ints[x].src_bus_id = id; 1381 } 1382 } 1383 } 1384 1385 /* Assign IO APIC IDs. 1386 * 1387 * First try the existing ID. If a conflict is detected, try 1388 * the ID in the MP table. If a conflict is still detected, find 1389 * a free id. 1390 * 1391 * We cannot use the ID_TO_IO table before all conflicts has been 1392 * resolved and the table has been corrected. 1393 */ 1394 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */ 1395 1396 /* First try to use the value set by the BIOS */ 1397 physid = io_apic_get_id(apic); 1398 if (io_apic_id_acceptable(apic, physid)) { 1399 if (IO_TO_ID(apic) != physid) 1400 swap_apic_id(apic, IO_TO_ID(apic), physid); 1401 continue; 1402 } 1403 1404 /* Then check if the value in the MP table is acceptable */ 1405 if (io_apic_id_acceptable(apic, IO_TO_ID(apic))) 1406 continue; 1407 1408 /* Last resort, find a free APIC ID and use it */ 1409 freeid = first_free_apic_id(); 1410 if (freeid >= NAPICID) 1411 panic("No free physical APIC IDs found"); 1412 1413 if (io_apic_id_acceptable(apic, freeid)) { 1414 swap_apic_id(apic, IO_TO_ID(apic), freeid); 1415 continue; 1416 } 1417 panic("Free physical APIC ID not usable"); 1418 } 1419 fix_id_to_io_mapping(); 1420 1421 /* detect and fix broken Compaq MP table */ 1422 if (apic_int_type(0, 0) == -1) { 1423 printf("APIC_IO: MP table broken: 8259->APIC entry missing!\n"); 1424 io_apic_ints[nintrs].int_type = 3; /* ExtInt */ 1425 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */ 1426 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */ 1427 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0); 1428 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */ 1429 nintrs++; 1430 } 1431} 1432 1433 1434/* Assign low level interrupt handlers */ 1435static void 1436setup_apic_irq_mapping(void) 1437{ 1438 int x; 1439 int int_vector; 1440 1441 /* Clear array */ 1442 for (x = 0; x < APIC_INTMAPSIZE; x++) { 1443 int_to_apicintpin[x].ioapic = -1; 1444 int_to_apicintpin[x].int_pin = 0; 1445 int_to_apicintpin[x].apic_address = NULL; 1446 int_to_apicintpin[x].redirindex = 0; 1447 } 1448 1449 /* First assign ISA/EISA interrupts */ 1450 for (x = 0; x < nintrs; x++) { 1451 int_vector = io_apic_ints[x].src_bus_irq; 1452 if (int_vector < APIC_INTMAPSIZE && 1453 io_apic_ints[x].int_vector == 0xff && 1454 int_to_apicintpin[int_vector].ioapic == -1 && 1455 (apic_int_is_bus_type(x, ISA) || 1456 apic_int_is_bus_type(x, EISA)) && 1457 io_apic_ints[x].int_type == 0) { 1458 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id), 1459 io_apic_ints[x].dst_apic_int, 1460 int_vector); 1461 } 1462 } 1463 1464 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */ 1465 for (x = 0; x < nintrs; x++) { 1466 if (io_apic_ints[x].dst_apic_int == 0 && 1467 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) && 1468 io_apic_ints[x].int_vector == 0xff && 1469 int_to_apicintpin[0].ioapic == -1 && 1470 io_apic_ints[x].int_type == 3) { 1471 assign_apic_irq(0, 0, 0); 1472 break; 1473 } 1474 } 1475 /* PCI interrupt assignment is deferred */ 1476} 1477 1478 1479static int 1480processor_entry(proc_entry_ptr entry, int cpu) 1481{ 1482 /* check for usability */ 1483 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN)) 1484 return 0; 1485 1486 if(entry->apic_id >= NAPICID) 1487 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1); 1488 /* check for BSP flag */ 1489 if (entry->cpu_flags & PROCENTRY_FLAG_BP) { 1490 boot_cpu_id = entry->apic_id; 1491 CPU_TO_ID(0) = entry->apic_id; 1492 ID_TO_CPU(entry->apic_id) = 0; 1493 return 0; /* its already been counted */ 1494 } 1495 1496 /* add another AP to list, if less than max number of CPUs */ 1497 else if (cpu < MAXCPU) { 1498 CPU_TO_ID(cpu) = entry->apic_id; 1499 ID_TO_CPU(entry->apic_id) = cpu; 1500 return 1; 1501 } 1502 1503 return 0; 1504} 1505 1506 1507static int 1508bus_entry(bus_entry_ptr entry, int bus) 1509{ 1510 int x; 1511 char c, name[8]; 1512 1513 /* encode the name into an index */ 1514 for (x = 0; x < 6; ++x) { 1515 if ((c = entry->bus_type[x]) == ' ') 1516 break; 1517 name[x] = c; 1518 } 1519 name[x] = '\0'; 1520 1521 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) 1522 panic("unknown bus type: '%s'", name); 1523 1524 bus_data[bus].bus_id = entry->bus_id; 1525 bus_data[bus].bus_type = x; 1526 1527 return 1; 1528} 1529 1530 1531static int 1532io_apic_entry(io_apic_entry_ptr entry, int apic) 1533{ 1534 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) 1535 return 0; 1536 1537 IO_TO_ID(apic) = entry->apic_id; 1538 if (entry->apic_id < NAPICID) 1539 ID_TO_IO(entry->apic_id) = apic; 1540 1541 return 1; 1542} 1543 1544 1545static int 1546lookup_bus_type(char *name) 1547{ 1548 int x; 1549 1550 for (x = 0; x < MAX_BUSTYPE; ++x) 1551 if (strcmp(bus_type_table[x].name, name) == 0) 1552 return bus_type_table[x].type; 1553 1554 return UNKNOWN_BUSTYPE; 1555} 1556 1557 1558static int 1559int_entry(int_entry_ptr entry, int intr) 1560{ 1561 int apic; 1562 1563 io_apic_ints[intr].int_type = entry->int_type; 1564 io_apic_ints[intr].int_flags = entry->int_flags; 1565 io_apic_ints[intr].src_bus_id = entry->src_bus_id; 1566 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq; 1567 if (entry->dst_apic_id == 255) { 1568 /* This signal goes to all IO APICS. Select an IO APIC 1569 with sufficient number of interrupt pins */ 1570 for (apic = 0; apic < mp_napics; apic++) 1571 if (((io_apic_read(apic, IOAPIC_VER) & 1572 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >= 1573 entry->dst_apic_int) 1574 break; 1575 if (apic < mp_napics) 1576 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic); 1577 else 1578 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; 1579 } else 1580 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; 1581 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int; 1582 1583 return 1; 1584} 1585 1586 1587static int 1588apic_int_is_bus_type(int intr, int bus_type) 1589{ 1590 int bus; 1591 1592 for (bus = 0; bus < mp_nbusses; ++bus) 1593 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) 1594 && ((int) bus_data[bus].bus_type == bus_type)) 1595 return 1; 1596 1597 return 0; 1598} 1599 1600 1601/* 1602 * Given a traditional ISA INT mask, return an APIC mask. 1603 */ 1604u_int 1605isa_apic_mask(u_int isa_mask) 1606{ 1607 int isa_irq; 1608 int apic_pin; 1609 1610#if defined(SKIP_IRQ15_REDIRECT) 1611 if (isa_mask == (1 << 15)) { 1612 printf("skipping ISA IRQ15 redirect\n"); 1613 return isa_mask; 1614 } 1615#endif /* SKIP_IRQ15_REDIRECT */ 1616 1617 isa_irq = ffs(isa_mask); /* find its bit position */ 1618 if (isa_irq == 0) /* doesn't exist */ 1619 return 0; 1620 --isa_irq; /* make it zero based */ 1621 1622 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */ 1623 if (apic_pin == -1) 1624 return 0; 1625 1626 return (1 << apic_pin); /* convert pin# to a mask */ 1627} 1628 1629 1630/* 1631 * Determine which APIC pin an ISA/EISA INT is attached to. 1632 */ 1633#define INTTYPE(I) (io_apic_ints[(I)].int_type) 1634#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) 1635#define INTIRQ(I) (io_apic_ints[(I)].int_vector) 1636#define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id)) 1637 1638#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) 1639int 1640isa_apic_irq(int isa_irq) 1641{ 1642 int intr; 1643 1644 for (intr = 0; intr < nintrs; ++intr) { /* check each record */ 1645 if (INTTYPE(intr) == 0) { /* standard INT */ 1646 if (SRCBUSIRQ(intr) == isa_irq) { 1647 if (apic_int_is_bus_type(intr, ISA) || 1648 apic_int_is_bus_type(intr, EISA)) { 1649 if (INTIRQ(intr) == 0xff) 1650 return -1; /* unassigned */ 1651 return INTIRQ(intr); /* found */ 1652 } 1653 } 1654 } 1655 } 1656 return -1; /* NOT found */ 1657} 1658 1659 1660/* 1661 * Determine which APIC pin a PCI INT is attached to. 1662 */ 1663#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) 1664#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) 1665#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) 1666int 1667pci_apic_irq(int pciBus, int pciDevice, int pciInt) 1668{ 1669 int intr; 1670 1671 --pciInt; /* zero based */ 1672 1673 for (intr = 0; intr < nintrs; ++intr) /* check each record */ 1674 if ((INTTYPE(intr) == 0) /* standard INT */ 1675 && (SRCBUSID(intr) == pciBus) 1676 && (SRCBUSDEVICE(intr) == pciDevice) 1677 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ 1678 if (apic_int_is_bus_type(intr, PCI)) { 1679 if (INTIRQ(intr) == 0xff) 1680 allocate_apic_irq(intr); 1681 if (INTIRQ(intr) == 0xff) 1682 return -1; /* unassigned */ 1683 return INTIRQ(intr); /* exact match */ 1684 } 1685 1686 return -1; /* NOT found */ 1687} 1688 1689int 1690next_apic_irq(int irq) 1691{ 1692 int intr, ointr; 1693 int bus, bustype; 1694 1695 bus = 0; 1696 bustype = 0; 1697 for (intr = 0; intr < nintrs; intr++) { 1698 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0) 1699 continue; 1700 bus = SRCBUSID(intr); 1701 bustype = apic_bus_type(bus); 1702 if (bustype != ISA && 1703 bustype != EISA && 1704 bustype != PCI) 1705 continue; 1706 break; 1707 } 1708 if (intr >= nintrs) { 1709 return -1; 1710 } 1711 for (ointr = intr + 1; ointr < nintrs; ointr++) { 1712 if (INTTYPE(ointr) != 0) 1713 continue; 1714 if (bus != SRCBUSID(ointr)) 1715 continue; 1716 if (bustype == PCI) { 1717 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr)) 1718 continue; 1719 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr)) 1720 continue; 1721 } 1722 if (bustype == ISA || bustype == EISA) { 1723 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr)) 1724 continue; 1725 } 1726 if (INTPIN(intr) == INTPIN(ointr)) 1727 continue; 1728 break; 1729 } 1730 if (ointr >= nintrs) { 1731 return -1; 1732 } 1733 return INTIRQ(ointr); 1734} 1735#undef SRCBUSLINE 1736#undef SRCBUSDEVICE 1737#undef SRCBUSID 1738#undef SRCBUSIRQ 1739 1740#undef INTPIN 1741#undef INTIRQ 1742#undef INTAPIC 1743#undef INTTYPE 1744 1745 1746/* 1747 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt. 1748 * 1749 * XXX FIXME: 1750 * Exactly what this means is unclear at this point. It is a solution 1751 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard 1752 * could route any of the ISA INTs to upper (>15) IRQ values. But most would 1753 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an 1754 * option. 1755 */ 1756int 1757undirect_isa_irq(int rirq) 1758{ 1759#if defined(READY) 1760 if (bootverbose) 1761 printf("Freeing redirected ISA irq %d.\n", rirq); 1762 /** FIXME: tickle the MB redirector chip */ 1763 return -1; 1764#else 1765 if (bootverbose) 1766 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq); 1767 return 0; 1768#endif /* READY */ 1769} 1770 1771 1772/* 1773 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt 1774 */ 1775int 1776undirect_pci_irq(int rirq) 1777{ 1778#if defined(READY) 1779 if (bootverbose) 1780 printf("Freeing redirected PCI irq %d.\n", rirq); 1781 1782 /** FIXME: tickle the MB redirector chip */ 1783 return -1; 1784#else 1785 if (bootverbose) 1786 printf("Freeing (NOT implemented) redirected PCI irq %d.\n", 1787 rirq); 1788 return 0; 1789#endif /* READY */ 1790} 1791 1792 1793/* 1794 * given a bus ID, return: 1795 * the bus type if found 1796 * -1 if NOT found 1797 */ 1798int 1799apic_bus_type(int id) 1800{ 1801 int x; 1802 1803 for (x = 0; x < mp_nbusses; ++x) 1804 if (bus_data[x].bus_id == id) 1805 return bus_data[x].bus_type; 1806 1807 return -1; 1808} 1809 1810 1811/* 1812 * given a LOGICAL APIC# and pin#, return: 1813 * the associated src bus ID if found 1814 * -1 if NOT found 1815 */ 1816int 1817apic_src_bus_id(int apic, int pin) 1818{ 1819 int x; 1820 1821 /* search each of the possible INTerrupt sources */ 1822 for (x = 0; x < nintrs; ++x) 1823 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1824 (pin == io_apic_ints[x].dst_apic_int)) 1825 return (io_apic_ints[x].src_bus_id); 1826 1827 return -1; /* NOT found */ 1828} 1829 1830 1831/* 1832 * given a LOGICAL APIC# and pin#, return: 1833 * the associated src bus IRQ if found 1834 * -1 if NOT found 1835 */ 1836int 1837apic_src_bus_irq(int apic, int pin) 1838{ 1839 int x; 1840 1841 for (x = 0; x < nintrs; x++) 1842 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1843 (pin == io_apic_ints[x].dst_apic_int)) 1844 return (io_apic_ints[x].src_bus_irq); 1845 1846 return -1; /* NOT found */ 1847} 1848 1849 1850/* 1851 * given a LOGICAL APIC# and pin#, return: 1852 * the associated INTerrupt type if found 1853 * -1 if NOT found 1854 */ 1855int 1856apic_int_type(int apic, int pin) 1857{ 1858 int x; 1859 1860 /* search each of the possible INTerrupt sources */ 1861 for (x = 0; x < nintrs; ++x) 1862 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1863 (pin == io_apic_ints[x].dst_apic_int)) 1864 return (io_apic_ints[x].int_type); 1865 1866 return -1; /* NOT found */ 1867} 1868 1869int 1870apic_irq(int apic, int pin) 1871{ 1872 int x; 1873 int res; 1874 1875 for (x = 0; x < nintrs; ++x) 1876 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1877 (pin == io_apic_ints[x].dst_apic_int)) { 1878 res = io_apic_ints[x].int_vector; 1879 if (res == 0xff) 1880 return -1; 1881 if (apic != int_to_apicintpin[res].ioapic) 1882 panic("apic_irq: inconsistent table"); 1883 if (pin != int_to_apicintpin[res].int_pin) 1884 panic("apic_irq inconsistent table (2)"); 1885 return res; 1886 } 1887 return -1; 1888} 1889 1890 1891/* 1892 * given a LOGICAL APIC# and pin#, return: 1893 * the associated trigger mode if found 1894 * -1 if NOT found 1895 */ 1896int 1897apic_trigger(int apic, int pin) 1898{ 1899 int x; 1900 1901 /* search each of the possible INTerrupt sources */ 1902 for (x = 0; x < nintrs; ++x) 1903 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1904 (pin == io_apic_ints[x].dst_apic_int)) 1905 return ((io_apic_ints[x].int_flags >> 2) & 0x03); 1906 1907 return -1; /* NOT found */ 1908} 1909 1910 1911/* 1912 * given a LOGICAL APIC# and pin#, return: 1913 * the associated 'active' level if found 1914 * -1 if NOT found 1915 */ 1916int 1917apic_polarity(int apic, int pin) 1918{ 1919 int x; 1920 1921 /* search each of the possible INTerrupt sources */ 1922 for (x = 0; x < nintrs; ++x) 1923 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1924 (pin == io_apic_ints[x].dst_apic_int)) 1925 return (io_apic_ints[x].int_flags & 0x03); 1926 1927 return -1; /* NOT found */ 1928} 1929 1930 1931/* 1932 * set data according to MP defaults 1933 * FIXME: probably not complete yet... 1934 */ 1935static void 1936default_mp_table(int type) 1937{ 1938 int ap_cpu_id; 1939#if defined(APIC_IO) 1940 int io_apic_id; 1941 int pin; 1942#endif /* APIC_IO */ 1943 1944#if 0 1945 printf(" MP default config type: %d\n", type); 1946 switch (type) { 1947 case 1: 1948 printf(" bus: ISA, APIC: 82489DX\n"); 1949 break; 1950 case 2: 1951 printf(" bus: EISA, APIC: 82489DX\n"); 1952 break; 1953 case 3: 1954 printf(" bus: EISA, APIC: 82489DX\n"); 1955 break; 1956 case 4: 1957 printf(" bus: MCA, APIC: 82489DX\n"); 1958 break; 1959 case 5: 1960 printf(" bus: ISA+PCI, APIC: Integrated\n"); 1961 break; 1962 case 6: 1963 printf(" bus: EISA+PCI, APIC: Integrated\n"); 1964 break; 1965 case 7: 1966 printf(" bus: MCA+PCI, APIC: Integrated\n"); 1967 break; 1968 default: 1969 printf(" future type\n"); 1970 break; 1971 /* NOTREACHED */ 1972 } 1973#endif /* 0 */ 1974 1975 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24; 1976 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; 1977 1978 /* BSP */ 1979 CPU_TO_ID(0) = boot_cpu_id; 1980 ID_TO_CPU(boot_cpu_id) = 0; 1981 1982 /* one and only AP */ 1983 CPU_TO_ID(1) = ap_cpu_id; 1984 ID_TO_CPU(ap_cpu_id) = 1; 1985 1986#if defined(APIC_IO) 1987 /* one and only IO APIC */ 1988 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; 1989 1990 /* 1991 * sanity check, refer to MP spec section 3.6.6, last paragraph 1992 * necessary as some hardware isn't properly setting up the IO APIC 1993 */ 1994#if defined(REALLY_ANAL_IOAPICID_VALUE) 1995 if (io_apic_id != 2) { 1996#else 1997 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { 1998#endif /* REALLY_ANAL_IOAPICID_VALUE */ 1999 io_apic_set_id(0, 2); 2000 io_apic_id = 2; 2001 } 2002 IO_TO_ID(0) = io_apic_id; 2003 ID_TO_IO(io_apic_id) = 0; 2004#endif /* APIC_IO */ 2005 2006 /* fill out bus entries */ 2007 switch (type) { 2008 case 1: 2009 case 2: 2010 case 3: 2011 case 4: 2012 case 5: 2013 case 6: 2014 case 7: 2015 bus_data[0].bus_id = default_data[type - 1][1]; 2016 bus_data[0].bus_type = default_data[type - 1][2]; 2017 bus_data[1].bus_id = default_data[type - 1][3]; 2018 bus_data[1].bus_type = default_data[type - 1][4]; 2019 break; 2020 2021 /* case 4: case 7: MCA NOT supported */ 2022 default: /* illegal/reserved */ 2023 panic("BAD default MP config: %d", type); 2024 /* NOTREACHED */ 2025 } 2026 2027#if defined(APIC_IO) 2028 /* general cases from MP v1.4, table 5-2 */ 2029 for (pin = 0; pin < 16; ++pin) { 2030 io_apic_ints[pin].int_type = 0; 2031 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */ 2032 io_apic_ints[pin].src_bus_id = 0; 2033 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */ 2034 io_apic_ints[pin].dst_apic_id = io_apic_id; 2035 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */ 2036 } 2037 2038 /* special cases from MP v1.4, table 5-2 */ 2039 if (type == 2) { 2040 io_apic_ints[2].int_type = 0xff; /* N/C */ 2041 io_apic_ints[13].int_type = 0xff; /* N/C */ 2042#if !defined(APIC_MIXED_MODE) 2043 /** FIXME: ??? */ 2044 panic("sorry, can't support type 2 default yet"); 2045#endif /* APIC_MIXED_MODE */ 2046 } 2047 else 2048 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ 2049 2050 if (type == 7) 2051 io_apic_ints[0].int_type = 0xff; /* N/C */ 2052 else 2053 io_apic_ints[0].int_type = 3; /* vectored 8259 */ 2054#endif /* APIC_IO */ 2055} 2056 2057 2058/* 2059 * start each AP in our list 2060 */ 2061static int 2062start_all_aps(u_int boot_addr) 2063{ 2064 int x, i, pg; 2065#ifndef PC98 2066 u_char mpbiosreason; 2067#endif 2068 u_long mpbioswarmvec; 2069 struct pcpu *pc; 2070 char *stack; 2071 uintptr_t kptbase; 2072 2073 POSTCODE(START_ALL_APS_POST); 2074 2075 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); 2076 2077 /* initialize BSP's local APIC */ 2078 apic_initialize(); 2079 bsp_apic_ready = 1; 2080 2081 /* install the AP 1st level boot code */ 2082 install_ap_tramp(boot_addr); 2083 2084 2085 /* save the current value of the warm-start vector */ 2086 mpbioswarmvec = *((u_long *) WARMBOOT_OFF); 2087#ifndef PC98 2088 outb(CMOS_REG, BIOS_RESET); 2089 mpbiosreason = inb(CMOS_DATA); 2090#endif 2091 2092 /* set up temporary P==V mapping for AP boot */ 2093 /* XXX this is a hack, we should boot the AP on its own stack/PTD */ 2094 kptbase = (uintptr_t)(void *)KPTphys; 2095 for (x = 0; x < NKPT; x++) 2096 PTD[x] = (pd_entry_t)(PG_V | PG_RW | 2097 ((kptbase + x * PAGE_SIZE) & PG_FRAME)); 2098 invltlb(); 2099 2100 /* start each AP */ 2101 for (x = 1; x <= mp_naps; ++x) { 2102 2103 /* This is a bit verbose, it will go away soon. */ 2104 2105 /* first page of AP's private space */ 2106 pg = x * i386_btop(sizeof(struct privatespace)); 2107 2108 /* allocate a new private data page */ 2109 pc = (struct pcpu *)kmem_alloc(kernel_map, PAGE_SIZE); 2110 2111 /* wire it into the private page table page */ 2112 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys(pc)); 2113 2114 /* allocate and set up an idle stack data page */ 2115 stack = (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE); /* XXXKSE */ 2116 for (i = 0; i < KSTACK_PAGES; i++) 2117 SMPpt[pg + 1 + i] = (pt_entry_t) 2118 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 2119 2120 /* prime data page for it to use */ 2121 pcpu_init(pc, x, sizeof(struct pcpu)); 2122 2123 /* setup a vector to our boot code */ 2124 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 2125 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); 2126#ifndef PC98 2127 outb(CMOS_REG, BIOS_RESET); 2128 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 2129#endif 2130 2131 bootSTK = &SMP_prvspace[x].idlekstack[KSTACK_PAGES * PAGE_SIZE]; 2132 bootAP = x; 2133 2134 /* attempt to start the Application Processor */ 2135 CHECK_INIT(99); /* setup checkpoints */ 2136 if (!start_ap(x, boot_addr)) { 2137 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); 2138 CHECK_PRINT("trace"); /* show checkpoints */ 2139 /* better panic as the AP may be running loose */ 2140 printf("panic y/n? [y] "); 2141 if (cngetc() != 'n') 2142 panic("bye-bye"); 2143 } 2144 CHECK_PRINT("trace"); /* show checkpoints */ 2145 2146 /* record its version info */ 2147 cpu_apic_versions[x] = cpu_apic_versions[0]; 2148 2149 all_cpus |= (1 << x); /* record AP in CPU map */ 2150 } 2151 2152 /* build our map of 'other' CPUs */ 2153 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 2154 2155 /* fill in our (BSP) APIC version */ 2156 cpu_apic_versions[0] = lapic.version; 2157 2158 /* restore the warmstart vector */ 2159 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 2160#ifndef PC98 2161 outb(CMOS_REG, BIOS_RESET); 2162 outb(CMOS_DATA, mpbiosreason); 2163#endif 2164 2165 /* 2166 * Set up the idle context for the BSP. Similar to above except 2167 * that some was done by locore, some by pmap.c and some is implicit 2168 * because the BSP is cpu#0 and the page is initially zero, and also 2169 * because we can refer to variables by name on the BSP.. 2170 */ 2171 2172 /* Allocate and setup BSP idle stack */ 2173 stack = (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE); 2174 for (i = 0; i < KSTACK_PAGES; i++) 2175 SMPpt[1 + i] = (pt_entry_t) 2176 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 2177 2178 for (x = 0; x < NKPT; x++) 2179 PTD[x] = 0; 2180 pmap_set_opt(); 2181 2182 /* number of APs actually started */ 2183 return mp_ncpus - 1; 2184} 2185 2186 2187/* 2188 * load the 1st level AP boot code into base memory. 2189 */ 2190 2191/* targets for relocation */ 2192extern void bigJump(void); 2193extern void bootCodeSeg(void); 2194extern void bootDataSeg(void); 2195extern void MPentry(void); 2196extern u_int MP_GDT; 2197extern u_int mp_gdtbase; 2198 2199static void 2200install_ap_tramp(u_int boot_addr) 2201{ 2202 int x; 2203 int size = *(int *) ((u_long) & bootMP_size); 2204 u_char *src = (u_char *) ((u_long) bootMP); 2205 u_char *dst = (u_char *) boot_addr + KERNBASE; 2206 u_int boot_base = (u_int) bootMP; 2207 u_int8_t *dst8; 2208 u_int16_t *dst16; 2209 u_int32_t *dst32; 2210 2211 POSTCODE(INSTALL_AP_TRAMP_POST); 2212 2213 for (x = 0; x < size; ++x) 2214 *dst++ = *src++; 2215 2216 /* 2217 * modify addresses in code we just moved to basemem. unfortunately we 2218 * need fairly detailed info about mpboot.s for this to work. changes 2219 * to mpboot.s might require changes here. 2220 */ 2221 2222 /* boot code is located in KERNEL space */ 2223 dst = (u_char *) boot_addr + KERNBASE; 2224 2225 /* modify the lgdt arg */ 2226 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 2227 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); 2228 2229 /* modify the ljmp target for MPentry() */ 2230 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 2231 *dst32 = ((u_int) MPentry - KERNBASE); 2232 2233 /* modify the target for boot code segment */ 2234 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 2235 dst8 = (u_int8_t *) (dst16 + 1); 2236 *dst16 = (u_int) boot_addr & 0xffff; 2237 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 2238 2239 /* modify the target for boot data segment */ 2240 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 2241 dst8 = (u_int8_t *) (dst16 + 1); 2242 *dst16 = (u_int) boot_addr & 0xffff; 2243 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 2244} 2245 2246 2247/* 2248 * this function starts the AP (application processor) identified 2249 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 2250 * to accomplish this. This is necessary because of the nuances 2251 * of the different hardware we might encounter. It ain't pretty, 2252 * but it seems to work. 2253 */ 2254static int 2255start_ap(int logical_cpu, u_int boot_addr) 2256{ 2257 int physical_cpu; 2258 int vector; 2259 int cpus; 2260 u_long icr_lo, icr_hi; 2261 2262 POSTCODE(START_AP_POST); 2263 2264 /* get the PHYSICAL APIC ID# */ 2265 physical_cpu = CPU_TO_ID(logical_cpu); 2266 2267 /* calculate the vector */ 2268 vector = (boot_addr >> 12) & 0xff; 2269 2270 /* used as a watchpoint to signal AP startup */ 2271 cpus = mp_ncpus; 2272 2273 /* 2274 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 2275 * and running the target CPU. OR this INIT IPI might be latched (P5 2276 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 2277 * ignored. 2278 */ 2279 2280 /* setup the address for the target AP */ 2281 icr_hi = lapic.icr_hi & ~APIC_ID_MASK; 2282 icr_hi |= (physical_cpu << 24); 2283 lapic.icr_hi = icr_hi; 2284 2285 /* setup common fields for subsequent IPIs */ 2286 icr_lo = lapic.icr_lo & APIC_ICRLO_RESV_MASK; 2287 icr_lo |= APIC_DESTMODE_PHY; 2288 2289 /* do an INIT IPI: assert RESET */ 2290 lapic.icr_lo = icr_lo | APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 2291 APIC_LEVEL_ASSERT | APIC_DELMODE_INIT; 2292 2293 /* wait for pending status end */ 2294 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2295 /* spin */ ; 2296 2297 /* do an INIT IPI: deassert RESET */ 2298 lapic.icr_lo = icr_lo | APIC_DEST_ALLESELF | APIC_TRIGMOD_LEVEL | 2299 APIC_LEVEL_DEASSERT | APIC_DELMODE_INIT; 2300 2301 /* wait for pending status end */ 2302 u_sleep(10000); /* wait ~10mS */ 2303 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2304 /* spin */ ; 2305 2306 /* 2307 * next we do a STARTUP IPI: the previous INIT IPI might still be 2308 * latched, (P5 bug) this 1st STARTUP would then terminate 2309 * immediately, and the previously started INIT IPI would continue. OR 2310 * the previous INIT IPI has already run. and this STARTUP IPI will 2311 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 2312 * will run. 2313 */ 2314 2315 /* do a STARTUP IPI */ 2316 lapic.icr_lo = icr_lo | APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 2317 APIC_LEVEL_DEASSERT | APIC_DELMODE_STARTUP | vector; 2318 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2319 /* spin */ ; 2320 u_sleep(200); /* wait ~200uS */ 2321 2322 /* 2323 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 2324 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 2325 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 2326 * recognized after hardware RESET or INIT IPI. 2327 */ 2328 2329 lapic.icr_lo = icr_lo | APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 2330 APIC_LEVEL_DEASSERT | APIC_DELMODE_STARTUP | vector; 2331 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2332 /* spin */ ; 2333 u_sleep(200); /* wait ~200uS */ 2334 2335 /* wait for it to start */ 2336 set_apic_timer(5000000);/* == 5 seconds */ 2337 while (read_apic_timer()) 2338 if (mp_ncpus > cpus) 2339 return 1; /* return SUCCESS */ 2340 2341 return 0; /* return FAILURE */ 2342} 2343 2344#if defined(APIC_IO) 2345 2346#ifdef COUNT_XINVLTLB_HITS 2347u_int xhits_gbl[MAXCPU]; 2348u_int xhits_pg[MAXCPU]; 2349u_int xhits_rng[MAXCPU]; 2350SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, ""); 2351SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl, 2352 sizeof(xhits_gbl), "IU", ""); 2353SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg, 2354 sizeof(xhits_pg), "IU", ""); 2355SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng, 2356 sizeof(xhits_rng), "IU", ""); 2357 2358u_int ipi_global; 2359u_int ipi_page; 2360u_int ipi_range; 2361u_int ipi_range_size; 2362SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, ""); 2363SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, ""); 2364SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, ""); 2365SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size, 2366 0, ""); 2367 2368u_int ipi_masked_global; 2369u_int ipi_masked_page; 2370u_int ipi_masked_range; 2371u_int ipi_masked_range_size; 2372SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW, 2373 &ipi_masked_global, 0, ""); 2374SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW, 2375 &ipi_masked_page, 0, ""); 2376SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW, 2377 &ipi_masked_range, 0, ""); 2378SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW, 2379 &ipi_masked_range_size, 0, ""); 2380#endif 2381 2382/* 2383 * Flush the TLB on all other CPU's 2384 */ 2385static void 2386smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2) 2387{ 2388 u_int ncpu; 2389 register_t eflags; 2390 2391 ncpu = mp_ncpus - 1; /* does not shootdown self */ 2392 if (ncpu < 1) 2393 return; /* no other cpus */ 2394 eflags = read_eflags(); 2395 if ((eflags & PSL_I) == 0) 2396 panic("absolutely cannot call smp_ipi_shootdown with interrupts already disabled"); 2397 mtx_lock_spin(&smp_tlb_mtx); 2398 smp_tlb_addr1 = addr1; 2399 smp_tlb_addr2 = addr2; 2400 atomic_store_rel_int(&smp_tlb_wait, 0); 2401 ipi_all_but_self(vector); 2402 while (smp_tlb_wait < ncpu) 2403 ia32_pause(); 2404 mtx_unlock_spin(&smp_tlb_mtx); 2405} 2406 2407/* 2408 * This is about as magic as it gets. fortune(1) has got similar code 2409 * for reversing bits in a word. Who thinks up this stuff?? 2410 * 2411 * Yes, it does appear to be consistently faster than: 2412 * while (i = ffs(m)) { 2413 * m >>= i; 2414 * bits++; 2415 * } 2416 * and 2417 * while (lsb = (m & -m)) { // This is magic too 2418 * m &= ~lsb; // or: m ^= lsb 2419 * bits++; 2420 * } 2421 * Both of these latter forms do some very strange things on gcc-3.1 with 2422 * -mcpu=pentiumpro and/or -march=pentiumpro and/or -O or -O2. 2423 * There is probably an SSE or MMX popcnt instruction. 2424 * 2425 * I wonder if this should be in libkern? 2426 * 2427 * XXX Stop the presses! Another one: 2428 * static __inline u_int32_t 2429 * popcnt1(u_int32_t v) 2430 * { 2431 * v -= ((v >> 1) & 0x55555555); 2432 * v = (v & 0x33333333) + ((v >> 2) & 0x33333333); 2433 * v = (v + (v >> 4)) & 0x0F0F0F0F; 2434 * return (v * 0x01010101) >> 24; 2435 * } 2436 * The downside is that it has a multiply. With a pentium3 with 2437 * -mcpu=pentiumpro and -march=pentiumpro then gcc-3.1 will use 2438 * an imull, and in that case it is faster. In most other cases 2439 * it appears slightly slower. 2440 */ 2441static __inline u_int32_t 2442popcnt(u_int32_t m) 2443{ 2444 2445 m = (m & 0x55555555) + ((m & 0xaaaaaaaa) >> 1); 2446 m = (m & 0x33333333) + ((m & 0xcccccccc) >> 2); 2447 m = (m & 0x0f0f0f0f) + ((m & 0xf0f0f0f0) >> 4); 2448 m = (m & 0x00ff00ff) + ((m & 0xff00ff00) >> 8); 2449 m = (m & 0x0000ffff) + ((m & 0xffff0000) >> 16); 2450 return m; 2451} 2452 2453static void 2454smp_targeted_tlb_shootdown(u_int mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2) 2455{ 2456 int ncpu, othercpus; 2457 register_t eflags; 2458 2459 othercpus = mp_ncpus - 1; 2460 if (mask == (u_int)-1) { 2461 ncpu = othercpus; 2462 if (ncpu < 1) 2463 return; 2464 } else { 2465 mask &= ~PCPU_GET(cpumask); 2466 if (mask == 0) 2467 return; 2468 ncpu = popcnt(mask); 2469 if (ncpu > othercpus) { 2470 /* XXX this should be a panic offence */ 2471 printf("SMP: tlb shootdown to %d other cpus (only have %d)\n", 2472 ncpu, othercpus); 2473 ncpu = othercpus; 2474 } 2475 /* XXX should be a panic, implied by mask == 0 above */ 2476 if (ncpu < 1) 2477 return; 2478 } 2479 eflags = read_eflags(); 2480 if ((eflags & PSL_I) == 0) 2481 panic("absolutely cannot call smp_targeted_ipi_shootdown with interrupts already disabled"); 2482 mtx_lock_spin(&smp_tlb_mtx); 2483 smp_tlb_addr1 = addr1; 2484 smp_tlb_addr2 = addr2; 2485 atomic_store_rel_int(&smp_tlb_wait, 0); 2486 if (mask == (u_int)-1) 2487 ipi_all_but_self(vector); 2488 else 2489 ipi_selected(mask, vector); 2490 while (smp_tlb_wait < ncpu) 2491 ia32_pause(); 2492 mtx_unlock_spin(&smp_tlb_mtx); 2493} 2494#endif 2495 2496void 2497smp_invltlb(void) 2498{ 2499#if defined(APIC_IO) 2500 if (smp_started) { 2501 smp_tlb_shootdown(IPI_INVLTLB, 0, 0); 2502#ifdef COUNT_XINVLTLB_HITS 2503 ipi_global++; 2504#endif 2505 } 2506#endif /* APIC_IO */ 2507} 2508 2509void 2510smp_invlpg(vm_offset_t addr) 2511{ 2512#if defined(APIC_IO) 2513 if (smp_started) { 2514 smp_tlb_shootdown(IPI_INVLPG, addr, 0); 2515#ifdef COUNT_XINVLTLB_HITS 2516 ipi_page++; 2517#endif 2518 } 2519#endif /* APIC_IO */ 2520} 2521 2522void 2523smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2) 2524{ 2525#if defined(APIC_IO) 2526 if (smp_started) { 2527 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2); 2528#ifdef COUNT_XINVLTLB_HITS 2529 ipi_range++; 2530 ipi_range_size += (addr2 - addr1) / PAGE_SIZE; 2531#endif 2532 } 2533#endif /* APIC_IO */ 2534} 2535 2536void 2537smp_masked_invltlb(u_int mask) 2538{ 2539#if defined(APIC_IO) 2540 if (smp_started) { 2541 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0); 2542#ifdef COUNT_XINVLTLB_HITS 2543 ipi_masked_global++; 2544#endif 2545 } 2546#endif /* APIC_IO */ 2547} 2548 2549void 2550smp_masked_invlpg(u_int mask, vm_offset_t addr) 2551{ 2552#if defined(APIC_IO) 2553 if (smp_started) { 2554 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0); 2555#ifdef COUNT_XINVLTLB_HITS 2556 ipi_masked_page++; 2557#endif 2558 } 2559#endif /* APIC_IO */ 2560} 2561 2562void 2563smp_masked_invlpg_range(u_int mask, vm_offset_t addr1, vm_offset_t addr2) 2564{ 2565#if defined(APIC_IO) 2566 if (smp_started) { 2567 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2); 2568#ifdef COUNT_XINVLTLB_HITS 2569 ipi_masked_range++; 2570 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE; 2571#endif 2572 } 2573#endif /* APIC_IO */ 2574} 2575 2576 2577/* 2578 * This is called once the rest of the system is up and running and we're 2579 * ready to let the AP's out of the pen. 2580 */ 2581void 2582ap_init(void) 2583{ 2584 u_int apic_id; 2585 2586 /* spin until all the AP's are ready */ 2587 while (!aps_ready) 2588 ia32_pause(); 2589 2590 /* BSP may have changed PTD while we were waiting */ 2591 invltlb(); 2592 2593#if defined(I586_CPU) && !defined(NO_F00F_HACK) 2594 lidt(&r_idt); 2595#endif 2596 2597 /* set up CPU registers and state */ 2598 cpu_setregs(); 2599 2600 /* set up FPU state on the AP */ 2601 npxinit(__INITIAL_NPXCW__); 2602 2603 /* set up SSE registers */ 2604 enable_sse(); 2605 2606 /* A quick check from sanity claus */ 2607 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]); 2608 if (PCPU_GET(cpuid) != apic_id) { 2609 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid)); 2610 printf("SMP: apic_id = %d\n", apic_id); 2611 printf("PTD[MPPTDI] = %#jx\n", (uintmax_t)PTD[MPPTDI]); 2612 panic("cpuid mismatch! boom!!"); 2613 } 2614 2615 /* Init local apic for irq's */ 2616 apic_initialize(); 2617 2618 /* Set memory range attributes for this CPU to match the BSP */ 2619 mem_range_AP_init(); 2620 2621 mtx_lock_spin(&ap_boot_mtx); 2622 2623 smp_cpus++; 2624 2625 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", PCPU_GET(cpuid)); 2626 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid)); 2627 2628 /* Build our map of 'other' CPUs. */ 2629 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 2630 2631 if (bootverbose) 2632 apic_dump("ap_init()"); 2633 2634 if (smp_cpus == mp_ncpus) { 2635 /* enable IPI's, tlb shootdown, freezes etc */ 2636 atomic_store_rel_int(&smp_started, 1); 2637 smp_active = 1; /* historic */ 2638 } 2639 2640 mtx_unlock_spin(&ap_boot_mtx); 2641 2642 /* wait until all the AP's are up */ 2643 while (smp_started == 0) 2644 ia32_pause(); 2645 2646 /* ok, now grab sched_lock and enter the scheduler */ 2647 mtx_lock_spin(&sched_lock); 2648 2649 binuptime(PCPU_PTR(switchtime)); 2650 PCPU_SET(switchticks, ticks); 2651 2652 cpu_throw(NULL, choosethread()); /* doesn't return */ 2653 2654 panic("scheduler returned us to %s", __func__); 2655} 2656 2657/* 2658 * For statclock, we send an IPI to all CPU's to have them call this 2659 * function. 2660 * 2661 * WARNING! unpend() will call statclock() directly and skip this 2662 * routine. 2663 */ 2664void 2665forwarded_statclock(struct clockframe frame) 2666{ 2667 2668 if (profprocs != 0) 2669 profclock(&frame); 2670 if (pscnt == psdiv) 2671 statclock(&frame); 2672} 2673 2674void 2675forward_statclock(void) 2676{ 2677 int map; 2678 2679 CTR0(KTR_SMP, "forward_statclock"); 2680 2681 if (!smp_started || cold || panicstr) 2682 return; 2683 2684 map = PCPU_GET(other_cpus) & ~(stopped_cpus|hlt_cpus_mask); 2685 if (map != 0) 2686 ipi_selected(map, IPI_STATCLOCK); 2687} 2688 2689/* 2690 * For each hardclock(), we send an IPI to all other CPU's to have them 2691 * execute this function. It would be nice to reduce contention on 2692 * sched_lock if we could simply peek at the CPU to determine the user/kernel 2693 * state and call hardclock_process() on the CPU receiving the clock interrupt 2694 * and then just use a simple IPI to handle any ast's if needed. 2695 * 2696 * WARNING! unpend() will call hardclock_process() directly and skip this 2697 * routine. 2698 */ 2699void 2700forwarded_hardclock(struct clockframe frame) 2701{ 2702 2703 hardclock_process(&frame); 2704} 2705 2706void 2707forward_hardclock(void) 2708{ 2709 u_int map; 2710 2711 CTR0(KTR_SMP, "forward_hardclock"); 2712 2713 if (!smp_started || cold || panicstr) 2714 return; 2715 2716 map = PCPU_GET(other_cpus) & ~(stopped_cpus|hlt_cpus_mask); 2717 if (map != 0) 2718 ipi_selected(map, IPI_HARDCLOCK); 2719} 2720 2721#ifdef APIC_INTR_REORDER 2722/* 2723 * Maintain mapping from softintr vector to isr bit in local apic. 2724 */ 2725void 2726set_lapic_isrloc(int intr, int vector) 2727{ 2728 if (intr < 0 || intr > 32) 2729 panic("set_apic_isrloc: bad intr argument: %d",intr); 2730 if (vector < ICU_OFFSET || vector > 255) 2731 panic("set_apic_isrloc: bad vector argument: %d",vector); 2732 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2); 2733 apic_isrbit_location[intr].bit = (1<<(vector & 31)); 2734} 2735#endif 2736 2737/* 2738 * send an IPI to a set of cpus. 2739 */ 2740void 2741ipi_selected(u_int32_t cpus, u_int ipi) 2742{ 2743 2744 CTR3(KTR_SMP, "%s: cpus: %x ipi: %x", __func__, cpus, ipi); 2745 selected_apic_ipi(cpus, ipi, APIC_DELMODE_FIXED); 2746} 2747 2748/* 2749 * send an IPI INTerrupt containing 'vector' to all CPUs, including myself 2750 */ 2751void 2752ipi_all(u_int ipi) 2753{ 2754 2755 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 2756 apic_ipi(APIC_DEST_ALLISELF, ipi, APIC_DELMODE_FIXED); 2757} 2758 2759/* 2760 * send an IPI to all CPUs EXCEPT myself 2761 */ 2762void 2763ipi_all_but_self(u_int ipi) 2764{ 2765 2766 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 2767 apic_ipi(APIC_DEST_ALLESELF, ipi, APIC_DELMODE_FIXED); 2768} 2769 2770/* 2771 * send an IPI to myself 2772 */ 2773void 2774ipi_self(u_int ipi) 2775{ 2776 2777 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 2778 apic_ipi(APIC_DEST_SELF, ipi, APIC_DELMODE_FIXED); 2779} 2780 2781static void 2782release_aps(void *dummy __unused) 2783{ 2784 2785 if (mp_ncpus == 1) 2786 return; 2787 mtx_lock_spin(&sched_lock); 2788 atomic_store_rel_int(&aps_ready, 1); 2789 while (smp_started == 0) 2790 ia32_pause(); 2791 mtx_unlock_spin(&sched_lock); 2792} 2793 2794SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL); 2795 2796static int 2797sysctl_hlt_cpus(SYSCTL_HANDLER_ARGS) 2798{ 2799 u_int mask; 2800 int error; 2801 2802 mask = hlt_cpus_mask; 2803 error = sysctl_handle_int(oidp, &mask, 0, req); 2804 if (error || !req->newptr) 2805 return (error); 2806 2807 if (logical_cpus_mask != 0 && 2808 (mask & logical_cpus_mask) == logical_cpus_mask) 2809 hlt_logical_cpus = 1; 2810 else 2811 hlt_logical_cpus = 0; 2812 2813 if ((mask & all_cpus) == all_cpus) 2814 mask &= ~(1<<0); 2815 hlt_cpus_mask = mask; 2816 return (error); 2817} 2818SYSCTL_PROC(_machdep, OID_AUTO, hlt_cpus, CTLTYPE_INT|CTLFLAG_RW, 2819 0, 0, sysctl_hlt_cpus, "IU", ""); 2820 2821static int 2822sysctl_hlt_logical_cpus(SYSCTL_HANDLER_ARGS) 2823{ 2824 int disable, error; 2825 2826 disable = hlt_logical_cpus; 2827 error = sysctl_handle_int(oidp, &disable, 0, req); 2828 if (error || !req->newptr) 2829 return (error); 2830 2831 if (disable) 2832 hlt_cpus_mask |= logical_cpus_mask; 2833 else 2834 hlt_cpus_mask &= ~logical_cpus_mask; 2835 2836 if ((hlt_cpus_mask & all_cpus) == all_cpus) 2837 hlt_cpus_mask &= ~(1<<0); 2838 2839 hlt_logical_cpus = disable; 2840 return (error); 2841} 2842 2843static void 2844cpu_hlt_setup(void *dummy __unused) 2845{ 2846 2847 if (logical_cpus_mask != 0) { 2848 TUNABLE_INT_FETCH("machdep.hlt_logical_cpus", 2849 &hlt_logical_cpus); 2850 sysctl_ctx_init(&logical_cpu_clist); 2851 SYSCTL_ADD_PROC(&logical_cpu_clist, 2852 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 2853 "hlt_logical_cpus", CTLTYPE_INT|CTLFLAG_RW, 0, 0, 2854 sysctl_hlt_logical_cpus, "IU", ""); 2855 SYSCTL_ADD_UINT(&logical_cpu_clist, 2856 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 2857 "logical_cpus_mask", CTLTYPE_INT|CTLFLAG_RD, 2858 &logical_cpus_mask, 0, ""); 2859 2860 if (hlt_logical_cpus) 2861 hlt_cpus_mask |= logical_cpus_mask; 2862 } 2863} 2864SYSINIT(cpu_hlt, SI_SUB_SMP, SI_ORDER_ANY, cpu_hlt_setup, NULL); 2865 2866int 2867mp_grab_cpu_hlt(void) 2868{ 2869 u_int mask = PCPU_GET(cpumask); 2870 int retval; 2871 2872 retval = mask & hlt_cpus_mask; 2873 while (mask & hlt_cpus_mask) 2874 __asm __volatile("sti; hlt" : : : "memory"); 2875 return (retval); 2876} 2877