mptable.c revision 112993
1/* 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: head/sys/i386/i386/mptable.c 112993 2003-04-02 23:53:30Z peter $ 26 */ 27 28#include "opt_cpu.h" 29#include "opt_kstack_pages.h" 30#include "opt_swtch.h" 31 32#ifdef SMP 33#include <machine/smptests.h> 34#else 35#error 36#endif 37 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/bus.h> 41#include <sys/cons.h> /* cngetc() */ 42#ifdef GPROF 43#include <sys/gmon.h> 44#endif 45#include <sys/kernel.h> 46#include <sys/ktr.h> 47#include <sys/lock.h> 48#include <sys/malloc.h> 49#include <sys/memrange.h> 50#include <sys/mutex.h> 51#include <sys/pcpu.h> 52#include <sys/proc.h> 53#include <sys/smp.h> 54#include <sys/sysctl.h> 55#include <sys/user.h> 56 57#include <vm/vm.h> 58#include <vm/vm_param.h> 59#include <vm/pmap.h> 60#include <vm/vm_kern.h> 61#include <vm/vm_extern.h> 62#include <vm/vm_map.h> 63 64#include <machine/apic.h> 65#include <machine/atomic.h> 66#include <machine/clock.h> 67#include <machine/cpu.h> 68#include <machine/cpufunc.h> 69#include <machine/mpapic.h> 70#include <machine/psl.h> 71#include <machine/segments.h> 72#include <machine/smp.h> 73#include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */ 74#include <machine/tss.h> 75#include <machine/specialreg.h> 76#include <machine/privatespace.h> 77 78#if defined(APIC_IO) 79#include <machine/md_var.h> /* setidt() */ 80#include <i386/isa/icu.h> /* IPIs */ 81#include <i386/isa/intr_machdep.h> /* IPIs */ 82#endif /* APIC_IO */ 83 84#if defined(TEST_DEFAULT_CONFIG) 85#define MPFPS_MPFB1 TEST_DEFAULT_CONFIG 86#else 87#define MPFPS_MPFB1 mpfps->mpfb1 88#endif /* TEST_DEFAULT_CONFIG */ 89 90#define WARMBOOT_TARGET 0 91#define WARMBOOT_OFF (KERNBASE + 0x0467) 92#define WARMBOOT_SEG (KERNBASE + 0x0469) 93 94#ifdef PC98 95#define BIOS_BASE (0xe8000) 96#define BIOS_SIZE (0x18000) 97#else 98#define BIOS_BASE (0xf0000) 99#define BIOS_SIZE (0x10000) 100#endif 101#define BIOS_COUNT (BIOS_SIZE/4) 102 103#define CMOS_REG (0x70) 104#define CMOS_DATA (0x71) 105#define BIOS_RESET (0x0f) 106#define BIOS_WARM (0x0a) 107 108#define PROCENTRY_FLAG_EN 0x01 109#define PROCENTRY_FLAG_BP 0x02 110#define IOAPICENTRY_FLAG_EN 0x01 111 112 113/* MP Floating Pointer Structure */ 114typedef struct MPFPS { 115 char signature[4]; 116 void *pap; 117 u_char length; 118 u_char spec_rev; 119 u_char checksum; 120 u_char mpfb1; 121 u_char mpfb2; 122 u_char mpfb3; 123 u_char mpfb4; 124 u_char mpfb5; 125} *mpfps_t; 126 127/* MP Configuration Table Header */ 128typedef struct MPCTH { 129 char signature[4]; 130 u_short base_table_length; 131 u_char spec_rev; 132 u_char checksum; 133 u_char oem_id[8]; 134 u_char product_id[12]; 135 void *oem_table_pointer; 136 u_short oem_table_size; 137 u_short entry_count; 138 void *apic_address; 139 u_short extended_table_length; 140 u_char extended_table_checksum; 141 u_char reserved; 142} *mpcth_t; 143 144 145typedef struct PROCENTRY { 146 u_char type; 147 u_char apic_id; 148 u_char apic_version; 149 u_char cpu_flags; 150 u_long cpu_signature; 151 u_long feature_flags; 152 u_long reserved1; 153 u_long reserved2; 154} *proc_entry_ptr; 155 156typedef struct BUSENTRY { 157 u_char type; 158 u_char bus_id; 159 char bus_type[6]; 160} *bus_entry_ptr; 161 162typedef struct IOAPICENTRY { 163 u_char type; 164 u_char apic_id; 165 u_char apic_version; 166 u_char apic_flags; 167 void *apic_address; 168} *io_apic_entry_ptr; 169 170typedef struct INTENTRY { 171 u_char type; 172 u_char int_type; 173 u_short int_flags; 174 u_char src_bus_id; 175 u_char src_bus_irq; 176 u_char dst_apic_id; 177 u_char dst_apic_int; 178} *int_entry_ptr; 179 180/* descriptions of MP basetable entries */ 181typedef struct BASETABLE_ENTRY { 182 u_char type; 183 u_char length; 184 char name[16]; 185} basetable_entry; 186 187/* 188 * this code MUST be enabled here and in mpboot.s. 189 * it follows the very early stages of AP boot by placing values in CMOS ram. 190 * it NORMALLY will never be needed and thus the primitive method for enabling. 191 * 192#define CHECK_POINTS 193 */ 194 195#if defined(CHECK_POINTS) && !defined(PC98) 196#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 197#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 198 199#define CHECK_INIT(D); \ 200 CHECK_WRITE(0x34, (D)); \ 201 CHECK_WRITE(0x35, (D)); \ 202 CHECK_WRITE(0x36, (D)); \ 203 CHECK_WRITE(0x37, (D)); \ 204 CHECK_WRITE(0x38, (D)); \ 205 CHECK_WRITE(0x39, (D)); 206 207#define CHECK_PRINT(S); \ 208 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 209 (S), \ 210 CHECK_READ(0x34), \ 211 CHECK_READ(0x35), \ 212 CHECK_READ(0x36), \ 213 CHECK_READ(0x37), \ 214 CHECK_READ(0x38), \ 215 CHECK_READ(0x39)); 216 217#else /* CHECK_POINTS */ 218 219#define CHECK_INIT(D) 220#define CHECK_PRINT(S) 221 222#endif /* CHECK_POINTS */ 223 224/* 225 * Values to send to the POST hardware. 226 */ 227#define MP_BOOTADDRESS_POST 0x10 228#define MP_PROBE_POST 0x11 229#define MPTABLE_PASS1_POST 0x12 230 231#define MP_START_POST 0x13 232#define MP_ENABLE_POST 0x14 233#define MPTABLE_PASS2_POST 0x15 234 235#define START_ALL_APS_POST 0x16 236#define INSTALL_AP_TRAMP_POST 0x17 237#define START_AP_POST 0x18 238 239#define MP_ANNOUNCE_POST 0x19 240 241static int need_hyperthreading_fixup; 242static u_int logical_cpus; 243static u_int logical_cpus_mask; 244 245/* used to hold the AP's until we are ready to release them */ 246static struct mtx ap_boot_mtx; 247 248/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ 249int current_postcode; 250 251/** XXX FIXME: what system files declare these??? */ 252extern struct region_descriptor r_gdt, r_idt; 253 254int bsp_apic_ready = 0; /* flags useability of BSP apic */ 255int mp_naps; /* # of Applications processors */ 256int mp_nbusses; /* # of busses */ 257int mp_napics; /* # of IO APICs */ 258int boot_cpu_id; /* designated BSP */ 259vm_offset_t cpu_apic_address; 260vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */ 261extern int nkpt; 262 263u_int32_t cpu_apic_versions[MAXCPU]; 264u_int32_t *io_apic_versions; 265 266#ifdef APIC_INTR_REORDER 267struct { 268 volatile int *location; 269 int bit; 270} apic_isrbit_location[32]; 271#endif 272 273struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE]; 274 275/* 276 * APIC ID logical/physical mapping structures. 277 * We oversize these to simplify boot-time config. 278 */ 279int cpu_num_to_apic_id[NAPICID]; 280int io_num_to_apic_id[NAPICID]; 281int apic_id_to_logical[NAPICID]; 282 283 284/* AP uses this during bootstrap. Do not staticize. */ 285char *bootSTK; 286static int bootAP; 287 288/* Hotwire a 0->4MB V==P mapping */ 289extern pt_entry_t *KPTphys; 290 291/* SMP page table page */ 292extern pt_entry_t *SMPpt; 293 294struct pcb stoppcbs[MAXCPU]; 295 296#ifdef APIC_IO 297/* Variables needed for SMP tlb shootdown. */ 298vm_offset_t smp_tlb_addr1; 299vm_offset_t smp_tlb_addr2; 300volatile int smp_tlb_wait; 301static struct mtx smp_tlb_mtx; 302#endif 303 304/* 305 * Local data and functions. 306 */ 307 308/* Set to 1 once we're ready to let the APs out of the pen. */ 309static volatile int aps_ready = 0; 310 311static int mp_capable; 312static u_int boot_address; 313static u_int base_memory; 314 315static int picmode; /* 0: virtual wire mode, 1: PIC mode */ 316static mpfps_t mpfps; 317static int search_for_sig(u_int32_t target, int count); 318static void mp_enable(u_int boot_addr); 319 320static void mptable_hyperthread_fixup(u_int id_mask); 321static void mptable_pass1(void); 322static int mptable_pass2(void); 323static void default_mp_table(int type); 324static void fix_mp_table(void); 325static void setup_apic_irq_mapping(void); 326static void init_locks(void); 327static int start_all_aps(u_int boot_addr); 328static void install_ap_tramp(u_int boot_addr); 329static int start_ap(int logicalCpu, u_int boot_addr); 330void ap_init(void); 331static int apic_int_is_bus_type(int intr, int bus_type); 332static void release_aps(void *dummy); 333 334/* 335 * initialize all the SMP locks 336 */ 337 338/* lock region used by kernel profiling */ 339int mcount_lock; 340 341#ifdef USE_COMLOCK 342/* locks com (tty) data/hardware accesses: a FASTINTR() */ 343struct mtx com_mtx; 344#endif /* USE_COMLOCK */ 345 346static void 347init_locks(void) 348{ 349 350#ifdef USE_COMLOCK 351 mtx_init(&com_mtx, "com", NULL, MTX_SPIN); 352#endif /* USE_COMLOCK */ 353#ifdef APIC_IO 354 mtx_init(&smp_tlb_mtx, "tlb", NULL, MTX_SPIN); 355#endif 356} 357 358/* 359 * Calculate usable address in base memory for AP trampoline code. 360 */ 361u_int 362mp_bootaddress(u_int basemem) 363{ 364 POSTCODE(MP_BOOTADDRESS_POST); 365 366 base_memory = basemem * 1024; /* convert to bytes */ 367 368 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ 369 if ((base_memory - boot_address) < bootMP_size) 370 boot_address -= 4096; /* not enough, lower by 4k */ 371 372 return boot_address; 373} 374 375 376/* 377 * Look for an Intel MP spec table (ie, SMP capable hardware). 378 */ 379void 380i386_mp_probe(void) 381{ 382 int x; 383 u_long segment; 384 u_int32_t target; 385 386 POSTCODE(MP_PROBE_POST); 387 388 /* see if EBDA exists */ 389 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) { 390 /* search first 1K of EBDA */ 391 target = (u_int32_t) (segment << 4); 392 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 393 goto found; 394 } else { 395 /* last 1K of base memory, effective 'top of base' passed in */ 396 target = (u_int32_t) (base_memory - 0x400); 397 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 398 goto found; 399 } 400 401 /* search the BIOS */ 402 target = (u_int32_t) BIOS_BASE; 403 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) 404 goto found; 405 406 /* nothing found */ 407 mpfps = (mpfps_t)0; 408 mp_capable = 0; 409 return; 410 411found: 412 /* calculate needed resources */ 413 mpfps = (mpfps_t)x; 414 mptable_pass1(); 415 416 /* flag fact that we are running multiple processors */ 417 mp_capable = 1; 418} 419 420int 421cpu_mp_probe(void) 422{ 423 /* 424 * Record BSP in CPU map 425 * This is done here so that MBUF init code works correctly. 426 */ 427 all_cpus = 1; 428 429 return (mp_capable); 430} 431 432/* 433 * Initialize the SMP hardware and the APIC and start up the AP's. 434 */ 435void 436cpu_mp_start(void) 437{ 438 POSTCODE(MP_START_POST); 439 440 /* look for MP capable motherboard */ 441 if (mp_capable) 442 mp_enable(boot_address); 443 else 444 panic("MP hardware not found!"); 445 446 cpu_setregs(); 447} 448 449 450/* 451 * Print various information about the SMP system hardware and setup. 452 */ 453void 454cpu_mp_announce(void) 455{ 456 int x; 457 458 POSTCODE(MP_ANNOUNCE_POST); 459 460 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0)); 461 printf(", version: 0x%08x", cpu_apic_versions[0]); 462 printf(", at 0x%08x\n", cpu_apic_address); 463 for (x = 1; x <= mp_naps; ++x) { 464 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x)); 465 printf(", version: 0x%08x", cpu_apic_versions[x]); 466 printf(", at 0x%08x\n", cpu_apic_address); 467 } 468 469#if defined(APIC_IO) 470 for (x = 0; x < mp_napics; ++x) { 471 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x)); 472 printf(", version: 0x%08x", io_apic_versions[x]); 473 printf(", at 0x%08x\n", io_apic_address[x]); 474 } 475#else 476 printf(" Warning: APIC I/O disabled\n"); 477#endif /* APIC_IO */ 478} 479 480/* 481 * AP cpu's call this to sync up protected mode. 482 */ 483void 484init_secondary(void) 485{ 486 int gsel_tss; 487 int x, myid = bootAP; 488 u_int cr0; 489 490 gdt_segs[GPRIV_SEL].ssd_base = (int) &SMP_prvspace[myid]; 491 gdt_segs[GPROC0_SEL].ssd_base = 492 (int) &SMP_prvspace[myid].pcpu.pc_common_tss; 493 SMP_prvspace[myid].pcpu.pc_prvspace = 494 &SMP_prvspace[myid].pcpu; 495 496 for (x = 0; x < NGDT; x++) { 497 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd); 498 } 499 500 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 501 r_gdt.rd_base = (int) &gdt[myid * NGDT]; 502 lgdt(&r_gdt); /* does magic intra-segment return */ 503 504 lidt(&r_idt); 505 506 lldt(_default_ldt); 507 PCPU_SET(currentldt, _default_ldt); 508 509 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 510 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS; 511 PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */ 512 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL)); 513 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16); 514 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd); 515 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt)); 516 ltr(gsel_tss); 517 518 /* 519 * Set to a known state: 520 * Set by mpboot.s: CR0_PG, CR0_PE 521 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM 522 */ 523 cr0 = rcr0(); 524 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM); 525 load_cr0(cr0); 526 527 pmap_set_opt(); 528} 529 530 531#if defined(APIC_IO) 532/* 533 * Final configuration of the BSP's local APIC: 534 * - disable 'pic mode'. 535 * - disable 'virtual wire mode'. 536 * - enable NMI. 537 */ 538void 539bsp_apic_configure(void) 540{ 541 u_char byte; 542 u_int32_t temp; 543 544 /* leave 'pic mode' if necessary */ 545 if (picmode) { 546 outb(0x22, 0x70); /* select IMCR */ 547 byte = inb(0x23); /* current contents */ 548 byte |= 0x01; /* mask external INTR */ 549 outb(0x23, byte); /* disconnect 8259s/NMI */ 550 } 551 552 /* mask lint0 (the 8259 'virtual wire' connection) */ 553 temp = lapic.lvt_lint0; 554 temp |= APIC_LVT_M; /* set the mask */ 555 lapic.lvt_lint0 = temp; 556 557 /* setup lint1 to handle NMI */ 558 temp = lapic.lvt_lint1; 559 temp &= ~APIC_LVT_M; /* clear the mask */ 560 lapic.lvt_lint1 = temp; 561 562 if (bootverbose) 563 apic_dump("bsp_apic_configure()"); 564} 565#endif /* APIC_IO */ 566 567 568/******************************************************************* 569 * local functions and data 570 */ 571 572/* 573 * start the SMP system 574 */ 575static void 576mp_enable(u_int boot_addr) 577{ 578 int x; 579#if defined(APIC_IO) 580 int apic; 581 u_int ux; 582#endif /* APIC_IO */ 583 584 POSTCODE(MP_ENABLE_POST); 585 586 /* turn on 4MB of V == P addressing so we can get to MP table */ 587 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME); 588 invltlb(); 589 590 /* examine the MP table for needed info, uses physical addresses */ 591 x = mptable_pass2(); 592 593 *(int *)PTD = 0; 594 invltlb(); 595 596 /* can't process default configs till the CPU APIC is pmapped */ 597 if (x) 598 default_mp_table(x); 599 600 /* post scan cleanup */ 601 fix_mp_table(); 602 setup_apic_irq_mapping(); 603 604#if defined(APIC_IO) 605 606 /* fill the LOGICAL io_apic_versions table */ 607 for (apic = 0; apic < mp_napics; ++apic) { 608 ux = io_apic_read(apic, IOAPIC_VER); 609 io_apic_versions[apic] = ux; 610 io_apic_set_id(apic, IO_TO_ID(apic)); 611 } 612 613 /* program each IO APIC in the system */ 614 for (apic = 0; apic < mp_napics; ++apic) 615 if (io_apic_setup(apic) < 0) 616 panic("IO APIC setup failure"); 617 618 /* install a 'Spurious INTerrupt' vector */ 619 setidt(XSPURIOUSINT_OFFSET, Xspuriousint, 620 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 621 622 /* install an inter-CPU IPI for TLB invalidation */ 623 setidt(XINVLTLB_OFFSET, Xinvltlb, 624 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 625 setidt(XINVLPG_OFFSET, Xinvlpg, 626 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 627 setidt(XINVLRNG_OFFSET, Xinvlrng, 628 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 629 630 /* install an inter-CPU IPI for forwarding hardclock() */ 631 setidt(XHARDCLOCK_OFFSET, Xhardclock, 632 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 633 634 /* install an inter-CPU IPI for forwarding statclock() */ 635 setidt(XSTATCLOCK_OFFSET, Xstatclock, 636 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 637 638#ifdef LAZY_SWITCH 639 /* install an inter-CPU IPI for lazy pmap release */ 640 setidt(XLAZYPMAP_OFFSET, Xlazypmap, 641 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 642#endif 643 644 /* install an inter-CPU IPI for all-CPU rendezvous */ 645 setidt(XRENDEZVOUS_OFFSET, Xrendezvous, 646 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 647 648 /* install an inter-CPU IPI for forcing an additional software trap */ 649 setidt(XCPUAST_OFFSET, Xcpuast, 650 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 651 652 /* install an inter-CPU IPI for CPU stop/restart */ 653 setidt(XCPUSTOP_OFFSET, Xcpustop, 654 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 655 656#if defined(TEST_TEST1) 657 /* install a "fake hardware INTerrupt" vector */ 658 setidt(XTEST1_OFFSET, Xtest1, 659 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 660#endif /** TEST_TEST1 */ 661 662#endif /* APIC_IO */ 663 664 /* initialize all SMP locks */ 665 init_locks(); 666 667 /* start each Application Processor */ 668 start_all_aps(boot_addr); 669} 670 671 672/* 673 * look for the MP spec signature 674 */ 675 676/* string defined by the Intel MP Spec as identifying the MP table */ 677#define MP_SIG 0x5f504d5f /* _MP_ */ 678#define NEXT(X) ((X) += 4) 679static int 680search_for_sig(u_int32_t target, int count) 681{ 682 int x; 683 u_int32_t *addr = (u_int32_t *) (KERNBASE + target); 684 685 for (x = 0; x < count; NEXT(x)) 686 if (addr[x] == MP_SIG) 687 /* make array index a byte index */ 688 return (target + (x * sizeof(u_int32_t))); 689 690 return -1; 691} 692 693 694static basetable_entry basetable_entry_types[] = 695{ 696 {0, 20, "Processor"}, 697 {1, 8, "Bus"}, 698 {2, 8, "I/O APIC"}, 699 {3, 8, "I/O INT"}, 700 {4, 8, "Local INT"} 701}; 702 703typedef struct BUSDATA { 704 u_char bus_id; 705 enum busTypes bus_type; 706} bus_datum; 707 708typedef struct INTDATA { 709 u_char int_type; 710 u_short int_flags; 711 u_char src_bus_id; 712 u_char src_bus_irq; 713 u_char dst_apic_id; 714 u_char dst_apic_int; 715 u_char int_vector; 716} io_int, local_int; 717 718typedef struct BUSTYPENAME { 719 u_char type; 720 char name[7]; 721} bus_type_name; 722 723static bus_type_name bus_type_table[] = 724{ 725 {CBUS, "CBUS"}, 726 {CBUSII, "CBUSII"}, 727 {EISA, "EISA"}, 728 {MCA, "MCA"}, 729 {UNKNOWN_BUSTYPE, "---"}, 730 {ISA, "ISA"}, 731 {MCA, "MCA"}, 732 {UNKNOWN_BUSTYPE, "---"}, 733 {UNKNOWN_BUSTYPE, "---"}, 734 {UNKNOWN_BUSTYPE, "---"}, 735 {UNKNOWN_BUSTYPE, "---"}, 736 {UNKNOWN_BUSTYPE, "---"}, 737 {PCI, "PCI"}, 738 {UNKNOWN_BUSTYPE, "---"}, 739 {UNKNOWN_BUSTYPE, "---"}, 740 {UNKNOWN_BUSTYPE, "---"}, 741 {UNKNOWN_BUSTYPE, "---"}, 742 {XPRESS, "XPRESS"}, 743 {UNKNOWN_BUSTYPE, "---"} 744}; 745/* from MP spec v1.4, table 5-1 */ 746static int default_data[7][5] = 747{ 748/* nbus, id0, type0, id1, type1 */ 749 {1, 0, ISA, 255, 255}, 750 {1, 0, EISA, 255, 255}, 751 {1, 0, EISA, 255, 255}, 752 {1, 0, MCA, 255, 255}, 753 {2, 0, ISA, 1, PCI}, 754 {2, 0, EISA, 1, PCI}, 755 {2, 0, MCA, 1, PCI} 756}; 757 758 759/* the bus data */ 760static bus_datum *bus_data; 761 762/* the IO INT data, one entry per possible APIC INTerrupt */ 763static io_int *io_apic_ints; 764 765static int nintrs; 766 767static int processor_entry(proc_entry_ptr entry, int cpu); 768static int bus_entry(bus_entry_ptr entry, int bus); 769static int io_apic_entry(io_apic_entry_ptr entry, int apic); 770static int int_entry(int_entry_ptr entry, int intr); 771static int lookup_bus_type(char *name); 772 773 774/* 775 * 1st pass on motherboard's Intel MP specification table. 776 * 777 * initializes: 778 * mp_ncpus = 1 779 * 780 * determines: 781 * cpu_apic_address (common to all CPUs) 782 * io_apic_address[N] 783 * mp_naps 784 * mp_nbusses 785 * mp_napics 786 * nintrs 787 */ 788static void 789mptable_pass1(void) 790{ 791 int x; 792 mpcth_t cth; 793 int totalSize; 794 void* position; 795 int count; 796 int type; 797 u_int id_mask; 798 799 POSTCODE(MPTABLE_PASS1_POST); 800 801 /* clear various tables */ 802 for (x = 0; x < NAPICID; ++x) { 803 io_apic_address[x] = ~0; /* IO APIC address table */ 804 } 805 806 /* init everything to empty */ 807 mp_naps = 0; 808 mp_nbusses = 0; 809 mp_napics = 0; 810 nintrs = 0; 811 id_mask = 0; 812 813 /* check for use of 'default' configuration */ 814 if (MPFPS_MPFB1 != 0) { 815 /* use default addresses */ 816 cpu_apic_address = DEFAULT_APIC_BASE; 817 io_apic_address[0] = DEFAULT_IO_APIC_BASE; 818 819 /* fill in with defaults */ 820 mp_naps = 2; /* includes BSP */ 821 mp_maxid = 1; 822 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0]; 823#if defined(APIC_IO) 824 mp_napics = 1; 825 nintrs = 16; 826#endif /* APIC_IO */ 827 } 828 else { 829 if ((cth = mpfps->pap) == 0) 830 panic("MP Configuration Table Header MISSING!"); 831 832 cpu_apic_address = (vm_offset_t) cth->apic_address; 833 834 /* walk the table, recording info of interest */ 835 totalSize = cth->base_table_length - sizeof(struct MPCTH); 836 position = (u_char *) cth + sizeof(struct MPCTH); 837 count = cth->entry_count; 838 839 while (count--) { 840 switch (type = *(u_char *) position) { 841 case 0: /* processor_entry */ 842 if (((proc_entry_ptr)position)->cpu_flags 843 & PROCENTRY_FLAG_EN) { 844 ++mp_naps; 845 mp_maxid++; 846 id_mask |= 1 << 847 ((proc_entry_ptr)position)->apic_id; 848 } 849 break; 850 case 1: /* bus_entry */ 851 ++mp_nbusses; 852 break; 853 case 2: /* io_apic_entry */ 854 if (((io_apic_entry_ptr)position)->apic_flags 855 & IOAPICENTRY_FLAG_EN) 856 io_apic_address[mp_napics++] = 857 (vm_offset_t)((io_apic_entry_ptr) 858 position)->apic_address; 859 break; 860 case 3: /* int_entry */ 861 ++nintrs; 862 break; 863 case 4: /* int_entry */ 864 break; 865 default: 866 panic("mpfps Base Table HOSED!"); 867 /* NOTREACHED */ 868 } 869 870 totalSize -= basetable_entry_types[type].length; 871 (u_char*)position += basetable_entry_types[type].length; 872 } 873 } 874 875 /* qualify the numbers */ 876 if (mp_naps > MAXCPU) { 877 printf("Warning: only using %d of %d available CPUs!\n", 878 MAXCPU, mp_naps); 879 mp_naps = MAXCPU; 880 } 881 882 /* See if we need to fixup HT logical CPUs. */ 883 mptable_hyperthread_fixup(id_mask); 884 885 /* 886 * Count the BSP. 887 * This is also used as a counter while starting the APs. 888 */ 889 mp_ncpus = 1; 890 891 --mp_naps; /* subtract the BSP */ 892} 893 894 895/* 896 * 2nd pass on motherboard's Intel MP specification table. 897 * 898 * sets: 899 * boot_cpu_id 900 * ID_TO_IO(N), phy APIC ID to log CPU/IO table 901 * CPU_TO_ID(N), logical CPU to APIC ID table 902 * IO_TO_ID(N), logical IO to APIC ID table 903 * bus_data[N] 904 * io_apic_ints[N] 905 */ 906static int 907mptable_pass2(void) 908{ 909 struct PROCENTRY proc; 910 int x; 911 mpcth_t cth; 912 int totalSize; 913 void* position; 914 int count; 915 int type; 916 int apic, bus, cpu, intr; 917 int i, j; 918 int pgeflag; 919 920 POSTCODE(MPTABLE_PASS2_POST); 921 922 /* Initialize fake proc entry for use with HT fixup. */ 923 bzero(&proc, sizeof(proc)); 924 proc.type = 0; 925 proc.cpu_flags = PROCENTRY_FLAG_EN; 926 927 pgeflag = 0; /* XXX - Not used under SMP yet. */ 928 929 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics, 930 M_DEVBUF, M_WAITOK); 931 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics, 932 M_DEVBUF, M_WAITOK); 933 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + 1), 934 M_DEVBUF, M_WAITOK); 935 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses, 936 M_DEVBUF, M_WAITOK); 937 938 bzero(ioapic, sizeof(ioapic_t *) * mp_napics); 939 940 for (i = 0; i < mp_napics; i++) { 941 for (j = 0; j < mp_napics; j++) { 942 /* same page frame as a previous IO apic? */ 943 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) == 944 (io_apic_address[i] & PG_FRAME)) { 945 ioapic[i] = (ioapic_t *)((u_int)SMP_prvspace 946 + (NPTEPG-2-j) * PAGE_SIZE 947 + (io_apic_address[i] & PAGE_MASK)); 948 break; 949 } 950 /* use this slot if available */ 951 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) == 0) { 952 SMPpt[NPTEPG-2-j] = (pt_entry_t)(PG_V | PG_RW | 953 pgeflag | (io_apic_address[i] & PG_FRAME)); 954 ioapic[i] = (ioapic_t *)((u_int)SMP_prvspace 955 + (NPTEPG-2-j) * PAGE_SIZE 956 + (io_apic_address[i] & PAGE_MASK)); 957 break; 958 } 959 } 960 } 961 962 /* clear various tables */ 963 for (x = 0; x < NAPICID; ++x) { 964 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */ 965 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */ 966 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */ 967 } 968 969 /* clear bus data table */ 970 for (x = 0; x < mp_nbusses; ++x) 971 bus_data[x].bus_id = 0xff; 972 973 /* clear IO APIC INT table */ 974 for (x = 0; x < (nintrs + 1); ++x) { 975 io_apic_ints[x].int_type = 0xff; 976 io_apic_ints[x].int_vector = 0xff; 977 } 978 979 /* setup the cpu/apic mapping arrays */ 980 boot_cpu_id = -1; 981 982 /* record whether PIC or virtual-wire mode */ 983 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0; 984 985 /* check for use of 'default' configuration */ 986 if (MPFPS_MPFB1 != 0) 987 return MPFPS_MPFB1; /* return default configuration type */ 988 989 if ((cth = mpfps->pap) == 0) 990 panic("MP Configuration Table Header MISSING!"); 991 992 /* walk the table, recording info of interest */ 993 totalSize = cth->base_table_length - sizeof(struct MPCTH); 994 position = (u_char *) cth + sizeof(struct MPCTH); 995 count = cth->entry_count; 996 apic = bus = intr = 0; 997 cpu = 1; /* pre-count the BSP */ 998 999 while (count--) { 1000 switch (type = *(u_char *) position) { 1001 case 0: 1002 if (processor_entry(position, cpu)) 1003 ++cpu; 1004 1005 if (need_hyperthreading_fixup) { 1006 /* 1007 * Create fake mptable processor entries 1008 * and feed them to processor_entry() to 1009 * enumerate the logical CPUs. 1010 */ 1011 proc.apic_id = ((proc_entry_ptr)position)->apic_id; 1012 for (i = 1; i < logical_cpus; i++) { 1013 proc.apic_id++; 1014 (void)processor_entry(&proc, cpu); 1015 logical_cpus_mask |= (1 << cpu); 1016 cpu++; 1017 } 1018 } 1019 break; 1020 case 1: 1021 if (bus_entry(position, bus)) 1022 ++bus; 1023 break; 1024 case 2: 1025 if (io_apic_entry(position, apic)) 1026 ++apic; 1027 break; 1028 case 3: 1029 if (int_entry(position, intr)) 1030 ++intr; 1031 break; 1032 case 4: 1033 /* int_entry(position); */ 1034 break; 1035 default: 1036 panic("mpfps Base Table HOSED!"); 1037 /* NOTREACHED */ 1038 } 1039 1040 totalSize -= basetable_entry_types[type].length; 1041 (u_char *) position += basetable_entry_types[type].length; 1042 } 1043 1044 if (boot_cpu_id == -1) 1045 panic("NO BSP found!"); 1046 1047 /* report fact that its NOT a default configuration */ 1048 return 0; 1049} 1050 1051/* 1052 * Check if we should perform a hyperthreading "fix-up" to 1053 * enumerate any logical CPU's that aren't already listed 1054 * in the table. 1055 * 1056 * XXX: We assume that all of the physical CPUs in the 1057 * system have the same number of logical CPUs. 1058 * 1059 * XXX: We assume that APIC ID's are allocated such that 1060 * the APIC ID's for a physical processor are aligned 1061 * with the number of logical CPU's in the processor. 1062 */ 1063static void 1064mptable_hyperthread_fixup(u_int id_mask) 1065{ 1066 u_int i, id; 1067 1068 /* Nothing to do if there is no HTT support. */ 1069 if ((cpu_feature & CPUID_HTT) == 0) 1070 return; 1071 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 1072 if (logical_cpus <= 1) 1073 return; 1074 1075 /* 1076 * For each APIC ID of a CPU that is set in the mask, 1077 * scan the other candidate APIC ID's for this 1078 * physical processor. If any of those ID's are 1079 * already in the table, then kill the fixup. 1080 */ 1081 for (id = 0; id <= MAXCPU; id++) { 1082 if ((id_mask & 1 << id) == 0) 1083 continue; 1084 /* First, make sure we are on a logical_cpus boundary. */ 1085 if (id % logical_cpus != 0) 1086 return; 1087 for (i = id + 1; i < id + logical_cpus; i++) 1088 if ((id_mask & 1 << i) != 0) 1089 return; 1090 } 1091 1092 /* 1093 * Ok, the ID's checked out, so enable the fixup. We have to fixup 1094 * mp_naps and mp_maxid right now. 1095 */ 1096 need_hyperthreading_fixup = 1; 1097 mp_maxid *= logical_cpus; 1098 mp_naps *= logical_cpus; 1099} 1100 1101void 1102assign_apic_irq(int apic, int intpin, int irq) 1103{ 1104 int x; 1105 1106 if (int_to_apicintpin[irq].ioapic != -1) 1107 panic("assign_apic_irq: inconsistent table"); 1108 1109 int_to_apicintpin[irq].ioapic = apic; 1110 int_to_apicintpin[irq].int_pin = intpin; 1111 int_to_apicintpin[irq].apic_address = ioapic[apic]; 1112 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin; 1113 1114 for (x = 0; x < nintrs; x++) { 1115 if ((io_apic_ints[x].int_type == 0 || 1116 io_apic_ints[x].int_type == 3) && 1117 io_apic_ints[x].int_vector == 0xff && 1118 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) && 1119 io_apic_ints[x].dst_apic_int == intpin) 1120 io_apic_ints[x].int_vector = irq; 1121 } 1122} 1123 1124void 1125revoke_apic_irq(int irq) 1126{ 1127 int x; 1128 int oldapic; 1129 int oldintpin; 1130 1131 if (int_to_apicintpin[irq].ioapic == -1) 1132 panic("revoke_apic_irq: inconsistent table"); 1133 1134 oldapic = int_to_apicintpin[irq].ioapic; 1135 oldintpin = int_to_apicintpin[irq].int_pin; 1136 1137 int_to_apicintpin[irq].ioapic = -1; 1138 int_to_apicintpin[irq].int_pin = 0; 1139 int_to_apicintpin[irq].apic_address = NULL; 1140 int_to_apicintpin[irq].redirindex = 0; 1141 1142 for (x = 0; x < nintrs; x++) { 1143 if ((io_apic_ints[x].int_type == 0 || 1144 io_apic_ints[x].int_type == 3) && 1145 io_apic_ints[x].int_vector != 0xff && 1146 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) && 1147 io_apic_ints[x].dst_apic_int == oldintpin) 1148 io_apic_ints[x].int_vector = 0xff; 1149 } 1150} 1151 1152 1153static void 1154allocate_apic_irq(int intr) 1155{ 1156 int apic; 1157 int intpin; 1158 int irq; 1159 1160 if (io_apic_ints[intr].int_vector != 0xff) 1161 return; /* Interrupt handler already assigned */ 1162 1163 if (io_apic_ints[intr].int_type != 0 && 1164 (io_apic_ints[intr].int_type != 3 || 1165 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) && 1166 io_apic_ints[intr].dst_apic_int == 0))) 1167 return; /* Not INT or ExtInt on != (0, 0) */ 1168 1169 irq = 0; 1170 while (irq < APIC_INTMAPSIZE && 1171 int_to_apicintpin[irq].ioapic != -1) 1172 irq++; 1173 1174 if (irq >= APIC_INTMAPSIZE) 1175 return; /* No free interrupt handlers */ 1176 1177 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id); 1178 intpin = io_apic_ints[intr].dst_apic_int; 1179 1180 assign_apic_irq(apic, intpin, irq); 1181 io_apic_setup_intpin(apic, intpin); 1182} 1183 1184 1185static void 1186swap_apic_id(int apic, int oldid, int newid) 1187{ 1188 int x; 1189 int oapic; 1190 1191 1192 if (oldid == newid) 1193 return; /* Nothing to do */ 1194 1195 printf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n", 1196 apic, oldid, newid); 1197 1198 /* Swap physical APIC IDs in interrupt entries */ 1199 for (x = 0; x < nintrs; x++) { 1200 if (io_apic_ints[x].dst_apic_id == oldid) 1201 io_apic_ints[x].dst_apic_id = newid; 1202 else if (io_apic_ints[x].dst_apic_id == newid) 1203 io_apic_ints[x].dst_apic_id = oldid; 1204 } 1205 1206 /* Swap physical APIC IDs in IO_TO_ID mappings */ 1207 for (oapic = 0; oapic < mp_napics; oapic++) 1208 if (IO_TO_ID(oapic) == newid) 1209 break; 1210 1211 if (oapic < mp_napics) { 1212 printf("Changing APIC ID for IO APIC #%d from " 1213 "%d to %d in MP table\n", 1214 oapic, newid, oldid); 1215 IO_TO_ID(oapic) = oldid; 1216 } 1217 IO_TO_ID(apic) = newid; 1218} 1219 1220 1221static void 1222fix_id_to_io_mapping(void) 1223{ 1224 int x; 1225 1226 for (x = 0; x < NAPICID; x++) 1227 ID_TO_IO(x) = -1; 1228 1229 for (x = 0; x <= mp_naps; x++) 1230 if (CPU_TO_ID(x) < NAPICID) 1231 ID_TO_IO(CPU_TO_ID(x)) = x; 1232 1233 for (x = 0; x < mp_napics; x++) 1234 if (IO_TO_ID(x) < NAPICID) 1235 ID_TO_IO(IO_TO_ID(x)) = x; 1236} 1237 1238 1239static int 1240first_free_apic_id(void) 1241{ 1242 int freeid, x; 1243 1244 for (freeid = 0; freeid < NAPICID; freeid++) { 1245 for (x = 0; x <= mp_naps; x++) 1246 if (CPU_TO_ID(x) == freeid) 1247 break; 1248 if (x <= mp_naps) 1249 continue; 1250 for (x = 0; x < mp_napics; x++) 1251 if (IO_TO_ID(x) == freeid) 1252 break; 1253 if (x < mp_napics) 1254 continue; 1255 return freeid; 1256 } 1257 return freeid; 1258} 1259 1260 1261static int 1262io_apic_id_acceptable(int apic, int id) 1263{ 1264 int cpu; /* Logical CPU number */ 1265 int oapic; /* Logical IO APIC number for other IO APIC */ 1266 1267 if (id >= NAPICID) 1268 return 0; /* Out of range */ 1269 1270 for (cpu = 0; cpu <= mp_naps; cpu++) 1271 if (CPU_TO_ID(cpu) == id) 1272 return 0; /* Conflict with CPU */ 1273 1274 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++) 1275 if (IO_TO_ID(oapic) == id) 1276 return 0; /* Conflict with other APIC */ 1277 1278 return 1; /* ID is acceptable for IO APIC */ 1279} 1280 1281 1282/* 1283 * parse an Intel MP specification table 1284 */ 1285static void 1286fix_mp_table(void) 1287{ 1288 int x; 1289 int id; 1290 int bus_0 = 0; /* Stop GCC warning */ 1291 int bus_pci = 0; /* Stop GCC warning */ 1292 int num_pci_bus; 1293 int apic; /* IO APIC unit number */ 1294 int freeid; /* Free physical APIC ID */ 1295 int physid; /* Current physical IO APIC ID */ 1296 1297 /* 1298 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS 1299 * did it wrong. The MP spec says that when more than 1 PCI bus 1300 * exists the BIOS must begin with bus entries for the PCI bus and use 1301 * actual PCI bus numbering. This implies that when only 1 PCI bus 1302 * exists the BIOS can choose to ignore this ordering, and indeed many 1303 * MP motherboards do ignore it. This causes a problem when the PCI 1304 * sub-system makes requests of the MP sub-system based on PCI bus 1305 * numbers. So here we look for the situation and renumber the 1306 * busses and associated INTs in an effort to "make it right". 1307 */ 1308 1309 /* find bus 0, PCI bus, count the number of PCI busses */ 1310 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { 1311 if (bus_data[x].bus_id == 0) { 1312 bus_0 = x; 1313 } 1314 if (bus_data[x].bus_type == PCI) { 1315 ++num_pci_bus; 1316 bus_pci = x; 1317 } 1318 } 1319 /* 1320 * bus_0 == slot of bus with ID of 0 1321 * bus_pci == slot of last PCI bus encountered 1322 */ 1323 1324 /* check the 1 PCI bus case for sanity */ 1325 /* if it is number 0 all is well */ 1326 if (num_pci_bus == 1 && 1327 bus_data[bus_pci].bus_id != 0) { 1328 1329 /* mis-numbered, swap with whichever bus uses slot 0 */ 1330 1331 /* swap the bus entry types */ 1332 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type; 1333 bus_data[bus_0].bus_type = PCI; 1334 1335 /* swap each relavant INTerrupt entry */ 1336 id = bus_data[bus_pci].bus_id; 1337 for (x = 0; x < nintrs; ++x) { 1338 if (io_apic_ints[x].src_bus_id == id) { 1339 io_apic_ints[x].src_bus_id = 0; 1340 } 1341 else if (io_apic_ints[x].src_bus_id == 0) { 1342 io_apic_ints[x].src_bus_id = id; 1343 } 1344 } 1345 } 1346 1347 /* Assign IO APIC IDs. 1348 * 1349 * First try the existing ID. If a conflict is detected, try 1350 * the ID in the MP table. If a conflict is still detected, find 1351 * a free id. 1352 * 1353 * We cannot use the ID_TO_IO table before all conflicts has been 1354 * resolved and the table has been corrected. 1355 */ 1356 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */ 1357 1358 /* First try to use the value set by the BIOS */ 1359 physid = io_apic_get_id(apic); 1360 if (io_apic_id_acceptable(apic, physid)) { 1361 if (IO_TO_ID(apic) != physid) 1362 swap_apic_id(apic, IO_TO_ID(apic), physid); 1363 continue; 1364 } 1365 1366 /* Then check if the value in the MP table is acceptable */ 1367 if (io_apic_id_acceptable(apic, IO_TO_ID(apic))) 1368 continue; 1369 1370 /* Last resort, find a free APIC ID and use it */ 1371 freeid = first_free_apic_id(); 1372 if (freeid >= NAPICID) 1373 panic("No free physical APIC IDs found"); 1374 1375 if (io_apic_id_acceptable(apic, freeid)) { 1376 swap_apic_id(apic, IO_TO_ID(apic), freeid); 1377 continue; 1378 } 1379 panic("Free physical APIC ID not usable"); 1380 } 1381 fix_id_to_io_mapping(); 1382 1383 /* detect and fix broken Compaq MP table */ 1384 if (apic_int_type(0, 0) == -1) { 1385 printf("APIC_IO: MP table broken: 8259->APIC entry missing!\n"); 1386 io_apic_ints[nintrs].int_type = 3; /* ExtInt */ 1387 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */ 1388 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */ 1389 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0); 1390 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */ 1391 nintrs++; 1392 } 1393} 1394 1395 1396/* Assign low level interrupt handlers */ 1397static void 1398setup_apic_irq_mapping(void) 1399{ 1400 int x; 1401 int int_vector; 1402 1403 /* Clear array */ 1404 for (x = 0; x < APIC_INTMAPSIZE; x++) { 1405 int_to_apicintpin[x].ioapic = -1; 1406 int_to_apicintpin[x].int_pin = 0; 1407 int_to_apicintpin[x].apic_address = NULL; 1408 int_to_apicintpin[x].redirindex = 0; 1409 } 1410 1411 /* First assign ISA/EISA interrupts */ 1412 for (x = 0; x < nintrs; x++) { 1413 int_vector = io_apic_ints[x].src_bus_irq; 1414 if (int_vector < APIC_INTMAPSIZE && 1415 io_apic_ints[x].int_vector == 0xff && 1416 int_to_apicintpin[int_vector].ioapic == -1 && 1417 (apic_int_is_bus_type(x, ISA) || 1418 apic_int_is_bus_type(x, EISA)) && 1419 io_apic_ints[x].int_type == 0) { 1420 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id), 1421 io_apic_ints[x].dst_apic_int, 1422 int_vector); 1423 } 1424 } 1425 1426 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */ 1427 for (x = 0; x < nintrs; x++) { 1428 if (io_apic_ints[x].dst_apic_int == 0 && 1429 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) && 1430 io_apic_ints[x].int_vector == 0xff && 1431 int_to_apicintpin[0].ioapic == -1 && 1432 io_apic_ints[x].int_type == 3) { 1433 assign_apic_irq(0, 0, 0); 1434 break; 1435 } 1436 } 1437 /* PCI interrupt assignment is deferred */ 1438} 1439 1440 1441static int 1442processor_entry(proc_entry_ptr entry, int cpu) 1443{ 1444 /* check for usability */ 1445 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN)) 1446 return 0; 1447 1448 if(entry->apic_id >= NAPICID) 1449 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1); 1450 /* check for BSP flag */ 1451 if (entry->cpu_flags & PROCENTRY_FLAG_BP) { 1452 boot_cpu_id = entry->apic_id; 1453 CPU_TO_ID(0) = entry->apic_id; 1454 ID_TO_CPU(entry->apic_id) = 0; 1455 return 0; /* its already been counted */ 1456 } 1457 1458 /* add another AP to list, if less than max number of CPUs */ 1459 else if (cpu < MAXCPU) { 1460 CPU_TO_ID(cpu) = entry->apic_id; 1461 ID_TO_CPU(entry->apic_id) = cpu; 1462 return 1; 1463 } 1464 1465 return 0; 1466} 1467 1468 1469static int 1470bus_entry(bus_entry_ptr entry, int bus) 1471{ 1472 int x; 1473 char c, name[8]; 1474 1475 /* encode the name into an index */ 1476 for (x = 0; x < 6; ++x) { 1477 if ((c = entry->bus_type[x]) == ' ') 1478 break; 1479 name[x] = c; 1480 } 1481 name[x] = '\0'; 1482 1483 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) 1484 panic("unknown bus type: '%s'", name); 1485 1486 bus_data[bus].bus_id = entry->bus_id; 1487 bus_data[bus].bus_type = x; 1488 1489 return 1; 1490} 1491 1492 1493static int 1494io_apic_entry(io_apic_entry_ptr entry, int apic) 1495{ 1496 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) 1497 return 0; 1498 1499 IO_TO_ID(apic) = entry->apic_id; 1500 if (entry->apic_id < NAPICID) 1501 ID_TO_IO(entry->apic_id) = apic; 1502 1503 return 1; 1504} 1505 1506 1507static int 1508lookup_bus_type(char *name) 1509{ 1510 int x; 1511 1512 for (x = 0; x < MAX_BUSTYPE; ++x) 1513 if (strcmp(bus_type_table[x].name, name) == 0) 1514 return bus_type_table[x].type; 1515 1516 return UNKNOWN_BUSTYPE; 1517} 1518 1519 1520static int 1521int_entry(int_entry_ptr entry, int intr) 1522{ 1523 int apic; 1524 1525 io_apic_ints[intr].int_type = entry->int_type; 1526 io_apic_ints[intr].int_flags = entry->int_flags; 1527 io_apic_ints[intr].src_bus_id = entry->src_bus_id; 1528 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq; 1529 if (entry->dst_apic_id == 255) { 1530 /* This signal goes to all IO APICS. Select an IO APIC 1531 with sufficient number of interrupt pins */ 1532 for (apic = 0; apic < mp_napics; apic++) 1533 if (((io_apic_read(apic, IOAPIC_VER) & 1534 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >= 1535 entry->dst_apic_int) 1536 break; 1537 if (apic < mp_napics) 1538 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic); 1539 else 1540 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; 1541 } else 1542 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; 1543 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int; 1544 1545 return 1; 1546} 1547 1548 1549static int 1550apic_int_is_bus_type(int intr, int bus_type) 1551{ 1552 int bus; 1553 1554 for (bus = 0; bus < mp_nbusses; ++bus) 1555 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) 1556 && ((int) bus_data[bus].bus_type == bus_type)) 1557 return 1; 1558 1559 return 0; 1560} 1561 1562 1563/* 1564 * Given a traditional ISA INT mask, return an APIC mask. 1565 */ 1566u_int 1567isa_apic_mask(u_int isa_mask) 1568{ 1569 int isa_irq; 1570 int apic_pin; 1571 1572#if defined(SKIP_IRQ15_REDIRECT) 1573 if (isa_mask == (1 << 15)) { 1574 printf("skipping ISA IRQ15 redirect\n"); 1575 return isa_mask; 1576 } 1577#endif /* SKIP_IRQ15_REDIRECT */ 1578 1579 isa_irq = ffs(isa_mask); /* find its bit position */ 1580 if (isa_irq == 0) /* doesn't exist */ 1581 return 0; 1582 --isa_irq; /* make it zero based */ 1583 1584 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */ 1585 if (apic_pin == -1) 1586 return 0; 1587 1588 return (1 << apic_pin); /* convert pin# to a mask */ 1589} 1590 1591 1592/* 1593 * Determine which APIC pin an ISA/EISA INT is attached to. 1594 */ 1595#define INTTYPE(I) (io_apic_ints[(I)].int_type) 1596#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) 1597#define INTIRQ(I) (io_apic_ints[(I)].int_vector) 1598#define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id)) 1599 1600#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) 1601int 1602isa_apic_irq(int isa_irq) 1603{ 1604 int intr; 1605 1606 for (intr = 0; intr < nintrs; ++intr) { /* check each record */ 1607 if (INTTYPE(intr) == 0) { /* standard INT */ 1608 if (SRCBUSIRQ(intr) == isa_irq) { 1609 if (apic_int_is_bus_type(intr, ISA) || 1610 apic_int_is_bus_type(intr, EISA)) { 1611 if (INTIRQ(intr) == 0xff) 1612 return -1; /* unassigned */ 1613 return INTIRQ(intr); /* found */ 1614 } 1615 } 1616 } 1617 } 1618 return -1; /* NOT found */ 1619} 1620 1621 1622/* 1623 * Determine which APIC pin a PCI INT is attached to. 1624 */ 1625#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) 1626#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) 1627#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) 1628int 1629pci_apic_irq(int pciBus, int pciDevice, int pciInt) 1630{ 1631 int intr; 1632 1633 --pciInt; /* zero based */ 1634 1635 for (intr = 0; intr < nintrs; ++intr) /* check each record */ 1636 if ((INTTYPE(intr) == 0) /* standard INT */ 1637 && (SRCBUSID(intr) == pciBus) 1638 && (SRCBUSDEVICE(intr) == pciDevice) 1639 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ 1640 if (apic_int_is_bus_type(intr, PCI)) { 1641 if (INTIRQ(intr) == 0xff) 1642 allocate_apic_irq(intr); 1643 if (INTIRQ(intr) == 0xff) 1644 return -1; /* unassigned */ 1645 return INTIRQ(intr); /* exact match */ 1646 } 1647 1648 return -1; /* NOT found */ 1649} 1650 1651int 1652next_apic_irq(int irq) 1653{ 1654 int intr, ointr; 1655 int bus, bustype; 1656 1657 bus = 0; 1658 bustype = 0; 1659 for (intr = 0; intr < nintrs; intr++) { 1660 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0) 1661 continue; 1662 bus = SRCBUSID(intr); 1663 bustype = apic_bus_type(bus); 1664 if (bustype != ISA && 1665 bustype != EISA && 1666 bustype != PCI) 1667 continue; 1668 break; 1669 } 1670 if (intr >= nintrs) { 1671 return -1; 1672 } 1673 for (ointr = intr + 1; ointr < nintrs; ointr++) { 1674 if (INTTYPE(ointr) != 0) 1675 continue; 1676 if (bus != SRCBUSID(ointr)) 1677 continue; 1678 if (bustype == PCI) { 1679 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr)) 1680 continue; 1681 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr)) 1682 continue; 1683 } 1684 if (bustype == ISA || bustype == EISA) { 1685 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr)) 1686 continue; 1687 } 1688 if (INTPIN(intr) == INTPIN(ointr)) 1689 continue; 1690 break; 1691 } 1692 if (ointr >= nintrs) { 1693 return -1; 1694 } 1695 return INTIRQ(ointr); 1696} 1697#undef SRCBUSLINE 1698#undef SRCBUSDEVICE 1699#undef SRCBUSID 1700#undef SRCBUSIRQ 1701 1702#undef INTPIN 1703#undef INTIRQ 1704#undef INTAPIC 1705#undef INTTYPE 1706 1707 1708/* 1709 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt. 1710 * 1711 * XXX FIXME: 1712 * Exactly what this means is unclear at this point. It is a solution 1713 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard 1714 * could route any of the ISA INTs to upper (>15) IRQ values. But most would 1715 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an 1716 * option. 1717 */ 1718int 1719undirect_isa_irq(int rirq) 1720{ 1721#if defined(READY) 1722 if (bootverbose) 1723 printf("Freeing redirected ISA irq %d.\n", rirq); 1724 /** FIXME: tickle the MB redirector chip */ 1725 return -1; 1726#else 1727 if (bootverbose) 1728 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq); 1729 return 0; 1730#endif /* READY */ 1731} 1732 1733 1734/* 1735 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt 1736 */ 1737int 1738undirect_pci_irq(int rirq) 1739{ 1740#if defined(READY) 1741 if (bootverbose) 1742 printf("Freeing redirected PCI irq %d.\n", rirq); 1743 1744 /** FIXME: tickle the MB redirector chip */ 1745 return -1; 1746#else 1747 if (bootverbose) 1748 printf("Freeing (NOT implemented) redirected PCI irq %d.\n", 1749 rirq); 1750 return 0; 1751#endif /* READY */ 1752} 1753 1754 1755/* 1756 * given a bus ID, return: 1757 * the bus type if found 1758 * -1 if NOT found 1759 */ 1760int 1761apic_bus_type(int id) 1762{ 1763 int x; 1764 1765 for (x = 0; x < mp_nbusses; ++x) 1766 if (bus_data[x].bus_id == id) 1767 return bus_data[x].bus_type; 1768 1769 return -1; 1770} 1771 1772 1773/* 1774 * given a LOGICAL APIC# and pin#, return: 1775 * the associated src bus ID if found 1776 * -1 if NOT found 1777 */ 1778int 1779apic_src_bus_id(int apic, int pin) 1780{ 1781 int x; 1782 1783 /* search each of the possible INTerrupt sources */ 1784 for (x = 0; x < nintrs; ++x) 1785 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1786 (pin == io_apic_ints[x].dst_apic_int)) 1787 return (io_apic_ints[x].src_bus_id); 1788 1789 return -1; /* NOT found */ 1790} 1791 1792 1793/* 1794 * given a LOGICAL APIC# and pin#, return: 1795 * the associated src bus IRQ if found 1796 * -1 if NOT found 1797 */ 1798int 1799apic_src_bus_irq(int apic, int pin) 1800{ 1801 int x; 1802 1803 for (x = 0; x < nintrs; x++) 1804 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1805 (pin == io_apic_ints[x].dst_apic_int)) 1806 return (io_apic_ints[x].src_bus_irq); 1807 1808 return -1; /* NOT found */ 1809} 1810 1811 1812/* 1813 * given a LOGICAL APIC# and pin#, return: 1814 * the associated INTerrupt type if found 1815 * -1 if NOT found 1816 */ 1817int 1818apic_int_type(int apic, int pin) 1819{ 1820 int x; 1821 1822 /* search each of the possible INTerrupt sources */ 1823 for (x = 0; x < nintrs; ++x) 1824 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1825 (pin == io_apic_ints[x].dst_apic_int)) 1826 return (io_apic_ints[x].int_type); 1827 1828 return -1; /* NOT found */ 1829} 1830 1831int 1832apic_irq(int apic, int pin) 1833{ 1834 int x; 1835 int res; 1836 1837 for (x = 0; x < nintrs; ++x) 1838 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1839 (pin == io_apic_ints[x].dst_apic_int)) { 1840 res = io_apic_ints[x].int_vector; 1841 if (res == 0xff) 1842 return -1; 1843 if (apic != int_to_apicintpin[res].ioapic) 1844 panic("apic_irq: inconsistent table"); 1845 if (pin != int_to_apicintpin[res].int_pin) 1846 panic("apic_irq inconsistent table (2)"); 1847 return res; 1848 } 1849 return -1; 1850} 1851 1852 1853/* 1854 * given a LOGICAL APIC# and pin#, return: 1855 * the associated trigger mode if found 1856 * -1 if NOT found 1857 */ 1858int 1859apic_trigger(int apic, int pin) 1860{ 1861 int x; 1862 1863 /* search each of the possible INTerrupt sources */ 1864 for (x = 0; x < nintrs; ++x) 1865 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1866 (pin == io_apic_ints[x].dst_apic_int)) 1867 return ((io_apic_ints[x].int_flags >> 2) & 0x03); 1868 1869 return -1; /* NOT found */ 1870} 1871 1872 1873/* 1874 * given a LOGICAL APIC# and pin#, return: 1875 * the associated 'active' level if found 1876 * -1 if NOT found 1877 */ 1878int 1879apic_polarity(int apic, int pin) 1880{ 1881 int x; 1882 1883 /* search each of the possible INTerrupt sources */ 1884 for (x = 0; x < nintrs; ++x) 1885 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1886 (pin == io_apic_ints[x].dst_apic_int)) 1887 return (io_apic_ints[x].int_flags & 0x03); 1888 1889 return -1; /* NOT found */ 1890} 1891 1892 1893/* 1894 * set data according to MP defaults 1895 * FIXME: probably not complete yet... 1896 */ 1897static void 1898default_mp_table(int type) 1899{ 1900 int ap_cpu_id; 1901#if defined(APIC_IO) 1902 int io_apic_id; 1903 int pin; 1904#endif /* APIC_IO */ 1905 1906#if 0 1907 printf(" MP default config type: %d\n", type); 1908 switch (type) { 1909 case 1: 1910 printf(" bus: ISA, APIC: 82489DX\n"); 1911 break; 1912 case 2: 1913 printf(" bus: EISA, APIC: 82489DX\n"); 1914 break; 1915 case 3: 1916 printf(" bus: EISA, APIC: 82489DX\n"); 1917 break; 1918 case 4: 1919 printf(" bus: MCA, APIC: 82489DX\n"); 1920 break; 1921 case 5: 1922 printf(" bus: ISA+PCI, APIC: Integrated\n"); 1923 break; 1924 case 6: 1925 printf(" bus: EISA+PCI, APIC: Integrated\n"); 1926 break; 1927 case 7: 1928 printf(" bus: MCA+PCI, APIC: Integrated\n"); 1929 break; 1930 default: 1931 printf(" future type\n"); 1932 break; 1933 /* NOTREACHED */ 1934 } 1935#endif /* 0 */ 1936 1937 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24; 1938 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; 1939 1940 /* BSP */ 1941 CPU_TO_ID(0) = boot_cpu_id; 1942 ID_TO_CPU(boot_cpu_id) = 0; 1943 1944 /* one and only AP */ 1945 CPU_TO_ID(1) = ap_cpu_id; 1946 ID_TO_CPU(ap_cpu_id) = 1; 1947 1948#if defined(APIC_IO) 1949 /* one and only IO APIC */ 1950 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; 1951 1952 /* 1953 * sanity check, refer to MP spec section 3.6.6, last paragraph 1954 * necessary as some hardware isn't properly setting up the IO APIC 1955 */ 1956#if defined(REALLY_ANAL_IOAPICID_VALUE) 1957 if (io_apic_id != 2) { 1958#else 1959 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { 1960#endif /* REALLY_ANAL_IOAPICID_VALUE */ 1961 io_apic_set_id(0, 2); 1962 io_apic_id = 2; 1963 } 1964 IO_TO_ID(0) = io_apic_id; 1965 ID_TO_IO(io_apic_id) = 0; 1966#endif /* APIC_IO */ 1967 1968 /* fill out bus entries */ 1969 switch (type) { 1970 case 1: 1971 case 2: 1972 case 3: 1973 case 4: 1974 case 5: 1975 case 6: 1976 case 7: 1977 bus_data[0].bus_id = default_data[type - 1][1]; 1978 bus_data[0].bus_type = default_data[type - 1][2]; 1979 bus_data[1].bus_id = default_data[type - 1][3]; 1980 bus_data[1].bus_type = default_data[type - 1][4]; 1981 break; 1982 1983 /* case 4: case 7: MCA NOT supported */ 1984 default: /* illegal/reserved */ 1985 panic("BAD default MP config: %d", type); 1986 /* NOTREACHED */ 1987 } 1988 1989#if defined(APIC_IO) 1990 /* general cases from MP v1.4, table 5-2 */ 1991 for (pin = 0; pin < 16; ++pin) { 1992 io_apic_ints[pin].int_type = 0; 1993 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */ 1994 io_apic_ints[pin].src_bus_id = 0; 1995 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */ 1996 io_apic_ints[pin].dst_apic_id = io_apic_id; 1997 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */ 1998 } 1999 2000 /* special cases from MP v1.4, table 5-2 */ 2001 if (type == 2) { 2002 io_apic_ints[2].int_type = 0xff; /* N/C */ 2003 io_apic_ints[13].int_type = 0xff; /* N/C */ 2004#if !defined(APIC_MIXED_MODE) 2005 /** FIXME: ??? */ 2006 panic("sorry, can't support type 2 default yet"); 2007#endif /* APIC_MIXED_MODE */ 2008 } 2009 else 2010 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ 2011 2012 if (type == 7) 2013 io_apic_ints[0].int_type = 0xff; /* N/C */ 2014 else 2015 io_apic_ints[0].int_type = 3; /* vectored 8259 */ 2016#endif /* APIC_IO */ 2017} 2018 2019 2020/* 2021 * start each AP in our list 2022 */ 2023static int 2024start_all_aps(u_int boot_addr) 2025{ 2026 int x, i, pg; 2027#ifndef PC98 2028 u_char mpbiosreason; 2029#endif 2030 u_long mpbioswarmvec; 2031 struct pcpu *pc; 2032 char *stack; 2033 uintptr_t kptbase; 2034 2035 POSTCODE(START_ALL_APS_POST); 2036 2037 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); 2038 2039 /* initialize BSP's local APIC */ 2040 apic_initialize(); 2041 bsp_apic_ready = 1; 2042 2043 /* install the AP 1st level boot code */ 2044 install_ap_tramp(boot_addr); 2045 2046 2047 /* save the current value of the warm-start vector */ 2048 mpbioswarmvec = *((u_long *) WARMBOOT_OFF); 2049#ifndef PC98 2050 outb(CMOS_REG, BIOS_RESET); 2051 mpbiosreason = inb(CMOS_DATA); 2052#endif 2053 2054 /* set up temporary P==V mapping for AP boot */ 2055 /* XXX this is a hack, we should boot the AP on its own stack/PTD */ 2056 kptbase = (uintptr_t)(void *)KPTphys; 2057 for (x = 0; x < NKPT; x++) 2058 PTD[x] = (pd_entry_t)(PG_V | PG_RW | 2059 ((kptbase + x * PAGE_SIZE) & PG_FRAME)); 2060 invltlb(); 2061 2062 /* start each AP */ 2063 for (x = 1; x <= mp_naps; ++x) { 2064 2065 /* This is a bit verbose, it will go away soon. */ 2066 2067 /* first page of AP's private space */ 2068 pg = x * i386_btop(sizeof(struct privatespace)); 2069 2070 /* allocate a new private data page */ 2071 pc = (struct pcpu *)kmem_alloc(kernel_map, PAGE_SIZE); 2072 2073 /* wire it into the private page table page */ 2074 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys(pc)); 2075 2076 /* allocate and set up an idle stack data page */ 2077 stack = (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE); /* XXXKSE */ 2078 for (i = 0; i < KSTACK_PAGES; i++) 2079 SMPpt[pg + 1 + i] = (pt_entry_t) 2080 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 2081 2082 /* prime data page for it to use */ 2083 pcpu_init(pc, x, sizeof(struct pcpu)); 2084 2085 /* setup a vector to our boot code */ 2086 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 2087 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); 2088#ifndef PC98 2089 outb(CMOS_REG, BIOS_RESET); 2090 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 2091#endif 2092 2093 bootSTK = &SMP_prvspace[x].idlekstack[KSTACK_PAGES * PAGE_SIZE]; 2094 bootAP = x; 2095 2096 /* attempt to start the Application Processor */ 2097 CHECK_INIT(99); /* setup checkpoints */ 2098 if (!start_ap(x, boot_addr)) { 2099 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); 2100 CHECK_PRINT("trace"); /* show checkpoints */ 2101 /* better panic as the AP may be running loose */ 2102 printf("panic y/n? [y] "); 2103 if (cngetc() != 'n') 2104 panic("bye-bye"); 2105 } 2106 CHECK_PRINT("trace"); /* show checkpoints */ 2107 2108 /* record its version info */ 2109 cpu_apic_versions[x] = cpu_apic_versions[0]; 2110 2111 all_cpus |= (1 << x); /* record AP in CPU map */ 2112 } 2113 2114 /* build our map of 'other' CPUs */ 2115 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 2116 2117 /* fill in our (BSP) APIC version */ 2118 cpu_apic_versions[0] = lapic.version; 2119 2120 /* restore the warmstart vector */ 2121 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 2122#ifndef PC98 2123 outb(CMOS_REG, BIOS_RESET); 2124 outb(CMOS_DATA, mpbiosreason); 2125#endif 2126 2127 /* 2128 * Set up the idle context for the BSP. Similar to above except 2129 * that some was done by locore, some by pmap.c and some is implicit 2130 * because the BSP is cpu#0 and the page is initially zero, and also 2131 * because we can refer to variables by name on the BSP.. 2132 */ 2133 2134 /* Allocate and setup BSP idle stack */ 2135 stack = (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE); 2136 for (i = 0; i < KSTACK_PAGES; i++) 2137 SMPpt[1 + i] = (pt_entry_t) 2138 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 2139 2140 for (x = 0; x < NKPT; x++) 2141 PTD[x] = 0; 2142 pmap_set_opt(); 2143 2144 /* number of APs actually started */ 2145 return mp_ncpus - 1; 2146} 2147 2148 2149/* 2150 * load the 1st level AP boot code into base memory. 2151 */ 2152 2153/* targets for relocation */ 2154extern void bigJump(void); 2155extern void bootCodeSeg(void); 2156extern void bootDataSeg(void); 2157extern void MPentry(void); 2158extern u_int MP_GDT; 2159extern u_int mp_gdtbase; 2160 2161static void 2162install_ap_tramp(u_int boot_addr) 2163{ 2164 int x; 2165 int size = *(int *) ((u_long) & bootMP_size); 2166 u_char *src = (u_char *) ((u_long) bootMP); 2167 u_char *dst = (u_char *) boot_addr + KERNBASE; 2168 u_int boot_base = (u_int) bootMP; 2169 u_int8_t *dst8; 2170 u_int16_t *dst16; 2171 u_int32_t *dst32; 2172 2173 POSTCODE(INSTALL_AP_TRAMP_POST); 2174 2175 for (x = 0; x < size; ++x) 2176 *dst++ = *src++; 2177 2178 /* 2179 * modify addresses in code we just moved to basemem. unfortunately we 2180 * need fairly detailed info about mpboot.s for this to work. changes 2181 * to mpboot.s might require changes here. 2182 */ 2183 2184 /* boot code is located in KERNEL space */ 2185 dst = (u_char *) boot_addr + KERNBASE; 2186 2187 /* modify the lgdt arg */ 2188 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 2189 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); 2190 2191 /* modify the ljmp target for MPentry() */ 2192 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 2193 *dst32 = ((u_int) MPentry - KERNBASE); 2194 2195 /* modify the target for boot code segment */ 2196 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 2197 dst8 = (u_int8_t *) (dst16 + 1); 2198 *dst16 = (u_int) boot_addr & 0xffff; 2199 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 2200 2201 /* modify the target for boot data segment */ 2202 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 2203 dst8 = (u_int8_t *) (dst16 + 1); 2204 *dst16 = (u_int) boot_addr & 0xffff; 2205 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 2206} 2207 2208 2209/* 2210 * this function starts the AP (application processor) identified 2211 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 2212 * to accomplish this. This is necessary because of the nuances 2213 * of the different hardware we might encounter. It ain't pretty, 2214 * but it seems to work. 2215 */ 2216static int 2217start_ap(int logical_cpu, u_int boot_addr) 2218{ 2219 int physical_cpu; 2220 int vector; 2221 int cpus; 2222 u_long icr_lo, icr_hi; 2223 2224 POSTCODE(START_AP_POST); 2225 2226 /* get the PHYSICAL APIC ID# */ 2227 physical_cpu = CPU_TO_ID(logical_cpu); 2228 2229 /* calculate the vector */ 2230 vector = (boot_addr >> 12) & 0xff; 2231 2232 /* used as a watchpoint to signal AP startup */ 2233 cpus = mp_ncpus; 2234 2235 /* 2236 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 2237 * and running the target CPU. OR this INIT IPI might be latched (P5 2238 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 2239 * ignored. 2240 */ 2241 2242 /* setup the address for the target AP */ 2243 icr_hi = lapic.icr_hi & ~APIC_ID_MASK; 2244 icr_hi |= (physical_cpu << 24); 2245 lapic.icr_hi = icr_hi; 2246 2247 /* do an INIT IPI: assert RESET */ 2248 icr_lo = lapic.icr_lo & 0xfff00000; 2249 lapic.icr_lo = icr_lo | 0x0000c500; 2250 2251 /* wait for pending status end */ 2252 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2253 /* spin */ ; 2254 2255 /* do an INIT IPI: deassert RESET */ 2256 lapic.icr_lo = icr_lo | 0x00008500; 2257 2258 /* wait for pending status end */ 2259 u_sleep(10000); /* wait ~10mS */ 2260 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2261 /* spin */ ; 2262 2263 /* 2264 * next we do a STARTUP IPI: the previous INIT IPI might still be 2265 * latched, (P5 bug) this 1st STARTUP would then terminate 2266 * immediately, and the previously started INIT IPI would continue. OR 2267 * the previous INIT IPI has already run. and this STARTUP IPI will 2268 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 2269 * will run. 2270 */ 2271 2272 /* do a STARTUP IPI */ 2273 lapic.icr_lo = icr_lo | 0x00000600 | vector; 2274 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2275 /* spin */ ; 2276 u_sleep(200); /* wait ~200uS */ 2277 2278 /* 2279 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 2280 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 2281 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 2282 * recognized after hardware RESET or INIT IPI. 2283 */ 2284 2285 lapic.icr_lo = icr_lo | 0x00000600 | vector; 2286 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2287 /* spin */ ; 2288 u_sleep(200); /* wait ~200uS */ 2289 2290 /* wait for it to start */ 2291 set_apic_timer(5000000);/* == 5 seconds */ 2292 while (read_apic_timer()) 2293 if (mp_ncpus > cpus) 2294 return 1; /* return SUCCESS */ 2295 2296 return 0; /* return FAILURE */ 2297} 2298 2299#if defined(APIC_IO) 2300 2301#ifdef COUNT_XINVLTLB_HITS 2302u_int xhits_gbl[MAXCPU]; 2303u_int xhits_pg[MAXCPU]; 2304u_int xhits_rng[MAXCPU]; 2305SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, ""); 2306SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl, 2307 sizeof(xhits_gbl), "IU", ""); 2308SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg, 2309 sizeof(xhits_pg), "IU", ""); 2310SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng, 2311 sizeof(xhits_rng), "IU", ""); 2312 2313u_int ipi_global; 2314u_int ipi_page; 2315u_int ipi_range; 2316u_int ipi_range_size; 2317SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, ""); 2318SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, ""); 2319SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, ""); 2320SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size, 2321 0, ""); 2322 2323u_int ipi_masked_global; 2324u_int ipi_masked_page; 2325u_int ipi_masked_range; 2326u_int ipi_masked_range_size; 2327SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW, 2328 &ipi_masked_global, 0, ""); 2329SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW, 2330 &ipi_masked_page, 0, ""); 2331SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW, 2332 &ipi_masked_range, 0, ""); 2333SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW, 2334 &ipi_masked_range_size, 0, ""); 2335#endif 2336 2337/* 2338 * Flush the TLB on all other CPU's 2339 */ 2340static void 2341smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2) 2342{ 2343 u_int ncpu; 2344 register_t eflags; 2345 2346 ncpu = mp_ncpus - 1; /* does not shootdown self */ 2347 if (ncpu < 1) 2348 return; /* no other cpus */ 2349 eflags = read_eflags(); 2350 if ((eflags & PSL_I) == 0) 2351 panic("absolutely cannot call smp_ipi_shootdown with interrupts already disabled"); 2352 mtx_lock_spin(&smp_tlb_mtx); 2353 smp_tlb_addr1 = addr1; 2354 smp_tlb_addr2 = addr2; 2355 atomic_store_rel_int(&smp_tlb_wait, 0); 2356 ipi_all_but_self(vector); 2357 while (smp_tlb_wait < ncpu) 2358 ia32_pause(); 2359 mtx_unlock_spin(&smp_tlb_mtx); 2360} 2361 2362/* 2363 * This is about as magic as it gets. fortune(1) has got similar code 2364 * for reversing bits in a word. Who thinks up this stuff?? 2365 * 2366 * Yes, it does appear to be consistently faster than: 2367 * while (i = ffs(m)) { 2368 * m >>= i; 2369 * bits++; 2370 * } 2371 * and 2372 * while (lsb = (m & -m)) { // This is magic too 2373 * m &= ~lsb; // or: m ^= lsb 2374 * bits++; 2375 * } 2376 * Both of these latter forms do some very strange things on gcc-3.1 with 2377 * -mcpu=pentiumpro and/or -march=pentiumpro and/or -O or -O2. 2378 * There is probably an SSE or MMX popcnt instruction. 2379 * 2380 * I wonder if this should be in libkern? 2381 * 2382 * XXX Stop the presses! Another one: 2383 * static __inline u_int32_t 2384 * popcnt1(u_int32_t v) 2385 * { 2386 * v -= ((v >> 1) & 0x55555555); 2387 * v = (v & 0x33333333) + ((v >> 2) & 0x33333333); 2388 * v = (v + (v >> 4)) & 0x0F0F0F0F; 2389 * return (v * 0x01010101) >> 24; 2390 * } 2391 * The downside is that it has a multiply. With a pentium3 with 2392 * -mcpu=pentiumpro and -march=pentiumpro then gcc-3.1 will use 2393 * an imull, and in that case it is faster. In most other cases 2394 * it appears slightly slower. 2395 */ 2396static __inline u_int32_t 2397popcnt(u_int32_t m) 2398{ 2399 2400 m = (m & 0x55555555) + ((m & 0xaaaaaaaa) >> 1); 2401 m = (m & 0x33333333) + ((m & 0xcccccccc) >> 2); 2402 m = (m & 0x0f0f0f0f) + ((m & 0xf0f0f0f0) >> 4); 2403 m = (m & 0x00ff00ff) + ((m & 0xff00ff00) >> 8); 2404 m = (m & 0x0000ffff) + ((m & 0xffff0000) >> 16); 2405 return m; 2406} 2407 2408static void 2409smp_targeted_tlb_shootdown(u_int mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2) 2410{ 2411 int ncpu, othercpus; 2412 register_t eflags; 2413 2414 othercpus = mp_ncpus - 1; 2415 if (mask == (u_int)-1) { 2416 ncpu = othercpus; 2417 if (ncpu < 1) 2418 return; 2419 } else { 2420 /* XXX there should be a pcpu self mask */ 2421 mask &= ~(1 << PCPU_GET(cpuid)); 2422 if (mask == 0) 2423 return; 2424 ncpu = popcnt(mask); 2425 if (ncpu > othercpus) { 2426 /* XXX this should be a panic offence */ 2427 printf("SMP: tlb shootdown to %d other cpus (only have %d)\n", 2428 ncpu, othercpus); 2429 ncpu = othercpus; 2430 } 2431 /* XXX should be a panic, implied by mask == 0 above */ 2432 if (ncpu < 1) 2433 return; 2434 } 2435 eflags = read_eflags(); 2436 if ((eflags & PSL_I) == 0) 2437 panic("absolutely cannot call smp_targeted_ipi_shootdown with interrupts already disabled"); 2438 mtx_lock_spin(&smp_tlb_mtx); 2439 smp_tlb_addr1 = addr1; 2440 smp_tlb_addr2 = addr2; 2441 atomic_store_rel_int(&smp_tlb_wait, 0); 2442 if (mask == (u_int)-1) 2443 ipi_all_but_self(vector); 2444 else 2445 ipi_selected(mask, vector); 2446 while (smp_tlb_wait < ncpu) 2447 ia32_pause(); 2448 mtx_unlock_spin(&smp_tlb_mtx); 2449} 2450#endif 2451 2452void 2453smp_invltlb(void) 2454{ 2455#if defined(APIC_IO) 2456 if (smp_started) { 2457 smp_tlb_shootdown(IPI_INVLTLB, 0, 0); 2458#ifdef COUNT_XINVLTLB_HITS 2459 ipi_global++; 2460#endif 2461 } 2462#endif /* APIC_IO */ 2463} 2464 2465void 2466smp_invlpg(vm_offset_t addr) 2467{ 2468#if defined(APIC_IO) 2469 if (smp_started) { 2470 smp_tlb_shootdown(IPI_INVLPG, addr, 0); 2471#ifdef COUNT_XINVLTLB_HITS 2472 ipi_page++; 2473#endif 2474 } 2475#endif /* APIC_IO */ 2476} 2477 2478void 2479smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2) 2480{ 2481#if defined(APIC_IO) 2482 if (smp_started) { 2483 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2); 2484#ifdef COUNT_XINVLTLB_HITS 2485 ipi_range++; 2486 ipi_range_size += (addr2 - addr1) / PAGE_SIZE; 2487#endif 2488 } 2489#endif /* APIC_IO */ 2490} 2491 2492void 2493smp_masked_invltlb(u_int mask) 2494{ 2495#if defined(APIC_IO) 2496 if (smp_started) { 2497 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0); 2498#ifdef COUNT_XINVLTLB_HITS 2499 ipi_masked_global++; 2500#endif 2501 } 2502#endif /* APIC_IO */ 2503} 2504 2505void 2506smp_masked_invlpg(u_int mask, vm_offset_t addr) 2507{ 2508#if defined(APIC_IO) 2509 if (smp_started) { 2510 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0); 2511#ifdef COUNT_XINVLTLB_HITS 2512 ipi_masked_page++; 2513#endif 2514 } 2515#endif /* APIC_IO */ 2516} 2517 2518void 2519smp_masked_invlpg_range(u_int mask, vm_offset_t addr1, vm_offset_t addr2) 2520{ 2521#if defined(APIC_IO) 2522 if (smp_started) { 2523 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2); 2524#ifdef COUNT_XINVLTLB_HITS 2525 ipi_masked_range++; 2526 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE; 2527#endif 2528 } 2529#endif /* APIC_IO */ 2530} 2531 2532 2533/* 2534 * This is called once the rest of the system is up and running and we're 2535 * ready to let the AP's out of the pen. 2536 */ 2537void 2538ap_init(void) 2539{ 2540 u_int apic_id; 2541 2542 /* spin until all the AP's are ready */ 2543 while (!aps_ready) 2544 ia32_pause(); 2545 2546 /* BSP may have changed PTD while we were waiting */ 2547 invltlb(); 2548 2549#if defined(I586_CPU) && !defined(NO_F00F_HACK) 2550 lidt(&r_idt); 2551#endif 2552 2553 /* set up CPU registers and state */ 2554 cpu_setregs(); 2555 2556 /* set up FPU state on the AP */ 2557 npxinit(__INITIAL_NPXCW__); 2558 2559 /* set up SSE registers */ 2560 enable_sse(); 2561 2562 /* A quick check from sanity claus */ 2563 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]); 2564 if (PCPU_GET(cpuid) != apic_id) { 2565 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid)); 2566 printf("SMP: apic_id = %d\n", apic_id); 2567 printf("PTD[MPPTDI] = %#jx\n", (uintmax_t)PTD[MPPTDI]); 2568 panic("cpuid mismatch! boom!!"); 2569 } 2570 2571 /* Init local apic for irq's */ 2572 apic_initialize(); 2573 2574 /* Set memory range attributes for this CPU to match the BSP */ 2575 mem_range_AP_init(); 2576 2577 mtx_lock_spin(&ap_boot_mtx); 2578 2579 smp_cpus++; 2580 2581 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", PCPU_GET(cpuid)); 2582 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid)); 2583 2584 /* Build our map of 'other' CPUs. */ 2585 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 2586 2587 if (bootverbose) 2588 apic_dump("ap_init()"); 2589 2590 if (smp_cpus == mp_ncpus) { 2591 /* enable IPI's, tlb shootdown, freezes etc */ 2592 atomic_store_rel_int(&smp_started, 1); 2593 smp_active = 1; /* historic */ 2594 } 2595 2596 mtx_unlock_spin(&ap_boot_mtx); 2597 2598 /* wait until all the AP's are up */ 2599 while (smp_started == 0) 2600 ia32_pause(); 2601 2602 /* ok, now grab sched_lock and enter the scheduler */ 2603 mtx_lock_spin(&sched_lock); 2604 2605 binuptime(PCPU_PTR(switchtime)); 2606 PCPU_SET(switchticks, ticks); 2607 2608 cpu_throw(NULL, choosethread()); /* doesn't return */ 2609 2610 panic("scheduler returned us to %s", __func__); 2611} 2612 2613/* 2614 * For statclock, we send an IPI to all CPU's to have them call this 2615 * function. 2616 * 2617 * WARNING! unpend() will call statclock() directly and skip this 2618 * routine. 2619 */ 2620void 2621forwarded_statclock(struct clockframe frame) 2622{ 2623 2624 if (profprocs != 0) 2625 profclock(&frame); 2626 if (pscnt == psdiv) 2627 statclock(&frame); 2628} 2629 2630void 2631forward_statclock(void) 2632{ 2633 int map; 2634 2635 CTR0(KTR_SMP, "forward_statclock"); 2636 2637 if (!smp_started || cold || panicstr) 2638 return; 2639 2640 map = PCPU_GET(other_cpus) & ~stopped_cpus ; 2641 if (map != 0) 2642 ipi_selected(map, IPI_STATCLOCK); 2643} 2644 2645/* 2646 * For each hardclock(), we send an IPI to all other CPU's to have them 2647 * execute this function. It would be nice to reduce contention on 2648 * sched_lock if we could simply peek at the CPU to determine the user/kernel 2649 * state and call hardclock_process() on the CPU receiving the clock interrupt 2650 * and then just use a simple IPI to handle any ast's if needed. 2651 * 2652 * WARNING! unpend() will call hardclock_process() directly and skip this 2653 * routine. 2654 */ 2655void 2656forwarded_hardclock(struct clockframe frame) 2657{ 2658 2659 hardclock_process(&frame); 2660} 2661 2662void 2663forward_hardclock(void) 2664{ 2665 u_int map; 2666 2667 CTR0(KTR_SMP, "forward_hardclock"); 2668 2669 if (!smp_started || cold || panicstr) 2670 return; 2671 2672 map = PCPU_GET(other_cpus) & ~stopped_cpus ; 2673 if (map != 0) 2674 ipi_selected(map, IPI_HARDCLOCK); 2675} 2676 2677#ifdef APIC_INTR_REORDER 2678/* 2679 * Maintain mapping from softintr vector to isr bit in local apic. 2680 */ 2681void 2682set_lapic_isrloc(int intr, int vector) 2683{ 2684 if (intr < 0 || intr > 32) 2685 panic("set_apic_isrloc: bad intr argument: %d",intr); 2686 if (vector < ICU_OFFSET || vector > 255) 2687 panic("set_apic_isrloc: bad vector argument: %d",vector); 2688 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2); 2689 apic_isrbit_location[intr].bit = (1<<(vector & 31)); 2690} 2691#endif 2692 2693/* 2694 * send an IPI to a set of cpus. 2695 */ 2696void 2697ipi_selected(u_int32_t cpus, u_int ipi) 2698{ 2699 2700 CTR3(KTR_SMP, "%s: cpus: %x ipi: %x", __func__, cpus, ipi); 2701 selected_apic_ipi(cpus, ipi, APIC_DELMODE_FIXED); 2702} 2703 2704/* 2705 * send an IPI INTerrupt containing 'vector' to all CPUs, including myself 2706 */ 2707void 2708ipi_all(u_int ipi) 2709{ 2710 2711 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 2712 apic_ipi(APIC_DEST_ALLISELF, ipi, APIC_DELMODE_FIXED); 2713} 2714 2715/* 2716 * send an IPI to all CPUs EXCEPT myself 2717 */ 2718void 2719ipi_all_but_self(u_int ipi) 2720{ 2721 2722 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 2723 apic_ipi(APIC_DEST_ALLESELF, ipi, APIC_DELMODE_FIXED); 2724} 2725 2726/* 2727 * send an IPI to myself 2728 */ 2729void 2730ipi_self(u_int ipi) 2731{ 2732 2733 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 2734 apic_ipi(APIC_DEST_SELF, ipi, APIC_DELMODE_FIXED); 2735} 2736 2737static void 2738release_aps(void *dummy __unused) 2739{ 2740 2741 if (mp_ncpus == 1) 2742 return; 2743 mtx_lock_spin(&sched_lock); 2744 atomic_store_rel_int(&aps_ready, 1); 2745 while (smp_started == 0) 2746 ia32_pause(); 2747 mtx_unlock_spin(&sched_lock); 2748} 2749 2750SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL); 2751 2752static int hlt_cpus_mask; 2753static int hlt_logical_cpus = 1; 2754static struct sysctl_ctx_list logical_cpu_clist; 2755 2756static int 2757sysctl_hlt_cpus(SYSCTL_HANDLER_ARGS) 2758{ 2759 u_int mask; 2760 int error; 2761 2762 mask = hlt_cpus_mask; 2763 error = sysctl_handle_int(oidp, &mask, 0, req); 2764 if (error || !req->newptr) 2765 return (error); 2766 2767 if (logical_cpus_mask != 0 && 2768 (mask & logical_cpus_mask) == logical_cpus_mask) 2769 hlt_logical_cpus = 1; 2770 else 2771 hlt_logical_cpus = 0; 2772 2773 if ((mask & all_cpus) == all_cpus) 2774 mask &= ~(1<<0); 2775 hlt_cpus_mask = mask; 2776 return (error); 2777} 2778SYSCTL_PROC(_machdep, OID_AUTO, hlt_cpus, CTLTYPE_INT|CTLFLAG_RW, 2779 0, 0, sysctl_hlt_cpus, "IU", ""); 2780 2781static int 2782sysctl_hlt_logical_cpus(SYSCTL_HANDLER_ARGS) 2783{ 2784 int disable, error; 2785 2786 disable = hlt_logical_cpus; 2787 error = sysctl_handle_int(oidp, &disable, 0, req); 2788 if (error || !req->newptr) 2789 return (error); 2790 2791 if (disable) 2792 hlt_cpus_mask |= logical_cpus_mask; 2793 else 2794 hlt_cpus_mask &= ~logical_cpus_mask; 2795 2796 if ((hlt_cpus_mask & all_cpus) == all_cpus) 2797 hlt_cpus_mask &= ~(1<<0); 2798 2799 hlt_logical_cpus = disable; 2800 return (error); 2801} 2802 2803static void 2804cpu_hlt_setup(void *dummy __unused) 2805{ 2806 2807 if (logical_cpus_mask != 0) { 2808 TUNABLE_INT_FETCH("machdep.hlt_logical_cpus", 2809 &hlt_logical_cpus); 2810 sysctl_ctx_init(&logical_cpu_clist); 2811 SYSCTL_ADD_PROC(&logical_cpu_clist, 2812 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 2813 "hlt_logical_cpus", CTLTYPE_INT|CTLFLAG_RW, 0, 0, 2814 sysctl_hlt_logical_cpus, "IU", ""); 2815 SYSCTL_ADD_UINT(&logical_cpu_clist, 2816 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 2817 "logical_cpus_mask", CTLTYPE_INT|CTLFLAG_RD, 2818 &logical_cpus_mask, 0, ""); 2819 2820 if (hlt_logical_cpus) 2821 hlt_cpus_mask |= logical_cpus_mask; 2822 } 2823} 2824SYSINIT(cpu_hlt, SI_SUB_SMP, SI_ORDER_ANY, cpu_hlt_setup, NULL); 2825 2826int 2827mp_grab_cpu_hlt(void) 2828{ 2829 u_int mask = PCPU_GET(cpumask); 2830 int retval; 2831 2832 retval = mask & hlt_cpus_mask; 2833 while (mask & hlt_cpus_mask) 2834 __asm __volatile("sti; hlt" : : : "memory"); 2835 return (retval); 2836} 2837