mp_x86.c revision 40067
1/* 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $Id: mp_machdep.c,v 1.80 1998/09/06 22:41:40 tegge Exp $ 26 */ 27 28#include "opt_smp.h" 29#include "opt_vm86.h" 30#include "opt_cpu.h" 31#include "opt_user_ldt.h" 32 33#ifdef SMP 34#include <machine/smptests.h> 35#else 36#error 37#endif 38 39#include <sys/param.h> 40#include <sys/systm.h> 41#include <sys/kernel.h> 42#include <sys/proc.h> 43#include <sys/sysctl.h> 44#ifdef BETTER_CLOCK 45#include <sys/dkstat.h> 46#endif 47 48#include <vm/vm.h> 49#include <vm/vm_param.h> 50#include <vm/pmap.h> 51#include <vm/vm_kern.h> 52#include <vm/vm_extern.h> 53#ifdef BETTER_CLOCK 54#include <sys/lock.h> 55#include <vm/vm_map.h> 56#include <sys/user.h> 57#ifdef GPROF 58#include <sys/gmon.h> 59#endif 60#endif 61 62#include <machine/smp.h> 63#include <machine/apic.h> 64#include <machine/mpapic.h> 65#include <machine/segments.h> 66#include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */ 67#include <machine/tss.h> 68#include <machine/specialreg.h> 69#include <machine/cputypes.h> 70#include <machine/globaldata.h> 71 72#include <i386/i386/cons.h> /* cngetc() */ 73 74#if defined(APIC_IO) 75#include <machine/md_var.h> /* setidt() */ 76#include <i386/isa/icu.h> /* IPIs */ 77#include <i386/isa/intr_machdep.h> /* IPIs */ 78#endif /* APIC_IO */ 79 80#if defined(TEST_DEFAULT_CONFIG) 81#define MPFPS_MPFB1 TEST_DEFAULT_CONFIG 82#else 83#define MPFPS_MPFB1 mpfps->mpfb1 84#endif /* TEST_DEFAULT_CONFIG */ 85 86#define WARMBOOT_TARGET 0 87#define WARMBOOT_OFF (KERNBASE + 0x0467) 88#define WARMBOOT_SEG (KERNBASE + 0x0469) 89 90#ifdef PC98 91#define BIOS_BASE (0xe8000) 92#define BIOS_SIZE (0x18000) 93#else 94#define BIOS_BASE (0xf0000) 95#define BIOS_SIZE (0x10000) 96#endif 97#define BIOS_COUNT (BIOS_SIZE/4) 98 99#define CMOS_REG (0x70) 100#define CMOS_DATA (0x71) 101#define BIOS_RESET (0x0f) 102#define BIOS_WARM (0x0a) 103 104#define PROCENTRY_FLAG_EN 0x01 105#define PROCENTRY_FLAG_BP 0x02 106#define IOAPICENTRY_FLAG_EN 0x01 107 108 109/* MP Floating Pointer Structure */ 110typedef struct MPFPS { 111 char signature[4]; 112 void *pap; 113 u_char length; 114 u_char spec_rev; 115 u_char checksum; 116 u_char mpfb1; 117 u_char mpfb2; 118 u_char mpfb3; 119 u_char mpfb4; 120 u_char mpfb5; 121} *mpfps_t; 122 123/* MP Configuration Table Header */ 124typedef struct MPCTH { 125 char signature[4]; 126 u_short base_table_length; 127 u_char spec_rev; 128 u_char checksum; 129 u_char oem_id[8]; 130 u_char product_id[12]; 131 void *oem_table_pointer; 132 u_short oem_table_size; 133 u_short entry_count; 134 void *apic_address; 135 u_short extended_table_length; 136 u_char extended_table_checksum; 137 u_char reserved; 138} *mpcth_t; 139 140 141typedef struct PROCENTRY { 142 u_char type; 143 u_char apic_id; 144 u_char apic_version; 145 u_char cpu_flags; 146 u_long cpu_signature; 147 u_long feature_flags; 148 u_long reserved1; 149 u_long reserved2; 150} *proc_entry_ptr; 151 152typedef struct BUSENTRY { 153 u_char type; 154 u_char bus_id; 155 char bus_type[6]; 156} *bus_entry_ptr; 157 158typedef struct IOAPICENTRY { 159 u_char type; 160 u_char apic_id; 161 u_char apic_version; 162 u_char apic_flags; 163 void *apic_address; 164} *io_apic_entry_ptr; 165 166typedef struct INTENTRY { 167 u_char type; 168 u_char int_type; 169 u_short int_flags; 170 u_char src_bus_id; 171 u_char src_bus_irq; 172 u_char dst_apic_id; 173 u_char dst_apic_int; 174} *int_entry_ptr; 175 176/* descriptions of MP basetable entries */ 177typedef struct BASETABLE_ENTRY { 178 u_char type; 179 u_char length; 180 char name[16]; 181} basetable_entry; 182 183/* 184 * this code MUST be enabled here and in mpboot.s. 185 * it follows the very early stages of AP boot by placing values in CMOS ram. 186 * it NORMALLY will never be needed and thus the primitive method for enabling. 187 * 188#define CHECK_POINTS 189 */ 190 191#if defined(CHECK_POINTS) 192#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 193#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 194 195#define CHECK_INIT(D); \ 196 CHECK_WRITE(0x34, (D)); \ 197 CHECK_WRITE(0x35, (D)); \ 198 CHECK_WRITE(0x36, (D)); \ 199 CHECK_WRITE(0x37, (D)); \ 200 CHECK_WRITE(0x38, (D)); \ 201 CHECK_WRITE(0x39, (D)); 202 203#define CHECK_PRINT(S); \ 204 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 205 (S), \ 206 CHECK_READ(0x34), \ 207 CHECK_READ(0x35), \ 208 CHECK_READ(0x36), \ 209 CHECK_READ(0x37), \ 210 CHECK_READ(0x38), \ 211 CHECK_READ(0x39)); 212 213#else /* CHECK_POINTS */ 214 215#define CHECK_INIT(D) 216#define CHECK_PRINT(S) 217 218#endif /* CHECK_POINTS */ 219 220/* 221 * Values to send to the POST hardware. 222 */ 223#define MP_BOOTADDRESS_POST 0x10 224#define MP_PROBE_POST 0x11 225#define MPTABLE_PASS1_POST 0x12 226 227#define MP_START_POST 0x13 228#define MP_ENABLE_POST 0x14 229#define MPTABLE_PASS2_POST 0x15 230 231#define START_ALL_APS_POST 0x16 232#define INSTALL_AP_TRAMP_POST 0x17 233#define START_AP_POST 0x18 234 235#define MP_ANNOUNCE_POST 0x19 236 237 238/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ 239int current_postcode; 240 241/** XXX FIXME: what system files declare these??? */ 242extern struct region_descriptor r_gdt, r_idt; 243 244int bsp_apic_ready = 0; /* flags useability of BSP apic */ 245int mp_ncpus; /* # of CPUs, including BSP */ 246int mp_naps; /* # of Applications processors */ 247int mp_nbusses; /* # of busses */ 248int mp_napics; /* # of IO APICs */ 249int boot_cpu_id; /* designated BSP */ 250vm_offset_t cpu_apic_address; 251vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */ 252extern int nkpt; 253 254u_int32_t cpu_apic_versions[NCPU]; 255u_int32_t io_apic_versions[NAPIC]; 256 257#ifdef APIC_INTR_DIAGNOSTIC 258int apic_itrace_enter[32]; 259int apic_itrace_tryisrlock[32]; 260int apic_itrace_gotisrlock[32]; 261int apic_itrace_active[32]; 262int apic_itrace_masked[32]; 263int apic_itrace_noisrlock[32]; 264int apic_itrace_masked2[32]; 265int apic_itrace_unmask[32]; 266int apic_itrace_noforward[32]; 267int apic_itrace_leave[32]; 268int apic_itrace_enter2[32]; 269int apic_itrace_doreti[32]; 270int apic_itrace_splz[32]; 271int apic_itrace_eoi[32]; 272#ifdef APIC_INTR_DIAGNOSTIC_IRQ 273unsigned short apic_itrace_debugbuffer[32768]; 274int apic_itrace_debugbuffer_idx; 275struct simplelock apic_itrace_debuglock; 276#endif 277#endif 278 279#ifdef APIC_INTR_REORDER 280struct { 281 volatile int *location; 282 int bit; 283} apic_isrbit_location[32]; 284#endif 285 286struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE]; 287 288/* 289 * APIC ID logical/physical mapping structures. 290 * We oversize these to simplify boot-time config. 291 */ 292int cpu_num_to_apic_id[NAPICID]; 293int io_num_to_apic_id[NAPICID]; 294int apic_id_to_logical[NAPICID]; 295 296 297/* Bitmap of all available CPUs */ 298u_int all_cpus; 299 300/* AP uses this PTD during bootstrap. Do not staticize. */ 301pd_entry_t *bootPTD; 302 303/* Hotwire a 0->4MB V==P mapping */ 304extern pt_entry_t *KPTphys; 305 306/* Virtual address of per-cpu common_tss */ 307extern struct i386tss common_tss; 308#ifdef VM86 309extern struct segment_descriptor common_tssd; 310extern u_int private_tss; /* flag indicating private tss */ 311extern u_int my_tr; 312#endif /* VM86 */ 313 314/* IdlePTD per cpu */ 315pd_entry_t *IdlePTDS[NCPU]; 316 317/* "my" private page table page, for BSP init */ 318extern pt_entry_t SMP_prvpt[]; 319 320/* Private page pointer to curcpu's PTD, used during BSP init */ 321extern pd_entry_t *my_idlePTD; 322 323struct pcb stoppcbs[NCPU]; 324 325int smp_started; /* has the system started? */ 326 327/* 328 * Local data and functions. 329 */ 330 331static int mp_capable; 332static u_int boot_address; 333static u_int base_memory; 334 335static int picmode; /* 0: virtual wire mode, 1: PIC mode */ 336static mpfps_t mpfps; 337static int search_for_sig(u_int32_t target, int count); 338static void mp_enable(u_int boot_addr); 339 340static int mptable_pass1(void); 341static int mptable_pass2(void); 342static void default_mp_table(int type); 343static void fix_mp_table(void); 344static void setup_apic_irq_mapping(void); 345static void init_locks(void); 346static int start_all_aps(u_int boot_addr); 347static void install_ap_tramp(u_int boot_addr); 348static int start_ap(int logicalCpu, u_int boot_addr); 349 350/* 351 * Calculate usable address in base memory for AP trampoline code. 352 */ 353u_int 354mp_bootaddress(u_int basemem) 355{ 356 POSTCODE(MP_BOOTADDRESS_POST); 357 358 base_memory = basemem * 1024; /* convert to bytes */ 359 360 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ 361 if ((base_memory - boot_address) < bootMP_size) 362 boot_address -= 4096; /* not enough, lower by 4k */ 363 364 return boot_address; 365} 366 367 368/* 369 * Look for an Intel MP spec table (ie, SMP capable hardware). 370 */ 371int 372mp_probe(void) 373{ 374 int x; 375 u_long segment; 376 u_int32_t target; 377 378 POSTCODE(MP_PROBE_POST); 379 380 /* see if EBDA exists */ 381 if (segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) { 382 /* search first 1K of EBDA */ 383 target = (u_int32_t) (segment << 4); 384 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 385 goto found; 386 } else { 387 /* last 1K of base memory, effective 'top of base' passed in */ 388 target = (u_int32_t) (base_memory - 0x400); 389 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 390 goto found; 391 } 392 393 /* search the BIOS */ 394 target = (u_int32_t) BIOS_BASE; 395 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) 396 goto found; 397 398 /* nothing found */ 399 mpfps = (mpfps_t)0; 400 mp_capable = 0; 401 return 0; 402 403found: 404 /* calculate needed resources */ 405 mpfps = (mpfps_t)x; 406 if (mptable_pass1()) 407 panic("you must reconfigure your kernel"); 408 409 /* flag fact that we are running multiple processors */ 410 mp_capable = 1; 411 return 1; 412} 413 414 415/* 416 * Startup the SMP processors. 417 */ 418void 419mp_start(void) 420{ 421 POSTCODE(MP_START_POST); 422 423 /* look for MP capable motherboard */ 424 if (mp_capable) 425 mp_enable(boot_address); 426 else 427 panic("MP hardware not found!"); 428} 429 430 431/* 432 * Print various information about the SMP system hardware and setup. 433 */ 434void 435mp_announce(void) 436{ 437 int x; 438 439 POSTCODE(MP_ANNOUNCE_POST); 440 441 printf("FreeBSD/SMP: Multiprocessor motherboard\n"); 442 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0)); 443 printf(", version: 0x%08x", cpu_apic_versions[0]); 444 printf(", at 0x%08x\n", cpu_apic_address); 445 for (x = 1; x <= mp_naps; ++x) { 446 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x)); 447 printf(", version: 0x%08x", cpu_apic_versions[x]); 448 printf(", at 0x%08x\n", cpu_apic_address); 449 } 450 451#if defined(APIC_IO) 452 for (x = 0; x < mp_napics; ++x) { 453 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x)); 454 printf(", version: 0x%08x", io_apic_versions[x]); 455 printf(", at 0x%08x\n", io_apic_address[x]); 456 } 457#else 458 printf(" Warning: APIC I/O disabled\n"); 459#endif /* APIC_IO */ 460} 461 462/* 463 * AP cpu's call this to sync up protected mode. 464 */ 465void 466init_secondary(void) 467{ 468 int gsel_tss; 469#ifndef VM86 470 u_int my_tr; 471#endif 472 473 r_gdt.rd_limit = sizeof(gdt[0]) * (NGDT + NCPU) - 1; 474 r_gdt.rd_base = (int) gdt; 475 lgdt(&r_gdt); /* does magic intra-segment return */ 476 lidt(&r_idt); 477 lldt(_default_ldt); 478#ifdef USER_LDT 479 currentldt = _default_ldt; 480#endif 481 482 my_tr = NGDT + cpuid; 483 gsel_tss = GSEL(my_tr, SEL_KPL); 484 gdt[my_tr].sd.sd_type = SDT_SYS386TSS; 485 common_tss.tss_esp0 = 0; /* not used until after switch */ 486 common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 487 common_tss.tss_ioopt = (sizeof common_tss) << 16; 488#ifdef VM86 489 common_tssd = gdt[my_tr].sd; 490 private_tss = 0; 491#endif /* VM86 */ 492 ltr(gsel_tss); 493 494 load_cr0(0x8005003b); /* XXX! */ 495 496 PTD[0] = 0; 497 pmap_set_opt((unsigned *)PTD); 498 499 putmtrr(); 500 pmap_setvidram(); 501 502 invltlb(); 503} 504 505 506#if defined(APIC_IO) 507/* 508 * Final configuration of the BSP's local APIC: 509 * - disable 'pic mode'. 510 * - disable 'virtual wire mode'. 511 * - enable NMI. 512 */ 513void 514bsp_apic_configure(void) 515{ 516 u_char byte; 517 u_int32_t temp; 518 519 /* leave 'pic mode' if necessary */ 520 if (picmode) { 521 outb(0x22, 0x70); /* select IMCR */ 522 byte = inb(0x23); /* current contents */ 523 byte |= 0x01; /* mask external INTR */ 524 outb(0x23, byte); /* disconnect 8259s/NMI */ 525 } 526 527 /* mask lint0 (the 8259 'virtual wire' connection) */ 528 temp = lapic.lvt_lint0; 529 temp |= APIC_LVT_M; /* set the mask */ 530 lapic.lvt_lint0 = temp; 531 532 /* setup lint1 to handle NMI */ 533 temp = lapic.lvt_lint1; 534 temp &= ~APIC_LVT_M; /* clear the mask */ 535 lapic.lvt_lint1 = temp; 536 537 if (bootverbose) 538 apic_dump("bsp_apic_configure()"); 539} 540#endif /* APIC_IO */ 541 542 543/******************************************************************* 544 * local functions and data 545 */ 546 547/* 548 * start the SMP system 549 */ 550static void 551mp_enable(u_int boot_addr) 552{ 553 int x; 554#if defined(APIC_IO) 555 int apic; 556 u_int ux; 557#endif /* APIC_IO */ 558 559 getmtrr(); 560 pmap_setvidram(); 561 562 POSTCODE(MP_ENABLE_POST); 563 564 /* turn on 4MB of V == P addressing so we can get to MP table */ 565 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME); 566 invltlb(); 567 568 /* examine the MP table for needed info, uses physical addresses */ 569 x = mptable_pass2(); 570 571 *(int *)PTD = 0; 572 invltlb(); 573 574 /* can't process default configs till the CPU APIC is pmapped */ 575 if (x) 576 default_mp_table(x); 577 578 /* post scan cleanup */ 579 fix_mp_table(); 580 setup_apic_irq_mapping(); 581 582#if defined(APIC_IO) 583 584 /* fill the LOGICAL io_apic_versions table */ 585 for (apic = 0; apic < mp_napics; ++apic) { 586 ux = io_apic_read(apic, IOAPIC_VER); 587 io_apic_versions[apic] = ux; 588 } 589 590 /* program each IO APIC in the system */ 591 for (apic = 0; apic < mp_napics; ++apic) 592 if (io_apic_setup(apic) < 0) 593 panic("IO APIC setup failure"); 594 595 /* install a 'Spurious INTerrupt' vector */ 596 setidt(XSPURIOUSINT_OFFSET, Xspuriousint, 597 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 598 599 /* install an inter-CPU IPI for TLB invalidation */ 600 setidt(XINVLTLB_OFFSET, Xinvltlb, 601 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 602 603#ifdef BETTER_CLOCK 604 /* install an inter-CPU IPI for reading processor state */ 605 setidt(XCPUCHECKSTATE_OFFSET, Xcpucheckstate, 606 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 607#endif 608 609 /* install an inter-CPU IPI for forcing an additional software trap */ 610 setidt(XCPUAST_OFFSET, Xcpuast, 611 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 612 613 /* install an inter-CPU IPI for interrupt forwarding */ 614 setidt(XFORWARD_IRQ_OFFSET, Xforward_irq, 615 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 616 617 /* install an inter-CPU IPI for CPU stop/restart */ 618 setidt(XCPUSTOP_OFFSET, Xcpustop, 619 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 620 621#if defined(TEST_TEST1) 622 /* install a "fake hardware INTerrupt" vector */ 623 setidt(XTEST1_OFFSET, Xtest1, 624 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 625#endif /** TEST_TEST1 */ 626 627#endif /* APIC_IO */ 628 629 /* initialize all SMP locks */ 630 init_locks(); 631 632 /* start each Application Processor */ 633 start_all_aps(boot_addr); 634 635 /* 636 * The init process might be started on a different CPU now, 637 * and the boot CPU might not call prepare_usermode to get 638 * cr0 correctly configured. Thus we initialize cr0 here. 639 */ 640 load_cr0(rcr0() | CR0_WP | CR0_AM); 641} 642 643 644/* 645 * look for the MP spec signature 646 */ 647 648/* string defined by the Intel MP Spec as identifying the MP table */ 649#define MP_SIG 0x5f504d5f /* _MP_ */ 650#define NEXT(X) ((X) += 4) 651static int 652search_for_sig(u_int32_t target, int count) 653{ 654 int x; 655 u_int32_t *addr = (u_int32_t *) (KERNBASE + target); 656 657 for (x = 0; x < count; NEXT(x)) 658 if (addr[x] == MP_SIG) 659 /* make array index a byte index */ 660 return (target + (x * sizeof(u_int32_t))); 661 662 return -1; 663} 664 665 666static basetable_entry basetable_entry_types[] = 667{ 668 {0, 20, "Processor"}, 669 {1, 8, "Bus"}, 670 {2, 8, "I/O APIC"}, 671 {3, 8, "I/O INT"}, 672 {4, 8, "Local INT"} 673}; 674 675typedef struct BUSDATA { 676 u_char bus_id; 677 enum busTypes bus_type; 678} bus_datum; 679 680typedef struct INTDATA { 681 u_char int_type; 682 u_short int_flags; 683 u_char src_bus_id; 684 u_char src_bus_irq; 685 u_char dst_apic_id; 686 u_char dst_apic_int; 687 u_char int_vector; 688} io_int, local_int; 689 690typedef struct BUSTYPENAME { 691 u_char type; 692 char name[7]; 693} bus_type_name; 694 695static bus_type_name bus_type_table[] = 696{ 697 {CBUS, "CBUS"}, 698 {CBUSII, "CBUSII"}, 699 {EISA, "EISA"}, 700 {UNKNOWN_BUSTYPE, "---"}, 701 {UNKNOWN_BUSTYPE, "---"}, 702 {ISA, "ISA"}, 703 {UNKNOWN_BUSTYPE, "---"}, 704 {UNKNOWN_BUSTYPE, "---"}, 705 {UNKNOWN_BUSTYPE, "---"}, 706 {UNKNOWN_BUSTYPE, "---"}, 707 {UNKNOWN_BUSTYPE, "---"}, 708 {UNKNOWN_BUSTYPE, "---"}, 709 {PCI, "PCI"}, 710 {UNKNOWN_BUSTYPE, "---"}, 711 {UNKNOWN_BUSTYPE, "---"}, 712 {UNKNOWN_BUSTYPE, "---"}, 713 {UNKNOWN_BUSTYPE, "---"}, 714 {XPRESS, "XPRESS"}, 715 {UNKNOWN_BUSTYPE, "---"} 716}; 717/* from MP spec v1.4, table 5-1 */ 718static int default_data[7][5] = 719{ 720/* nbus, id0, type0, id1, type1 */ 721 {1, 0, ISA, 255, 255}, 722 {1, 0, EISA, 255, 255}, 723 {1, 0, EISA, 255, 255}, 724 {0, 255, 255, 255, 255},/* MCA not supported */ 725 {2, 0, ISA, 1, PCI}, 726 {2, 0, EISA, 1, PCI}, 727 {0, 255, 255, 255, 255} /* MCA not supported */ 728}; 729 730 731/* the bus data */ 732static bus_datum bus_data[NBUS]; 733 734/* the IO INT data, one entry per possible APIC INTerrupt */ 735static io_int io_apic_ints[NINTR]; 736 737static int nintrs; 738 739static int processor_entry __P((proc_entry_ptr entry, int cpu)); 740static int bus_entry __P((bus_entry_ptr entry, int bus)); 741static int io_apic_entry __P((io_apic_entry_ptr entry, int apic)); 742static int int_entry __P((int_entry_ptr entry, int intr)); 743static int lookup_bus_type __P((char *name)); 744 745 746/* 747 * 1st pass on motherboard's Intel MP specification table. 748 * 749 * initializes: 750 * mp_ncpus = 1 751 * 752 * determines: 753 * cpu_apic_address (common to all CPUs) 754 * io_apic_address[N] 755 * mp_naps 756 * mp_nbusses 757 * mp_napics 758 * nintrs 759 */ 760static int 761mptable_pass1(void) 762{ 763 int x; 764 mpcth_t cth; 765 int totalSize; 766 void* position; 767 int count; 768 int type; 769 int mustpanic; 770 771 POSTCODE(MPTABLE_PASS1_POST); 772 773 mustpanic = 0; 774 775 /* clear various tables */ 776 for (x = 0; x < NAPICID; ++x) { 777 io_apic_address[x] = ~0; /* IO APIC address table */ 778 } 779 780 /* init everything to empty */ 781 mp_naps = 0; 782 mp_nbusses = 0; 783 mp_napics = 0; 784 nintrs = 0; 785 786 /* check for use of 'default' configuration */ 787 if (MPFPS_MPFB1 != 0) { 788 /* use default addresses */ 789 cpu_apic_address = DEFAULT_APIC_BASE; 790 io_apic_address[0] = DEFAULT_IO_APIC_BASE; 791 792 /* fill in with defaults */ 793 mp_naps = 2; /* includes BSP */ 794 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0]; 795#if defined(APIC_IO) 796 mp_napics = 1; 797 nintrs = 16; 798#endif /* APIC_IO */ 799 } 800 else { 801 if ((cth = mpfps->pap) == 0) 802 panic("MP Configuration Table Header MISSING!"); 803 804 cpu_apic_address = (vm_offset_t) cth->apic_address; 805 806 /* walk the table, recording info of interest */ 807 totalSize = cth->base_table_length - sizeof(struct MPCTH); 808 position = (u_char *) cth + sizeof(struct MPCTH); 809 count = cth->entry_count; 810 811 while (count--) { 812 switch (type = *(u_char *) position) { 813 case 0: /* processor_entry */ 814 if (((proc_entry_ptr)position)->cpu_flags 815 & PROCENTRY_FLAG_EN) 816 ++mp_naps; 817 break; 818 case 1: /* bus_entry */ 819 ++mp_nbusses; 820 break; 821 case 2: /* io_apic_entry */ 822 if (((io_apic_entry_ptr)position)->apic_flags 823 & IOAPICENTRY_FLAG_EN) 824 io_apic_address[mp_napics++] = 825 (vm_offset_t)((io_apic_entry_ptr) 826 position)->apic_address; 827 break; 828 case 3: /* int_entry */ 829 ++nintrs; 830 break; 831 case 4: /* int_entry */ 832 break; 833 default: 834 panic("mpfps Base Table HOSED!"); 835 /* NOTREACHED */ 836 } 837 838 totalSize -= basetable_entry_types[type].length; 839 (u_char*)position += basetable_entry_types[type].length; 840 } 841 } 842 843 /* qualify the numbers */ 844 if (mp_naps > NCPU) 845#if 0 /* XXX FIXME: kern/4255 */ 846 printf("Warning: only using %d of %d available CPUs!\n", 847 NCPU, mp_naps); 848#else 849 { 850 printf("NCPU cannot be different than actual CPU count.\n"); 851 printf(" add 'options NCPU=%d' to your kernel config file,\n", 852 mp_naps); 853 printf(" then rerun config & rebuild your SMP kernel\n"); 854 mustpanic = 1; 855 } 856#endif /* XXX FIXME: kern/4255 */ 857 if (mp_nbusses > NBUS) { 858 printf("found %d busses, increase NBUS\n", mp_nbusses); 859 mustpanic = 1; 860 } 861 if (mp_napics > NAPIC) { 862 printf("found %d apics, increase NAPIC\n", mp_napics); 863 mustpanic = 1; 864 } 865 if (nintrs > NINTR) { 866 printf("found %d intrs, increase NINTR\n", nintrs); 867 mustpanic = 1; 868 } 869 870 /* 871 * Count the BSP. 872 * This is also used as a counter while starting the APs. 873 */ 874 mp_ncpus = 1; 875 876 --mp_naps; /* subtract the BSP */ 877 878 return mustpanic; 879} 880 881 882/* 883 * 2nd pass on motherboard's Intel MP specification table. 884 * 885 * sets: 886 * boot_cpu_id 887 * ID_TO_IO(N), phy APIC ID to log CPU/IO table 888 * CPU_TO_ID(N), logical CPU to APIC ID table 889 * IO_TO_ID(N), logical IO to APIC ID table 890 * bus_data[N] 891 * io_apic_ints[N] 892 */ 893static int 894mptable_pass2(void) 895{ 896 int x; 897 mpcth_t cth; 898 int totalSize; 899 void* position; 900 int count; 901 int type; 902 int apic, bus, cpu, intr; 903 904 POSTCODE(MPTABLE_PASS2_POST); 905 906 /* clear various tables */ 907 for (x = 0; x < NAPICID; ++x) { 908 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */ 909 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */ 910 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */ 911 } 912 913 /* clear bus data table */ 914 for (x = 0; x < NBUS; ++x) 915 bus_data[x].bus_id = 0xff; 916 917 /* clear IO APIC INT table */ 918 for (x = 0; x < NINTR; ++x) { 919 io_apic_ints[x].int_type = 0xff; 920 io_apic_ints[x].int_vector = 0xff; 921 } 922 923 /* setup the cpu/apic mapping arrays */ 924 boot_cpu_id = -1; 925 926 /* record whether PIC or virtual-wire mode */ 927 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0; 928 929 /* check for use of 'default' configuration */ 930 if (MPFPS_MPFB1 != 0) 931 return MPFPS_MPFB1; /* return default configuration type */ 932 933 if ((cth = mpfps->pap) == 0) 934 panic("MP Configuration Table Header MISSING!"); 935 936 /* walk the table, recording info of interest */ 937 totalSize = cth->base_table_length - sizeof(struct MPCTH); 938 position = (u_char *) cth + sizeof(struct MPCTH); 939 count = cth->entry_count; 940 apic = bus = intr = 0; 941 cpu = 1; /* pre-count the BSP */ 942 943 while (count--) { 944 switch (type = *(u_char *) position) { 945 case 0: 946 if (processor_entry(position, cpu)) 947 ++cpu; 948 break; 949 case 1: 950 if (bus_entry(position, bus)) 951 ++bus; 952 break; 953 case 2: 954 if (io_apic_entry(position, apic)) 955 ++apic; 956 break; 957 case 3: 958 if (int_entry(position, intr)) 959 ++intr; 960 break; 961 case 4: 962 /* int_entry(position); */ 963 break; 964 default: 965 panic("mpfps Base Table HOSED!"); 966 /* NOTREACHED */ 967 } 968 969 totalSize -= basetable_entry_types[type].length; 970 (u_char *) position += basetable_entry_types[type].length; 971 } 972 973 if (boot_cpu_id == -1) 974 panic("NO BSP found!"); 975 976 /* report fact that its NOT a default configuration */ 977 return 0; 978} 979 980 981static void 982assign_apic_irq(int apic, int intpin, int irq) 983{ 984 int x; 985 986 if (int_to_apicintpin[irq].ioapic != -1) 987 panic("assign_apic_irq: inconsistent table"); 988 989 int_to_apicintpin[irq].ioapic = apic; 990 int_to_apicintpin[irq].int_pin = intpin; 991 int_to_apicintpin[irq].apic_address = ioapic[apic]; 992 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin; 993 994 for (x = 0; x < nintrs; x++) { 995 if ((io_apic_ints[x].int_type == 0 || 996 io_apic_ints[x].int_type == 3) && 997 io_apic_ints[x].int_vector == 0xff && 998 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) && 999 io_apic_ints[x].dst_apic_int == intpin) 1000 io_apic_ints[x].int_vector = irq; 1001 } 1002} 1003 1004/* 1005 * parse an Intel MP specification table 1006 */ 1007static void 1008fix_mp_table(void) 1009{ 1010 int x; 1011 int id; 1012 int bus_0; 1013 int bus_pci; 1014 int num_pci_bus; 1015 1016 /* 1017 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS 1018 * did it wrong. The MP spec says that when more than 1 PCI bus 1019 * exists the BIOS must begin with bus entries for the PCI bus and use 1020 * actual PCI bus numbering. This implies that when only 1 PCI bus 1021 * exists the BIOS can choose to ignore this ordering, and indeed many 1022 * MP motherboards do ignore it. This causes a problem when the PCI 1023 * sub-system makes requests of the MP sub-system based on PCI bus 1024 * numbers. So here we look for the situation and renumber the 1025 * busses and associated INTs in an effort to "make it right". 1026 */ 1027 1028 /* find bus 0, PCI bus, count the number of PCI busses */ 1029 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { 1030 if (bus_data[x].bus_id == 0) { 1031 bus_0 = x; 1032 } 1033 if (bus_data[x].bus_type == PCI) { 1034 ++num_pci_bus; 1035 bus_pci = x; 1036 } 1037 } 1038 /* 1039 * bus_0 == slot of bus with ID of 0 1040 * bus_pci == slot of last PCI bus encountered 1041 */ 1042 1043 /* check the 1 PCI bus case for sanity */ 1044 if (num_pci_bus == 1) { 1045 1046 /* if it is number 0 all is well */ 1047 if (bus_data[bus_pci].bus_id == 0) 1048 return; 1049 1050 /* mis-numbered, swap with whichever bus uses slot 0 */ 1051 1052 /* swap the bus entry types */ 1053 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type; 1054 bus_data[bus_0].bus_type = PCI; 1055 1056 /* swap each relavant INTerrupt entry */ 1057 id = bus_data[bus_pci].bus_id; 1058 for (x = 0; x < nintrs; ++x) { 1059 if (io_apic_ints[x].src_bus_id == id) { 1060 io_apic_ints[x].src_bus_id = 0; 1061 } 1062 else if (io_apic_ints[x].src_bus_id == 0) { 1063 io_apic_ints[x].src_bus_id = id; 1064 } 1065 } 1066 } 1067 /* sanity check if more than 1 PCI bus */ 1068 else if (num_pci_bus > 1) { 1069 for (x = 0; x < mp_nbusses; ++x) { 1070 if (bus_data[x].bus_type != PCI) 1071 continue; 1072 if (bus_data[x].bus_id >= num_pci_bus) 1073 panic("bad PCI bus numbering"); 1074 } 1075 } 1076} 1077 1078 1079static void 1080setup_apic_irq_mapping(void) 1081{ 1082 int x; 1083 int int_vector; 1084 1085 /* Assign low level interrupt handlers */ 1086 for (x = 0; x < APIC_INTMAPSIZE; x++) { 1087 int_to_apicintpin[x].ioapic = -1; 1088 int_to_apicintpin[x].int_pin = 0; 1089 int_to_apicintpin[x].apic_address = NULL; 1090 int_to_apicintpin[x].redirindex = 0; 1091 } 1092 for (x = 0; x < nintrs; x++) { 1093 if (io_apic_ints[x].dst_apic_int <= APIC_INTMAPSIZE && 1094 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) && 1095 io_apic_ints[x].int_vector == 0xff && 1096 (io_apic_ints[x].int_type == 0 || 1097 io_apic_ints[x].int_type == 3)) { 1098 assign_apic_irq(0, 1099 io_apic_ints[x].dst_apic_int, 1100 io_apic_ints[x].dst_apic_int); 1101 } 1102 } 1103 int_vector = 0; 1104 while (int_vector < APIC_INTMAPSIZE && 1105 int_to_apicintpin[int_vector].ioapic != -1) 1106 int_vector++; 1107 for (x = 0; x < nintrs && int_vector < APIC_INTMAPSIZE; x++) { 1108 if ((io_apic_ints[x].int_type == 0 || 1109 io_apic_ints[x].int_type == 3) && 1110 io_apic_ints[x].int_vector == 0xff) { 1111 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id), 1112 io_apic_ints[x].dst_apic_int, 1113 int_vector); 1114 int_vector++; 1115 while (int_vector < APIC_INTMAPSIZE && 1116 int_to_apicintpin[int_vector].ioapic != -1) 1117 int_vector++; 1118 } 1119 } 1120} 1121 1122 1123static int 1124processor_entry(proc_entry_ptr entry, int cpu) 1125{ 1126 /* check for usability */ 1127 if ((cpu >= NCPU) || !(entry->cpu_flags & PROCENTRY_FLAG_EN)) 1128 return 0; 1129 1130 /* check for BSP flag */ 1131 if (entry->cpu_flags & PROCENTRY_FLAG_BP) { 1132 boot_cpu_id = entry->apic_id; 1133 CPU_TO_ID(0) = entry->apic_id; 1134 ID_TO_CPU(entry->apic_id) = 0; 1135 return 0; /* its already been counted */ 1136 } 1137 1138 /* add another AP to list, if less than max number of CPUs */ 1139 else { 1140 CPU_TO_ID(cpu) = entry->apic_id; 1141 ID_TO_CPU(entry->apic_id) = cpu; 1142 return 1; 1143 } 1144} 1145 1146 1147static int 1148bus_entry(bus_entry_ptr entry, int bus) 1149{ 1150 int x; 1151 char c, name[8]; 1152 1153 /* encode the name into an index */ 1154 for (x = 0; x < 6; ++x) { 1155 if ((c = entry->bus_type[x]) == ' ') 1156 break; 1157 name[x] = c; 1158 } 1159 name[x] = '\0'; 1160 1161 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) 1162 panic("unknown bus type: '%s'", name); 1163 1164 bus_data[bus].bus_id = entry->bus_id; 1165 bus_data[bus].bus_type = x; 1166 1167 return 1; 1168} 1169 1170 1171static int 1172io_apic_entry(io_apic_entry_ptr entry, int apic) 1173{ 1174 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) 1175 return 0; 1176 1177 IO_TO_ID(apic) = entry->apic_id; 1178 ID_TO_IO(entry->apic_id) = apic; 1179 1180 return 1; 1181} 1182 1183 1184static int 1185lookup_bus_type(char *name) 1186{ 1187 int x; 1188 1189 for (x = 0; x < MAX_BUSTYPE; ++x) 1190 if (strcmp(bus_type_table[x].name, name) == 0) 1191 return bus_type_table[x].type; 1192 1193 return UNKNOWN_BUSTYPE; 1194} 1195 1196 1197static int 1198int_entry(int_entry_ptr entry, int intr) 1199{ 1200 io_apic_ints[intr].int_type = entry->int_type; 1201 io_apic_ints[intr].int_flags = entry->int_flags; 1202 io_apic_ints[intr].src_bus_id = entry->src_bus_id; 1203 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq; 1204 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; 1205 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int; 1206 1207 return 1; 1208} 1209 1210 1211static int 1212apic_int_is_bus_type(int intr, int bus_type) 1213{ 1214 int bus; 1215 1216 for (bus = 0; bus < mp_nbusses; ++bus) 1217 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) 1218 && ((int) bus_data[bus].bus_type == bus_type)) 1219 return 1; 1220 1221 return 0; 1222} 1223 1224 1225/* 1226 * Given a traditional ISA INT mask, return an APIC mask. 1227 */ 1228u_int 1229isa_apic_mask(u_int isa_mask) 1230{ 1231 int isa_irq; 1232 int apic_pin; 1233 1234#if defined(SKIP_IRQ15_REDIRECT) 1235 if (isa_mask == (1 << 15)) { 1236 printf("skipping ISA IRQ15 redirect\n"); 1237 return isa_mask; 1238 } 1239#endif /* SKIP_IRQ15_REDIRECT */ 1240 1241 isa_irq = ffs(isa_mask); /* find its bit position */ 1242 if (isa_irq == 0) /* doesn't exist */ 1243 return 0; 1244 --isa_irq; /* make it zero based */ 1245 1246 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */ 1247 if (apic_pin == -1) 1248 return 0; 1249 1250 return (1 << apic_pin); /* convert pin# to a mask */ 1251} 1252 1253 1254/* 1255 * Determine which APIC pin an ISA/EISA INT is attached to. 1256 */ 1257#define INTTYPE(I) (io_apic_ints[(I)].int_type) 1258#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) 1259#define INTIRQ(I) (io_apic_ints[(I)].int_vector) 1260#define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id)) 1261 1262#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) 1263int 1264isa_apic_irq(int isa_irq) 1265{ 1266 int intr; 1267 1268 for (intr = 0; intr < nintrs; ++intr) { /* check each record */ 1269 if (INTTYPE(intr) == 0) { /* standard INT */ 1270 if (SRCBUSIRQ(intr) == isa_irq) { 1271 if (apic_int_is_bus_type(intr, ISA) || 1272 apic_int_is_bus_type(intr, EISA)) 1273 return INTIRQ(intr); /* found */ 1274 } 1275 } 1276 } 1277 return -1; /* NOT found */ 1278} 1279 1280 1281/* 1282 * Determine which APIC pin a PCI INT is attached to. 1283 */ 1284#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) 1285#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) 1286#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) 1287int 1288pci_apic_irq(int pciBus, int pciDevice, int pciInt) 1289{ 1290 int intr; 1291 1292 --pciInt; /* zero based */ 1293 1294 for (intr = 0; intr < nintrs; ++intr) /* check each record */ 1295 if ((INTTYPE(intr) == 0) /* standard INT */ 1296 && (SRCBUSID(intr) == pciBus) 1297 && (SRCBUSDEVICE(intr) == pciDevice) 1298 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ 1299 if (apic_int_is_bus_type(intr, PCI)) 1300 return INTIRQ(intr); /* exact match */ 1301 1302 return -1; /* NOT found */ 1303} 1304 1305int 1306next_apic_irq(int irq) 1307{ 1308 int intr, ointr; 1309 int bus, bustype; 1310 1311 bus = 0; 1312 bustype = 0; 1313 for (intr = 0; intr < nintrs; intr++) { 1314 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0) 1315 continue; 1316 bus = SRCBUSID(intr); 1317 bustype = apic_bus_type(bus); 1318 if (bustype != ISA && 1319 bustype != EISA && 1320 bustype != PCI) 1321 continue; 1322 break; 1323 } 1324 if (intr >= nintrs) { 1325 return -1; 1326 } 1327 for (ointr = intr + 1; ointr < nintrs; ointr++) { 1328 if (INTTYPE(ointr) != 0) 1329 continue; 1330 if (bus != SRCBUSID(ointr)) 1331 continue; 1332 if (bustype == PCI) { 1333 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr)) 1334 continue; 1335 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr)) 1336 continue; 1337 } 1338 if (bustype == ISA || bustype == EISA) { 1339 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr)) 1340 continue; 1341 } 1342 if (INTPIN(intr) == INTPIN(ointr)) 1343 continue; 1344 break; 1345 } 1346 if (ointr >= nintrs) { 1347 return -1; 1348 } 1349 return INTIRQ(ointr); 1350} 1351#undef SRCBUSLINE 1352#undef SRCBUSDEVICE 1353#undef SRCBUSID 1354#undef SRCBUSIRQ 1355 1356#undef INTPIN 1357#undef INTIRQ 1358#undef INTAPIC 1359#undef INTTYPE 1360 1361 1362/* 1363 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt. 1364 * 1365 * XXX FIXME: 1366 * Exactly what this means is unclear at this point. It is a solution 1367 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard 1368 * could route any of the ISA INTs to upper (>15) IRQ values. But most would 1369 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an 1370 * option. 1371 */ 1372int 1373undirect_isa_irq(int rirq) 1374{ 1375#if defined(READY) 1376 printf("Freeing redirected ISA irq %d.\n", rirq); 1377 /** FIXME: tickle the MB redirector chip */ 1378 return ???; 1379#else 1380 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq); 1381 return 0; 1382#endif /* READY */ 1383} 1384 1385 1386/* 1387 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt 1388 */ 1389int 1390undirect_pci_irq(int rirq) 1391{ 1392#if defined(READY) 1393 if (bootverbose) 1394 printf("Freeing redirected PCI irq %d.\n", rirq); 1395 1396 /** FIXME: tickle the MB redirector chip */ 1397 return ???; 1398#else 1399 if (bootverbose) 1400 printf("Freeing (NOT implemented) redirected PCI irq %d.\n", 1401 rirq); 1402 return 0; 1403#endif /* READY */ 1404} 1405 1406 1407/* 1408 * given a bus ID, return: 1409 * the bus type if found 1410 * -1 if NOT found 1411 */ 1412int 1413apic_bus_type(int id) 1414{ 1415 int x; 1416 1417 for (x = 0; x < mp_nbusses; ++x) 1418 if (bus_data[x].bus_id == id) 1419 return bus_data[x].bus_type; 1420 1421 return -1; 1422} 1423 1424 1425/* 1426 * given a LOGICAL APIC# and pin#, return: 1427 * the associated src bus ID if found 1428 * -1 if NOT found 1429 */ 1430int 1431apic_src_bus_id(int apic, int pin) 1432{ 1433 int x; 1434 1435 /* search each of the possible INTerrupt sources */ 1436 for (x = 0; x < nintrs; ++x) 1437 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1438 (pin == io_apic_ints[x].dst_apic_int)) 1439 return (io_apic_ints[x].src_bus_id); 1440 1441 return -1; /* NOT found */ 1442} 1443 1444 1445/* 1446 * given a LOGICAL APIC# and pin#, return: 1447 * the associated src bus IRQ if found 1448 * -1 if NOT found 1449 */ 1450int 1451apic_src_bus_irq(int apic, int pin) 1452{ 1453 int x; 1454 1455 for (x = 0; x < nintrs; x++) 1456 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1457 (pin == io_apic_ints[x].dst_apic_int)) 1458 return (io_apic_ints[x].src_bus_irq); 1459 1460 return -1; /* NOT found */ 1461} 1462 1463 1464/* 1465 * given a LOGICAL APIC# and pin#, return: 1466 * the associated INTerrupt type if found 1467 * -1 if NOT found 1468 */ 1469int 1470apic_int_type(int apic, int pin) 1471{ 1472 int x; 1473 1474 /* search each of the possible INTerrupt sources */ 1475 for (x = 0; x < nintrs; ++x) 1476 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1477 (pin == io_apic_ints[x].dst_apic_int)) 1478 return (io_apic_ints[x].int_type); 1479 1480 return -1; /* NOT found */ 1481} 1482 1483int 1484apic_irq(int apic, int pin) 1485{ 1486 int x; 1487 int res; 1488 1489 for (x = 0; x < nintrs; ++x) 1490 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1491 (pin == io_apic_ints[x].dst_apic_int)) { 1492 res = io_apic_ints[x].int_vector; 1493 if (res == 0xff) 1494 return -1; 1495 if (apic != int_to_apicintpin[res].ioapic) 1496 panic("apic_irq: inconsistent table"); 1497 if (pin != int_to_apicintpin[res].int_pin) 1498 panic("apic_irq inconsistent table (2)"); 1499 return res; 1500 } 1501 return -1; 1502} 1503 1504 1505/* 1506 * given a LOGICAL APIC# and pin#, return: 1507 * the associated trigger mode if found 1508 * -1 if NOT found 1509 */ 1510int 1511apic_trigger(int apic, int pin) 1512{ 1513 int x; 1514 1515 /* search each of the possible INTerrupt sources */ 1516 for (x = 0; x < nintrs; ++x) 1517 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1518 (pin == io_apic_ints[x].dst_apic_int)) 1519 return ((io_apic_ints[x].int_flags >> 2) & 0x03); 1520 1521 return -1; /* NOT found */ 1522} 1523 1524 1525/* 1526 * given a LOGICAL APIC# and pin#, return: 1527 * the associated 'active' level if found 1528 * -1 if NOT found 1529 */ 1530int 1531apic_polarity(int apic, int pin) 1532{ 1533 int x; 1534 1535 /* search each of the possible INTerrupt sources */ 1536 for (x = 0; x < nintrs; ++x) 1537 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1538 (pin == io_apic_ints[x].dst_apic_int)) 1539 return (io_apic_ints[x].int_flags & 0x03); 1540 1541 return -1; /* NOT found */ 1542} 1543 1544 1545/* 1546 * set data according to MP defaults 1547 * FIXME: probably not complete yet... 1548 */ 1549static void 1550default_mp_table(int type) 1551{ 1552 int ap_cpu_id; 1553#if defined(APIC_IO) 1554 u_int32_t ux; 1555 int io_apic_id; 1556 int pin; 1557#endif /* APIC_IO */ 1558 1559#if 0 1560 printf(" MP default config type: %d\n", type); 1561 switch (type) { 1562 case 1: 1563 printf(" bus: ISA, APIC: 82489DX\n"); 1564 break; 1565 case 2: 1566 printf(" bus: EISA, APIC: 82489DX\n"); 1567 break; 1568 case 3: 1569 printf(" bus: EISA, APIC: 82489DX\n"); 1570 break; 1571 case 4: 1572 printf(" bus: MCA, APIC: 82489DX\n"); 1573 break; 1574 case 5: 1575 printf(" bus: ISA+PCI, APIC: Integrated\n"); 1576 break; 1577 case 6: 1578 printf(" bus: EISA+PCI, APIC: Integrated\n"); 1579 break; 1580 case 7: 1581 printf(" bus: MCA+PCI, APIC: Integrated\n"); 1582 break; 1583 default: 1584 printf(" future type\n"); 1585 break; 1586 /* NOTREACHED */ 1587 } 1588#endif /* 0 */ 1589 1590 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24; 1591 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; 1592 1593 /* BSP */ 1594 CPU_TO_ID(0) = boot_cpu_id; 1595 ID_TO_CPU(boot_cpu_id) = 0; 1596 1597 /* one and only AP */ 1598 CPU_TO_ID(1) = ap_cpu_id; 1599 ID_TO_CPU(ap_cpu_id) = 1; 1600 1601#if defined(APIC_IO) 1602 /* one and only IO APIC */ 1603 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; 1604 1605 /* 1606 * sanity check, refer to MP spec section 3.6.6, last paragraph 1607 * necessary as some hardware isn't properly setting up the IO APIC 1608 */ 1609#if defined(REALLY_ANAL_IOAPICID_VALUE) 1610 if (io_apic_id != 2) { 1611#else 1612 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { 1613#endif /* REALLY_ANAL_IOAPICID_VALUE */ 1614 ux = io_apic_read(0, IOAPIC_ID); /* get current contents */ 1615 ux &= ~APIC_ID_MASK; /* clear the ID field */ 1616 ux |= 0x02000000; /* set it to '2' */ 1617 io_apic_write(0, IOAPIC_ID, ux); /* write new value */ 1618 ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */ 1619 if ((ux & APIC_ID_MASK) != 0x02000000) 1620 panic("can't control IO APIC ID, reg: 0x%08x", ux); 1621 io_apic_id = 2; 1622 } 1623 IO_TO_ID(0) = io_apic_id; 1624 ID_TO_IO(io_apic_id) = 0; 1625#endif /* APIC_IO */ 1626 1627 /* fill out bus entries */ 1628 switch (type) { 1629 case 1: 1630 case 2: 1631 case 3: 1632 case 5: 1633 case 6: 1634 bus_data[0].bus_id = default_data[type - 1][1]; 1635 bus_data[0].bus_type = default_data[type - 1][2]; 1636 bus_data[1].bus_id = default_data[type - 1][3]; 1637 bus_data[1].bus_type = default_data[type - 1][4]; 1638 break; 1639 1640 /* case 4: case 7: MCA NOT supported */ 1641 default: /* illegal/reserved */ 1642 panic("BAD default MP config: %d", type); 1643 /* NOTREACHED */ 1644 } 1645 1646#if defined(APIC_IO) 1647 /* general cases from MP v1.4, table 5-2 */ 1648 for (pin = 0; pin < 16; ++pin) { 1649 io_apic_ints[pin].int_type = 0; 1650 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */ 1651 io_apic_ints[pin].src_bus_id = 0; 1652 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */ 1653 io_apic_ints[pin].dst_apic_id = io_apic_id; 1654 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */ 1655 } 1656 1657 /* special cases from MP v1.4, table 5-2 */ 1658 if (type == 2) { 1659 io_apic_ints[2].int_type = 0xff; /* N/C */ 1660 io_apic_ints[13].int_type = 0xff; /* N/C */ 1661#if !defined(APIC_MIXED_MODE) 1662 /** FIXME: ??? */ 1663 panic("sorry, can't support type 2 default yet"); 1664#endif /* APIC_MIXED_MODE */ 1665 } 1666 else 1667 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ 1668 1669 if (type == 7) 1670 io_apic_ints[0].int_type = 0xff; /* N/C */ 1671 else 1672 io_apic_ints[0].int_type = 3; /* vectored 8259 */ 1673#endif /* APIC_IO */ 1674} 1675 1676 1677/* 1678 * initialize all the SMP locks 1679 */ 1680 1681/* critical region around IO APIC, apic_imen */ 1682struct simplelock imen_lock; 1683 1684/* critical region around splxx(), cpl, cml, cil, ipending */ 1685struct simplelock cpl_lock; 1686 1687/* Make FAST_INTR() routines sequential */ 1688struct simplelock fast_intr_lock; 1689 1690/* critical region around INTR() routines */ 1691struct simplelock intr_lock; 1692 1693/* lock regions protected in UP kernel via cli/sti */ 1694struct simplelock mpintr_lock; 1695 1696/* lock region used by kernel profiling */ 1697struct simplelock mcount_lock; 1698 1699#ifdef USE_COMLOCK 1700/* locks com (tty) data/hardware accesses: a FASTINTR() */ 1701struct simplelock com_lock; 1702#endif /* USE_COMLOCK */ 1703 1704#ifdef USE_CLOCKLOCK 1705/* lock regions around the clock hardware */ 1706struct simplelock clock_lock; 1707#endif /* USE_CLOCKLOCK */ 1708 1709static void 1710init_locks(void) 1711{ 1712 /* 1713 * Get the initial mp_lock with a count of 1 for the BSP. 1714 * This uses a LOGICAL cpu ID, ie BSP == 0. 1715 */ 1716 mp_lock = 0x00000001; 1717 1718 /* ISR uses its own "giant lock" */ 1719 isr_lock = FREE_LOCK; 1720 1721#if defined(APIC_INTR_DIAGNOSTIC) && defined(APIC_INTR_DIAGNOSTIC_IRQ) 1722 s_lock_init((struct simplelock*)&apic_itrace_debuglock); 1723#endif 1724 1725 s_lock_init((struct simplelock*)&mpintr_lock); 1726 1727 s_lock_init((struct simplelock*)&mcount_lock); 1728 1729 s_lock_init((struct simplelock*)&fast_intr_lock); 1730 s_lock_init((struct simplelock*)&intr_lock); 1731 s_lock_init((struct simplelock*)&imen_lock); 1732 s_lock_init((struct simplelock*)&cpl_lock); 1733 1734#ifdef USE_COMLOCK 1735 s_lock_init((struct simplelock*)&com_lock); 1736#endif /* USE_COMLOCK */ 1737#ifdef USE_CLOCKLOCK 1738 s_lock_init((struct simplelock*)&clock_lock); 1739#endif /* USE_CLOCKLOCK */ 1740} 1741 1742 1743/* 1744 * start each AP in our list 1745 */ 1746static int 1747start_all_aps(u_int boot_addr) 1748{ 1749 int x, i; 1750 u_char mpbiosreason; 1751 u_long mpbioswarmvec; 1752 pd_entry_t *newptd; 1753 pt_entry_t *newpt; 1754 struct globaldata *gd; 1755 char *stack; 1756 pd_entry_t *myPTD; 1757 1758 POSTCODE(START_ALL_APS_POST); 1759 1760 /* initialize BSP's local APIC */ 1761 apic_initialize(); 1762 bsp_apic_ready = 1; 1763 1764 /* install the AP 1st level boot code */ 1765 install_ap_tramp(boot_addr); 1766 1767 1768 /* save the current value of the warm-start vector */ 1769 mpbioswarmvec = *((u_long *) WARMBOOT_OFF); 1770 outb(CMOS_REG, BIOS_RESET); 1771 mpbiosreason = inb(CMOS_DATA); 1772 1773 /* record BSP in CPU map */ 1774 all_cpus = 1; 1775 1776 /* start each AP */ 1777 for (x = 1; x <= mp_naps; ++x) { 1778 1779 /* This is a bit verbose, it will go away soon. */ 1780 1781 /* alloc new page table directory */ 1782 newptd = (pd_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE)); 1783 1784 /* Store the virtual PTD address for this CPU */ 1785 IdlePTDS[x] = newptd; 1786 1787 /* clone currently active one (ie: IdlePTD) */ 1788 bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */ 1789 1790 /* set up 0 -> 4MB P==V mapping for AP boot */ 1791 newptd[0] = (void *)(uintptr_t)(PG_V | PG_RW | 1792 ((uintptr_t)(void *)KPTphys & PG_FRAME)); 1793 1794 /* store PTD for this AP's boot sequence */ 1795 myPTD = (pd_entry_t *)vtophys(newptd); 1796 1797 /* alloc new page table page */ 1798 newpt = (pt_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE)); 1799 1800 /* set the new PTD's private page to point there */ 1801 newptd[MPPTDI] = (pt_entry_t)(PG_V | PG_RW | vtophys(newpt)); 1802 1803 /* install self referential entry */ 1804 newptd[PTDPTDI] = (pd_entry_t)(PG_V | PG_RW | vtophys(newptd)); 1805 1806 /* allocate a new private data page */ 1807 gd = (struct globaldata *)kmem_alloc(kernel_map, PAGE_SIZE); 1808 1809 /* wire it into the private page table page */ 1810 newpt[0] = (pt_entry_t)(PG_V | PG_RW | vtophys(gd)); 1811 1812 /* wire the ptp into itself for access */ 1813 newpt[1] = (pt_entry_t)(PG_V | PG_RW | vtophys(newpt)); 1814 1815 /* copy in the pointer to the local apic */ 1816 newpt[2] = SMP_prvpt[2]; 1817 1818 /* and the IO apic mapping[s] */ 1819 for (i = 16; i < 32; i++) 1820 newpt[i] = SMP_prvpt[i]; 1821 1822 /* allocate and set up an idle stack data page */ 1823 stack = (char *)kmem_alloc(kernel_map, UPAGES*PAGE_SIZE); 1824 for (i = 0; i < UPAGES; i++) 1825 newpt[i + 3] = (pt_entry_t)(PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 1826 1827 newpt[3 + UPAGES] = 0; /* *prv_CMAP1 */ 1828 newpt[4 + UPAGES] = 0; /* *prv_CMAP2 */ 1829 newpt[5 + UPAGES] = 0; /* *prv_CMAP3 */ 1830 newpt[6 + UPAGES] = 0; /* *prv_PMAP1 */ 1831 1832 /* prime data page for it to use */ 1833 gd->cpuid = x; 1834 gd->cpu_lockid = x << 24; 1835 gd->my_idlePTD = myPTD; 1836 gd->prv_CMAP1 = &newpt[3 + UPAGES]; 1837 gd->prv_CMAP2 = &newpt[4 + UPAGES]; 1838 gd->prv_CMAP3 = &newpt[5 + UPAGES]; 1839 gd->prv_PMAP1 = &newpt[6 + UPAGES]; 1840 1841 /* setup a vector to our boot code */ 1842 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 1843 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); 1844 outb(CMOS_REG, BIOS_RESET); 1845 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 1846 1847 bootPTD = myPTD; 1848 /* attempt to start the Application Processor */ 1849 CHECK_INIT(99); /* setup checkpoints */ 1850 if (!start_ap(x, boot_addr)) { 1851 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); 1852 CHECK_PRINT("trace"); /* show checkpoints */ 1853 /* better panic as the AP may be running loose */ 1854 printf("panic y/n? [y] "); 1855 if (cngetc() != 'n') 1856 panic("bye-bye"); 1857 } 1858 CHECK_PRINT("trace"); /* show checkpoints */ 1859 1860 /* record its version info */ 1861 cpu_apic_versions[x] = cpu_apic_versions[0]; 1862 1863 all_cpus |= (1 << x); /* record AP in CPU map */ 1864 } 1865 1866 /* build our map of 'other' CPUs */ 1867 other_cpus = all_cpus & ~(1 << cpuid); 1868 1869 /* fill in our (BSP) APIC version */ 1870 cpu_apic_versions[0] = lapic.version; 1871 1872 /* restore the warmstart vector */ 1873 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 1874 outb(CMOS_REG, BIOS_RESET); 1875 outb(CMOS_DATA, mpbiosreason); 1876 1877 /* 1878 * Set up the idle context for the BSP. Similar to above except 1879 * that some was done by locore, some by pmap.c and some is implicit 1880 * because the BSP is cpu#0 and the page is initially zero, and also 1881 * because we can refer to variables by name on the BSP.. 1882 */ 1883 newptd = (pd_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE)); 1884 1885 bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */ 1886 IdlePTDS[0] = newptd; 1887 1888 /* Point PTD[] to this page instead of IdlePTD's physical page */ 1889 newptd[PTDPTDI] = (pd_entry_t)(PG_V | PG_RW | vtophys(newptd)); 1890 1891 my_idlePTD = (pd_entry_t *)vtophys(newptd); 1892 1893 /* Allocate and setup BSP idle stack */ 1894 stack = (char *)kmem_alloc(kernel_map, UPAGES * PAGE_SIZE); 1895 for (i = 0; i < UPAGES; i++) 1896 SMP_prvpt[i + 3] = (pt_entry_t)(PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 1897 1898 pmap_set_opt_bsp(); 1899 1900 for (i = 0; i < mp_ncpus; i++) { 1901 bcopy( (int *) PTD + KPTDI, (int *) IdlePTDS[i] + KPTDI, NKPDE * sizeof (int)); 1902 } 1903 1904 /* number of APs actually started */ 1905 return mp_ncpus - 1; 1906} 1907 1908 1909/* 1910 * load the 1st level AP boot code into base memory. 1911 */ 1912 1913/* targets for relocation */ 1914extern void bigJump(void); 1915extern void bootCodeSeg(void); 1916extern void bootDataSeg(void); 1917extern void MPentry(void); 1918extern u_int MP_GDT; 1919extern u_int mp_gdtbase; 1920 1921static void 1922install_ap_tramp(u_int boot_addr) 1923{ 1924 int x; 1925 int size = *(int *) ((u_long) & bootMP_size); 1926 u_char *src = (u_char *) ((u_long) bootMP); 1927 u_char *dst = (u_char *) boot_addr + KERNBASE; 1928 u_int boot_base = (u_int) bootMP; 1929 u_int8_t *dst8; 1930 u_int16_t *dst16; 1931 u_int32_t *dst32; 1932 1933 POSTCODE(INSTALL_AP_TRAMP_POST); 1934 1935 for (x = 0; x < size; ++x) 1936 *dst++ = *src++; 1937 1938 /* 1939 * modify addresses in code we just moved to basemem. unfortunately we 1940 * need fairly detailed info about mpboot.s for this to work. changes 1941 * to mpboot.s might require changes here. 1942 */ 1943 1944 /* boot code is located in KERNEL space */ 1945 dst = (u_char *) boot_addr + KERNBASE; 1946 1947 /* modify the lgdt arg */ 1948 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 1949 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); 1950 1951 /* modify the ljmp target for MPentry() */ 1952 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 1953 *dst32 = ((u_int) MPentry - KERNBASE); 1954 1955 /* modify the target for boot code segment */ 1956 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 1957 dst8 = (u_int8_t *) (dst16 + 1); 1958 *dst16 = (u_int) boot_addr & 0xffff; 1959 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1960 1961 /* modify the target for boot data segment */ 1962 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 1963 dst8 = (u_int8_t *) (dst16 + 1); 1964 *dst16 = (u_int) boot_addr & 0xffff; 1965 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1966} 1967 1968 1969/* 1970 * this function starts the AP (application processor) identified 1971 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 1972 * to accomplish this. This is necessary because of the nuances 1973 * of the different hardware we might encounter. It ain't pretty, 1974 * but it seems to work. 1975 */ 1976static int 1977start_ap(int logical_cpu, u_int boot_addr) 1978{ 1979 int physical_cpu; 1980 int vector; 1981 int cpus; 1982 u_long icr_lo, icr_hi; 1983 1984 POSTCODE(START_AP_POST); 1985 1986 /* get the PHYSICAL APIC ID# */ 1987 physical_cpu = CPU_TO_ID(logical_cpu); 1988 1989 /* calculate the vector */ 1990 vector = (boot_addr >> 12) & 0xff; 1991 1992 /* used as a watchpoint to signal AP startup */ 1993 cpus = mp_ncpus; 1994 1995 /* 1996 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 1997 * and running the target CPU. OR this INIT IPI might be latched (P5 1998 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 1999 * ignored. 2000 */ 2001 2002 /* setup the address for the target AP */ 2003 icr_hi = lapic.icr_hi & ~APIC_ID_MASK; 2004 icr_hi |= (physical_cpu << 24); 2005 lapic.icr_hi = icr_hi; 2006 2007 /* do an INIT IPI: assert RESET */ 2008 icr_lo = lapic.icr_lo & 0xfff00000; 2009 lapic.icr_lo = icr_lo | 0x0000c500; 2010 2011 /* wait for pending status end */ 2012 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2013 /* spin */ ; 2014 2015 /* do an INIT IPI: deassert RESET */ 2016 lapic.icr_lo = icr_lo | 0x00008500; 2017 2018 /* wait for pending status end */ 2019 u_sleep(10000); /* wait ~10mS */ 2020 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2021 /* spin */ ; 2022 2023 /* 2024 * next we do a STARTUP IPI: the previous INIT IPI might still be 2025 * latched, (P5 bug) this 1st STARTUP would then terminate 2026 * immediately, and the previously started INIT IPI would continue. OR 2027 * the previous INIT IPI has already run. and this STARTUP IPI will 2028 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 2029 * will run. 2030 */ 2031 2032 /* do a STARTUP IPI */ 2033 lapic.icr_lo = icr_lo | 0x00000600 | vector; 2034 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2035 /* spin */ ; 2036 u_sleep(200); /* wait ~200uS */ 2037 2038 /* 2039 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 2040 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 2041 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 2042 * recognized after hardware RESET or INIT IPI. 2043 */ 2044 2045 lapic.icr_lo = icr_lo | 0x00000600 | vector; 2046 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2047 /* spin */ ; 2048 u_sleep(200); /* wait ~200uS */ 2049 2050 /* wait for it to start */ 2051 set_apic_timer(5000000);/* == 5 seconds */ 2052 while (read_apic_timer()) 2053 if (mp_ncpus > cpus) 2054 return 1; /* return SUCCESS */ 2055 2056 return 0; /* return FAILURE */ 2057} 2058 2059 2060/* 2061 * Flush the TLB on all other CPU's 2062 * 2063 * XXX: Needs to handshake and wait for completion before proceding. 2064 */ 2065void 2066smp_invltlb(void) 2067{ 2068#if defined(APIC_IO) 2069 if (smp_started && invltlb_ok) 2070 all_but_self_ipi(XINVLTLB_OFFSET); 2071#endif /* APIC_IO */ 2072} 2073 2074void 2075invlpg(u_int addr) 2076{ 2077 __asm __volatile("invlpg (%0)"::"r"(addr):"memory"); 2078 2079 /* send a message to the other CPUs */ 2080 smp_invltlb(); 2081} 2082 2083void 2084invltlb(void) 2085{ 2086 u_long temp; 2087 2088 /* 2089 * This should be implemented as load_cr3(rcr3()) when load_cr3() is 2090 * inlined. 2091 */ 2092 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory"); 2093 2094 /* send a message to the other CPUs */ 2095 smp_invltlb(); 2096} 2097 2098 2099/* 2100 * When called the executing CPU will send an IPI to all other CPUs 2101 * requesting that they halt execution. 2102 * 2103 * Usually (but not necessarily) called with 'other_cpus' as its arg. 2104 * 2105 * - Signals all CPUs in map to stop. 2106 * - Waits for each to stop. 2107 * 2108 * Returns: 2109 * -1: error 2110 * 0: NA 2111 * 1: ok 2112 * 2113 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs 2114 * from executing at same time. 2115 */ 2116int 2117stop_cpus(u_int map) 2118{ 2119 if (!smp_started) 2120 return 0; 2121 2122 /* send the Xcpustop IPI to all CPUs in map */ 2123 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED); 2124 2125 while ((stopped_cpus & map) != map) 2126 /* spin */ ; 2127 2128 return 1; 2129} 2130 2131 2132/* 2133 * Called by a CPU to restart stopped CPUs. 2134 * 2135 * Usually (but not necessarily) called with 'stopped_cpus' as its arg. 2136 * 2137 * - Signals all CPUs in map to restart. 2138 * - Waits for each to restart. 2139 * 2140 * Returns: 2141 * -1: error 2142 * 0: NA 2143 * 1: ok 2144 */ 2145int 2146restart_cpus(u_int map) 2147{ 2148 if (!smp_started) 2149 return 0; 2150 2151 started_cpus = map; /* signal other cpus to restart */ 2152 2153 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */ 2154 /* spin */ ; 2155 2156 return 1; 2157} 2158 2159int smp_active = 0; /* are the APs allowed to run? */ 2160SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RW, &smp_active, 0, ""); 2161 2162/* XXX maybe should be hw.ncpu */ 2163static int smp_cpus = 1; /* how many cpu's running */ 2164SYSCTL_INT(_machdep, OID_AUTO, smp_cpus, CTLFLAG_RD, &smp_cpus, 0, ""); 2165 2166int invltlb_ok = 0; /* throttle smp_invltlb() till safe */ 2167SYSCTL_INT(_machdep, OID_AUTO, invltlb_ok, CTLFLAG_RW, &invltlb_ok, 0, ""); 2168 2169/* Warning: Do not staticize. Used from swtch.s */ 2170int do_page_zero_idle = 1; /* bzero pages for fun and profit in idleloop */ 2171SYSCTL_INT(_machdep, OID_AUTO, do_page_zero_idle, CTLFLAG_RW, 2172 &do_page_zero_idle, 0, ""); 2173 2174/* Is forwarding of a interrupt to the CPU holding the ISR lock enabled ? */ 2175int forward_irq_enabled = 1; 2176SYSCTL_INT(_machdep, OID_AUTO, forward_irq_enabled, CTLFLAG_RW, 2177 &forward_irq_enabled, 0, ""); 2178 2179/* Enable forwarding of a signal to a process running on a different CPU */ 2180int forward_signal_enabled = 1; 2181SYSCTL_INT(_machdep, OID_AUTO, forward_signal_enabled, CTLFLAG_RW, 2182 &forward_signal_enabled, 0, ""); 2183 2184/* Enable forwarding of roundrobin to all other cpus */ 2185int forward_roundrobin_enabled = 1; 2186SYSCTL_INT(_machdep, OID_AUTO, forward_roundrobin_enabled, CTLFLAG_RW, 2187 &forward_roundrobin_enabled, 0, ""); 2188 2189/* 2190 * This is called once the rest of the system is up and running and we're 2191 * ready to let the AP's out of the pen. 2192 */ 2193void ap_init(void); 2194 2195void 2196ap_init() 2197{ 2198 u_int temp; 2199 u_int apic_id; 2200 2201 smp_cpus++; 2202 2203#if defined(I586_CPU) && !defined(NO_F00F_HACK) 2204 lidt(&r_idt); 2205#endif 2206 2207 /* Build our map of 'other' CPUs. */ 2208 other_cpus = all_cpus & ~(1 << cpuid); 2209 2210 printf("SMP: AP CPU #%d Launched!\n", cpuid); 2211 2212 /* XXX FIXME: i386 specific, and redundant: Setup the FPU. */ 2213 load_cr0((rcr0() & ~CR0_EM) | CR0_MP | CR0_NE | CR0_TS); 2214 2215 /* A quick check from sanity claus */ 2216 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]); 2217 if (cpuid != apic_id) { 2218 printf("SMP: cpuid = %d\n", cpuid); 2219 printf("SMP: apic_id = %d\n", apic_id); 2220 printf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]); 2221 panic("cpuid mismatch! boom!!"); 2222 } 2223 2224 getmtrr(); 2225 2226 /* Init local apic for irq's */ 2227 apic_initialize(); 2228 2229 /* 2230 * Activate smp_invltlb, although strictly speaking, this isn't 2231 * quite correct yet. We should have a bitfield for cpus willing 2232 * to accept TLB flush IPI's or something and sync them. 2233 */ 2234 if (smp_cpus == mp_ncpus) { 2235 invltlb_ok = 1; 2236 smp_started = 1; /* enable IPI's, tlb shootdown, freezes etc */ 2237 smp_active = 1; /* historic */ 2238 } 2239 2240 curproc = NULL; /* make sure */ 2241} 2242 2243#ifdef BETTER_CLOCK 2244 2245#define CHECKSTATE_USER 0 2246#define CHECKSTATE_SYS 1 2247#define CHECKSTATE_INTR 2 2248 2249/* Do not staticize. Used from apic_vector.s */ 2250struct proc* checkstate_curproc[NCPU]; 2251int checkstate_cpustate[NCPU]; 2252u_long checkstate_pc[NCPU]; 2253 2254extern long cp_time[CPUSTATES]; 2255 2256#define PC_TO_INDEX(pc, prof) \ 2257 ((int)(((u_quad_t)((pc) - (prof)->pr_off) * \ 2258 (u_quad_t)((prof)->pr_scale)) >> 16) & ~1) 2259 2260static void 2261addupc_intr_forwarded(struct proc *p, int id, int *astmap) 2262{ 2263 int i; 2264 struct uprof *prof; 2265 u_long pc; 2266 2267 pc = checkstate_pc[id]; 2268 prof = &p->p_stats->p_prof; 2269 if (pc >= prof->pr_off && 2270 (i = PC_TO_INDEX(pc, prof)) < prof->pr_size) { 2271 if ((p->p_flag & P_OWEUPC) == 0) { 2272 prof->pr_addr = pc; 2273 prof->pr_ticks = 1; 2274 p->p_flag |= P_OWEUPC; 2275 } 2276 *astmap |= (1 << id); 2277 } 2278} 2279 2280static void 2281forwarded_statclock(int id, int pscnt, int *astmap) 2282{ 2283 struct pstats *pstats; 2284 long rss; 2285 struct rusage *ru; 2286 struct vmspace *vm; 2287 int cpustate; 2288 struct proc *p; 2289#ifdef GPROF 2290 register struct gmonparam *g; 2291 int i; 2292#endif 2293 2294 p = checkstate_curproc[id]; 2295 cpustate = checkstate_cpustate[id]; 2296 2297 switch (cpustate) { 2298 case CHECKSTATE_USER: 2299 if (p->p_flag & P_PROFIL) 2300 addupc_intr_forwarded(p, id, astmap); 2301 if (pscnt > 1) 2302 return; 2303 p->p_uticks++; 2304 if (p->p_nice > NZERO) 2305 cp_time[CP_NICE]++; 2306 else 2307 cp_time[CP_USER]++; 2308 break; 2309 case CHECKSTATE_SYS: 2310#ifdef GPROF 2311 /* 2312 * Kernel statistics are just like addupc_intr, only easier. 2313 */ 2314 g = &_gmonparam; 2315 if (g->state == GMON_PROF_ON) { 2316 i = checkstate_pc[id] - g->lowpc; 2317 if (i < g->textsize) { 2318 i /= HISTFRACTION * sizeof(*g->kcount); 2319 g->kcount[i]++; 2320 } 2321 } 2322#endif 2323 if (pscnt > 1) 2324 return; 2325 2326 if (!p) 2327 cp_time[CP_IDLE]++; 2328 else { 2329 p->p_sticks++; 2330 cp_time[CP_SYS]++; 2331 } 2332 break; 2333 case CHECKSTATE_INTR: 2334 default: 2335#ifdef GPROF 2336 /* 2337 * Kernel statistics are just like addupc_intr, only easier. 2338 */ 2339 g = &_gmonparam; 2340 if (g->state == GMON_PROF_ON) { 2341 i = checkstate_pc[id] - g->lowpc; 2342 if (i < g->textsize) { 2343 i /= HISTFRACTION * sizeof(*g->kcount); 2344 g->kcount[i]++; 2345 } 2346 } 2347#endif 2348 if (pscnt > 1) 2349 return; 2350 if (p) 2351 p->p_iticks++; 2352 cp_time[CP_INTR]++; 2353 } 2354 if (p != NULL) { 2355 p->p_cpticks++; 2356 if (++p->p_estcpu == 0) 2357 p->p_estcpu--; 2358 if ((p->p_estcpu & 3) == 0) { 2359 resetpriority(p); 2360 if (p->p_priority >= PUSER) 2361 p->p_priority = p->p_usrpri; 2362 } 2363 2364 /* Update resource usage integrals and maximums. */ 2365 if ((pstats = p->p_stats) != NULL && 2366 (ru = &pstats->p_ru) != NULL && 2367 (vm = p->p_vmspace) != NULL) { 2368 ru->ru_ixrss += vm->vm_tsize * PAGE_SIZE / 1024; 2369 ru->ru_idrss += vm->vm_dsize * PAGE_SIZE / 1024; 2370 ru->ru_isrss += vm->vm_ssize * PAGE_SIZE / 1024; 2371 rss = vm->vm_pmap.pm_stats.resident_count * 2372 PAGE_SIZE / 1024; 2373 if (ru->ru_maxrss < rss) 2374 ru->ru_maxrss = rss; 2375 } 2376 } 2377} 2378 2379void 2380forward_statclock(int pscnt) 2381{ 2382 int map; 2383 int id; 2384 int i; 2385 2386 /* Kludge. We don't yet have separate locks for the interrupts 2387 * and the kernel. This means that we cannot let the other processors 2388 * handle complex interrupts while inhibiting them from entering 2389 * the kernel in a non-interrupt context. 2390 * 2391 * What we can do, without changing the locking mechanisms yet, 2392 * is letting the other processors handle a very simple interrupt 2393 * (wich determines the processor states), and do the main 2394 * work ourself. 2395 */ 2396 2397 if (!smp_started || !invltlb_ok || cold || panicstr) 2398 return; 2399 2400 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle ) */ 2401 2402 map = other_cpus & ~stopped_cpus ; 2403 checkstate_probed_cpus = 0; 2404 if (map != 0) 2405 selected_apic_ipi(map, 2406 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED); 2407 2408 i = 0; 2409 while (checkstate_probed_cpus != map) { 2410 /* spin */ 2411 i++; 2412 if (i == 100000) { 2413#ifdef BETTER_CLOCK_DIAGNOSTIC 2414 printf("forward_statclock: checkstate %x\n", 2415 checkstate_probed_cpus); 2416#endif 2417 break; 2418 } 2419 } 2420 2421 /* 2422 * Step 2: walk through other processors processes, update ticks and 2423 * profiling info. 2424 */ 2425 2426 map = 0; 2427 for (id = 0; id < mp_ncpus; id++) { 2428 if (id == cpuid) 2429 continue; 2430 if (((1 << id) & checkstate_probed_cpus) == 0) 2431 continue; 2432 forwarded_statclock(id, pscnt, &map); 2433 } 2434 if (map != 0) { 2435 checkstate_need_ast |= map; 2436 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED); 2437 i = 0; 2438 while ((checkstate_need_ast & map) != 0) { 2439 /* spin */ 2440 i++; 2441 if (i > 100000) { 2442#ifdef BETTER_CLOCK_DIAGNOSTIC 2443 printf("forward_statclock: dropped ast 0x%x\n", 2444 checkstate_need_ast & map); 2445#endif 2446 break; 2447 } 2448 } 2449 } 2450} 2451 2452void 2453forward_hardclock(int pscnt) 2454{ 2455 int map; 2456 int id; 2457 struct proc *p; 2458 struct pstats *pstats; 2459 int i; 2460 2461 /* Kludge. We don't yet have separate locks for the interrupts 2462 * and the kernel. This means that we cannot let the other processors 2463 * handle complex interrupts while inhibiting them from entering 2464 * the kernel in a non-interrupt context. 2465 * 2466 * What we can do, without changing the locking mechanisms yet, 2467 * is letting the other processors handle a very simple interrupt 2468 * (wich determines the processor states), and do the main 2469 * work ourself. 2470 */ 2471 2472 if (!smp_started || !invltlb_ok || cold || panicstr) 2473 return; 2474 2475 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle) */ 2476 2477 map = other_cpus & ~stopped_cpus ; 2478 checkstate_probed_cpus = 0; 2479 if (map != 0) 2480 selected_apic_ipi(map, 2481 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED); 2482 2483 i = 0; 2484 while (checkstate_probed_cpus != map) { 2485 /* spin */ 2486 i++; 2487 if (i == 100000) { 2488#ifdef BETTER_CLOCK_DIAGNOSTIC 2489 printf("forward_hardclock: checkstate %x\n", 2490 checkstate_probed_cpus); 2491#endif 2492 break; 2493 } 2494 } 2495 2496 /* 2497 * Step 2: walk through other processors processes, update virtual 2498 * timer and profiling timer. If stathz == 0, also update ticks and 2499 * profiling info. 2500 */ 2501 2502 map = 0; 2503 for (id = 0; id < mp_ncpus; id++) { 2504 if (id == cpuid) 2505 continue; 2506 if (((1 << id) & checkstate_probed_cpus) == 0) 2507 continue; 2508 p = checkstate_curproc[id]; 2509 if (p) { 2510 pstats = p->p_stats; 2511 if (checkstate_cpustate[id] == CHECKSTATE_USER && 2512 timevalisset(&pstats->p_timer[ITIMER_VIRTUAL].it_value) && 2513 itimerdecr(&pstats->p_timer[ITIMER_VIRTUAL], tick) == 0) { 2514 psignal(p, SIGVTALRM); 2515 map |= (1 << id); 2516 } 2517 if (timevalisset(&pstats->p_timer[ITIMER_PROF].it_value) && 2518 itimerdecr(&pstats->p_timer[ITIMER_PROF], tick) == 0) { 2519 psignal(p, SIGPROF); 2520 map |= (1 << id); 2521 } 2522 } 2523 if (stathz == 0) { 2524 forwarded_statclock( id, pscnt, &map); 2525 } 2526 } 2527 if (map != 0) { 2528 checkstate_need_ast |= map; 2529 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED); 2530 i = 0; 2531 while ((checkstate_need_ast & map) != 0) { 2532 /* spin */ 2533 i++; 2534 if (i > 100000) { 2535#ifdef BETTER_CLOCK_DIAGNOSTIC 2536 printf("forward_hardclock: dropped ast 0x%x\n", 2537 checkstate_need_ast & map); 2538#endif 2539 break; 2540 } 2541 } 2542 } 2543} 2544 2545#endif /* BETTER_CLOCK */ 2546 2547void 2548forward_signal(struct proc *p) 2549{ 2550 int map; 2551 int id; 2552 int i; 2553 2554 /* Kludge. We don't yet have separate locks for the interrupts 2555 * and the kernel. This means that we cannot let the other processors 2556 * handle complex interrupts while inhibiting them from entering 2557 * the kernel in a non-interrupt context. 2558 * 2559 * What we can do, without changing the locking mechanisms yet, 2560 * is letting the other processors handle a very simple interrupt 2561 * (wich determines the processor states), and do the main 2562 * work ourself. 2563 */ 2564 2565 if (!smp_started || !invltlb_ok || cold || panicstr) 2566 return; 2567 if (!forward_signal_enabled) 2568 return; 2569 while (1) { 2570 if (p->p_stat != SRUN) 2571 return; 2572 id = (u_char) p->p_oncpu; 2573 if (id == 0xff) 2574 return; 2575 map = (1<<id); 2576 checkstate_need_ast |= map; 2577 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED); 2578 i = 0; 2579 while ((checkstate_need_ast & map) != 0) { 2580 /* spin */ 2581 i++; 2582 if (i > 100000) { 2583#if 0 2584 printf("forward_signal: dropped ast 0x%x\n", 2585 checkstate_need_ast & map); 2586#endif 2587 break; 2588 } 2589 } 2590 if (id == (u_char) p->p_oncpu) 2591 return; 2592 } 2593} 2594 2595void 2596forward_roundrobin(void) 2597{ 2598 u_int map; 2599 int i; 2600 2601 if (!smp_started || !invltlb_ok || cold || panicstr) 2602 return; 2603 if (!forward_roundrobin_enabled) 2604 return; 2605 resched_cpus |= other_cpus; 2606 map = other_cpus & ~stopped_cpus ; 2607#if 1 2608 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED); 2609#else 2610 (void) all_but_self_ipi(XCPUAST_OFFSET); 2611#endif 2612 i = 0; 2613 while ((checkstate_need_ast & map) != 0) { 2614 /* spin */ 2615 i++; 2616 if (i > 100000) { 2617#if 0 2618 printf("forward_roundrobin: dropped ast 0x%x\n", 2619 checkstate_need_ast & map); 2620#endif 2621 break; 2622 } 2623 } 2624} 2625 2626 2627#ifdef APIC_INTR_REORDER 2628/* 2629 * Maintain mapping from softintr vector to isr bit in local apic. 2630 */ 2631void 2632set_lapic_isrloc(int intr, int vector) 2633{ 2634 if (intr < 0 || intr > 32) 2635 panic("set_apic_isrloc: bad intr argument: %d",intr); 2636 if (vector < ICU_OFFSET || vector > 255) 2637 panic("set_apic_isrloc: bad vector argument: %d",vector); 2638 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2); 2639 apic_isrbit_location[intr].bit = (1<<(vector & 31)); 2640} 2641#endif 2642