mp_x86.c revision 279699
1/*- 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26#include <sys/cdefs.h> 27__FBSDID("$FreeBSD: head/sys/i386/i386/mp_machdep.c 279699 2015-03-06 20:34:28Z jhb $"); 28 29#include "opt_apic.h" 30#include "opt_cpu.h" 31#include "opt_kstack_pages.h" 32#include "opt_pmap.h" 33#include "opt_sched.h" 34#include "opt_smp.h" 35 36#if !defined(lint) 37#if !defined(SMP) 38#error How did you get here? 39#endif 40 41#ifndef DEV_APIC 42#error The apic device is required for SMP, add "device apic" to your config file. 43#endif 44#if defined(CPU_DISABLE_CMPXCHG) && !defined(COMPILING_LINT) 45#error SMP not supported with CPU_DISABLE_CMPXCHG 46#endif 47#endif /* not lint */ 48 49#include <sys/param.h> 50#include <sys/systm.h> 51#include <sys/bus.h> 52#include <sys/cons.h> /* cngetc() */ 53#include <sys/cpuset.h> 54#ifdef GPROF 55#include <sys/gmon.h> 56#endif 57#include <sys/kernel.h> 58#include <sys/ktr.h> 59#include <sys/lock.h> 60#include <sys/malloc.h> 61#include <sys/memrange.h> 62#include <sys/mutex.h> 63#include <sys/pcpu.h> 64#include <sys/proc.h> 65#include <sys/sched.h> 66#include <sys/smp.h> 67#include <sys/sysctl.h> 68 69#include <vm/vm.h> 70#include <vm/vm_param.h> 71#include <vm/pmap.h> 72#include <vm/vm_kern.h> 73#include <vm/vm_extern.h> 74 75#include <x86/apicreg.h> 76#include <machine/clock.h> 77#include <machine/cputypes.h> 78#include <x86/mca.h> 79#include <machine/md_var.h> 80#include <machine/pcb.h> 81#include <machine/psl.h> 82#include <machine/smp.h> 83#include <machine/specialreg.h> 84#include <machine/cpu.h> 85 86#define WARMBOOT_TARGET 0 87#define WARMBOOT_OFF (KERNBASE + 0x0467) 88#define WARMBOOT_SEG (KERNBASE + 0x0469) 89 90#define CMOS_REG (0x70) 91#define CMOS_DATA (0x71) 92#define BIOS_RESET (0x0f) 93#define BIOS_WARM (0x0a) 94 95/* 96 * this code MUST be enabled here and in mpboot.s. 97 * it follows the very early stages of AP boot by placing values in CMOS ram. 98 * it NORMALLY will never be needed and thus the primitive method for enabling. 99 * 100#define CHECK_POINTS 101 */ 102 103#if defined(CHECK_POINTS) && !defined(PC98) 104#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 105#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 106 107#define CHECK_INIT(D); \ 108 CHECK_WRITE(0x34, (D)); \ 109 CHECK_WRITE(0x35, (D)); \ 110 CHECK_WRITE(0x36, (D)); \ 111 CHECK_WRITE(0x37, (D)); \ 112 CHECK_WRITE(0x38, (D)); \ 113 CHECK_WRITE(0x39, (D)); 114 115#define CHECK_PRINT(S); \ 116 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 117 (S), \ 118 CHECK_READ(0x34), \ 119 CHECK_READ(0x35), \ 120 CHECK_READ(0x36), \ 121 CHECK_READ(0x37), \ 122 CHECK_READ(0x38), \ 123 CHECK_READ(0x39)); 124 125#else /* CHECK_POINTS */ 126 127#define CHECK_INIT(D) 128#define CHECK_PRINT(S) 129#define CHECK_WRITE(A, D) 130 131#endif /* CHECK_POINTS */ 132 133/* lock region used by kernel profiling */ 134int mcount_lock; 135 136int mp_naps; /* # of Applications processors */ 137int boot_cpu_id = -1; /* designated BSP */ 138 139extern struct pcpu __pcpu[]; 140 141/* AP uses this during bootstrap. Do not staticize. */ 142char *bootSTK; 143static int bootAP; 144 145/* Free these after use */ 146void *bootstacks[MAXCPU]; 147static void *dpcpu; 148 149struct pcb stoppcbs[MAXCPU]; 150struct susppcb **susppcbs; 151 152/* Variables needed for SMP tlb shootdown. */ 153vm_offset_t smp_tlb_addr1; 154vm_offset_t smp_tlb_addr2; 155volatile int smp_tlb_wait; 156 157#ifdef COUNT_IPIS 158/* Interrupt counts. */ 159static u_long *ipi_preempt_counts[MAXCPU]; 160static u_long *ipi_ast_counts[MAXCPU]; 161u_long *ipi_invltlb_counts[MAXCPU]; 162u_long *ipi_invlrng_counts[MAXCPU]; 163u_long *ipi_invlpg_counts[MAXCPU]; 164u_long *ipi_invlcache_counts[MAXCPU]; 165u_long *ipi_rendezvous_counts[MAXCPU]; 166u_long *ipi_lazypmap_counts[MAXCPU]; 167static u_long *ipi_hardclock_counts[MAXCPU]; 168#endif 169 170/* Default cpu_ops implementation. */ 171struct cpu_ops cpu_ops; 172 173/* 174 * Local data and functions. 175 */ 176 177static volatile cpuset_t ipi_nmi_pending; 178 179/* used to hold the AP's until we are ready to release them */ 180static struct mtx ap_boot_mtx; 181 182/* Set to 1 once we're ready to let the APs out of the pen. */ 183static volatile int aps_ready = 0; 184 185/* 186 * Store data from cpu_add() until later in the boot when we actually setup 187 * the APs. 188 */ 189struct cpu_info { 190 int cpu_present:1; 191 int cpu_bsp:1; 192 int cpu_disabled:1; 193 int cpu_hyperthread:1; 194} static cpu_info[MAX_APIC_ID + 1]; 195int cpu_apic_ids[MAXCPU]; 196int apic_cpuids[MAX_APIC_ID + 1]; 197 198/* Holds pending bitmap based IPIs per CPU */ 199volatile u_int cpu_ipi_pending[MAXCPU]; 200 201static u_int boot_address; 202static int cpu_logical; /* logical cpus per core */ 203static int cpu_cores; /* cores per package */ 204 205static void assign_cpu_ids(void); 206static void install_ap_tramp(void); 207static void set_interrupt_apic_ids(void); 208static int start_all_aps(void); 209static int start_ap(int apic_id); 210static void release_aps(void *dummy); 211 212static u_int hyperthreading_cpus; /* logical cpus sharing L1 cache */ 213static int hyperthreading_allowed = 1; 214 215static void 216mem_range_AP_init(void) 217{ 218 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP) 219 mem_range_softc.mr_op->initAP(&mem_range_softc); 220} 221 222static void 223topo_probe_amd(void) 224{ 225 int core_id_bits; 226 int id; 227 228 /* AMD processors do not support HTT. */ 229 cpu_logical = 1; 230 231 if ((amd_feature2 & AMDID2_CMP) == 0) { 232 cpu_cores = 1; 233 return; 234 } 235 236 core_id_bits = (cpu_procinfo2 & AMDID_COREID_SIZE) >> 237 AMDID_COREID_SIZE_SHIFT; 238 if (core_id_bits == 0) { 239 cpu_cores = (cpu_procinfo2 & AMDID_CMP_CORES) + 1; 240 return; 241 } 242 243 /* Fam 10h and newer should get here. */ 244 for (id = 0; id <= MAX_APIC_ID; id++) { 245 /* Check logical CPU availability. */ 246 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled) 247 continue; 248 /* Check if logical CPU has the same package ID. */ 249 if ((id >> core_id_bits) != (boot_cpu_id >> core_id_bits)) 250 continue; 251 cpu_cores++; 252 } 253} 254 255/* 256 * Round up to the next power of two, if necessary, and then 257 * take log2. 258 * Returns -1 if argument is zero. 259 */ 260static __inline int 261mask_width(u_int x) 262{ 263 264 return (fls(x << (1 - powerof2(x))) - 1); 265} 266 267static void 268topo_probe_0x4(void) 269{ 270 u_int p[4]; 271 int pkg_id_bits; 272 int core_id_bits; 273 int max_cores; 274 int max_logical; 275 int id; 276 277 /* Both zero and one here mean one logical processor per package. */ 278 max_logical = (cpu_feature & CPUID_HTT) != 0 ? 279 (cpu_procinfo & CPUID_HTT_CORES) >> 16 : 1; 280 if (max_logical <= 1) 281 return; 282 283 /* 284 * Because of uniformity assumption we examine only 285 * those logical processors that belong to the same 286 * package as BSP. Further, we count number of 287 * logical processors that belong to the same core 288 * as BSP thus deducing number of threads per core. 289 */ 290 if (cpu_high >= 0x4) { 291 cpuid_count(0x04, 0, p); 292 max_cores = ((p[0] >> 26) & 0x3f) + 1; 293 } else 294 max_cores = 1; 295 core_id_bits = mask_width(max_logical/max_cores); 296 if (core_id_bits < 0) 297 return; 298 pkg_id_bits = core_id_bits + mask_width(max_cores); 299 300 for (id = 0; id <= MAX_APIC_ID; id++) { 301 /* Check logical CPU availability. */ 302 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled) 303 continue; 304 /* Check if logical CPU has the same package ID. */ 305 if ((id >> pkg_id_bits) != (boot_cpu_id >> pkg_id_bits)) 306 continue; 307 cpu_cores++; 308 /* Check if logical CPU has the same package and core IDs. */ 309 if ((id >> core_id_bits) == (boot_cpu_id >> core_id_bits)) 310 cpu_logical++; 311 } 312 313 KASSERT(cpu_cores >= 1 && cpu_logical >= 1, 314 ("topo_probe_0x4 couldn't find BSP")); 315 316 cpu_cores /= cpu_logical; 317 hyperthreading_cpus = cpu_logical; 318} 319 320static void 321topo_probe_0xb(void) 322{ 323 u_int p[4]; 324 int bits; 325 int cnt; 326 int i; 327 int logical; 328 int type; 329 int x; 330 331 /* We only support three levels for now. */ 332 for (i = 0; i < 3; i++) { 333 cpuid_count(0x0b, i, p); 334 335 /* Fall back if CPU leaf 11 doesn't really exist. */ 336 if (i == 0 && p[1] == 0) { 337 topo_probe_0x4(); 338 return; 339 } 340 341 bits = p[0] & 0x1f; 342 logical = p[1] &= 0xffff; 343 type = (p[2] >> 8) & 0xff; 344 if (type == 0 || logical == 0) 345 break; 346 /* 347 * Because of uniformity assumption we examine only 348 * those logical processors that belong to the same 349 * package as BSP. 350 */ 351 for (cnt = 0, x = 0; x <= MAX_APIC_ID; x++) { 352 if (!cpu_info[x].cpu_present || 353 cpu_info[x].cpu_disabled) 354 continue; 355 if (x >> bits == boot_cpu_id >> bits) 356 cnt++; 357 } 358 if (type == CPUID_TYPE_SMT) 359 cpu_logical = cnt; 360 else if (type == CPUID_TYPE_CORE) 361 cpu_cores = cnt; 362 } 363 if (cpu_logical == 0) 364 cpu_logical = 1; 365 cpu_cores /= cpu_logical; 366} 367 368/* 369 * Both topology discovery code and code that consumes topology 370 * information assume top-down uniformity of the topology. 371 * That is, all physical packages must be identical and each 372 * core in a package must have the same number of threads. 373 * Topology information is queried only on BSP, on which this 374 * code runs and for which it can query CPUID information. 375 * Then topology is extrapolated on all packages using the 376 * uniformity assumption. 377 */ 378static void 379topo_probe(void) 380{ 381 static int cpu_topo_probed = 0; 382 383 if (cpu_topo_probed) 384 return; 385 386 CPU_ZERO(&logical_cpus_mask); 387 if (mp_ncpus <= 1) 388 cpu_cores = cpu_logical = 1; 389 else if (cpu_vendor_id == CPU_VENDOR_AMD) 390 topo_probe_amd(); 391 else if (cpu_vendor_id == CPU_VENDOR_INTEL) { 392 /* 393 * See Intel(R) 64 Architecture Processor 394 * Topology Enumeration article for details. 395 * 396 * Note that 0x1 <= cpu_high < 4 case should be 397 * compatible with topo_probe_0x4() logic when 398 * CPUID.1:EBX[23:16] > 0 (cpu_cores will be 1) 399 * or it should trigger the fallback otherwise. 400 */ 401 if (cpu_high >= 0xb) 402 topo_probe_0xb(); 403 else if (cpu_high >= 0x1) 404 topo_probe_0x4(); 405 } 406 407 /* 408 * Fallback: assume each logical CPU is in separate 409 * physical package. That is, no multi-core, no SMT. 410 */ 411 if (cpu_cores == 0 || cpu_logical == 0) 412 cpu_cores = cpu_logical = 1; 413 cpu_topo_probed = 1; 414} 415 416struct cpu_group * 417cpu_topo(void) 418{ 419 int cg_flags; 420 421 /* 422 * Determine whether any threading flags are 423 * necessry. 424 */ 425 topo_probe(); 426 if (cpu_logical > 1 && hyperthreading_cpus) 427 cg_flags = CG_FLAG_HTT; 428 else if (cpu_logical > 1) 429 cg_flags = CG_FLAG_SMT; 430 else 431 cg_flags = 0; 432 if (mp_ncpus % (cpu_cores * cpu_logical) != 0) { 433 printf("WARNING: Non-uniform processors.\n"); 434 printf("WARNING: Using suboptimal topology.\n"); 435 return (smp_topo_none()); 436 } 437 /* 438 * No multi-core or hyper-threaded. 439 */ 440 if (cpu_logical * cpu_cores == 1) 441 return (smp_topo_none()); 442 /* 443 * Only HTT no multi-core. 444 */ 445 if (cpu_logical > 1 && cpu_cores == 1) 446 return (smp_topo_1level(CG_SHARE_L1, cpu_logical, cg_flags)); 447 /* 448 * Only multi-core no HTT. 449 */ 450 if (cpu_cores > 1 && cpu_logical == 1) 451 return (smp_topo_1level(CG_SHARE_L2, cpu_cores, cg_flags)); 452 /* 453 * Both HTT and multi-core. 454 */ 455 return (smp_topo_2level(CG_SHARE_L2, cpu_cores, 456 CG_SHARE_L1, cpu_logical, cg_flags)); 457} 458 459 460/* 461 * Calculate usable address in base memory for AP trampoline code. 462 */ 463u_int 464mp_bootaddress(u_int basemem) 465{ 466 467 boot_address = trunc_page(basemem); /* round down to 4k boundary */ 468 if ((basemem - boot_address) < bootMP_size) 469 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */ 470 471 return boot_address; 472} 473 474void 475cpu_add(u_int apic_id, char boot_cpu) 476{ 477 478 if (apic_id > MAX_APIC_ID) { 479 panic("SMP: APIC ID %d too high", apic_id); 480 return; 481 } 482 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice", 483 apic_id)); 484 cpu_info[apic_id].cpu_present = 1; 485 if (boot_cpu) { 486 KASSERT(boot_cpu_id == -1, 487 ("CPU %d claims to be BSP, but CPU %d already is", apic_id, 488 boot_cpu_id)); 489 boot_cpu_id = apic_id; 490 cpu_info[apic_id].cpu_bsp = 1; 491 } 492 if (mp_ncpus < MAXCPU) { 493 mp_ncpus++; 494 mp_maxid = mp_ncpus - 1; 495 } 496 if (bootverbose) 497 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" : 498 "AP"); 499} 500 501void 502cpu_mp_setmaxid(void) 503{ 504 505 /* 506 * mp_maxid should be already set by calls to cpu_add(). 507 * Just sanity check its value here. 508 */ 509 if (mp_ncpus == 0) 510 KASSERT(mp_maxid == 0, 511 ("%s: mp_ncpus is zero, but mp_maxid is not", __func__)); 512 else if (mp_ncpus == 1) 513 mp_maxid = 0; 514 else 515 KASSERT(mp_maxid >= mp_ncpus - 1, 516 ("%s: counters out of sync: max %d, count %d", __func__, 517 mp_maxid, mp_ncpus)); 518} 519 520int 521cpu_mp_probe(void) 522{ 523 524 /* 525 * Always record BSP in CPU map so that the mbuf init code works 526 * correctly. 527 */ 528 CPU_SETOF(0, &all_cpus); 529 if (mp_ncpus == 0) { 530 /* 531 * No CPUs were found, so this must be a UP system. Setup 532 * the variables to represent a system with a single CPU 533 * with an id of 0. 534 */ 535 mp_ncpus = 1; 536 return (0); 537 } 538 539 /* At least one CPU was found. */ 540 if (mp_ncpus == 1) { 541 /* 542 * One CPU was found, so this must be a UP system with 543 * an I/O APIC. 544 */ 545 mp_maxid = 0; 546 return (0); 547 } 548 549 /* At least two CPUs were found. */ 550 return (1); 551} 552 553/* 554 * Initialize the IPI handlers and start up the AP's. 555 */ 556void 557cpu_mp_start(void) 558{ 559 int i; 560 561 /* Initialize the logical ID to APIC ID table. */ 562 for (i = 0; i < MAXCPU; i++) { 563 cpu_apic_ids[i] = -1; 564 cpu_ipi_pending[i] = 0; 565 } 566 567 /* Install an inter-CPU IPI for TLB invalidation */ 568 setidt(IPI_INVLTLB, IDTVEC(invltlb), 569 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 570 setidt(IPI_INVLPG, IDTVEC(invlpg), 571 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 572 setidt(IPI_INVLRNG, IDTVEC(invlrng), 573 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 574 575 /* Install an inter-CPU IPI for cache invalidation. */ 576 setidt(IPI_INVLCACHE, IDTVEC(invlcache), 577 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 578 579 /* Install an inter-CPU IPI for lazy pmap release */ 580 setidt(IPI_LAZYPMAP, IDTVEC(lazypmap), 581 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 582 583 /* Install an inter-CPU IPI for all-CPU rendezvous */ 584 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous), 585 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 586 587 /* Install generic inter-CPU IPI handler */ 588 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler), 589 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 590 591 /* Install an inter-CPU IPI for CPU stop/restart */ 592 setidt(IPI_STOP, IDTVEC(cpustop), 593 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 594 595 /* Install an inter-CPU IPI for CPU suspend/resume */ 596 setidt(IPI_SUSPEND, IDTVEC(cpususpend), 597 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 598 599 /* Set boot_cpu_id if needed. */ 600 if (boot_cpu_id == -1) { 601 boot_cpu_id = PCPU_GET(apic_id); 602 cpu_info[boot_cpu_id].cpu_bsp = 1; 603 } else 604 KASSERT(boot_cpu_id == PCPU_GET(apic_id), 605 ("BSP's APIC ID doesn't match boot_cpu_id")); 606 607 /* Probe logical/physical core configuration. */ 608 topo_probe(); 609 610 assign_cpu_ids(); 611 612 /* Start each Application Processor */ 613 start_all_aps(); 614 615 set_interrupt_apic_ids(); 616} 617 618 619/* 620 * Print various information about the SMP system hardware and setup. 621 */ 622void 623cpu_mp_announce(void) 624{ 625 const char *hyperthread; 626 int i; 627 628 printf("FreeBSD/SMP: %d package(s) x %d core(s)", 629 mp_ncpus / (cpu_cores * cpu_logical), cpu_cores); 630 if (hyperthreading_cpus > 1) 631 printf(" x %d HTT threads", cpu_logical); 632 else if (cpu_logical > 1) 633 printf(" x %d SMT threads", cpu_logical); 634 printf("\n"); 635 636 /* List active CPUs first. */ 637 printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id); 638 for (i = 1; i < mp_ncpus; i++) { 639 if (cpu_info[cpu_apic_ids[i]].cpu_hyperthread) 640 hyperthread = "/HT"; 641 else 642 hyperthread = ""; 643 printf(" cpu%d (AP%s): APIC ID: %2d\n", i, hyperthread, 644 cpu_apic_ids[i]); 645 } 646 647 /* List disabled CPUs last. */ 648 for (i = 0; i <= MAX_APIC_ID; i++) { 649 if (!cpu_info[i].cpu_present || !cpu_info[i].cpu_disabled) 650 continue; 651 if (cpu_info[i].cpu_hyperthread) 652 hyperthread = "/HT"; 653 else 654 hyperthread = ""; 655 printf(" cpu (AP%s): APIC ID: %2d (disabled)\n", hyperthread, 656 i); 657 } 658} 659 660/* 661 * AP CPU's call this to initialize themselves. 662 */ 663void 664init_secondary(void) 665{ 666 struct pcpu *pc; 667 vm_offset_t addr; 668 int gsel_tss; 669 int x, myid; 670 u_int cpuid, cr0; 671 672 /* bootAP is set in start_ap() to our ID. */ 673 myid = bootAP; 674 675 /* Get per-cpu data */ 676 pc = &__pcpu[myid]; 677 678 /* prime data page for it to use */ 679 pcpu_init(pc, myid, sizeof(struct pcpu)); 680 dpcpu_init(dpcpu, myid); 681 pc->pc_apic_id = cpu_apic_ids[myid]; 682 pc->pc_prvspace = pc; 683 pc->pc_curthread = 0; 684 685 gdt_segs[GPRIV_SEL].ssd_base = (int) pc; 686 gdt_segs[GPROC0_SEL].ssd_base = (int) &pc->pc_common_tss; 687 688 for (x = 0; x < NGDT; x++) { 689 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd); 690 } 691 692 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 693 r_gdt.rd_base = (int) &gdt[myid * NGDT]; 694 lgdt(&r_gdt); /* does magic intra-segment return */ 695 696 lidt(&r_idt); 697 698 lldt(_default_ldt); 699 PCPU_SET(currentldt, _default_ldt); 700 701 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 702 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS; 703 PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */ 704 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL)); 705 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16); 706 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd); 707 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt)); 708 ltr(gsel_tss); 709 710 PCPU_SET(fsgs_gdt, &gdt[myid * NGDT + GUFS_SEL].sd); 711 712 /* 713 * Set to a known state: 714 * Set by mpboot.s: CR0_PG, CR0_PE 715 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM 716 */ 717 cr0 = rcr0(); 718 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM); 719 load_cr0(cr0); 720 CHECK_WRITE(0x38, 5); 721 722 /* signal our startup to the BSP. */ 723 mp_naps++; 724 CHECK_WRITE(0x39, 6); 725 726 /* Spin until the BSP releases the AP's. */ 727 while (!aps_ready) 728 ia32_pause(); 729 730 /* BSP may have changed PTD while we were waiting */ 731 invltlb(); 732 for (addr = 0; addr < NKPT * NBPDR - 1; addr += PAGE_SIZE) 733 invlpg(addr); 734 735#if defined(I586_CPU) && !defined(NO_F00F_HACK) 736 lidt(&r_idt); 737#endif 738 739 /* 740 * On real hardware, switch to x2apic mode if possible. Do it 741 * after aps_ready was signalled, to avoid manipulating the 742 * mode while BSP might still want to send some IPI to us 743 * (second startup IPI is ignored on modern hardware etc). 744 */ 745 lapic_xapic_mode(); 746 747 /* Initialize the PAT MSR if present. */ 748 pmap_init_pat(); 749 750 /* set up CPU registers and state */ 751 cpu_setregs(); 752 753 /* set up SSE/NX */ 754 initializecpu(); 755 756 /* set up FPU state on the AP */ 757 npxinit(false); 758 759 if (cpu_ops.cpu_init) 760 cpu_ops.cpu_init(); 761 762 /* A quick check from sanity claus */ 763 cpuid = PCPU_GET(cpuid); 764 if (PCPU_GET(apic_id) != lapic_id()) { 765 printf("SMP: cpuid = %d\n", cpuid); 766 printf("SMP: actual apic_id = %d\n", lapic_id()); 767 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id)); 768 panic("cpuid mismatch! boom!!"); 769 } 770 771 /* Initialize curthread. */ 772 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread")); 773 PCPU_SET(curthread, PCPU_GET(idlethread)); 774 775 mca_init(); 776 777 mtx_lock_spin(&ap_boot_mtx); 778 779 /* Init local apic for irq's */ 780 lapic_setup(1); 781 782 /* Set memory range attributes for this CPU to match the BSP */ 783 mem_range_AP_init(); 784 785 smp_cpus++; 786 787 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", cpuid); 788 printf("SMP: AP CPU #%d Launched!\n", cpuid); 789 790 /* Determine if we are a logical CPU. */ 791 /* XXX Calculation depends on cpu_logical being a power of 2, e.g. 2 */ 792 if (cpu_logical > 1 && PCPU_GET(apic_id) % cpu_logical != 0) 793 CPU_SET(cpuid, &logical_cpus_mask); 794 795 if (bootverbose) 796 lapic_dump("AP"); 797 798 if (smp_cpus == mp_ncpus) { 799 /* enable IPI's, tlb shootdown, freezes etc */ 800 atomic_store_rel_int(&smp_started, 1); 801 } 802 803 mtx_unlock_spin(&ap_boot_mtx); 804 805 /* Wait until all the AP's are up. */ 806 while (smp_started == 0) 807 ia32_pause(); 808 809 /* Start per-CPU event timers. */ 810 cpu_initclocks_ap(); 811 812 /* Enter the scheduler. */ 813 sched_throw(NULL); 814 815 panic("scheduler returned us to %s", __func__); 816 /* NOTREACHED */ 817} 818 819/******************************************************************* 820 * local functions and data 821 */ 822 823/* 824 * We tell the I/O APIC code about all the CPUs we want to receive 825 * interrupts. If we don't want certain CPUs to receive IRQs we 826 * can simply not tell the I/O APIC code about them in this function. 827 * We also do not tell it about the BSP since it tells itself about 828 * the BSP internally to work with UP kernels and on UP machines. 829 */ 830static void 831set_interrupt_apic_ids(void) 832{ 833 u_int i, apic_id; 834 835 for (i = 0; i < MAXCPU; i++) { 836 apic_id = cpu_apic_ids[i]; 837 if (apic_id == -1) 838 continue; 839 if (cpu_info[apic_id].cpu_bsp) 840 continue; 841 if (cpu_info[apic_id].cpu_disabled) 842 continue; 843 844 /* Don't let hyperthreads service interrupts. */ 845 if (cpu_logical > 1 && 846 apic_id % cpu_logical != 0) 847 continue; 848 849 intr_add_cpu(i); 850 } 851} 852 853/* 854 * Assign logical CPU IDs to local APICs. 855 */ 856static void 857assign_cpu_ids(void) 858{ 859 u_int i; 860 861 TUNABLE_INT_FETCH("machdep.hyperthreading_allowed", 862 &hyperthreading_allowed); 863 864 /* Check for explicitly disabled CPUs. */ 865 for (i = 0; i <= MAX_APIC_ID; i++) { 866 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp) 867 continue; 868 869 if (hyperthreading_cpus > 1 && i % hyperthreading_cpus != 0) { 870 cpu_info[i].cpu_hyperthread = 1; 871 872 /* 873 * Don't use HT CPU if it has been disabled by a 874 * tunable. 875 */ 876 if (hyperthreading_allowed == 0) { 877 cpu_info[i].cpu_disabled = 1; 878 continue; 879 } 880 } 881 882 /* Don't use this CPU if it has been disabled by a tunable. */ 883 if (resource_disabled("lapic", i)) { 884 cpu_info[i].cpu_disabled = 1; 885 continue; 886 } 887 } 888 889 if (hyperthreading_allowed == 0 && hyperthreading_cpus > 1) { 890 hyperthreading_cpus = 0; 891 cpu_logical = 1; 892 } 893 894 /* 895 * Assign CPU IDs to local APIC IDs and disable any CPUs 896 * beyond MAXCPU. CPU 0 is always assigned to the BSP. 897 * 898 * To minimize confusion for userland, we attempt to number 899 * CPUs such that all threads and cores in a package are 900 * grouped together. For now we assume that the BSP is always 901 * the first thread in a package and just start adding APs 902 * starting with the BSP's APIC ID. 903 */ 904 mp_ncpus = 1; 905 cpu_apic_ids[0] = boot_cpu_id; 906 apic_cpuids[boot_cpu_id] = 0; 907 for (i = boot_cpu_id + 1; i != boot_cpu_id; 908 i == MAX_APIC_ID ? i = 0 : i++) { 909 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp || 910 cpu_info[i].cpu_disabled) 911 continue; 912 913 if (mp_ncpus < MAXCPU) { 914 cpu_apic_ids[mp_ncpus] = i; 915 apic_cpuids[i] = mp_ncpus; 916 mp_ncpus++; 917 } else 918 cpu_info[i].cpu_disabled = 1; 919 } 920 KASSERT(mp_maxid >= mp_ncpus - 1, 921 ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid, 922 mp_ncpus)); 923} 924 925/* 926 * start each AP in our list 927 */ 928/* Lowest 1MB is already mapped: don't touch*/ 929#define TMPMAP_START 1 930static int 931start_all_aps(void) 932{ 933#ifndef PC98 934 u_char mpbiosreason; 935#endif 936 u_int32_t mpbioswarmvec; 937 int apic_id, cpu, i; 938 939 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); 940 941 /* install the AP 1st level boot code */ 942 install_ap_tramp(); 943 944 /* save the current value of the warm-start vector */ 945 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF); 946#ifndef PC98 947 outb(CMOS_REG, BIOS_RESET); 948 mpbiosreason = inb(CMOS_DATA); 949#endif 950 951 /* set up temporary P==V mapping for AP boot */ 952 /* XXX this is a hack, we should boot the AP on its own stack/PTD */ 953 for (i = TMPMAP_START; i < NKPT; i++) 954 PTD[i] = PTD[KPTDI + i]; 955 invltlb(); 956 957 /* start each AP */ 958 for (cpu = 1; cpu < mp_ncpus; cpu++) { 959 apic_id = cpu_apic_ids[cpu]; 960 961 /* allocate and set up a boot stack data page */ 962 bootstacks[cpu] = 963 (char *)kmem_malloc(kernel_arena, KSTACK_PAGES * PAGE_SIZE, 964 M_WAITOK | M_ZERO); 965 dpcpu = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE, 966 M_WAITOK | M_ZERO); 967 /* setup a vector to our boot code */ 968 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 969 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4); 970#ifndef PC98 971 outb(CMOS_REG, BIOS_RESET); 972 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 973#endif 974 975 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 4; 976 bootAP = cpu; 977 978 /* attempt to start the Application Processor */ 979 CHECK_INIT(99); /* setup checkpoints */ 980 if (!start_ap(apic_id)) { 981 printf("AP #%d (PHY# %d) failed!\n", cpu, apic_id); 982 CHECK_PRINT("trace"); /* show checkpoints */ 983 /* better panic as the AP may be running loose */ 984 printf("panic y/n? [y] "); 985 if (cngetc() != 'n') 986 panic("bye-bye"); 987 } 988 CHECK_PRINT("trace"); /* show checkpoints */ 989 990 CPU_SET(cpu, &all_cpus); /* record AP in CPU map */ 991 } 992 993 /* restore the warmstart vector */ 994 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec; 995 996#ifndef PC98 997 outb(CMOS_REG, BIOS_RESET); 998 outb(CMOS_DATA, mpbiosreason); 999#endif 1000 1001 /* Undo V==P hack from above */ 1002 for (i = TMPMAP_START; i < NKPT; i++) 1003 PTD[i] = 0; 1004 pmap_invalidate_range(kernel_pmap, 0, NKPT * NBPDR - 1); 1005 1006 /* number of APs actually started */ 1007 return mp_naps; 1008} 1009 1010/* 1011 * load the 1st level AP boot code into base memory. 1012 */ 1013 1014/* targets for relocation */ 1015extern void bigJump(void); 1016extern void bootCodeSeg(void); 1017extern void bootDataSeg(void); 1018extern void MPentry(void); 1019extern u_int MP_GDT; 1020extern u_int mp_gdtbase; 1021 1022static void 1023install_ap_tramp(void) 1024{ 1025 int x; 1026 int size = *(int *) ((u_long) & bootMP_size); 1027 vm_offset_t va = boot_address + KERNBASE; 1028 u_char *src = (u_char *) ((u_long) bootMP); 1029 u_char *dst = (u_char *) va; 1030 u_int boot_base = (u_int) bootMP; 1031 u_int8_t *dst8; 1032 u_int16_t *dst16; 1033 u_int32_t *dst32; 1034 1035 KASSERT (size <= PAGE_SIZE, 1036 ("'size' do not fit into PAGE_SIZE, as expected.")); 1037 pmap_kenter(va, boot_address); 1038 pmap_invalidate_page (kernel_pmap, va); 1039 for (x = 0; x < size; ++x) 1040 *dst++ = *src++; 1041 1042 /* 1043 * modify addresses in code we just moved to basemem. unfortunately we 1044 * need fairly detailed info about mpboot.s for this to work. changes 1045 * to mpboot.s might require changes here. 1046 */ 1047 1048 /* boot code is located in KERNEL space */ 1049 dst = (u_char *) va; 1050 1051 /* modify the lgdt arg */ 1052 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 1053 *dst32 = boot_address + ((u_int) & MP_GDT - boot_base); 1054 1055 /* modify the ljmp target for MPentry() */ 1056 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 1057 *dst32 = ((u_int) MPentry - KERNBASE); 1058 1059 /* modify the target for boot code segment */ 1060 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 1061 dst8 = (u_int8_t *) (dst16 + 1); 1062 *dst16 = (u_int) boot_address & 0xffff; 1063 *dst8 = ((u_int) boot_address >> 16) & 0xff; 1064 1065 /* modify the target for boot data segment */ 1066 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 1067 dst8 = (u_int8_t *) (dst16 + 1); 1068 *dst16 = (u_int) boot_address & 0xffff; 1069 *dst8 = ((u_int) boot_address >> 16) & 0xff; 1070} 1071 1072/* 1073 * This function starts the AP (application processor) identified 1074 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 1075 * to accomplish this. This is necessary because of the nuances 1076 * of the different hardware we might encounter. It isn't pretty, 1077 * but it seems to work. 1078 */ 1079static int 1080start_ap(int apic_id) 1081{ 1082 int vector, ms; 1083 int cpus; 1084 1085 /* calculate the vector */ 1086 vector = (boot_address >> 12) & 0xff; 1087 1088 /* used as a watchpoint to signal AP startup */ 1089 cpus = mp_naps; 1090 1091 ipi_startup(apic_id, vector); 1092 1093 /* Wait up to 5 seconds for it to start. */ 1094 for (ms = 0; ms < 5000; ms++) { 1095 if (mp_naps > cpus) 1096 return 1; /* return SUCCESS */ 1097 DELAY(1000); 1098 } 1099 return 0; /* return FAILURE */ 1100} 1101 1102#ifdef COUNT_XINVLTLB_HITS 1103u_int xhits_gbl[MAXCPU]; 1104u_int xhits_pg[MAXCPU]; 1105u_int xhits_rng[MAXCPU]; 1106static SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, ""); 1107SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl, 1108 sizeof(xhits_gbl), "IU", ""); 1109SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg, 1110 sizeof(xhits_pg), "IU", ""); 1111SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng, 1112 sizeof(xhits_rng), "IU", ""); 1113 1114u_int ipi_global; 1115u_int ipi_page; 1116u_int ipi_range; 1117u_int ipi_range_size; 1118SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, ""); 1119SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, ""); 1120SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, ""); 1121SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size, 1122 0, ""); 1123 1124u_int ipi_masked_global; 1125u_int ipi_masked_page; 1126u_int ipi_masked_range; 1127u_int ipi_masked_range_size; 1128SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW, 1129 &ipi_masked_global, 0, ""); 1130SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW, 1131 &ipi_masked_page, 0, ""); 1132SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW, 1133 &ipi_masked_range, 0, ""); 1134SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW, 1135 &ipi_masked_range_size, 0, ""); 1136#endif /* COUNT_XINVLTLB_HITS */ 1137 1138/* 1139 * Init and startup IPI. 1140 */ 1141void 1142ipi_startup(int apic_id, int vector) 1143{ 1144 1145 /* 1146 * This attempts to follow the algorithm described in the 1147 * Intel Multiprocessor Specification v1.4 in section B.4. 1148 * For each IPI, we allow the local APIC ~20us to deliver the 1149 * IPI. If that times out, we panic. 1150 */ 1151 1152 /* 1153 * first we do an INIT IPI: this INIT IPI might be run, resetting 1154 * and running the target CPU. OR this INIT IPI might be latched (P5 1155 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 1156 * ignored. 1157 */ 1158 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_LEVEL | 1159 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id); 1160 lapic_ipi_wait(20); 1161 1162 /* Explicitly deassert the INIT IPI. */ 1163 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_LEVEL | 1164 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, 1165 apic_id); 1166 1167 DELAY(10000); /* wait ~10mS */ 1168 1169 /* 1170 * next we do a STARTUP IPI: the previous INIT IPI might still be 1171 * latched, (P5 bug) this 1st STARTUP would then terminate 1172 * immediately, and the previously started INIT IPI would continue. OR 1173 * the previous INIT IPI has already run. and this STARTUP IPI will 1174 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 1175 * will run. 1176 */ 1177 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 1178 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 1179 vector, apic_id); 1180 if (!lapic_ipi_wait(20)) 1181 panic("Failed to deliver first STARTUP IPI to APIC %d", 1182 apic_id); 1183 DELAY(200); /* wait ~200uS */ 1184 1185 /* 1186 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 1187 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 1188 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 1189 * recognized after hardware RESET or INIT IPI. 1190 */ 1191 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 1192 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 1193 vector, apic_id); 1194 if (!lapic_ipi_wait(20)) 1195 panic("Failed to deliver second STARTUP IPI to APIC %d", 1196 apic_id); 1197 1198 DELAY(200); /* wait ~200uS */ 1199} 1200 1201/* 1202 * Send an IPI to specified CPU handling the bitmap logic. 1203 */ 1204static void 1205ipi_send_cpu(int cpu, u_int ipi) 1206{ 1207 u_int bitmap, old_pending, new_pending; 1208 1209 KASSERT(cpu_apic_ids[cpu] != -1, ("IPI to non-existent CPU %d", cpu)); 1210 1211 if (IPI_IS_BITMAPED(ipi)) { 1212 bitmap = 1 << ipi; 1213 ipi = IPI_BITMAP_VECTOR; 1214 do { 1215 old_pending = cpu_ipi_pending[cpu]; 1216 new_pending = old_pending | bitmap; 1217 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu], 1218 old_pending, new_pending)); 1219 if (old_pending) 1220 return; 1221 } 1222 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]); 1223} 1224 1225/* 1226 * Flush the TLB on all other CPU's 1227 */ 1228static void 1229smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2) 1230{ 1231 u_int ncpu; 1232 1233 ncpu = mp_ncpus - 1; /* does not shootdown self */ 1234 if (ncpu < 1) 1235 return; /* no other cpus */ 1236 if (!(read_eflags() & PSL_I)) 1237 panic("%s: interrupts disabled", __func__); 1238 mtx_lock_spin(&smp_ipi_mtx); 1239 smp_tlb_addr1 = addr1; 1240 smp_tlb_addr2 = addr2; 1241 atomic_store_rel_int(&smp_tlb_wait, 0); 1242 ipi_all_but_self(vector); 1243 while (smp_tlb_wait < ncpu) 1244 ia32_pause(); 1245 mtx_unlock_spin(&smp_ipi_mtx); 1246} 1247 1248static void 1249smp_targeted_tlb_shootdown(cpuset_t mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2) 1250{ 1251 int cpu, ncpu, othercpus; 1252 1253 othercpus = mp_ncpus - 1; 1254 if (CPU_ISFULLSET(&mask)) { 1255 if (othercpus < 1) 1256 return; 1257 } else { 1258 CPU_CLR(PCPU_GET(cpuid), &mask); 1259 if (CPU_EMPTY(&mask)) 1260 return; 1261 } 1262 if (!(read_eflags() & PSL_I)) 1263 panic("%s: interrupts disabled", __func__); 1264 mtx_lock_spin(&smp_ipi_mtx); 1265 smp_tlb_addr1 = addr1; 1266 smp_tlb_addr2 = addr2; 1267 atomic_store_rel_int(&smp_tlb_wait, 0); 1268 if (CPU_ISFULLSET(&mask)) { 1269 ncpu = othercpus; 1270 ipi_all_but_self(vector); 1271 } else { 1272 ncpu = 0; 1273 while ((cpu = CPU_FFS(&mask)) != 0) { 1274 cpu--; 1275 CPU_CLR(cpu, &mask); 1276 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, 1277 vector); 1278 ipi_send_cpu(cpu, vector); 1279 ncpu++; 1280 } 1281 } 1282 while (smp_tlb_wait < ncpu) 1283 ia32_pause(); 1284 mtx_unlock_spin(&smp_ipi_mtx); 1285} 1286 1287void 1288smp_cache_flush(void) 1289{ 1290 1291 if (smp_started) 1292 smp_tlb_shootdown(IPI_INVLCACHE, 0, 0); 1293} 1294 1295void 1296smp_invltlb(void) 1297{ 1298 1299 if (smp_started) { 1300 smp_tlb_shootdown(IPI_INVLTLB, 0, 0); 1301#ifdef COUNT_XINVLTLB_HITS 1302 ipi_global++; 1303#endif 1304 } 1305} 1306 1307void 1308smp_invlpg(vm_offset_t addr) 1309{ 1310 1311 if (smp_started) { 1312 smp_tlb_shootdown(IPI_INVLPG, addr, 0); 1313#ifdef COUNT_XINVLTLB_HITS 1314 ipi_page++; 1315#endif 1316 } 1317} 1318 1319void 1320smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2) 1321{ 1322 1323 if (smp_started) { 1324 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2); 1325#ifdef COUNT_XINVLTLB_HITS 1326 ipi_range++; 1327 ipi_range_size += (addr2 - addr1) / PAGE_SIZE; 1328#endif 1329 } 1330} 1331 1332void 1333smp_masked_invltlb(cpuset_t mask) 1334{ 1335 1336 if (smp_started) { 1337 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0); 1338#ifdef COUNT_XINVLTLB_HITS 1339 ipi_masked_global++; 1340#endif 1341 } 1342} 1343 1344void 1345smp_masked_invlpg(cpuset_t mask, vm_offset_t addr) 1346{ 1347 1348 if (smp_started) { 1349 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0); 1350#ifdef COUNT_XINVLTLB_HITS 1351 ipi_masked_page++; 1352#endif 1353 } 1354} 1355 1356void 1357smp_masked_invlpg_range(cpuset_t mask, vm_offset_t addr1, vm_offset_t addr2) 1358{ 1359 1360 if (smp_started) { 1361 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2); 1362#ifdef COUNT_XINVLTLB_HITS 1363 ipi_masked_range++; 1364 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE; 1365#endif 1366 } 1367} 1368 1369void 1370ipi_bitmap_handler(struct trapframe frame) 1371{ 1372 struct trapframe *oldframe; 1373 struct thread *td; 1374 int cpu = PCPU_GET(cpuid); 1375 u_int ipi_bitmap; 1376 1377 critical_enter(); 1378 td = curthread; 1379 td->td_intr_nesting_level++; 1380 oldframe = td->td_intr_frame; 1381 td->td_intr_frame = &frame; 1382 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]); 1383 if (ipi_bitmap & (1 << IPI_PREEMPT)) { 1384#ifdef COUNT_IPIS 1385 (*ipi_preempt_counts[cpu])++; 1386#endif 1387 sched_preempt(td); 1388 } 1389 if (ipi_bitmap & (1 << IPI_AST)) { 1390#ifdef COUNT_IPIS 1391 (*ipi_ast_counts[cpu])++; 1392#endif 1393 /* Nothing to do for AST */ 1394 } 1395 if (ipi_bitmap & (1 << IPI_HARDCLOCK)) { 1396#ifdef COUNT_IPIS 1397 (*ipi_hardclock_counts[cpu])++; 1398#endif 1399 hardclockintr(); 1400 } 1401 td->td_intr_frame = oldframe; 1402 td->td_intr_nesting_level--; 1403 critical_exit(); 1404} 1405 1406/* 1407 * send an IPI to a set of cpus. 1408 */ 1409void 1410ipi_selected(cpuset_t cpus, u_int ipi) 1411{ 1412 int cpu; 1413 1414 /* 1415 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit 1416 * of help in order to understand what is the source. 1417 * Set the mask of receiving CPUs for this purpose. 1418 */ 1419 if (ipi == IPI_STOP_HARD) 1420 CPU_OR_ATOMIC(&ipi_nmi_pending, &cpus); 1421 1422 while ((cpu = CPU_FFS(&cpus)) != 0) { 1423 cpu--; 1424 CPU_CLR(cpu, &cpus); 1425 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi); 1426 ipi_send_cpu(cpu, ipi); 1427 } 1428} 1429 1430/* 1431 * send an IPI to a specific CPU. 1432 */ 1433void 1434ipi_cpu(int cpu, u_int ipi) 1435{ 1436 1437 /* 1438 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit 1439 * of help in order to understand what is the source. 1440 * Set the mask of receiving CPUs for this purpose. 1441 */ 1442 if (ipi == IPI_STOP_HARD) 1443 CPU_SET_ATOMIC(cpu, &ipi_nmi_pending); 1444 1445 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi); 1446 ipi_send_cpu(cpu, ipi); 1447} 1448 1449/* 1450 * send an IPI to all CPUs EXCEPT myself 1451 */ 1452void 1453ipi_all_but_self(u_int ipi) 1454{ 1455 cpuset_t other_cpus; 1456 1457 other_cpus = all_cpus; 1458 CPU_CLR(PCPU_GET(cpuid), &other_cpus); 1459 if (IPI_IS_BITMAPED(ipi)) { 1460 ipi_selected(other_cpus, ipi); 1461 return; 1462 } 1463 1464 /* 1465 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit 1466 * of help in order to understand what is the source. 1467 * Set the mask of receiving CPUs for this purpose. 1468 */ 1469 if (ipi == IPI_STOP_HARD) 1470 CPU_OR_ATOMIC(&ipi_nmi_pending, &other_cpus); 1471 1472 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1473 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS); 1474} 1475 1476int 1477ipi_nmi_handler() 1478{ 1479 u_int cpuid; 1480 1481 /* 1482 * As long as there is not a simple way to know about a NMI's 1483 * source, if the bitmask for the current CPU is present in 1484 * the global pending bitword an IPI_STOP_HARD has been issued 1485 * and should be handled. 1486 */ 1487 cpuid = PCPU_GET(cpuid); 1488 if (!CPU_ISSET(cpuid, &ipi_nmi_pending)) 1489 return (1); 1490 1491 CPU_CLR_ATOMIC(cpuid, &ipi_nmi_pending); 1492 cpustop_handler(); 1493 return (0); 1494} 1495 1496/* 1497 * Handle an IPI_STOP by saving our current context and spinning until we 1498 * are resumed. 1499 */ 1500void 1501cpustop_handler(void) 1502{ 1503 u_int cpu; 1504 1505 cpu = PCPU_GET(cpuid); 1506 1507 savectx(&stoppcbs[cpu]); 1508 1509 /* Indicate that we are stopped */ 1510 CPU_SET_ATOMIC(cpu, &stopped_cpus); 1511 1512 /* Wait for restart */ 1513 while (!CPU_ISSET(cpu, &started_cpus)) 1514 ia32_pause(); 1515 1516 CPU_CLR_ATOMIC(cpu, &started_cpus); 1517 CPU_CLR_ATOMIC(cpu, &stopped_cpus); 1518 1519 if (cpu == 0 && cpustop_restartfunc != NULL) { 1520 cpustop_restartfunc(); 1521 cpustop_restartfunc = NULL; 1522 } 1523} 1524 1525/* 1526 * Handle an IPI_SUSPEND by saving our current context and spinning until we 1527 * are resumed. 1528 */ 1529void 1530cpususpend_handler(void) 1531{ 1532 u_int cpu; 1533 1534 mtx_assert(&smp_ipi_mtx, MA_NOTOWNED); 1535 1536 cpu = PCPU_GET(cpuid); 1537 if (savectx(&susppcbs[cpu]->sp_pcb)) { 1538 npxsuspend(susppcbs[cpu]->sp_fpususpend); 1539 wbinvd(); 1540 CPU_SET_ATOMIC(cpu, &suspended_cpus); 1541 } else { 1542 npxresume(susppcbs[cpu]->sp_fpususpend); 1543 pmap_init_pat(); 1544 initializecpu(); 1545 PCPU_SET(switchtime, 0); 1546 PCPU_SET(switchticks, ticks); 1547 1548 /* Indicate that we are resumed */ 1549 CPU_CLR_ATOMIC(cpu, &suspended_cpus); 1550 } 1551 1552 /* Wait for resume */ 1553 while (!CPU_ISSET(cpu, &started_cpus)) 1554 ia32_pause(); 1555 1556 if (cpu_ops.cpu_resume) 1557 cpu_ops.cpu_resume(); 1558 1559 /* Resume MCA and local APIC */ 1560 lapic_xapic_mode(); 1561 mca_resume(); 1562 lapic_setup(0); 1563 1564 /* Indicate that we are resumed */ 1565 CPU_CLR_ATOMIC(cpu, &suspended_cpus); 1566 CPU_CLR_ATOMIC(cpu, &started_cpus); 1567} 1568 1569/* 1570 * Handlers for TLB related IPIs 1571 */ 1572void 1573invltlb_handler(void) 1574{ 1575 uint64_t cr3; 1576#ifdef COUNT_XINVLTLB_HITS 1577 xhits_gbl[PCPU_GET(cpuid)]++; 1578#endif /* COUNT_XINVLTLB_HITS */ 1579#ifdef COUNT_IPIS 1580 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++; 1581#endif /* COUNT_IPIS */ 1582 1583 cr3 = rcr3(); 1584 load_cr3(cr3); 1585 atomic_add_int(&smp_tlb_wait, 1); 1586} 1587 1588void 1589invlpg_handler(void) 1590{ 1591#ifdef COUNT_XINVLTLB_HITS 1592 xhits_pg[PCPU_GET(cpuid)]++; 1593#endif /* COUNT_XINVLTLB_HITS */ 1594#ifdef COUNT_IPIS 1595 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++; 1596#endif /* COUNT_IPIS */ 1597 1598 invlpg(smp_tlb_addr1); 1599 1600 atomic_add_int(&smp_tlb_wait, 1); 1601} 1602 1603void 1604invlrng_handler(void) 1605{ 1606 vm_offset_t addr; 1607#ifdef COUNT_XINVLTLB_HITS 1608 xhits_rng[PCPU_GET(cpuid)]++; 1609#endif /* COUNT_XINVLTLB_HITS */ 1610#ifdef COUNT_IPIS 1611 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++; 1612#endif /* COUNT_IPIS */ 1613 1614 addr = smp_tlb_addr1; 1615 do { 1616 invlpg(addr); 1617 addr += PAGE_SIZE; 1618 } while (addr < smp_tlb_addr2); 1619 1620 atomic_add_int(&smp_tlb_wait, 1); 1621} 1622 1623void 1624invlcache_handler(void) 1625{ 1626#ifdef COUNT_IPIS 1627 (*ipi_invlcache_counts[PCPU_GET(cpuid)])++; 1628#endif /* COUNT_IPIS */ 1629 1630 wbinvd(); 1631 atomic_add_int(&smp_tlb_wait, 1); 1632} 1633 1634/* 1635 * This is called once the rest of the system is up and running and we're 1636 * ready to let the AP's out of the pen. 1637 */ 1638static void 1639release_aps(void *dummy __unused) 1640{ 1641 1642 if (mp_ncpus == 1) 1643 return; 1644 atomic_store_rel_int(&aps_ready, 1); 1645 while (smp_started == 0) 1646 ia32_pause(); 1647} 1648SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL); 1649 1650#ifdef COUNT_IPIS 1651/* 1652 * Setup interrupt counters for IPI handlers. 1653 */ 1654static void 1655mp_ipi_intrcnt(void *dummy) 1656{ 1657 char buf[64]; 1658 int i; 1659 1660 CPU_FOREACH(i) { 1661 snprintf(buf, sizeof(buf), "cpu%d:invltlb", i); 1662 intrcnt_add(buf, &ipi_invltlb_counts[i]); 1663 snprintf(buf, sizeof(buf), "cpu%d:invlrng", i); 1664 intrcnt_add(buf, &ipi_invlrng_counts[i]); 1665 snprintf(buf, sizeof(buf), "cpu%d:invlpg", i); 1666 intrcnt_add(buf, &ipi_invlpg_counts[i]); 1667 snprintf(buf, sizeof(buf), "cpu%d:invlcache", i); 1668 intrcnt_add(buf, &ipi_invlcache_counts[i]); 1669 snprintf(buf, sizeof(buf), "cpu%d:preempt", i); 1670 intrcnt_add(buf, &ipi_preempt_counts[i]); 1671 snprintf(buf, sizeof(buf), "cpu%d:ast", i); 1672 intrcnt_add(buf, &ipi_ast_counts[i]); 1673 snprintf(buf, sizeof(buf), "cpu%d:rendezvous", i); 1674 intrcnt_add(buf, &ipi_rendezvous_counts[i]); 1675 snprintf(buf, sizeof(buf), "cpu%d:lazypmap", i); 1676 intrcnt_add(buf, &ipi_lazypmap_counts[i]); 1677 snprintf(buf, sizeof(buf), "cpu%d:hardclock", i); 1678 intrcnt_add(buf, &ipi_hardclock_counts[i]); 1679 } 1680} 1681SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL); 1682#endif 1683