mp_x86.c revision 228535
1/*- 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26#include <sys/cdefs.h> 27__FBSDID("$FreeBSD: head/sys/i386/i386/mp_machdep.c 228535 2011-12-15 17:54:23Z alc $"); 28 29#include "opt_apic.h" 30#include "opt_cpu.h" 31#include "opt_kstack_pages.h" 32#include "opt_pmap.h" 33#include "opt_sched.h" 34#include "opt_smp.h" 35 36#if !defined(lint) 37#if !defined(SMP) 38#error How did you get here? 39#endif 40 41#ifndef DEV_APIC 42#error The apic device is required for SMP, add "device apic" to your config file. 43#endif 44#if defined(CPU_DISABLE_CMPXCHG) && !defined(COMPILING_LINT) 45#error SMP not supported with CPU_DISABLE_CMPXCHG 46#endif 47#endif /* not lint */ 48 49#include <sys/param.h> 50#include <sys/systm.h> 51#include <sys/bus.h> 52#include <sys/cons.h> /* cngetc() */ 53#include <sys/cpuset.h> 54#ifdef GPROF 55#include <sys/gmon.h> 56#endif 57#include <sys/kernel.h> 58#include <sys/ktr.h> 59#include <sys/lock.h> 60#include <sys/malloc.h> 61#include <sys/memrange.h> 62#include <sys/mutex.h> 63#include <sys/pcpu.h> 64#include <sys/proc.h> 65#include <sys/sched.h> 66#include <sys/smp.h> 67#include <sys/sysctl.h> 68 69#include <vm/vm.h> 70#include <vm/vm_param.h> 71#include <vm/pmap.h> 72#include <vm/vm_kern.h> 73#include <vm/vm_extern.h> 74 75#include <x86/apicreg.h> 76#include <machine/clock.h> 77#include <machine/cputypes.h> 78#include <x86/mca.h> 79#include <machine/md_var.h> 80#include <machine/pcb.h> 81#include <machine/psl.h> 82#include <machine/smp.h> 83#include <machine/specialreg.h> 84 85#define WARMBOOT_TARGET 0 86#define WARMBOOT_OFF (KERNBASE + 0x0467) 87#define WARMBOOT_SEG (KERNBASE + 0x0469) 88 89#define CMOS_REG (0x70) 90#define CMOS_DATA (0x71) 91#define BIOS_RESET (0x0f) 92#define BIOS_WARM (0x0a) 93 94/* 95 * this code MUST be enabled here and in mpboot.s. 96 * it follows the very early stages of AP boot by placing values in CMOS ram. 97 * it NORMALLY will never be needed and thus the primitive method for enabling. 98 * 99#define CHECK_POINTS 100 */ 101 102#if defined(CHECK_POINTS) && !defined(PC98) 103#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 104#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 105 106#define CHECK_INIT(D); \ 107 CHECK_WRITE(0x34, (D)); \ 108 CHECK_WRITE(0x35, (D)); \ 109 CHECK_WRITE(0x36, (D)); \ 110 CHECK_WRITE(0x37, (D)); \ 111 CHECK_WRITE(0x38, (D)); \ 112 CHECK_WRITE(0x39, (D)); 113 114#define CHECK_PRINT(S); \ 115 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 116 (S), \ 117 CHECK_READ(0x34), \ 118 CHECK_READ(0x35), \ 119 CHECK_READ(0x36), \ 120 CHECK_READ(0x37), \ 121 CHECK_READ(0x38), \ 122 CHECK_READ(0x39)); 123 124#else /* CHECK_POINTS */ 125 126#define CHECK_INIT(D) 127#define CHECK_PRINT(S) 128#define CHECK_WRITE(A, D) 129 130#endif /* CHECK_POINTS */ 131 132/* lock region used by kernel profiling */ 133int mcount_lock; 134 135int mp_naps; /* # of Applications processors */ 136int boot_cpu_id = -1; /* designated BSP */ 137 138extern struct pcpu __pcpu[]; 139 140/* AP uses this during bootstrap. Do not staticize. */ 141char *bootSTK; 142static int bootAP; 143 144/* Free these after use */ 145void *bootstacks[MAXCPU]; 146static void *dpcpu; 147 148struct pcb stoppcbs[MAXCPU]; 149 150/* Variables needed for SMP tlb shootdown. */ 151vm_offset_t smp_tlb_addr1; 152vm_offset_t smp_tlb_addr2; 153volatile int smp_tlb_wait; 154 155#ifdef COUNT_IPIS 156/* Interrupt counts. */ 157static u_long *ipi_preempt_counts[MAXCPU]; 158static u_long *ipi_ast_counts[MAXCPU]; 159u_long *ipi_invltlb_counts[MAXCPU]; 160u_long *ipi_invlrng_counts[MAXCPU]; 161u_long *ipi_invlpg_counts[MAXCPU]; 162u_long *ipi_invlcache_counts[MAXCPU]; 163u_long *ipi_rendezvous_counts[MAXCPU]; 164u_long *ipi_lazypmap_counts[MAXCPU]; 165static u_long *ipi_hardclock_counts[MAXCPU]; 166#endif 167 168/* 169 * Local data and functions. 170 */ 171 172static volatile cpuset_t ipi_nmi_pending; 173 174/* used to hold the AP's until we are ready to release them */ 175static struct mtx ap_boot_mtx; 176 177/* Set to 1 once we're ready to let the APs out of the pen. */ 178static volatile int aps_ready = 0; 179 180/* 181 * Store data from cpu_add() until later in the boot when we actually setup 182 * the APs. 183 */ 184struct cpu_info { 185 int cpu_present:1; 186 int cpu_bsp:1; 187 int cpu_disabled:1; 188 int cpu_hyperthread:1; 189} static cpu_info[MAX_APIC_ID + 1]; 190int cpu_apic_ids[MAXCPU]; 191int apic_cpuids[MAX_APIC_ID + 1]; 192 193/* Holds pending bitmap based IPIs per CPU */ 194static volatile u_int cpu_ipi_pending[MAXCPU]; 195 196static u_int boot_address; 197static int cpu_logical; /* logical cpus per core */ 198static int cpu_cores; /* cores per package */ 199 200static void assign_cpu_ids(void); 201static void install_ap_tramp(void); 202static void set_interrupt_apic_ids(void); 203static int start_all_aps(void); 204static int start_ap(int apic_id); 205static void release_aps(void *dummy); 206 207static u_int hyperthreading_cpus; /* logical cpus sharing L1 cache */ 208static int hyperthreading_allowed = 1; 209 210static void 211mem_range_AP_init(void) 212{ 213 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP) 214 mem_range_softc.mr_op->initAP(&mem_range_softc); 215} 216 217static void 218topo_probe_amd(void) 219{ 220 int core_id_bits; 221 int id; 222 223 /* AMD processors do not support HTT. */ 224 cpu_logical = 1; 225 226 if ((amd_feature2 & AMDID2_CMP) == 0) { 227 cpu_cores = 1; 228 return; 229 } 230 231 core_id_bits = (cpu_procinfo2 & AMDID_COREID_SIZE) >> 232 AMDID_COREID_SIZE_SHIFT; 233 if (core_id_bits == 0) { 234 cpu_cores = (cpu_procinfo2 & AMDID_CMP_CORES) + 1; 235 return; 236 } 237 238 /* Fam 10h and newer should get here. */ 239 for (id = 0; id <= MAX_APIC_ID; id++) { 240 /* Check logical CPU availability. */ 241 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled) 242 continue; 243 /* Check if logical CPU has the same package ID. */ 244 if ((id >> core_id_bits) != (boot_cpu_id >> core_id_bits)) 245 continue; 246 cpu_cores++; 247 } 248} 249 250/* 251 * Round up to the next power of two, if necessary, and then 252 * take log2. 253 * Returns -1 if argument is zero. 254 */ 255static __inline int 256mask_width(u_int x) 257{ 258 259 return (fls(x << (1 - powerof2(x))) - 1); 260} 261 262static void 263topo_probe_0x4(void) 264{ 265 u_int p[4]; 266 int pkg_id_bits; 267 int core_id_bits; 268 int max_cores; 269 int max_logical; 270 int id; 271 272 /* Both zero and one here mean one logical processor per package. */ 273 max_logical = (cpu_feature & CPUID_HTT) != 0 ? 274 (cpu_procinfo & CPUID_HTT_CORES) >> 16 : 1; 275 if (max_logical <= 1) 276 return; 277 278 /* 279 * Because of uniformity assumption we examine only 280 * those logical processors that belong to the same 281 * package as BSP. Further, we count number of 282 * logical processors that belong to the same core 283 * as BSP thus deducing number of threads per core. 284 */ 285 if (cpu_high >= 0x4) { 286 cpuid_count(0x04, 0, p); 287 max_cores = ((p[0] >> 26) & 0x3f) + 1; 288 } else 289 max_cores = 1; 290 core_id_bits = mask_width(max_logical/max_cores); 291 if (core_id_bits < 0) 292 return; 293 pkg_id_bits = core_id_bits + mask_width(max_cores); 294 295 for (id = 0; id <= MAX_APIC_ID; id++) { 296 /* Check logical CPU availability. */ 297 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled) 298 continue; 299 /* Check if logical CPU has the same package ID. */ 300 if ((id >> pkg_id_bits) != (boot_cpu_id >> pkg_id_bits)) 301 continue; 302 cpu_cores++; 303 /* Check if logical CPU has the same package and core IDs. */ 304 if ((id >> core_id_bits) == (boot_cpu_id >> core_id_bits)) 305 cpu_logical++; 306 } 307 308 KASSERT(cpu_cores >= 1 && cpu_logical >= 1, 309 ("topo_probe_0x4 couldn't find BSP")); 310 311 cpu_cores /= cpu_logical; 312 hyperthreading_cpus = cpu_logical; 313} 314 315static void 316topo_probe_0xb(void) 317{ 318 u_int p[4]; 319 int bits; 320 int cnt; 321 int i; 322 int logical; 323 int type; 324 int x; 325 326 /* We only support three levels for now. */ 327 for (i = 0; i < 3; i++) { 328 cpuid_count(0x0b, i, p); 329 330 /* Fall back if CPU leaf 11 doesn't really exist. */ 331 if (i == 0 && p[1] == 0) { 332 topo_probe_0x4(); 333 return; 334 } 335 336 bits = p[0] & 0x1f; 337 logical = p[1] &= 0xffff; 338 type = (p[2] >> 8) & 0xff; 339 if (type == 0 || logical == 0) 340 break; 341 /* 342 * Because of uniformity assumption we examine only 343 * those logical processors that belong to the same 344 * package as BSP. 345 */ 346 for (cnt = 0, x = 0; x <= MAX_APIC_ID; x++) { 347 if (!cpu_info[x].cpu_present || 348 cpu_info[x].cpu_disabled) 349 continue; 350 if (x >> bits == boot_cpu_id >> bits) 351 cnt++; 352 } 353 if (type == CPUID_TYPE_SMT) 354 cpu_logical = cnt; 355 else if (type == CPUID_TYPE_CORE) 356 cpu_cores = cnt; 357 } 358 if (cpu_logical == 0) 359 cpu_logical = 1; 360 cpu_cores /= cpu_logical; 361} 362 363/* 364 * Both topology discovery code and code that consumes topology 365 * information assume top-down uniformity of the topology. 366 * That is, all physical packages must be identical and each 367 * core in a package must have the same number of threads. 368 * Topology information is queried only on BSP, on which this 369 * code runs and for which it can query CPUID information. 370 * Then topology is extrapolated on all packages using the 371 * uniformity assumption. 372 */ 373static void 374topo_probe(void) 375{ 376 static int cpu_topo_probed = 0; 377 378 if (cpu_topo_probed) 379 return; 380 381 CPU_ZERO(&logical_cpus_mask); 382 if (mp_ncpus <= 1) 383 cpu_cores = cpu_logical = 1; 384 else if (cpu_vendor_id == CPU_VENDOR_AMD) 385 topo_probe_amd(); 386 else if (cpu_vendor_id == CPU_VENDOR_INTEL) { 387 /* 388 * See Intel(R) 64 Architecture Processor 389 * Topology Enumeration article for details. 390 * 391 * Note that 0x1 <= cpu_high < 4 case should be 392 * compatible with topo_probe_0x4() logic when 393 * CPUID.1:EBX[23:16] > 0 (cpu_cores will be 1) 394 * or it should trigger the fallback otherwise. 395 */ 396 if (cpu_high >= 0xb) 397 topo_probe_0xb(); 398 else if (cpu_high >= 0x1) 399 topo_probe_0x4(); 400 } 401 402 /* 403 * Fallback: assume each logical CPU is in separate 404 * physical package. That is, no multi-core, no SMT. 405 */ 406 if (cpu_cores == 0 || cpu_logical == 0) 407 cpu_cores = cpu_logical = 1; 408 cpu_topo_probed = 1; 409} 410 411struct cpu_group * 412cpu_topo(void) 413{ 414 int cg_flags; 415 416 /* 417 * Determine whether any threading flags are 418 * necessry. 419 */ 420 topo_probe(); 421 if (cpu_logical > 1 && hyperthreading_cpus) 422 cg_flags = CG_FLAG_HTT; 423 else if (cpu_logical > 1) 424 cg_flags = CG_FLAG_SMT; 425 else 426 cg_flags = 0; 427 if (mp_ncpus % (cpu_cores * cpu_logical) != 0) { 428 printf("WARNING: Non-uniform processors.\n"); 429 printf("WARNING: Using suboptimal topology.\n"); 430 return (smp_topo_none()); 431 } 432 /* 433 * No multi-core or hyper-threaded. 434 */ 435 if (cpu_logical * cpu_cores == 1) 436 return (smp_topo_none()); 437 /* 438 * Only HTT no multi-core. 439 */ 440 if (cpu_logical > 1 && cpu_cores == 1) 441 return (smp_topo_1level(CG_SHARE_L1, cpu_logical, cg_flags)); 442 /* 443 * Only multi-core no HTT. 444 */ 445 if (cpu_cores > 1 && cpu_logical == 1) 446 return (smp_topo_1level(CG_SHARE_L2, cpu_cores, cg_flags)); 447 /* 448 * Both HTT and multi-core. 449 */ 450 return (smp_topo_2level(CG_SHARE_L2, cpu_cores, 451 CG_SHARE_L1, cpu_logical, cg_flags)); 452} 453 454 455/* 456 * Calculate usable address in base memory for AP trampoline code. 457 */ 458u_int 459mp_bootaddress(u_int basemem) 460{ 461 462 boot_address = trunc_page(basemem); /* round down to 4k boundary */ 463 if ((basemem - boot_address) < bootMP_size) 464 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */ 465 466 return boot_address; 467} 468 469void 470cpu_add(u_int apic_id, char boot_cpu) 471{ 472 473 if (apic_id > MAX_APIC_ID) { 474 panic("SMP: APIC ID %d too high", apic_id); 475 return; 476 } 477 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice", 478 apic_id)); 479 cpu_info[apic_id].cpu_present = 1; 480 if (boot_cpu) { 481 KASSERT(boot_cpu_id == -1, 482 ("CPU %d claims to be BSP, but CPU %d already is", apic_id, 483 boot_cpu_id)); 484 boot_cpu_id = apic_id; 485 cpu_info[apic_id].cpu_bsp = 1; 486 } 487 if (mp_ncpus < MAXCPU) { 488 mp_ncpus++; 489 mp_maxid = mp_ncpus - 1; 490 } 491 if (bootverbose) 492 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" : 493 "AP"); 494} 495 496void 497cpu_mp_setmaxid(void) 498{ 499 500 /* 501 * mp_maxid should be already set by calls to cpu_add(). 502 * Just sanity check its value here. 503 */ 504 if (mp_ncpus == 0) 505 KASSERT(mp_maxid == 0, 506 ("%s: mp_ncpus is zero, but mp_maxid is not", __func__)); 507 else if (mp_ncpus == 1) 508 mp_maxid = 0; 509 else 510 KASSERT(mp_maxid >= mp_ncpus - 1, 511 ("%s: counters out of sync: max %d, count %d", __func__, 512 mp_maxid, mp_ncpus)); 513} 514 515int 516cpu_mp_probe(void) 517{ 518 519 /* 520 * Always record BSP in CPU map so that the mbuf init code works 521 * correctly. 522 */ 523 CPU_SETOF(0, &all_cpus); 524 if (mp_ncpus == 0) { 525 /* 526 * No CPUs were found, so this must be a UP system. Setup 527 * the variables to represent a system with a single CPU 528 * with an id of 0. 529 */ 530 mp_ncpus = 1; 531 return (0); 532 } 533 534 /* At least one CPU was found. */ 535 if (mp_ncpus == 1) { 536 /* 537 * One CPU was found, so this must be a UP system with 538 * an I/O APIC. 539 */ 540 mp_maxid = 0; 541 return (0); 542 } 543 544 /* At least two CPUs were found. */ 545 return (1); 546} 547 548/* 549 * Initialize the IPI handlers and start up the AP's. 550 */ 551void 552cpu_mp_start(void) 553{ 554 int i; 555 556 /* Initialize the logical ID to APIC ID table. */ 557 for (i = 0; i < MAXCPU; i++) { 558 cpu_apic_ids[i] = -1; 559 cpu_ipi_pending[i] = 0; 560 } 561 562 /* Install an inter-CPU IPI for TLB invalidation */ 563 setidt(IPI_INVLTLB, IDTVEC(invltlb), 564 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 565 setidt(IPI_INVLPG, IDTVEC(invlpg), 566 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 567 setidt(IPI_INVLRNG, IDTVEC(invlrng), 568 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 569 570 /* Install an inter-CPU IPI for cache invalidation. */ 571 setidt(IPI_INVLCACHE, IDTVEC(invlcache), 572 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 573 574 /* Install an inter-CPU IPI for lazy pmap release */ 575 setidt(IPI_LAZYPMAP, IDTVEC(lazypmap), 576 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 577 578 /* Install an inter-CPU IPI for all-CPU rendezvous */ 579 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous), 580 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 581 582 /* Install generic inter-CPU IPI handler */ 583 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler), 584 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 585 586 /* Install an inter-CPU IPI for CPU stop/restart */ 587 setidt(IPI_STOP, IDTVEC(cpustop), 588 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 589 590 591 /* Set boot_cpu_id if needed. */ 592 if (boot_cpu_id == -1) { 593 boot_cpu_id = PCPU_GET(apic_id); 594 cpu_info[boot_cpu_id].cpu_bsp = 1; 595 } else 596 KASSERT(boot_cpu_id == PCPU_GET(apic_id), 597 ("BSP's APIC ID doesn't match boot_cpu_id")); 598 599 /* Probe logical/physical core configuration. */ 600 topo_probe(); 601 602 assign_cpu_ids(); 603 604 /* Start each Application Processor */ 605 start_all_aps(); 606 607 set_interrupt_apic_ids(); 608} 609 610 611/* 612 * Print various information about the SMP system hardware and setup. 613 */ 614void 615cpu_mp_announce(void) 616{ 617 const char *hyperthread; 618 int i; 619 620 printf("FreeBSD/SMP: %d package(s) x %d core(s)", 621 mp_ncpus / (cpu_cores * cpu_logical), cpu_cores); 622 if (hyperthreading_cpus > 1) 623 printf(" x %d HTT threads", cpu_logical); 624 else if (cpu_logical > 1) 625 printf(" x %d SMT threads", cpu_logical); 626 printf("\n"); 627 628 /* List active CPUs first. */ 629 printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id); 630 for (i = 1; i < mp_ncpus; i++) { 631 if (cpu_info[cpu_apic_ids[i]].cpu_hyperthread) 632 hyperthread = "/HT"; 633 else 634 hyperthread = ""; 635 printf(" cpu%d (AP%s): APIC ID: %2d\n", i, hyperthread, 636 cpu_apic_ids[i]); 637 } 638 639 /* List disabled CPUs last. */ 640 for (i = 0; i <= MAX_APIC_ID; i++) { 641 if (!cpu_info[i].cpu_present || !cpu_info[i].cpu_disabled) 642 continue; 643 if (cpu_info[i].cpu_hyperthread) 644 hyperthread = "/HT"; 645 else 646 hyperthread = ""; 647 printf(" cpu (AP%s): APIC ID: %2d (disabled)\n", hyperthread, 648 i); 649 } 650} 651 652/* 653 * AP CPU's call this to initialize themselves. 654 */ 655void 656init_secondary(void) 657{ 658 struct pcpu *pc; 659 vm_offset_t addr; 660 int gsel_tss; 661 int x, myid; 662 u_int cpuid, cr0; 663 664 /* bootAP is set in start_ap() to our ID. */ 665 myid = bootAP; 666 667 /* Get per-cpu data */ 668 pc = &__pcpu[myid]; 669 670 /* prime data page for it to use */ 671 pcpu_init(pc, myid, sizeof(struct pcpu)); 672 dpcpu_init(dpcpu, myid); 673 pc->pc_apic_id = cpu_apic_ids[myid]; 674 pc->pc_prvspace = pc; 675 pc->pc_curthread = 0; 676 677 gdt_segs[GPRIV_SEL].ssd_base = (int) pc; 678 gdt_segs[GPROC0_SEL].ssd_base = (int) &pc->pc_common_tss; 679 680 for (x = 0; x < NGDT; x++) { 681 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd); 682 } 683 684 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 685 r_gdt.rd_base = (int) &gdt[myid * NGDT]; 686 lgdt(&r_gdt); /* does magic intra-segment return */ 687 688 lidt(&r_idt); 689 690 lldt(_default_ldt); 691 PCPU_SET(currentldt, _default_ldt); 692 693 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 694 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS; 695 PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */ 696 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL)); 697 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16); 698 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd); 699 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt)); 700 ltr(gsel_tss); 701 702 PCPU_SET(fsgs_gdt, &gdt[myid * NGDT + GUFS_SEL].sd); 703 704 /* 705 * Set to a known state: 706 * Set by mpboot.s: CR0_PG, CR0_PE 707 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM 708 */ 709 cr0 = rcr0(); 710 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM); 711 load_cr0(cr0); 712 CHECK_WRITE(0x38, 5); 713 714 /* Disable local APIC just to be sure. */ 715 lapic_disable(); 716 717 /* signal our startup to the BSP. */ 718 mp_naps++; 719 CHECK_WRITE(0x39, 6); 720 721 /* Spin until the BSP releases the AP's. */ 722 while (!aps_ready) 723 ia32_pause(); 724 725 /* BSP may have changed PTD while we were waiting */ 726 invltlb(); 727 for (addr = 0; addr < NKPT * NBPDR - 1; addr += PAGE_SIZE) 728 invlpg(addr); 729 730#if defined(I586_CPU) && !defined(NO_F00F_HACK) 731 lidt(&r_idt); 732#endif 733 734 /* Initialize the PAT MSR if present. */ 735 pmap_init_pat(); 736 737 /* set up CPU registers and state */ 738 cpu_setregs(); 739 740 /* set up FPU state on the AP */ 741 npxinit(); 742 743 /* set up SSE registers */ 744 enable_sse(); 745 746#ifdef PAE 747 /* Enable the PTE no-execute bit. */ 748 if ((amd_feature & AMDID_NX) != 0) { 749 uint64_t msr; 750 751 msr = rdmsr(MSR_EFER) | EFER_NXE; 752 wrmsr(MSR_EFER, msr); 753 } 754#endif 755 756 /* A quick check from sanity claus */ 757 cpuid = PCPU_GET(cpuid); 758 if (PCPU_GET(apic_id) != lapic_id()) { 759 printf("SMP: cpuid = %d\n", cpuid); 760 printf("SMP: actual apic_id = %d\n", lapic_id()); 761 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id)); 762 panic("cpuid mismatch! boom!!"); 763 } 764 765 /* Initialize curthread. */ 766 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread")); 767 PCPU_SET(curthread, PCPU_GET(idlethread)); 768 769 mca_init(); 770 771 mtx_lock_spin(&ap_boot_mtx); 772 773 /* Init local apic for irq's */ 774 lapic_setup(1); 775 776 /* Set memory range attributes for this CPU to match the BSP */ 777 mem_range_AP_init(); 778 779 smp_cpus++; 780 781 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", cpuid); 782 printf("SMP: AP CPU #%d Launched!\n", cpuid); 783 784 /* Determine if we are a logical CPU. */ 785 /* XXX Calculation depends on cpu_logical being a power of 2, e.g. 2 */ 786 if (cpu_logical > 1 && PCPU_GET(apic_id) % cpu_logical != 0) 787 CPU_SET(cpuid, &logical_cpus_mask); 788 789 if (bootverbose) 790 lapic_dump("AP"); 791 792 if (smp_cpus == mp_ncpus) { 793 /* enable IPI's, tlb shootdown, freezes etc */ 794 atomic_store_rel_int(&smp_started, 1); 795 smp_active = 1; /* historic */ 796 } 797 798 mtx_unlock_spin(&ap_boot_mtx); 799 800 /* Wait until all the AP's are up. */ 801 while (smp_started == 0) 802 ia32_pause(); 803 804 /* Start per-CPU event timers. */ 805 cpu_initclocks_ap(); 806 807 /* Enter the scheduler. */ 808 sched_throw(NULL); 809 810 panic("scheduler returned us to %s", __func__); 811 /* NOTREACHED */ 812} 813 814/******************************************************************* 815 * local functions and data 816 */ 817 818/* 819 * We tell the I/O APIC code about all the CPUs we want to receive 820 * interrupts. If we don't want certain CPUs to receive IRQs we 821 * can simply not tell the I/O APIC code about them in this function. 822 * We also do not tell it about the BSP since it tells itself about 823 * the BSP internally to work with UP kernels and on UP machines. 824 */ 825static void 826set_interrupt_apic_ids(void) 827{ 828 u_int i, apic_id; 829 830 for (i = 0; i < MAXCPU; i++) { 831 apic_id = cpu_apic_ids[i]; 832 if (apic_id == -1) 833 continue; 834 if (cpu_info[apic_id].cpu_bsp) 835 continue; 836 if (cpu_info[apic_id].cpu_disabled) 837 continue; 838 839 /* Don't let hyperthreads service interrupts. */ 840 if (hyperthreading_cpus > 1 && 841 apic_id % hyperthreading_cpus != 0) 842 continue; 843 844 intr_add_cpu(i); 845 } 846} 847 848/* 849 * Assign logical CPU IDs to local APICs. 850 */ 851static void 852assign_cpu_ids(void) 853{ 854 u_int i; 855 856 TUNABLE_INT_FETCH("machdep.hyperthreading_allowed", 857 &hyperthreading_allowed); 858 859 /* Check for explicitly disabled CPUs. */ 860 for (i = 0; i <= MAX_APIC_ID; i++) { 861 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp) 862 continue; 863 864 if (hyperthreading_cpus > 1 && i % hyperthreading_cpus != 0) { 865 cpu_info[i].cpu_hyperthread = 1; 866 867 /* 868 * Don't use HT CPU if it has been disabled by a 869 * tunable. 870 */ 871 if (hyperthreading_allowed == 0) { 872 cpu_info[i].cpu_disabled = 1; 873 continue; 874 } 875 } 876 877 /* Don't use this CPU if it has been disabled by a tunable. */ 878 if (resource_disabled("lapic", i)) { 879 cpu_info[i].cpu_disabled = 1; 880 continue; 881 } 882 } 883 884 if (hyperthreading_allowed == 0 && hyperthreading_cpus > 1) { 885 hyperthreading_cpus = 0; 886 cpu_logical = 1; 887 } 888 889 /* 890 * Assign CPU IDs to local APIC IDs and disable any CPUs 891 * beyond MAXCPU. CPU 0 is always assigned to the BSP. 892 * 893 * To minimize confusion for userland, we attempt to number 894 * CPUs such that all threads and cores in a package are 895 * grouped together. For now we assume that the BSP is always 896 * the first thread in a package and just start adding APs 897 * starting with the BSP's APIC ID. 898 */ 899 mp_ncpus = 1; 900 cpu_apic_ids[0] = boot_cpu_id; 901 apic_cpuids[boot_cpu_id] = 0; 902 for (i = boot_cpu_id + 1; i != boot_cpu_id; 903 i == MAX_APIC_ID ? i = 0 : i++) { 904 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp || 905 cpu_info[i].cpu_disabled) 906 continue; 907 908 if (mp_ncpus < MAXCPU) { 909 cpu_apic_ids[mp_ncpus] = i; 910 apic_cpuids[i] = mp_ncpus; 911 mp_ncpus++; 912 } else 913 cpu_info[i].cpu_disabled = 1; 914 } 915 KASSERT(mp_maxid >= mp_ncpus - 1, 916 ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid, 917 mp_ncpus)); 918} 919 920/* 921 * start each AP in our list 922 */ 923/* Lowest 1MB is already mapped: don't touch*/ 924#define TMPMAP_START 1 925static int 926start_all_aps(void) 927{ 928#ifndef PC98 929 u_char mpbiosreason; 930#endif 931 u_int32_t mpbioswarmvec; 932 int apic_id, cpu, i; 933 934 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); 935 936 /* install the AP 1st level boot code */ 937 install_ap_tramp(); 938 939 /* save the current value of the warm-start vector */ 940 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF); 941#ifndef PC98 942 outb(CMOS_REG, BIOS_RESET); 943 mpbiosreason = inb(CMOS_DATA); 944#endif 945 946 /* set up temporary P==V mapping for AP boot */ 947 /* XXX this is a hack, we should boot the AP on its own stack/PTD */ 948 for (i = TMPMAP_START; i < NKPT; i++) 949 PTD[i] = PTD[KPTDI + i]; 950 invltlb(); 951 952 /* start each AP */ 953 for (cpu = 1; cpu < mp_ncpus; cpu++) { 954 apic_id = cpu_apic_ids[cpu]; 955 956 /* allocate and set up a boot stack data page */ 957 bootstacks[cpu] = 958 (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE); 959 dpcpu = (void *)kmem_alloc(kernel_map, DPCPU_SIZE); 960 /* setup a vector to our boot code */ 961 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 962 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4); 963#ifndef PC98 964 outb(CMOS_REG, BIOS_RESET); 965 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 966#endif 967 968 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 4; 969 bootAP = cpu; 970 971 /* attempt to start the Application Processor */ 972 CHECK_INIT(99); /* setup checkpoints */ 973 if (!start_ap(apic_id)) { 974 printf("AP #%d (PHY# %d) failed!\n", cpu, apic_id); 975 CHECK_PRINT("trace"); /* show checkpoints */ 976 /* better panic as the AP may be running loose */ 977 printf("panic y/n? [y] "); 978 if (cngetc() != 'n') 979 panic("bye-bye"); 980 } 981 CHECK_PRINT("trace"); /* show checkpoints */ 982 983 CPU_SET(cpu, &all_cpus); /* record AP in CPU map */ 984 } 985 986 /* restore the warmstart vector */ 987 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec; 988 989#ifndef PC98 990 outb(CMOS_REG, BIOS_RESET); 991 outb(CMOS_DATA, mpbiosreason); 992#endif 993 994 /* Undo V==P hack from above */ 995 for (i = TMPMAP_START; i < NKPT; i++) 996 PTD[i] = 0; 997 pmap_invalidate_range(kernel_pmap, 0, NKPT * NBPDR - 1); 998 999 /* number of APs actually started */ 1000 return mp_naps; 1001} 1002 1003/* 1004 * load the 1st level AP boot code into base memory. 1005 */ 1006 1007/* targets for relocation */ 1008extern void bigJump(void); 1009extern void bootCodeSeg(void); 1010extern void bootDataSeg(void); 1011extern void MPentry(void); 1012extern u_int MP_GDT; 1013extern u_int mp_gdtbase; 1014 1015static void 1016install_ap_tramp(void) 1017{ 1018 int x; 1019 int size = *(int *) ((u_long) & bootMP_size); 1020 vm_offset_t va = boot_address + KERNBASE; 1021 u_char *src = (u_char *) ((u_long) bootMP); 1022 u_char *dst = (u_char *) va; 1023 u_int boot_base = (u_int) bootMP; 1024 u_int8_t *dst8; 1025 u_int16_t *dst16; 1026 u_int32_t *dst32; 1027 1028 KASSERT (size <= PAGE_SIZE, 1029 ("'size' do not fit into PAGE_SIZE, as expected.")); 1030 pmap_kenter(va, boot_address); 1031 pmap_invalidate_page (kernel_pmap, va); 1032 for (x = 0; x < size; ++x) 1033 *dst++ = *src++; 1034 1035 /* 1036 * modify addresses in code we just moved to basemem. unfortunately we 1037 * need fairly detailed info about mpboot.s for this to work. changes 1038 * to mpboot.s might require changes here. 1039 */ 1040 1041 /* boot code is located in KERNEL space */ 1042 dst = (u_char *) va; 1043 1044 /* modify the lgdt arg */ 1045 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 1046 *dst32 = boot_address + ((u_int) & MP_GDT - boot_base); 1047 1048 /* modify the ljmp target for MPentry() */ 1049 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 1050 *dst32 = ((u_int) MPentry - KERNBASE); 1051 1052 /* modify the target for boot code segment */ 1053 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 1054 dst8 = (u_int8_t *) (dst16 + 1); 1055 *dst16 = (u_int) boot_address & 0xffff; 1056 *dst8 = ((u_int) boot_address >> 16) & 0xff; 1057 1058 /* modify the target for boot data segment */ 1059 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 1060 dst8 = (u_int8_t *) (dst16 + 1); 1061 *dst16 = (u_int) boot_address & 0xffff; 1062 *dst8 = ((u_int) boot_address >> 16) & 0xff; 1063} 1064 1065/* 1066 * This function starts the AP (application processor) identified 1067 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 1068 * to accomplish this. This is necessary because of the nuances 1069 * of the different hardware we might encounter. It isn't pretty, 1070 * but it seems to work. 1071 */ 1072static int 1073start_ap(int apic_id) 1074{ 1075 int vector, ms; 1076 int cpus; 1077 1078 /* calculate the vector */ 1079 vector = (boot_address >> 12) & 0xff; 1080 1081 /* used as a watchpoint to signal AP startup */ 1082 cpus = mp_naps; 1083 1084 /* 1085 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 1086 * and running the target CPU. OR this INIT IPI might be latched (P5 1087 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 1088 * ignored. 1089 */ 1090 1091 /* do an INIT IPI: assert RESET */ 1092 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 1093 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id); 1094 1095 /* wait for pending status end */ 1096 lapic_ipi_wait(-1); 1097 1098 /* do an INIT IPI: deassert RESET */ 1099 lapic_ipi_raw(APIC_DEST_ALLESELF | APIC_TRIGMOD_LEVEL | 1100 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, 0); 1101 1102 /* wait for pending status end */ 1103 DELAY(10000); /* wait ~10mS */ 1104 lapic_ipi_wait(-1); 1105 1106 /* 1107 * next we do a STARTUP IPI: the previous INIT IPI might still be 1108 * latched, (P5 bug) this 1st STARTUP would then terminate 1109 * immediately, and the previously started INIT IPI would continue. OR 1110 * the previous INIT IPI has already run. and this STARTUP IPI will 1111 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 1112 * will run. 1113 */ 1114 1115 /* do a STARTUP IPI */ 1116 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 1117 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 1118 vector, apic_id); 1119 lapic_ipi_wait(-1); 1120 DELAY(200); /* wait ~200uS */ 1121 1122 /* 1123 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 1124 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 1125 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 1126 * recognized after hardware RESET or INIT IPI. 1127 */ 1128 1129 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 1130 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 1131 vector, apic_id); 1132 lapic_ipi_wait(-1); 1133 DELAY(200); /* wait ~200uS */ 1134 1135 /* Wait up to 5 seconds for it to start. */ 1136 for (ms = 0; ms < 5000; ms++) { 1137 if (mp_naps > cpus) 1138 return 1; /* return SUCCESS */ 1139 DELAY(1000); 1140 } 1141 return 0; /* return FAILURE */ 1142} 1143 1144#ifdef COUNT_XINVLTLB_HITS 1145u_int xhits_gbl[MAXCPU]; 1146u_int xhits_pg[MAXCPU]; 1147u_int xhits_rng[MAXCPU]; 1148static SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, ""); 1149SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl, 1150 sizeof(xhits_gbl), "IU", ""); 1151SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg, 1152 sizeof(xhits_pg), "IU", ""); 1153SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng, 1154 sizeof(xhits_rng), "IU", ""); 1155 1156u_int ipi_global; 1157u_int ipi_page; 1158u_int ipi_range; 1159u_int ipi_range_size; 1160SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, ""); 1161SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, ""); 1162SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, ""); 1163SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size, 1164 0, ""); 1165 1166u_int ipi_masked_global; 1167u_int ipi_masked_page; 1168u_int ipi_masked_range; 1169u_int ipi_masked_range_size; 1170SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW, 1171 &ipi_masked_global, 0, ""); 1172SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW, 1173 &ipi_masked_page, 0, ""); 1174SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW, 1175 &ipi_masked_range, 0, ""); 1176SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW, 1177 &ipi_masked_range_size, 0, ""); 1178#endif /* COUNT_XINVLTLB_HITS */ 1179 1180/* 1181 * Send an IPI to specified CPU handling the bitmap logic. 1182 */ 1183static void 1184ipi_send_cpu(int cpu, u_int ipi) 1185{ 1186 u_int bitmap, old_pending, new_pending; 1187 1188 KASSERT(cpu_apic_ids[cpu] != -1, ("IPI to non-existent CPU %d", cpu)); 1189 1190 if (IPI_IS_BITMAPED(ipi)) { 1191 bitmap = 1 << ipi; 1192 ipi = IPI_BITMAP_VECTOR; 1193 do { 1194 old_pending = cpu_ipi_pending[cpu]; 1195 new_pending = old_pending | bitmap; 1196 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu], 1197 old_pending, new_pending)); 1198 if (old_pending) 1199 return; 1200 } 1201 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]); 1202} 1203 1204/* 1205 * Flush the TLB on all other CPU's 1206 */ 1207static void 1208smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2) 1209{ 1210 u_int ncpu; 1211 1212 ncpu = mp_ncpus - 1; /* does not shootdown self */ 1213 if (ncpu < 1) 1214 return; /* no other cpus */ 1215 if (!(read_eflags() & PSL_I)) 1216 panic("%s: interrupts disabled", __func__); 1217 mtx_lock_spin(&smp_ipi_mtx); 1218 smp_tlb_addr1 = addr1; 1219 smp_tlb_addr2 = addr2; 1220 atomic_store_rel_int(&smp_tlb_wait, 0); 1221 ipi_all_but_self(vector); 1222 while (smp_tlb_wait < ncpu) 1223 ia32_pause(); 1224 mtx_unlock_spin(&smp_ipi_mtx); 1225} 1226 1227static void 1228smp_targeted_tlb_shootdown(cpuset_t mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2) 1229{ 1230 int cpu, ncpu, othercpus; 1231 1232 othercpus = mp_ncpus - 1; 1233 if (CPU_ISFULLSET(&mask)) { 1234 if (othercpus < 1) 1235 return; 1236 } else { 1237 CPU_CLR(PCPU_GET(cpuid), &mask); 1238 if (CPU_EMPTY(&mask)) 1239 return; 1240 } 1241 if (!(read_eflags() & PSL_I)) 1242 panic("%s: interrupts disabled", __func__); 1243 mtx_lock_spin(&smp_ipi_mtx); 1244 smp_tlb_addr1 = addr1; 1245 smp_tlb_addr2 = addr2; 1246 atomic_store_rel_int(&smp_tlb_wait, 0); 1247 if (CPU_ISFULLSET(&mask)) { 1248 ncpu = othercpus; 1249 ipi_all_but_self(vector); 1250 } else { 1251 ncpu = 0; 1252 while ((cpu = cpusetobj_ffs(&mask)) != 0) { 1253 cpu--; 1254 CPU_CLR(cpu, &mask); 1255 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, 1256 vector); 1257 ipi_send_cpu(cpu, vector); 1258 ncpu++; 1259 } 1260 } 1261 while (smp_tlb_wait < ncpu) 1262 ia32_pause(); 1263 mtx_unlock_spin(&smp_ipi_mtx); 1264} 1265 1266void 1267smp_cache_flush(void) 1268{ 1269 1270 if (smp_started) 1271 smp_tlb_shootdown(IPI_INVLCACHE, 0, 0); 1272} 1273 1274void 1275smp_invltlb(void) 1276{ 1277 1278 if (smp_started) { 1279 smp_tlb_shootdown(IPI_INVLTLB, 0, 0); 1280#ifdef COUNT_XINVLTLB_HITS 1281 ipi_global++; 1282#endif 1283 } 1284} 1285 1286void 1287smp_invlpg(vm_offset_t addr) 1288{ 1289 1290 if (smp_started) { 1291 smp_tlb_shootdown(IPI_INVLPG, addr, 0); 1292#ifdef COUNT_XINVLTLB_HITS 1293 ipi_page++; 1294#endif 1295 } 1296} 1297 1298void 1299smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2) 1300{ 1301 1302 if (smp_started) { 1303 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2); 1304#ifdef COUNT_XINVLTLB_HITS 1305 ipi_range++; 1306 ipi_range_size += (addr2 - addr1) / PAGE_SIZE; 1307#endif 1308 } 1309} 1310 1311void 1312smp_masked_invltlb(cpuset_t mask) 1313{ 1314 1315 if (smp_started) { 1316 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0); 1317#ifdef COUNT_XINVLTLB_HITS 1318 ipi_masked_global++; 1319#endif 1320 } 1321} 1322 1323void 1324smp_masked_invlpg(cpuset_t mask, vm_offset_t addr) 1325{ 1326 1327 if (smp_started) { 1328 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0); 1329#ifdef COUNT_XINVLTLB_HITS 1330 ipi_masked_page++; 1331#endif 1332 } 1333} 1334 1335void 1336smp_masked_invlpg_range(cpuset_t mask, vm_offset_t addr1, vm_offset_t addr2) 1337{ 1338 1339 if (smp_started) { 1340 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2); 1341#ifdef COUNT_XINVLTLB_HITS 1342 ipi_masked_range++; 1343 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE; 1344#endif 1345 } 1346} 1347 1348void 1349ipi_bitmap_handler(struct trapframe frame) 1350{ 1351 struct trapframe *oldframe; 1352 struct thread *td; 1353 int cpu = PCPU_GET(cpuid); 1354 u_int ipi_bitmap; 1355 1356 critical_enter(); 1357 td = curthread; 1358 td->td_intr_nesting_level++; 1359 oldframe = td->td_intr_frame; 1360 td->td_intr_frame = &frame; 1361 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]); 1362 if (ipi_bitmap & (1 << IPI_PREEMPT)) { 1363#ifdef COUNT_IPIS 1364 (*ipi_preempt_counts[cpu])++; 1365#endif 1366 sched_preempt(td); 1367 } 1368 if (ipi_bitmap & (1 << IPI_AST)) { 1369#ifdef COUNT_IPIS 1370 (*ipi_ast_counts[cpu])++; 1371#endif 1372 /* Nothing to do for AST */ 1373 } 1374 if (ipi_bitmap & (1 << IPI_HARDCLOCK)) { 1375#ifdef COUNT_IPIS 1376 (*ipi_hardclock_counts[cpu])++; 1377#endif 1378 hardclockintr(); 1379 } 1380 td->td_intr_frame = oldframe; 1381 td->td_intr_nesting_level--; 1382 critical_exit(); 1383} 1384 1385/* 1386 * send an IPI to a set of cpus. 1387 */ 1388void 1389ipi_selected(cpuset_t cpus, u_int ipi) 1390{ 1391 int cpu; 1392 1393 /* 1394 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit 1395 * of help in order to understand what is the source. 1396 * Set the mask of receiving CPUs for this purpose. 1397 */ 1398 if (ipi == IPI_STOP_HARD) 1399 CPU_OR_ATOMIC(&ipi_nmi_pending, &cpus); 1400 1401 while ((cpu = cpusetobj_ffs(&cpus)) != 0) { 1402 cpu--; 1403 CPU_CLR(cpu, &cpus); 1404 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi); 1405 ipi_send_cpu(cpu, ipi); 1406 } 1407} 1408 1409/* 1410 * send an IPI to a specific CPU. 1411 */ 1412void 1413ipi_cpu(int cpu, u_int ipi) 1414{ 1415 1416 /* 1417 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit 1418 * of help in order to understand what is the source. 1419 * Set the mask of receiving CPUs for this purpose. 1420 */ 1421 if (ipi == IPI_STOP_HARD) 1422 CPU_SET_ATOMIC(cpu, &ipi_nmi_pending); 1423 1424 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi); 1425 ipi_send_cpu(cpu, ipi); 1426} 1427 1428/* 1429 * send an IPI to all CPUs EXCEPT myself 1430 */ 1431void 1432ipi_all_but_self(u_int ipi) 1433{ 1434 cpuset_t other_cpus; 1435 1436 other_cpus = all_cpus; 1437 CPU_CLR(PCPU_GET(cpuid), &other_cpus); 1438 if (IPI_IS_BITMAPED(ipi)) { 1439 ipi_selected(other_cpus, ipi); 1440 return; 1441 } 1442 1443 /* 1444 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit 1445 * of help in order to understand what is the source. 1446 * Set the mask of receiving CPUs for this purpose. 1447 */ 1448 if (ipi == IPI_STOP_HARD) 1449 CPU_OR_ATOMIC(&ipi_nmi_pending, &other_cpus); 1450 1451 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1452 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS); 1453} 1454 1455int 1456ipi_nmi_handler() 1457{ 1458 u_int cpuid; 1459 1460 /* 1461 * As long as there is not a simple way to know about a NMI's 1462 * source, if the bitmask for the current CPU is present in 1463 * the global pending bitword an IPI_STOP_HARD has been issued 1464 * and should be handled. 1465 */ 1466 cpuid = PCPU_GET(cpuid); 1467 if (!CPU_ISSET(cpuid, &ipi_nmi_pending)) 1468 return (1); 1469 1470 CPU_CLR_ATOMIC(cpuid, &ipi_nmi_pending); 1471 cpustop_handler(); 1472 return (0); 1473} 1474 1475/* 1476 * Handle an IPI_STOP by saving our current context and spinning until we 1477 * are resumed. 1478 */ 1479void 1480cpustop_handler(void) 1481{ 1482 u_int cpu; 1483 1484 cpu = PCPU_GET(cpuid); 1485 1486 savectx(&stoppcbs[cpu]); 1487 1488 /* Indicate that we are stopped */ 1489 CPU_SET_ATOMIC(cpu, &stopped_cpus); 1490 1491 /* Wait for restart */ 1492 while (!CPU_ISSET(cpu, &started_cpus)) 1493 ia32_pause(); 1494 1495 CPU_CLR_ATOMIC(cpu, &started_cpus); 1496 CPU_CLR_ATOMIC(cpu, &stopped_cpus); 1497 1498 if (cpu == 0 && cpustop_restartfunc != NULL) { 1499 cpustop_restartfunc(); 1500 cpustop_restartfunc = NULL; 1501 } 1502} 1503 1504/* 1505 * This is called once the rest of the system is up and running and we're 1506 * ready to let the AP's out of the pen. 1507 */ 1508static void 1509release_aps(void *dummy __unused) 1510{ 1511 1512 if (mp_ncpus == 1) 1513 return; 1514 atomic_store_rel_int(&aps_ready, 1); 1515 while (smp_started == 0) 1516 ia32_pause(); 1517} 1518SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL); 1519 1520#ifdef COUNT_IPIS 1521/* 1522 * Setup interrupt counters for IPI handlers. 1523 */ 1524static void 1525mp_ipi_intrcnt(void *dummy) 1526{ 1527 char buf[64]; 1528 int i; 1529 1530 CPU_FOREACH(i) { 1531 snprintf(buf, sizeof(buf), "cpu%d:invltlb", i); 1532 intrcnt_add(buf, &ipi_invltlb_counts[i]); 1533 snprintf(buf, sizeof(buf), "cpu%d:invlrng", i); 1534 intrcnt_add(buf, &ipi_invlrng_counts[i]); 1535 snprintf(buf, sizeof(buf), "cpu%d:invlpg", i); 1536 intrcnt_add(buf, &ipi_invlpg_counts[i]); 1537 snprintf(buf, sizeof(buf), "cpu%d:preempt", i); 1538 intrcnt_add(buf, &ipi_preempt_counts[i]); 1539 snprintf(buf, sizeof(buf), "cpu%d:ast", i); 1540 intrcnt_add(buf, &ipi_ast_counts[i]); 1541 snprintf(buf, sizeof(buf), "cpu%d:rendezvous", i); 1542 intrcnt_add(buf, &ipi_rendezvous_counts[i]); 1543 snprintf(buf, sizeof(buf), "cpu%d:lazypmap", i); 1544 intrcnt_add(buf, &ipi_lazypmap_counts[i]); 1545 snprintf(buf, sizeof(buf), "cpu%d:hardclock", i); 1546 intrcnt_add(buf, &ipi_hardclock_counts[i]); 1547 } 1548} 1549SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL); 1550#endif 1551