mp_x86.c revision 176734
1/*- 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26#include <sys/cdefs.h> 27__FBSDID("$FreeBSD: head/sys/i386/i386/mp_machdep.c 176734 2008-03-02 07:58:42Z jeff $"); 28 29#include "opt_apic.h" 30#include "opt_cpu.h" 31#include "opt_kstack_pages.h" 32#include "opt_mp_watchdog.h" 33#include "opt_sched.h" 34#include "opt_smp.h" 35 36#if !defined(lint) 37#if !defined(SMP) 38#error How did you get here? 39#endif 40 41#ifndef DEV_APIC 42#error The apic device is required for SMP, add "device apic" to your config file. 43#endif 44#if defined(CPU_DISABLE_CMPXCHG) && !defined(COMPILING_LINT) 45#error SMP not supported with CPU_DISABLE_CMPXCHG 46#endif 47#endif /* not lint */ 48 49#include <sys/param.h> 50#include <sys/systm.h> 51#include <sys/bus.h> 52#include <sys/cons.h> /* cngetc() */ 53#ifdef GPROF 54#include <sys/gmon.h> 55#endif 56#include <sys/kernel.h> 57#include <sys/ktr.h> 58#include <sys/lock.h> 59#include <sys/malloc.h> 60#include <sys/memrange.h> 61#include <sys/mutex.h> 62#include <sys/pcpu.h> 63#include <sys/proc.h> 64#include <sys/sched.h> 65#include <sys/smp.h> 66#include <sys/sysctl.h> 67 68#include <vm/vm.h> 69#include <vm/vm_param.h> 70#include <vm/pmap.h> 71#include <vm/vm_kern.h> 72#include <vm/vm_extern.h> 73 74#include <machine/apicreg.h> 75#include <machine/md_var.h> 76#include <machine/mp_watchdog.h> 77#include <machine/pcb.h> 78#include <machine/psl.h> 79#include <machine/smp.h> 80#include <machine/specialreg.h> 81 82#define WARMBOOT_TARGET 0 83#define WARMBOOT_OFF (KERNBASE + 0x0467) 84#define WARMBOOT_SEG (KERNBASE + 0x0469) 85 86#define CMOS_REG (0x70) 87#define CMOS_DATA (0x71) 88#define BIOS_RESET (0x0f) 89#define BIOS_WARM (0x0a) 90 91/* 92 * this code MUST be enabled here and in mpboot.s. 93 * it follows the very early stages of AP boot by placing values in CMOS ram. 94 * it NORMALLY will never be needed and thus the primitive method for enabling. 95 * 96#define CHECK_POINTS 97 */ 98 99#if defined(CHECK_POINTS) && !defined(PC98) 100#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 101#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 102 103#define CHECK_INIT(D); \ 104 CHECK_WRITE(0x34, (D)); \ 105 CHECK_WRITE(0x35, (D)); \ 106 CHECK_WRITE(0x36, (D)); \ 107 CHECK_WRITE(0x37, (D)); \ 108 CHECK_WRITE(0x38, (D)); \ 109 CHECK_WRITE(0x39, (D)); 110 111#define CHECK_PRINT(S); \ 112 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 113 (S), \ 114 CHECK_READ(0x34), \ 115 CHECK_READ(0x35), \ 116 CHECK_READ(0x36), \ 117 CHECK_READ(0x37), \ 118 CHECK_READ(0x38), \ 119 CHECK_READ(0x39)); 120 121#else /* CHECK_POINTS */ 122 123#define CHECK_INIT(D) 124#define CHECK_PRINT(S) 125#define CHECK_WRITE(A, D) 126 127#endif /* CHECK_POINTS */ 128 129/* lock region used by kernel profiling */ 130int mcount_lock; 131 132int mp_naps; /* # of Applications processors */ 133int boot_cpu_id = -1; /* designated BSP */ 134extern int nkpt; 135 136extern struct pcpu __pcpu[]; 137 138/* AP uses this during bootstrap. Do not staticize. */ 139char *bootSTK; 140static int bootAP; 141 142/* Free these after use */ 143void *bootstacks[MAXCPU]; 144 145/* Hotwire a 0->4MB V==P mapping */ 146extern pt_entry_t *KPTphys; 147 148struct pcb stoppcbs[MAXCPU]; 149 150/* Variables needed for SMP tlb shootdown. */ 151vm_offset_t smp_tlb_addr1; 152vm_offset_t smp_tlb_addr2; 153volatile int smp_tlb_wait; 154 155#ifdef STOP_NMI 156volatile cpumask_t ipi_nmi_pending; 157 158static void ipi_nmi_selected(u_int32_t cpus); 159#endif 160 161#ifdef COUNT_IPIS 162/* Interrupt counts. */ 163static u_long *ipi_preempt_counts[MAXCPU]; 164static u_long *ipi_ast_counts[MAXCPU]; 165u_long *ipi_invltlb_counts[MAXCPU]; 166u_long *ipi_invlrng_counts[MAXCPU]; 167u_long *ipi_invlpg_counts[MAXCPU]; 168u_long *ipi_invlcache_counts[MAXCPU]; 169u_long *ipi_rendezvous_counts[MAXCPU]; 170u_long *ipi_lazypmap_counts[MAXCPU]; 171#endif 172 173/* 174 * Local data and functions. 175 */ 176 177#ifdef STOP_NMI 178/* 179 * Provide an alternate method of stopping other CPUs. If another CPU has 180 * disabled interrupts the conventional STOP IPI will be blocked. This 181 * NMI-based stop should get through in that case. 182 */ 183static int stop_cpus_with_nmi = 1; 184SYSCTL_INT(_debug, OID_AUTO, stop_cpus_with_nmi, CTLTYPE_INT | CTLFLAG_RW, 185 &stop_cpus_with_nmi, 0, ""); 186TUNABLE_INT("debug.stop_cpus_with_nmi", &stop_cpus_with_nmi); 187#else 188#define stop_cpus_with_nmi 0 189#endif 190 191static u_int logical_cpus; 192 193/* used to hold the AP's until we are ready to release them */ 194static struct mtx ap_boot_mtx; 195 196/* Set to 1 once we're ready to let the APs out of the pen. */ 197static volatile int aps_ready = 0; 198 199/* 200 * Store data from cpu_add() until later in the boot when we actually setup 201 * the APs. 202 */ 203struct cpu_info { 204 int cpu_present:1; 205 int cpu_bsp:1; 206 int cpu_disabled:1; 207} static cpu_info[MAX_APIC_ID + 1]; 208int cpu_apic_ids[MAXCPU]; 209 210/* Holds pending bitmap based IPIs per CPU */ 211static volatile u_int cpu_ipi_pending[MAXCPU]; 212 213static u_int boot_address; 214 215static void assign_cpu_ids(void); 216static void install_ap_tramp(void); 217static void set_interrupt_apic_ids(void); 218static int start_all_aps(void); 219static int start_ap(int apic_id); 220static void release_aps(void *dummy); 221 222static int hlt_logical_cpus; 223static u_int hyperthreading_cpus; 224static cpumask_t hyperthreading_cpus_mask; 225static int hyperthreading_allowed = 1; 226static struct sysctl_ctx_list logical_cpu_clist; 227 228static void 229mem_range_AP_init(void) 230{ 231 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP) 232 mem_range_softc.mr_op->initAP(&mem_range_softc); 233} 234 235struct cpu_group * 236cpu_topo(void) 237{ 238 if (cpu_cores == 0) 239 cpu_cores = 1; 240 if (cpu_logical == 0) 241 cpu_logical = 1; 242 if (mp_ncpus % (cpu_cores * cpu_logical) != 0) { 243 printf("WARNING: Non-uniform processors.\n"); 244 printf("WARNING: Using suboptimal topology.\n"); 245 return (smp_topo_none()); 246 } 247 /* 248 * No multi-core or hyper-threaded. 249 */ 250 if (cpu_logical * cpu_cores == 1) 251 return (smp_topo_none()); 252 /* 253 * Only HTT no multi-core. 254 */ 255 if (cpu_logical > 1 && cpu_cores == 1) 256 return (smp_topo_1level(CG_SHARE_L1, cpu_logical, CG_FLAG_HTT)); 257 /* 258 * Only multi-core no HTT. 259 */ 260 if (cpu_cores > 1 && cpu_logical == 1) 261 return (smp_topo_1level(CG_SHARE_NONE, cpu_cores, 0)); 262 /* 263 * Both HTT and multi-core. 264 */ 265 return (smp_topo_2level(CG_SHARE_NONE, cpu_cores, 266 CG_SHARE_L1, cpu_logical, CG_FLAG_HTT)); 267} 268 269 270/* 271 * Calculate usable address in base memory for AP trampoline code. 272 */ 273u_int 274mp_bootaddress(u_int basemem) 275{ 276 277 boot_address = trunc_page(basemem); /* round down to 4k boundary */ 278 if ((basemem - boot_address) < bootMP_size) 279 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */ 280 281 return boot_address; 282} 283 284void 285cpu_add(u_int apic_id, char boot_cpu) 286{ 287 288 if (apic_id > MAX_APIC_ID) { 289 panic("SMP: APIC ID %d too high", apic_id); 290 return; 291 } 292 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice", 293 apic_id)); 294 cpu_info[apic_id].cpu_present = 1; 295 if (boot_cpu) { 296 KASSERT(boot_cpu_id == -1, 297 ("CPU %d claims to be BSP, but CPU %d already is", apic_id, 298 boot_cpu_id)); 299 boot_cpu_id = apic_id; 300 cpu_info[apic_id].cpu_bsp = 1; 301 } 302 if (mp_ncpus < MAXCPU) 303 mp_ncpus++; 304 if (bootverbose) 305 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" : 306 "AP"); 307} 308 309void 310cpu_mp_setmaxid(void) 311{ 312 313 mp_maxid = MAXCPU - 1; 314} 315 316int 317cpu_mp_probe(void) 318{ 319 320 /* 321 * Always record BSP in CPU map so that the mbuf init code works 322 * correctly. 323 */ 324 all_cpus = 1; 325 if (mp_ncpus == 0) { 326 /* 327 * No CPUs were found, so this must be a UP system. Setup 328 * the variables to represent a system with a single CPU 329 * with an id of 0. 330 */ 331 mp_ncpus = 1; 332 return (0); 333 } 334 335 /* At least one CPU was found. */ 336 if (mp_ncpus == 1) { 337 /* 338 * One CPU was found, so this must be a UP system with 339 * an I/O APIC. 340 */ 341 return (0); 342 } 343 344 /* At least two CPUs were found. */ 345 return (1); 346} 347 348/* 349 * Initialize the IPI handlers and start up the AP's. 350 */ 351void 352cpu_mp_start(void) 353{ 354 int i; 355 u_int threads_per_cache, p[4]; 356 357 /* Initialize the logical ID to APIC ID table. */ 358 for (i = 0; i < MAXCPU; i++) { 359 cpu_apic_ids[i] = -1; 360 cpu_ipi_pending[i] = 0; 361 } 362 363 /* Install an inter-CPU IPI for TLB invalidation */ 364 setidt(IPI_INVLTLB, IDTVEC(invltlb), 365 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 366 setidt(IPI_INVLPG, IDTVEC(invlpg), 367 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 368 setidt(IPI_INVLRNG, IDTVEC(invlrng), 369 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 370 371 /* Install an inter-CPU IPI for cache invalidation. */ 372 setidt(IPI_INVLCACHE, IDTVEC(invlcache), 373 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 374 375 /* Install an inter-CPU IPI for lazy pmap release */ 376 setidt(IPI_LAZYPMAP, IDTVEC(lazypmap), 377 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 378 379 /* Install an inter-CPU IPI for all-CPU rendezvous */ 380 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous), 381 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 382 383 /* Install generic inter-CPU IPI handler */ 384 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler), 385 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 386 387 /* Install an inter-CPU IPI for CPU stop/restart */ 388 setidt(IPI_STOP, IDTVEC(cpustop), 389 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 390 391 392 /* Set boot_cpu_id if needed. */ 393 if (boot_cpu_id == -1) { 394 boot_cpu_id = PCPU_GET(apic_id); 395 cpu_info[boot_cpu_id].cpu_bsp = 1; 396 } else 397 KASSERT(boot_cpu_id == PCPU_GET(apic_id), 398 ("BSP's APIC ID doesn't match boot_cpu_id")); 399 cpu_apic_ids[0] = boot_cpu_id; 400 401 assign_cpu_ids(); 402 403 /* Start each Application Processor */ 404 start_all_aps(); 405 406 /* Setup the initial logical CPUs info. */ 407 logical_cpus = logical_cpus_mask = 0; 408 if (cpu_feature & CPUID_HTT) 409 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 410 411 /* 412 * Work out if hyperthreading is *really* enabled. This 413 * is made really ugly by the fact that processors lie: Dual 414 * core processors claim to be hyperthreaded even when they're 415 * not, presumably because they want to be treated the same 416 * way as HTT with respect to per-cpu software licensing. 417 * At the time of writing (May 12, 2005) the only hyperthreaded 418 * cpus are from Intel, and Intel's dual-core processors can be 419 * identified via the "deterministic cache parameters" cpuid 420 * calls. 421 */ 422 /* 423 * First determine if this is an Intel processor which claims 424 * to have hyperthreading support. 425 */ 426 if ((cpu_feature & CPUID_HTT) && 427 (strcmp(cpu_vendor, "GenuineIntel") == 0)) { 428 /* 429 * If the "deterministic cache parameters" cpuid calls 430 * are available, use them. 431 */ 432 if (cpu_high >= 4) { 433 /* Ask the processor about the L1 cache. */ 434 for (i = 0; i < 1; i++) { 435 cpuid_count(4, i, p); 436 threads_per_cache = ((p[0] & 0x3ffc000) >> 14) + 1; 437 if (hyperthreading_cpus < threads_per_cache) 438 hyperthreading_cpus = threads_per_cache; 439 if ((p[0] & 0x1f) == 0) 440 break; 441 } 442 } 443 444 /* 445 * If the deterministic cache parameters are not 446 * available, or if no caches were reported to exist, 447 * just accept what the HTT flag indicated. 448 */ 449 if (hyperthreading_cpus == 0) 450 hyperthreading_cpus = logical_cpus; 451 } 452 453 set_interrupt_apic_ids(); 454} 455 456 457/* 458 * Print various information about the SMP system hardware and setup. 459 */ 460void 461cpu_mp_announce(void) 462{ 463 int i, x; 464 465 /* List CPUs */ 466 printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id); 467 for (i = 1, x = 0; x <= MAX_APIC_ID; x++) { 468 if (!cpu_info[x].cpu_present || cpu_info[x].cpu_bsp) 469 continue; 470 if (cpu_info[x].cpu_disabled) 471 printf(" cpu (AP): APIC ID: %2d (disabled)\n", x); 472 else { 473 KASSERT(i < mp_ncpus, 474 ("mp_ncpus and actual cpus are out of whack")); 475 printf(" cpu%d (AP): APIC ID: %2d\n", i++, x); 476 } 477 } 478} 479 480/* 481 * AP CPU's call this to initialize themselves. 482 */ 483void 484init_secondary(void) 485{ 486 struct pcpu *pc; 487 vm_offset_t addr; 488 int gsel_tss; 489 int x, myid; 490 u_int cr0; 491 492 /* bootAP is set in start_ap() to our ID. */ 493 myid = bootAP; 494 495 /* Get per-cpu data */ 496 pc = &__pcpu[myid]; 497 498 /* prime data page for it to use */ 499 pcpu_init(pc, myid, sizeof(struct pcpu)); 500 pc->pc_apic_id = cpu_apic_ids[myid]; 501 pc->pc_prvspace = pc; 502 pc->pc_curthread = 0; 503 504 gdt_segs[GPRIV_SEL].ssd_base = (int) pc; 505 gdt_segs[GPROC0_SEL].ssd_base = (int) &pc->pc_common_tss; 506 507 for (x = 0; x < NGDT; x++) { 508 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd); 509 } 510 511 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 512 r_gdt.rd_base = (int) &gdt[myid * NGDT]; 513 lgdt(&r_gdt); /* does magic intra-segment return */ 514 515 lidt(&r_idt); 516 517 lldt(_default_ldt); 518 PCPU_SET(currentldt, _default_ldt); 519 520 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 521 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS; 522 PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */ 523 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL)); 524 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16); 525 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd); 526 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt)); 527 ltr(gsel_tss); 528 529 PCPU_SET(fsgs_gdt, &gdt[myid * NGDT + GUFS_SEL].sd); 530 531 /* 532 * Set to a known state: 533 * Set by mpboot.s: CR0_PG, CR0_PE 534 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM 535 */ 536 cr0 = rcr0(); 537 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM); 538 load_cr0(cr0); 539 CHECK_WRITE(0x38, 5); 540 541 /* Disable local APIC just to be sure. */ 542 lapic_disable(); 543 544 /* signal our startup to the BSP. */ 545 mp_naps++; 546 CHECK_WRITE(0x39, 6); 547 548 /* Spin until the BSP releases the AP's. */ 549 while (!aps_ready) 550 ia32_pause(); 551 552 /* BSP may have changed PTD while we were waiting */ 553 invltlb(); 554 for (addr = 0; addr < NKPT * NBPDR - 1; addr += PAGE_SIZE) 555 invlpg(addr); 556 557#if defined(I586_CPU) && !defined(NO_F00F_HACK) 558 lidt(&r_idt); 559#endif 560 561 /* Initialize the PAT MSR if present. */ 562 pmap_init_pat(); 563 564 /* set up CPU registers and state */ 565 cpu_setregs(); 566 567 /* set up FPU state on the AP */ 568 npxinit(__INITIAL_NPXCW__); 569 570 /* set up SSE registers */ 571 enable_sse(); 572 573#ifdef PAE 574 /* Enable the PTE no-execute bit. */ 575 if ((amd_feature & AMDID_NX) != 0) { 576 uint64_t msr; 577 578 msr = rdmsr(MSR_EFER) | EFER_NXE; 579 wrmsr(MSR_EFER, msr); 580 } 581#endif 582 583 /* A quick check from sanity claus */ 584 if (PCPU_GET(apic_id) != lapic_id()) { 585 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid)); 586 printf("SMP: actual apic_id = %d\n", lapic_id()); 587 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id)); 588 panic("cpuid mismatch! boom!!"); 589 } 590 591 /* Initialize curthread. */ 592 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread")); 593 PCPU_SET(curthread, PCPU_GET(idlethread)); 594 595 mtx_lock_spin(&ap_boot_mtx); 596 597 /* Init local apic for irq's */ 598 lapic_setup(1); 599 600 /* Set memory range attributes for this CPU to match the BSP */ 601 mem_range_AP_init(); 602 603 smp_cpus++; 604 605 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", PCPU_GET(cpuid)); 606 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid)); 607 608 /* Determine if we are a logical CPU. */ 609 if (logical_cpus > 1 && PCPU_GET(apic_id) % logical_cpus != 0) 610 logical_cpus_mask |= PCPU_GET(cpumask); 611 612 /* Determine if we are a hyperthread. */ 613 if (hyperthreading_cpus > 1 && 614 PCPU_GET(apic_id) % hyperthreading_cpus != 0) 615 hyperthreading_cpus_mask |= PCPU_GET(cpumask); 616 617 /* Build our map of 'other' CPUs. */ 618 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 619 620 if (bootverbose) 621 lapic_dump("AP"); 622 623 if (smp_cpus == mp_ncpus) { 624 /* enable IPI's, tlb shootdown, freezes etc */ 625 atomic_store_rel_int(&smp_started, 1); 626 smp_active = 1; /* historic */ 627 } 628 629 mtx_unlock_spin(&ap_boot_mtx); 630 631 /* wait until all the AP's are up */ 632 while (smp_started == 0) 633 ia32_pause(); 634 635 /* enter the scheduler */ 636 sched_throw(NULL); 637 638 panic("scheduler returned us to %s", __func__); 639 /* NOTREACHED */ 640} 641 642/******************************************************************* 643 * local functions and data 644 */ 645 646/* 647 * We tell the I/O APIC code about all the CPUs we want to receive 648 * interrupts. If we don't want certain CPUs to receive IRQs we 649 * can simply not tell the I/O APIC code about them in this function. 650 * We also do not tell it about the BSP since it tells itself about 651 * the BSP internally to work with UP kernels and on UP machines. 652 */ 653static void 654set_interrupt_apic_ids(void) 655{ 656 u_int i, apic_id; 657 658 for (i = 0; i < MAXCPU; i++) { 659 apic_id = cpu_apic_ids[i]; 660 if (apic_id == -1) 661 continue; 662 if (cpu_info[apic_id].cpu_bsp) 663 continue; 664 if (cpu_info[apic_id].cpu_disabled) 665 continue; 666 667 /* Don't let hyperthreads service interrupts. */ 668 if (hyperthreading_cpus > 1 && 669 apic_id % hyperthreading_cpus != 0) 670 continue; 671 672 intr_add_cpu(i); 673 } 674} 675 676/* 677 * Assign logical CPU IDs to local APICs. 678 */ 679static void 680assign_cpu_ids(void) 681{ 682 u_int i; 683 684 /* Check for explicitly disabled CPUs. */ 685 for (i = 0; i <= MAX_APIC_ID; i++) { 686 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp) 687 continue; 688 689 /* Don't use this CPU if it has been disabled by a tunable. */ 690 if (resource_disabled("lapic", i)) { 691 cpu_info[i].cpu_disabled = 1; 692 continue; 693 } 694 } 695 696 /* 697 * Assign CPU IDs to local APIC IDs and disable any CPUs 698 * beyond MAXCPU. CPU 0 has already been assigned to the BSP, 699 * so we only have to assign IDs for APs. 700 */ 701 mp_ncpus = 1; 702 for (i = 0; i <= MAX_APIC_ID; i++) { 703 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp || 704 cpu_info[i].cpu_disabled) 705 continue; 706 707 if (mp_ncpus < MAXCPU) { 708 cpu_apic_ids[mp_ncpus] = i; 709 mp_ncpus++; 710 } else 711 cpu_info[i].cpu_disabled = 1; 712 } 713 KASSERT(mp_maxid >= mp_ncpus - 1, 714 ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid, 715 mp_ncpus)); 716} 717 718/* 719 * start each AP in our list 720 */ 721static int 722start_all_aps(void) 723{ 724#ifndef PC98 725 u_char mpbiosreason; 726#endif 727 uintptr_t kptbase; 728 u_int32_t mpbioswarmvec; 729 int apic_id, cpu, i; 730 731 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); 732 733 /* install the AP 1st level boot code */ 734 install_ap_tramp(); 735 736 /* save the current value of the warm-start vector */ 737 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF); 738#ifndef PC98 739 outb(CMOS_REG, BIOS_RESET); 740 mpbiosreason = inb(CMOS_DATA); 741#endif 742 743 /* set up temporary P==V mapping for AP boot */ 744 /* XXX this is a hack, we should boot the AP on its own stack/PTD */ 745 kptbase = (uintptr_t)(void *)KPTphys; 746 for (i = 0; i < NKPT; i++) 747 PTD[i] = (pd_entry_t)(PG_V | PG_RW | 748 ((kptbase + i * PAGE_SIZE) & PG_FRAME)); 749 invltlb(); 750 751 /* start each AP */ 752 for (cpu = 1; cpu < mp_ncpus; cpu++) { 753 apic_id = cpu_apic_ids[cpu]; 754 755 /* allocate and set up an idle stack data page */ 756 bootstacks[cpu] = (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE); 757 758 /* setup a vector to our boot code */ 759 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 760 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4); 761#ifndef PC98 762 outb(CMOS_REG, BIOS_RESET); 763 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 764#endif 765 766 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 4; 767 bootAP = cpu; 768 769 /* attempt to start the Application Processor */ 770 CHECK_INIT(99); /* setup checkpoints */ 771 if (!start_ap(apic_id)) { 772 printf("AP #%d (PHY# %d) failed!\n", cpu, apic_id); 773 CHECK_PRINT("trace"); /* show checkpoints */ 774 /* better panic as the AP may be running loose */ 775 printf("panic y/n? [y] "); 776 if (cngetc() != 'n') 777 panic("bye-bye"); 778 } 779 CHECK_PRINT("trace"); /* show checkpoints */ 780 781 all_cpus |= (1 << cpu); /* record AP in CPU map */ 782 } 783 784 /* build our map of 'other' CPUs */ 785 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 786 787 /* restore the warmstart vector */ 788 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec; 789 790#ifndef PC98 791 outb(CMOS_REG, BIOS_RESET); 792 outb(CMOS_DATA, mpbiosreason); 793#endif 794 795 /* Undo V==P hack from above */ 796 for (i = 0; i < NKPT; i++) 797 PTD[i] = 0; 798 pmap_invalidate_range(kernel_pmap, 0, NKPT * NBPDR - 1); 799 800 /* number of APs actually started */ 801 return mp_naps; 802} 803 804/* 805 * load the 1st level AP boot code into base memory. 806 */ 807 808/* targets for relocation */ 809extern void bigJump(void); 810extern void bootCodeSeg(void); 811extern void bootDataSeg(void); 812extern void MPentry(void); 813extern u_int MP_GDT; 814extern u_int mp_gdtbase; 815 816static void 817install_ap_tramp(void) 818{ 819 int x; 820 int size = *(int *) ((u_long) & bootMP_size); 821 vm_offset_t va = boot_address + KERNBASE; 822 u_char *src = (u_char *) ((u_long) bootMP); 823 u_char *dst = (u_char *) va; 824 u_int boot_base = (u_int) bootMP; 825 u_int8_t *dst8; 826 u_int16_t *dst16; 827 u_int32_t *dst32; 828 829 KASSERT (size <= PAGE_SIZE, 830 ("'size' do not fit into PAGE_SIZE, as expected.")); 831 pmap_kenter(va, boot_address); 832 pmap_invalidate_page (kernel_pmap, va); 833 for (x = 0; x < size; ++x) 834 *dst++ = *src++; 835 836 /* 837 * modify addresses in code we just moved to basemem. unfortunately we 838 * need fairly detailed info about mpboot.s for this to work. changes 839 * to mpboot.s might require changes here. 840 */ 841 842 /* boot code is located in KERNEL space */ 843 dst = (u_char *) va; 844 845 /* modify the lgdt arg */ 846 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 847 *dst32 = boot_address + ((u_int) & MP_GDT - boot_base); 848 849 /* modify the ljmp target for MPentry() */ 850 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 851 *dst32 = ((u_int) MPentry - KERNBASE); 852 853 /* modify the target for boot code segment */ 854 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 855 dst8 = (u_int8_t *) (dst16 + 1); 856 *dst16 = (u_int) boot_address & 0xffff; 857 *dst8 = ((u_int) boot_address >> 16) & 0xff; 858 859 /* modify the target for boot data segment */ 860 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 861 dst8 = (u_int8_t *) (dst16 + 1); 862 *dst16 = (u_int) boot_address & 0xffff; 863 *dst8 = ((u_int) boot_address >> 16) & 0xff; 864} 865 866/* 867 * This function starts the AP (application processor) identified 868 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 869 * to accomplish this. This is necessary because of the nuances 870 * of the different hardware we might encounter. It isn't pretty, 871 * but it seems to work. 872 */ 873static int 874start_ap(int apic_id) 875{ 876 int vector, ms; 877 int cpus; 878 879 /* calculate the vector */ 880 vector = (boot_address >> 12) & 0xff; 881 882 /* used as a watchpoint to signal AP startup */ 883 cpus = mp_naps; 884 885 /* 886 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 887 * and running the target CPU. OR this INIT IPI might be latched (P5 888 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 889 * ignored. 890 */ 891 892 /* do an INIT IPI: assert RESET */ 893 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 894 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id); 895 896 /* wait for pending status end */ 897 lapic_ipi_wait(-1); 898 899 /* do an INIT IPI: deassert RESET */ 900 lapic_ipi_raw(APIC_DEST_ALLESELF | APIC_TRIGMOD_LEVEL | 901 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, 0); 902 903 /* wait for pending status end */ 904 DELAY(10000); /* wait ~10mS */ 905 lapic_ipi_wait(-1); 906 907 /* 908 * next we do a STARTUP IPI: the previous INIT IPI might still be 909 * latched, (P5 bug) this 1st STARTUP would then terminate 910 * immediately, and the previously started INIT IPI would continue. OR 911 * the previous INIT IPI has already run. and this STARTUP IPI will 912 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 913 * will run. 914 */ 915 916 /* do a STARTUP IPI */ 917 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 918 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 919 vector, apic_id); 920 lapic_ipi_wait(-1); 921 DELAY(200); /* wait ~200uS */ 922 923 /* 924 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 925 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 926 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 927 * recognized after hardware RESET or INIT IPI. 928 */ 929 930 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 931 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 932 vector, apic_id); 933 lapic_ipi_wait(-1); 934 DELAY(200); /* wait ~200uS */ 935 936 /* Wait up to 5 seconds for it to start. */ 937 for (ms = 0; ms < 5000; ms++) { 938 if (mp_naps > cpus) 939 return 1; /* return SUCCESS */ 940 DELAY(1000); 941 } 942 return 0; /* return FAILURE */ 943} 944 945#ifdef COUNT_XINVLTLB_HITS 946u_int xhits_gbl[MAXCPU]; 947u_int xhits_pg[MAXCPU]; 948u_int xhits_rng[MAXCPU]; 949SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, ""); 950SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl, 951 sizeof(xhits_gbl), "IU", ""); 952SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg, 953 sizeof(xhits_pg), "IU", ""); 954SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng, 955 sizeof(xhits_rng), "IU", ""); 956 957u_int ipi_global; 958u_int ipi_page; 959u_int ipi_range; 960u_int ipi_range_size; 961SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, ""); 962SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, ""); 963SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, ""); 964SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size, 965 0, ""); 966 967u_int ipi_masked_global; 968u_int ipi_masked_page; 969u_int ipi_masked_range; 970u_int ipi_masked_range_size; 971SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW, 972 &ipi_masked_global, 0, ""); 973SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW, 974 &ipi_masked_page, 0, ""); 975SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW, 976 &ipi_masked_range, 0, ""); 977SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW, 978 &ipi_masked_range_size, 0, ""); 979#endif /* COUNT_XINVLTLB_HITS */ 980 981/* 982 * Flush the TLB on all other CPU's 983 */ 984static void 985smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2) 986{ 987 u_int ncpu; 988 989 ncpu = mp_ncpus - 1; /* does not shootdown self */ 990 if (ncpu < 1) 991 return; /* no other cpus */ 992 if (!(read_eflags() & PSL_I)) 993 panic("%s: interrupts disabled", __func__); 994 mtx_lock_spin(&smp_ipi_mtx); 995 smp_tlb_addr1 = addr1; 996 smp_tlb_addr2 = addr2; 997 atomic_store_rel_int(&smp_tlb_wait, 0); 998 ipi_all_but_self(vector); 999 while (smp_tlb_wait < ncpu) 1000 ia32_pause(); 1001 mtx_unlock_spin(&smp_ipi_mtx); 1002} 1003 1004static void 1005smp_targeted_tlb_shootdown(u_int mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2) 1006{ 1007 int ncpu, othercpus; 1008 1009 othercpus = mp_ncpus - 1; 1010 if (mask == (u_int)-1) { 1011 ncpu = othercpus; 1012 if (ncpu < 1) 1013 return; 1014 } else { 1015 mask &= ~PCPU_GET(cpumask); 1016 if (mask == 0) 1017 return; 1018 ncpu = bitcount32(mask); 1019 if (ncpu > othercpus) { 1020 /* XXX this should be a panic offence */ 1021 printf("SMP: tlb shootdown to %d other cpus (only have %d)\n", 1022 ncpu, othercpus); 1023 ncpu = othercpus; 1024 } 1025 /* XXX should be a panic, implied by mask == 0 above */ 1026 if (ncpu < 1) 1027 return; 1028 } 1029 if (!(read_eflags() & PSL_I)) 1030 panic("%s: interrupts disabled", __func__); 1031 mtx_lock_spin(&smp_ipi_mtx); 1032 smp_tlb_addr1 = addr1; 1033 smp_tlb_addr2 = addr2; 1034 atomic_store_rel_int(&smp_tlb_wait, 0); 1035 if (mask == (u_int)-1) 1036 ipi_all_but_self(vector); 1037 else 1038 ipi_selected(mask, vector); 1039 while (smp_tlb_wait < ncpu) 1040 ia32_pause(); 1041 mtx_unlock_spin(&smp_ipi_mtx); 1042} 1043 1044void 1045smp_cache_flush(void) 1046{ 1047 1048 if (smp_started) 1049 smp_tlb_shootdown(IPI_INVLCACHE, 0, 0); 1050} 1051 1052void 1053smp_invltlb(void) 1054{ 1055 1056 if (smp_started) { 1057 smp_tlb_shootdown(IPI_INVLTLB, 0, 0); 1058#ifdef COUNT_XINVLTLB_HITS 1059 ipi_global++; 1060#endif 1061 } 1062} 1063 1064void 1065smp_invlpg(vm_offset_t addr) 1066{ 1067 1068 if (smp_started) { 1069 smp_tlb_shootdown(IPI_INVLPG, addr, 0); 1070#ifdef COUNT_XINVLTLB_HITS 1071 ipi_page++; 1072#endif 1073 } 1074} 1075 1076void 1077smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2) 1078{ 1079 1080 if (smp_started) { 1081 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2); 1082#ifdef COUNT_XINVLTLB_HITS 1083 ipi_range++; 1084 ipi_range_size += (addr2 - addr1) / PAGE_SIZE; 1085#endif 1086 } 1087} 1088 1089void 1090smp_masked_invltlb(u_int mask) 1091{ 1092 1093 if (smp_started) { 1094 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0); 1095#ifdef COUNT_XINVLTLB_HITS 1096 ipi_masked_global++; 1097#endif 1098 } 1099} 1100 1101void 1102smp_masked_invlpg(u_int mask, vm_offset_t addr) 1103{ 1104 1105 if (smp_started) { 1106 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0); 1107#ifdef COUNT_XINVLTLB_HITS 1108 ipi_masked_page++; 1109#endif 1110 } 1111} 1112 1113void 1114smp_masked_invlpg_range(u_int mask, vm_offset_t addr1, vm_offset_t addr2) 1115{ 1116 1117 if (smp_started) { 1118 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2); 1119#ifdef COUNT_XINVLTLB_HITS 1120 ipi_masked_range++; 1121 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE; 1122#endif 1123 } 1124} 1125 1126void 1127ipi_bitmap_handler(struct trapframe frame) 1128{ 1129 int cpu = PCPU_GET(cpuid); 1130 u_int ipi_bitmap; 1131 1132 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]); 1133 1134 if (ipi_bitmap & (1 << IPI_PREEMPT)) { 1135 struct thread *running_thread = curthread; 1136#ifdef COUNT_IPIS 1137 (*ipi_preempt_counts[cpu])++; 1138#endif 1139 thread_lock(running_thread); 1140 if (running_thread->td_critnest > 1) 1141 running_thread->td_owepreempt = 1; 1142 else 1143 mi_switch(SW_INVOL | SW_PREEMPT, NULL); 1144 thread_unlock(running_thread); 1145 } 1146 1147 if (ipi_bitmap & (1 << IPI_AST)) { 1148#ifdef COUNT_IPIS 1149 (*ipi_ast_counts[cpu])++; 1150#endif 1151 /* Nothing to do for AST */ 1152 } 1153} 1154 1155/* 1156 * send an IPI to a set of cpus. 1157 */ 1158void 1159ipi_selected(u_int32_t cpus, u_int ipi) 1160{ 1161 int cpu; 1162 u_int bitmap = 0; 1163 u_int old_pending; 1164 u_int new_pending; 1165 1166 if (IPI_IS_BITMAPED(ipi)) { 1167 bitmap = 1 << ipi; 1168 ipi = IPI_BITMAP_VECTOR; 1169 } 1170 1171#ifdef STOP_NMI 1172 if (ipi == IPI_STOP && stop_cpus_with_nmi) { 1173 ipi_nmi_selected(cpus); 1174 return; 1175 } 1176#endif 1177 CTR3(KTR_SMP, "%s: cpus: %x ipi: %x", __func__, cpus, ipi); 1178 while ((cpu = ffs(cpus)) != 0) { 1179 cpu--; 1180 cpus &= ~(1 << cpu); 1181 1182 KASSERT(cpu_apic_ids[cpu] != -1, 1183 ("IPI to non-existent CPU %d", cpu)); 1184 1185 if (bitmap) { 1186 do { 1187 old_pending = cpu_ipi_pending[cpu]; 1188 new_pending = old_pending | bitmap; 1189 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu],old_pending, new_pending)); 1190 1191 if (old_pending) 1192 continue; 1193 } 1194 1195 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]); 1196 } 1197 1198} 1199 1200/* 1201 * send an IPI INTerrupt containing 'vector' to all CPUs, including myself 1202 */ 1203void 1204ipi_all(u_int ipi) 1205{ 1206 1207 if (IPI_IS_BITMAPED(ipi) || (ipi == IPI_STOP && stop_cpus_with_nmi)) { 1208 ipi_selected(all_cpus, ipi); 1209 return; 1210 } 1211 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1212 lapic_ipi_vectored(ipi, APIC_IPI_DEST_ALL); 1213} 1214 1215/* 1216 * send an IPI to all CPUs EXCEPT myself 1217 */ 1218void 1219ipi_all_but_self(u_int ipi) 1220{ 1221 1222 if (IPI_IS_BITMAPED(ipi) || (ipi == IPI_STOP && stop_cpus_with_nmi)) { 1223 ipi_selected(PCPU_GET(other_cpus), ipi); 1224 return; 1225 } 1226 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1227 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS); 1228} 1229 1230/* 1231 * send an IPI to myself 1232 */ 1233void 1234ipi_self(u_int ipi) 1235{ 1236 1237 if (IPI_IS_BITMAPED(ipi) || (ipi == IPI_STOP && stop_cpus_with_nmi)) { 1238 ipi_selected(PCPU_GET(cpumask), ipi); 1239 return; 1240 } 1241 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1242 lapic_ipi_vectored(ipi, APIC_IPI_DEST_SELF); 1243} 1244 1245#ifdef STOP_NMI 1246/* 1247 * send NMI IPI to selected CPUs 1248 */ 1249 1250#define BEFORE_SPIN 1000000 1251 1252void 1253ipi_nmi_selected(u_int32_t cpus) 1254{ 1255 int cpu; 1256 register_t icrlo; 1257 1258 icrlo = APIC_DELMODE_NMI | APIC_DESTMODE_PHY | APIC_LEVEL_ASSERT 1259 | APIC_TRIGMOD_EDGE; 1260 1261 CTR2(KTR_SMP, "%s: cpus: %x nmi", __func__, cpus); 1262 1263 atomic_set_int(&ipi_nmi_pending, cpus); 1264 1265 while ((cpu = ffs(cpus)) != 0) { 1266 cpu--; 1267 cpus &= ~(1 << cpu); 1268 1269 KASSERT(cpu_apic_ids[cpu] != -1, 1270 ("IPI NMI to non-existent CPU %d", cpu)); 1271 1272 /* Wait for an earlier IPI to finish. */ 1273 if (!lapic_ipi_wait(BEFORE_SPIN)) 1274 panic("ipi_nmi_selected: previous IPI has not cleared"); 1275 1276 lapic_ipi_raw(icrlo, cpu_apic_ids[cpu]); 1277 } 1278} 1279 1280int 1281ipi_nmi_handler(void) 1282{ 1283 int cpumask = PCPU_GET(cpumask); 1284 1285 if (!(ipi_nmi_pending & cpumask)) 1286 return 1; 1287 1288 atomic_clear_int(&ipi_nmi_pending, cpumask); 1289 cpustop_handler(); 1290 return 0; 1291} 1292 1293#endif /* STOP_NMI */ 1294 1295/* 1296 * Handle an IPI_STOP by saving our current context and spinning until we 1297 * are resumed. 1298 */ 1299void 1300cpustop_handler(void) 1301{ 1302 int cpu = PCPU_GET(cpuid); 1303 int cpumask = PCPU_GET(cpumask); 1304 1305 savectx(&stoppcbs[cpu]); 1306 1307 /* Indicate that we are stopped */ 1308 atomic_set_int(&stopped_cpus, cpumask); 1309 1310 /* Wait for restart */ 1311 while (!(started_cpus & cpumask)) 1312 ia32_pause(); 1313 1314 atomic_clear_int(&started_cpus, cpumask); 1315 atomic_clear_int(&stopped_cpus, cpumask); 1316 1317 if (cpu == 0 && cpustop_restartfunc != NULL) { 1318 cpustop_restartfunc(); 1319 cpustop_restartfunc = NULL; 1320 } 1321} 1322 1323/* 1324 * This is called once the rest of the system is up and running and we're 1325 * ready to let the AP's out of the pen. 1326 */ 1327static void 1328release_aps(void *dummy __unused) 1329{ 1330 1331 if (mp_ncpus == 1) 1332 return; 1333 atomic_store_rel_int(&aps_ready, 1); 1334 while (smp_started == 0) 1335 ia32_pause(); 1336} 1337SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL); 1338 1339static int 1340sysctl_hlt_cpus(SYSCTL_HANDLER_ARGS) 1341{ 1342 u_int mask; 1343 int error; 1344 1345 mask = hlt_cpus_mask; 1346 error = sysctl_handle_int(oidp, &mask, 0, req); 1347 if (error || !req->newptr) 1348 return (error); 1349 1350 if (logical_cpus_mask != 0 && 1351 (mask & logical_cpus_mask) == logical_cpus_mask) 1352 hlt_logical_cpus = 1; 1353 else 1354 hlt_logical_cpus = 0; 1355 1356 if (! hyperthreading_allowed) 1357 mask |= hyperthreading_cpus_mask; 1358 1359 if ((mask & all_cpus) == all_cpus) 1360 mask &= ~(1<<0); 1361 hlt_cpus_mask = mask; 1362 return (error); 1363} 1364SYSCTL_PROC(_machdep, OID_AUTO, hlt_cpus, CTLTYPE_INT|CTLFLAG_RW, 1365 0, 0, sysctl_hlt_cpus, "IU", 1366 "Bitmap of CPUs to halt. 101 (binary) will halt CPUs 0 and 2."); 1367 1368static int 1369sysctl_hlt_logical_cpus(SYSCTL_HANDLER_ARGS) 1370{ 1371 int disable, error; 1372 1373 disable = hlt_logical_cpus; 1374 error = sysctl_handle_int(oidp, &disable, 0, req); 1375 if (error || !req->newptr) 1376 return (error); 1377 1378 if (disable) 1379 hlt_cpus_mask |= logical_cpus_mask; 1380 else 1381 hlt_cpus_mask &= ~logical_cpus_mask; 1382 1383 if (! hyperthreading_allowed) 1384 hlt_cpus_mask |= hyperthreading_cpus_mask; 1385 1386 if ((hlt_cpus_mask & all_cpus) == all_cpus) 1387 hlt_cpus_mask &= ~(1<<0); 1388 1389 hlt_logical_cpus = disable; 1390 return (error); 1391} 1392 1393static int 1394sysctl_hyperthreading_allowed(SYSCTL_HANDLER_ARGS) 1395{ 1396 int allowed, error; 1397 1398 allowed = hyperthreading_allowed; 1399 error = sysctl_handle_int(oidp, &allowed, 0, req); 1400 if (error || !req->newptr) 1401 return (error); 1402 1403 if (allowed) 1404 hlt_cpus_mask &= ~hyperthreading_cpus_mask; 1405 else 1406 hlt_cpus_mask |= hyperthreading_cpus_mask; 1407 1408 if (logical_cpus_mask != 0 && 1409 (hlt_cpus_mask & logical_cpus_mask) == logical_cpus_mask) 1410 hlt_logical_cpus = 1; 1411 else 1412 hlt_logical_cpus = 0; 1413 1414 if ((hlt_cpus_mask & all_cpus) == all_cpus) 1415 hlt_cpus_mask &= ~(1<<0); 1416 1417 hyperthreading_allowed = allowed; 1418 return (error); 1419} 1420 1421static void 1422cpu_hlt_setup(void *dummy __unused) 1423{ 1424 1425 if (logical_cpus_mask != 0) { 1426 TUNABLE_INT_FETCH("machdep.hlt_logical_cpus", 1427 &hlt_logical_cpus); 1428 sysctl_ctx_init(&logical_cpu_clist); 1429 SYSCTL_ADD_PROC(&logical_cpu_clist, 1430 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1431 "hlt_logical_cpus", CTLTYPE_INT|CTLFLAG_RW, 0, 0, 1432 sysctl_hlt_logical_cpus, "IU", ""); 1433 SYSCTL_ADD_UINT(&logical_cpu_clist, 1434 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1435 "logical_cpus_mask", CTLTYPE_INT|CTLFLAG_RD, 1436 &logical_cpus_mask, 0, ""); 1437 1438 if (hlt_logical_cpus) 1439 hlt_cpus_mask |= logical_cpus_mask; 1440 1441 /* 1442 * If necessary for security purposes, force 1443 * hyperthreading off, regardless of the value 1444 * of hlt_logical_cpus. 1445 */ 1446 if (hyperthreading_cpus_mask) { 1447 TUNABLE_INT_FETCH("machdep.hyperthreading_allowed", 1448 &hyperthreading_allowed); 1449 SYSCTL_ADD_PROC(&logical_cpu_clist, 1450 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1451 "hyperthreading_allowed", CTLTYPE_INT|CTLFLAG_RW, 1452 0, 0, sysctl_hyperthreading_allowed, "IU", ""); 1453 if (! hyperthreading_allowed) 1454 hlt_cpus_mask |= hyperthreading_cpus_mask; 1455 } 1456 } 1457} 1458SYSINIT(cpu_hlt, SI_SUB_SMP, SI_ORDER_ANY, cpu_hlt_setup, NULL); 1459 1460int 1461mp_grab_cpu_hlt(void) 1462{ 1463 u_int mask = PCPU_GET(cpumask); 1464#ifdef MP_WATCHDOG 1465 u_int cpuid = PCPU_GET(cpuid); 1466#endif 1467 int retval; 1468 1469#ifdef MP_WATCHDOG 1470 ap_watchdog(cpuid); 1471#endif 1472 1473 retval = mask & hlt_cpus_mask; 1474 while (mask & hlt_cpus_mask) 1475 __asm __volatile("sti; hlt" : : : "memory"); 1476 return (retval); 1477} 1478 1479#ifdef COUNT_IPIS 1480/* 1481 * Setup interrupt counters for IPI handlers. 1482 */ 1483static void 1484mp_ipi_intrcnt(void *dummy) 1485{ 1486 char buf[64]; 1487 int i; 1488 1489 for (i = 0; i < mp_maxid; i++) { 1490 if (CPU_ABSENT(i)) 1491 continue; 1492 snprintf(buf, sizeof(buf), "cpu%d: invltlb", i); 1493 intrcnt_add(buf, &ipi_invltlb_counts[i]); 1494 snprintf(buf, sizeof(buf), "cpu%d: invlrng", i); 1495 intrcnt_add(buf, &ipi_invlrng_counts[i]); 1496 snprintf(buf, sizeof(buf), "cpu%d: invlpg", i); 1497 intrcnt_add(buf, &ipi_invlpg_counts[i]); 1498 snprintf(buf, sizeof(buf), "cpu%d: preempt", i); 1499 intrcnt_add(buf, &ipi_preempt_counts[i]); 1500 snprintf(buf, sizeof(buf), "cpu%d: ast", i); 1501 intrcnt_add(buf, &ipi_ast_counts[i]); 1502 snprintf(buf, sizeof(buf), "cpu%d: rendezvous", i); 1503 intrcnt_add(buf, &ipi_rendezvous_counts[i]); 1504 snprintf(buf, sizeof(buf), "cpu%d: lazypmap", i); 1505 intrcnt_add(buf, &ipi_lazypmap_counts[i]); 1506 } 1507} 1508SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL) 1509#endif 1510