mp_x86.c revision 158238
155682Smarkm/*- 2233294Sstas * Copyright (c) 1996, by Steve Passe 3233294Sstas * All rights reserved. 4233294Sstas * 555682Smarkm * Redistribution and use in source and binary forms, with or without 6233294Sstas * modification, are permitted provided that the following conditions 7233294Sstas * are met: 8233294Sstas * 1. Redistributions of source code must retain the above copyright 955682Smarkm * notice, this list of conditions and the following disclaimer. 10233294Sstas * 2. The name of the developer may NOT be used to endorse or promote products 11233294Sstas * derived from this software without specific prior written permission. 1255682Smarkm * 13233294Sstas * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14233294Sstas * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15233294Sstas * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1655682Smarkm * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17233294Sstas * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18233294Sstas * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19233294Sstas * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2055682Smarkm * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21233294Sstas * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22233294Sstas * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23233294Sstas * SUCH DAMAGE. 24233294Sstas */ 25233294Sstas 26233294Sstas#include <sys/cdefs.h> 27233294Sstas__FBSDID("$FreeBSD: head/sys/i386/i386/mp_machdep.c 158238 2006-05-01 22:07:00Z jhb $"); 28233294Sstas 29233294Sstas#include "opt_apic.h" 30233294Sstas#include "opt_cpu.h" 31233294Sstas#include "opt_kstack_pages.h" 3255682Smarkm#include "opt_mp_watchdog.h" 3355682Smarkm#include "opt_sched.h" 3455682Smarkm#include "opt_smp.h" 35178825Sdfr 3655682Smarkm#if !defined(lint) 37178825Sdfr#if !defined(SMP) 38178825Sdfr#error How did you get here? 39178825Sdfr#endif 4055682Smarkm 4155682Smarkm#ifndef DEV_APIC 4255682Smarkm#error The apic device is required for SMP, add "device apic" to your config file. 4355682Smarkm#endif 44178825Sdfr#if defined(CPU_DISABLE_CMPXCHG) && !defined(COMPILING_LINT) 45178825Sdfr#error SMP not supported with CPU_DISABLE_CMPXCHG 46178825Sdfr#endif 47178825Sdfr#endif /* not lint */ 48178825Sdfr 49178825Sdfr#include <sys/param.h> 50178825Sdfr#include <sys/systm.h> 51178825Sdfr#include <sys/bus.h> 52178825Sdfr#include <sys/cons.h> /* cngetc() */ 53178825Sdfr#ifdef GPROF 54178825Sdfr#include <sys/gmon.h> 55178825Sdfr#endif 56178825Sdfr#include <sys/kernel.h> 57178825Sdfr#include <sys/ktr.h> 58178825Sdfr#include <sys/lock.h> 59178825Sdfr#include <sys/malloc.h> 60178825Sdfr#include <sys/memrange.h> 61178825Sdfr#include <sys/mutex.h> 62178825Sdfr#include <sys/pcpu.h> 63178825Sdfr#include <sys/proc.h> 6455682Smarkm#include <sys/smp.h> 65178825Sdfr#include <sys/sysctl.h> 66178825Sdfr 67178825Sdfr#include <vm/vm.h> 6855682Smarkm#include <vm/vm_param.h> 69178825Sdfr#include <vm/pmap.h> 70178825Sdfr#include <vm/vm_kern.h> 71178825Sdfr#include <vm/vm_extern.h> 72178825Sdfr 73178825Sdfr#include <machine/apicreg.h> 74178825Sdfr#include <machine/clock.h> 75178825Sdfr#include <machine/md_var.h> 76178825Sdfr#include <machine/mp_watchdog.h> 77178825Sdfr#include <machine/pcb.h> 78178825Sdfr#include <machine/smp.h> 7955682Smarkm#include <machine/specialreg.h> 8055682Smarkm#include <machine/privatespace.h> 8155682Smarkm 82178825Sdfr#define WARMBOOT_TARGET 0 83178825Sdfr#define WARMBOOT_OFF (KERNBASE + 0x0467) 84178825Sdfr#define WARMBOOT_SEG (KERNBASE + 0x0469) 85178825Sdfr 86178825Sdfr#define CMOS_REG (0x70) 87178825Sdfr#define CMOS_DATA (0x71) 88178825Sdfr#define BIOS_RESET (0x0f) 89178825Sdfr#define BIOS_WARM (0x0a) 90178825Sdfr 91178825Sdfr/* 92178825Sdfr * this code MUST be enabled here and in mpboot.s. 93178825Sdfr * it follows the very early stages of AP boot by placing values in CMOS ram. 94178825Sdfr * it NORMALLY will never be needed and thus the primitive method for enabling. 95178825Sdfr * 96233294Sstas#define CHECK_POINTS 97233294Sstas */ 98178825Sdfr 9955682Smarkm#if defined(CHECK_POINTS) && !defined(PC98) 100178825Sdfr#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 101178825Sdfr#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 102178825Sdfr 103178825Sdfr#define CHECK_INIT(D); \ 10455682Smarkm CHECK_WRITE(0x34, (D)); \ 105178825Sdfr CHECK_WRITE(0x35, (D)); \ 106178825Sdfr CHECK_WRITE(0x36, (D)); \ 107178825Sdfr CHECK_WRITE(0x37, (D)); \ 108178825Sdfr CHECK_WRITE(0x38, (D)); \ 109178825Sdfr CHECK_WRITE(0x39, (D)); 110178825Sdfr 111178825Sdfr#define CHECK_PRINT(S); \ 112178825Sdfr printf("%s: %d, %d, %d, %d, %d, %d\n", \ 11355682Smarkm (S), \ 114178825Sdfr CHECK_READ(0x34), \ 115178825Sdfr CHECK_READ(0x35), \ 116178825Sdfr CHECK_READ(0x36), \ 117178825Sdfr CHECK_READ(0x37), \ 118178825Sdfr CHECK_READ(0x38), \ 119178825Sdfr CHECK_READ(0x39)); 120178825Sdfr 121178825Sdfr#else /* CHECK_POINTS */ 122178825Sdfr 123178825Sdfr#define CHECK_INIT(D) 124178825Sdfr#define CHECK_PRINT(S) 125178825Sdfr#define CHECK_WRITE(A, D) 126178825Sdfr 127178825Sdfr#endif /* CHECK_POINTS */ 128178825Sdfr 129178825Sdfr/* lock region used by kernel profiling */ 130178825Sdfrint mcount_lock; 131178825Sdfr 13255682Smarkmint mp_naps; /* # of Applications processors */ 133178825Sdfrint boot_cpu_id = -1; /* designated BSP */ 134178825Sdfrextern int nkpt; 135178825Sdfr 136178825Sdfr/* 137178825Sdfr * CPU topology map datastructures for HTT. 138178825Sdfr */ 139178825Sdfrstatic struct cpu_group mp_groups[MAXCPU]; 140178825Sdfrstatic struct cpu_top mp_top; 141178825Sdfr 142178825Sdfr/* AP uses this during bootstrap. Do not staticize. */ 143178825Sdfrchar *bootSTK; 144178825Sdfrstatic int bootAP; 145178825Sdfr 146178825Sdfr/* Hotwire a 0->4MB V==P mapping */ 147178825Sdfrextern pt_entry_t *KPTphys; 148178825Sdfr 149233294Sstas/* SMP page table page */ 150178825Sdfrextern pt_entry_t *SMPpt; 151178825Sdfr 152178825Sdfrstruct pcb stoppcbs[MAXCPU]; 153178825Sdfr 154178825Sdfr/* Variables needed for SMP tlb shootdown. */ 155178825Sdfrvm_offset_t smp_tlb_addr1; 156178825Sdfrvm_offset_t smp_tlb_addr2; 157178825Sdfrvolatile int smp_tlb_wait; 158178825Sdfr 159178825Sdfr#ifdef STOP_NMI 160178825Sdfrvolatile cpumask_t ipi_nmi_pending; 161178825Sdfr 162178825Sdfrstatic void ipi_nmi_selected(u_int32_t cpus); 163178825Sdfr#endif 164178825Sdfr 165178825Sdfr#ifdef COUNT_IPIS 166178825Sdfr/* Interrupt counts. */ 167178825Sdfr#ifdef IPI_PREEMPTION 168178825Sdfrstatic u_long *ipi_preempt_counts[MAXCPU]; 169178825Sdfr#endif 170178825Sdfrstatic u_long *ipi_ast_counts[MAXCPU]; 171233294Sstasu_long *ipi_invltlb_counts[MAXCPU]; 172178825Sdfru_long *ipi_invlrng_counts[MAXCPU]; 173178825Sdfru_long *ipi_invlpg_counts[MAXCPU]; 174178825Sdfru_long *ipi_invlcache_counts[MAXCPU]; 175178825Sdfru_long *ipi_rendezvous_counts[MAXCPU]; 176178825Sdfru_long *ipi_lazypmap_counts[MAXCPU]; 177178825Sdfr#endif 178178825Sdfr 179178825Sdfr/* 180178825Sdfr * Local data and functions. 181178825Sdfr */ 182178825Sdfr 183233294Sstas#ifdef STOP_NMI 184178825Sdfr/* 185178825Sdfr * Provide an alternate method of stopping other CPUs. If another CPU has 186178825Sdfr * disabled interrupts the conventional STOP IPI will be blocked. This 187178825Sdfr * NMI-based stop should get through in that case. 188178825Sdfr */ 189178825Sdfrstatic int stop_cpus_with_nmi = 1; 190178825SdfrSYSCTL_INT(_debug, OID_AUTO, stop_cpus_with_nmi, CTLTYPE_INT | CTLFLAG_RW, 191178825Sdfr &stop_cpus_with_nmi, 0, ""); 192178825SdfrTUNABLE_INT("debug.stop_cpus_with_nmi", &stop_cpus_with_nmi); 193178825Sdfr#else 194178825Sdfr#define stop_cpus_with_nmi 0 195178825Sdfr#endif 196178825Sdfr 197178825Sdfrstatic u_int logical_cpus; 198178825Sdfr 199178825Sdfr/* used to hold the AP's until we are ready to release them */ 200233294Sstasstatic struct mtx ap_boot_mtx; 201178825Sdfr 202178825Sdfr/* Set to 1 once we're ready to let the APs out of the pen. */ 203178825Sdfrstatic volatile int aps_ready = 0; 204178825Sdfr 205178825Sdfr/* 206178825Sdfr * Store data from cpu_add() until later in the boot when we actually setup 207178825Sdfr * the APs. 208233294Sstas */ 209233294Sstasstruct cpu_info { 210233294Sstas int cpu_present:1; 211178825Sdfr int cpu_bsp:1; 212178825Sdfr int cpu_disabled:1; 213178825Sdfr} static cpu_info[MAXCPU]; 214178825Sdfrstatic int cpu_apic_ids[MAXCPU]; 215178825Sdfr 216178825Sdfr/* Holds pending bitmap based IPIs per CPU */ 217178825Sdfrstatic volatile u_int cpu_ipi_pending[MAXCPU]; 218178825Sdfr 219178825Sdfrstatic u_int boot_address; 220178825Sdfr 221178825Sdfrstatic void set_interrupt_apic_ids(void); 222178825Sdfrstatic int start_all_aps(void); 223178825Sdfrstatic void install_ap_tramp(void); 224178825Sdfrstatic int start_ap(int apic_id); 225178825Sdfrstatic void release_aps(void *dummy); 226178825Sdfr 227178825Sdfrstatic int hlt_logical_cpus; 228233294Sstasstatic u_int hyperthreading_cpus; 229178825Sdfrstatic cpumask_t hyperthreading_cpus_mask; 230178825Sdfrstatic int hyperthreading_allowed = 1; 231178825Sdfrstatic struct sysctl_ctx_list logical_cpu_clist; 232178825Sdfr 233178825Sdfrstatic void 234178825Sdfrmem_range_AP_init(void) 235233294Sstas{ 236178825Sdfr if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP) 237178825Sdfr mem_range_softc.mr_op->initAP(&mem_range_softc); 238233294Sstas} 239233294Sstas 240178825Sdfrvoid 241178825Sdfrmp_topology(void) 242178825Sdfr{ 243178825Sdfr struct cpu_group *group; 244178825Sdfr u_int regs[4]; 245178825Sdfr int logical_cpus; 246178825Sdfr int apic_id; 24755682Smarkm int groups; 24855682Smarkm int cpu; 24955682Smarkm 25055682Smarkm /* Build the smp_topology map. */ 251178825Sdfr /* Nothing to do if there is no HTT support. */ 252178825Sdfr if ((cpu_feature & CPUID_HTT) == 0) 253178825Sdfr return; 254178825Sdfr logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 25555682Smarkm if (logical_cpus <= 1) 25655682Smarkm return; 25755682Smarkm /* Nothing to do if reported cores are physical cores. */ 25855682Smarkm if (strcmp(cpu_vendor, "GenuineIntel") == 0 && cpu_high >= 4) { 25955682Smarkm cpuid_count(4, 0, regs); 26055682Smarkm if ((regs[0] & 0x1f) != 0 && 26155682Smarkm logical_cpus <= ((regs[0] >> 26) & 0x3f) + 1) 26255682Smarkm return; 26355682Smarkm } 26455682Smarkm group = &mp_groups[0]; 26555682Smarkm groups = 1; 26655682Smarkm for (cpu = 0, apic_id = 0; apic_id < MAXCPU; apic_id++) { 267233294Sstas if (!cpu_info[apic_id].cpu_present) 268233294Sstas continue; 269233294Sstas /* 27055682Smarkm * If the current group has members and we're not a logical 27155682Smarkm * cpu, create a new group. 27255682Smarkm */ 27355682Smarkm if (group->cg_count != 0 && (apic_id % logical_cpus) == 0) { 27455682Smarkm group++; 275233294Sstas groups++; 276233294Sstas } 277233294Sstas group->cg_count++; 27855682Smarkm group->cg_mask |= 1 << cpu; 27955682Smarkm cpu++; 28055682Smarkm } 28155682Smarkm 28255682Smarkm mp_top.ct_count = groups; 28355682Smarkm mp_top.ct_group = mp_groups; 28455682Smarkm smp_topology = &mp_top; 28555682Smarkm} 28655682Smarkm 287178825Sdfr 28855682Smarkm/* 28955682Smarkm * Calculate usable address in base memory for AP trampoline code. 29055682Smarkm */ 29155682Smarkmu_int 292233294Sstasmp_bootaddress(u_int basemem) 29355682Smarkm{ 29455682Smarkm 29555682Smarkm boot_address = trunc_page(basemem); /* round down to 4k boundary */ 29655682Smarkm if ((basemem - boot_address) < bootMP_size) 29755682Smarkm boot_address -= PAGE_SIZE; /* not enough, lower by 4k */ 29855682Smarkm 299178825Sdfr return boot_address; 30055682Smarkm} 30155682Smarkm 302178825Sdfrvoid 30355682Smarkmcpu_add(u_int apic_id, char boot_cpu) 30455682Smarkm{ 30555682Smarkm 30655682Smarkm if (apic_id >= MAXCPU) { 30755682Smarkm printf("SMP: CPU %d exceeds maximum CPU %d, ignoring\n", 308233294Sstas apic_id, MAXCPU - 1); 309233294Sstas return; 31055682Smarkm } 31155682Smarkm KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice", 31255682Smarkm apic_id)); 31355682Smarkm cpu_info[apic_id].cpu_present = 1; 314178825Sdfr if (boot_cpu) { 31555682Smarkm KASSERT(boot_cpu_id == -1, 31655682Smarkm ("CPU %d claims to be BSP, but CPU %d already is", apic_id, 31755682Smarkm boot_cpu_id)); 318178825Sdfr boot_cpu_id = apic_id; 319178825Sdfr cpu_info[apic_id].cpu_bsp = 1; 320178825Sdfr } 321178825Sdfr mp_ncpus++; 322178825Sdfr if (bootverbose) 323178825Sdfr printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" : 324178825Sdfr "AP"); 325178825Sdfr 326178825Sdfr} 327178825Sdfr 328178825Sdfrvoid 329178825Sdfrcpu_mp_setmaxid(void) 330178825Sdfr{ 331178825Sdfr 332233294Sstas mp_maxid = MAXCPU - 1; 333178825Sdfr} 334178825Sdfr 335178825Sdfrint 336178825Sdfrcpu_mp_probe(void) 337178825Sdfr{ 338178825Sdfr 339178825Sdfr /* 340178825Sdfr * Always record BSP in CPU map so that the mbuf init code works 341178825Sdfr * correctly. 342178825Sdfr */ 343178825Sdfr all_cpus = 1; 344178825Sdfr if (mp_ncpus == 0) { 345178825Sdfr /* 346178825Sdfr * No CPUs were found, so this must be a UP system. Setup 347178825Sdfr * the variables to represent a system with a single CPU 348178825Sdfr * with an id of 0. 349178825Sdfr */ 350178825Sdfr mp_ncpus = 1; 351178825Sdfr return (0); 352178825Sdfr } 353178825Sdfr 354178825Sdfr /* At least one CPU was found. */ 355178825Sdfr if (mp_ncpus == 1) { 356178825Sdfr /* 357178825Sdfr * One CPU was found, so this must be a UP system with 358178825Sdfr * an I/O APIC. 359178825Sdfr */ 360178825Sdfr return (0); 361178825Sdfr } 362178825Sdfr 363178825Sdfr /* At least two CPUs were found. */ 364178825Sdfr return (1); 365178825Sdfr} 366178825Sdfr 367178825Sdfr/* 368178825Sdfr * Initialize the IPI handlers and start up the AP's. 369178825Sdfr */ 370178825Sdfrvoid 371178825Sdfrcpu_mp_start(void) 372178825Sdfr{ 373178825Sdfr int i; 374178825Sdfr u_int threads_per_cache, p[4]; 375178825Sdfr 376178825Sdfr /* Initialize the logical ID to APIC ID table. */ 377178825Sdfr for (i = 0; i < MAXCPU; i++) { 378178825Sdfr cpu_apic_ids[i] = -1; 379178825Sdfr cpu_ipi_pending[i] = 0; 380178825Sdfr } 381178825Sdfr 382178825Sdfr /* Install an inter-CPU IPI for TLB invalidation */ 383233294Sstas setidt(IPI_INVLTLB, IDTVEC(invltlb), 384233294Sstas SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 385233294Sstas setidt(IPI_INVLPG, IDTVEC(invlpg), 386178825Sdfr SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 387233294Sstas setidt(IPI_INVLRNG, IDTVEC(invlrng), 388178825Sdfr SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 389178825Sdfr 390233294Sstas /* Install an inter-CPU IPI for lazy pmap release */ 391178825Sdfr setidt(IPI_LAZYPMAP, IDTVEC(lazypmap), 392178825Sdfr SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 393178825Sdfr 394178825Sdfr /* Install an inter-CPU IPI for all-CPU rendezvous */ 395178825Sdfr setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous), 396233294Sstas SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 397233294Sstas 398233294Sstas /* Install generic inter-CPU IPI handler */ 399178825Sdfr setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler), 400178825Sdfr SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 401178825Sdfr 402178825Sdfr /* Install an inter-CPU IPI for CPU stop/restart */ 403178825Sdfr setidt(IPI_STOP, IDTVEC(cpustop), 404178825Sdfr SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 405178825Sdfr 406178825Sdfr 407178825Sdfr /* Set boot_cpu_id if needed. */ 408178825Sdfr if (boot_cpu_id == -1) { 409178825Sdfr boot_cpu_id = PCPU_GET(apic_id); 410178825Sdfr cpu_info[boot_cpu_id].cpu_bsp = 1; 411178825Sdfr } else 412178825Sdfr KASSERT(boot_cpu_id == PCPU_GET(apic_id), 413178825Sdfr ("BSP's APIC ID doesn't match boot_cpu_id")); 414178825Sdfr cpu_apic_ids[0] = boot_cpu_id; 415178825Sdfr 416178825Sdfr /* Start each Application Processor */ 417178825Sdfr start_all_aps(); 418178825Sdfr 419233294Sstas /* Setup the initial logical CPUs info. */ 420178825Sdfr logical_cpus = logical_cpus_mask = 0; 421233294Sstas if (cpu_feature & CPUID_HTT) 422178825Sdfr logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 423178825Sdfr 424233294Sstas /* 425178825Sdfr * Work out if hyperthreading is *really* enabled. This 426178825Sdfr * is made really ugly by the fact that processors lie: Dual 427178825Sdfr * core processors claim to be hyperthreaded even when they're 428178825Sdfr * not, presumably because they want to be treated the same 429178825Sdfr * way as HTT with respect to per-cpu software licensing. 430178825Sdfr * At the time of writing (May 12, 2005) the only hyperthreaded 431178825Sdfr * cpus are from Intel, and Intel's dual-core processors can be 432178825Sdfr * identified via the "deterministic cache parameters" cpuid 433233294Sstas * calls. 434178825Sdfr */ 435178825Sdfr /* 436178825Sdfr * First determine if this is an Intel processor which claims 437178825Sdfr * to have hyperthreading support. 438178825Sdfr */ 439178825Sdfr if ((cpu_feature & CPUID_HTT) && 440178825Sdfr (strcmp(cpu_vendor, "GenuineIntel") == 0)) { 441178825Sdfr /* 442178825Sdfr * If the "deterministic cache parameters" cpuid calls 443178825Sdfr * are available, use them. 444178825Sdfr */ 445178825Sdfr if (cpu_high >= 4) { 446178825Sdfr /* Ask the processor about the L1 cache. */ 447178825Sdfr for (i = 0; i < 1; i++) { 448178825Sdfr cpuid_count(4, i, p); 449178825Sdfr threads_per_cache = ((p[0] & 0x3ffc000) >> 14) + 1; 450178825Sdfr if (hyperthreading_cpus < threads_per_cache) 451178825Sdfr hyperthreading_cpus = threads_per_cache; 452178825Sdfr if ((p[0] & 0x1f) == 0) 45355682Smarkm break; 45455682Smarkm } 45555682Smarkm } 45655682Smarkm 45755682Smarkm /* 458178825Sdfr * If the deterministic cache parameters are not 459178825Sdfr * available, or if no caches were reported to exist, 460178825Sdfr * just accept what the HTT flag indicated. 461178825Sdfr */ 462178825Sdfr if (hyperthreading_cpus == 0) 463178825Sdfr hyperthreading_cpus = logical_cpus; 464178825Sdfr } 465178825Sdfr 466178825Sdfr set_interrupt_apic_ids(); 467178825Sdfr} 468233294Sstas 469233294Sstas 470233294Sstas/* 471178825Sdfr * Print various information about the SMP system hardware and setup. 472178825Sdfr */ 473178825Sdfrvoid 474234027Sstascpu_mp_announce(void) 475234027Sstas{ 476178825Sdfr int i, x; 477178825Sdfr 478178825Sdfr /* List CPUs */ 479178825Sdfr printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id); 480178825Sdfr for (i = 1, x = 0; x < MAXCPU; x++) { 481178825Sdfr if (!cpu_info[x].cpu_present || cpu_info[x].cpu_bsp) 482178825Sdfr continue; 483178825Sdfr if (cpu_info[x].cpu_disabled) 484178825Sdfr printf(" cpu (AP): APIC ID: %2d (disabled)\n", x); 485178825Sdfr else { 486233294Sstas KASSERT(i < mp_ncpus, 487233294Sstas ("mp_ncpus and actual cpus are out of whack")); 488178825Sdfr printf(" cpu%d (AP): APIC ID: %2d\n", i++, x); 489178825Sdfr } 490178825Sdfr } 491178825Sdfr} 492178825Sdfr 493233294Sstas/* 494233294Sstas * AP CPU's call this to initialize themselves. 495233294Sstas */ 496178825Sdfrvoid 497178825Sdfrinit_secondary(void) 498178825Sdfr{ 499178825Sdfr vm_offset_t addr; 500178825Sdfr int gsel_tss; 501178825Sdfr int x, myid; 502178825Sdfr u_int cr0; 503178825Sdfr 504178825Sdfr /* bootAP is set in start_ap() to our ID. */ 505178825Sdfr myid = bootAP; 506178825Sdfr gdt_segs[GPRIV_SEL].ssd_base = (int) &SMP_prvspace[myid]; 507233294Sstas gdt_segs[GPROC0_SEL].ssd_base = 508233294Sstas (int) &SMP_prvspace[myid].pcpu.pc_common_tss; 509233294Sstas SMP_prvspace[myid].pcpu.pc_prvspace = 510178825Sdfr &SMP_prvspace[myid].pcpu; 511178825Sdfr 51255682Smarkm for (x = 0; x < NGDT; x++) { 513 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd); 514 } 515 516 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 517 r_gdt.rd_base = (int) &gdt[myid * NGDT]; 518 lgdt(&r_gdt); /* does magic intra-segment return */ 519 520 lidt(&r_idt); 521 522 lldt(_default_ldt); 523 PCPU_SET(currentldt, _default_ldt); 524 525 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 526 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS; 527 PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */ 528 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL)); 529 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16); 530 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd); 531 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt)); 532 ltr(gsel_tss); 533 534 PCPU_SET(fsgs_gdt, &gdt[myid * NGDT + GUFS_SEL].sd); 535 536 /* 537 * Set to a known state: 538 * Set by mpboot.s: CR0_PG, CR0_PE 539 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM 540 */ 541 cr0 = rcr0(); 542 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM); 543 load_cr0(cr0); 544 CHECK_WRITE(0x38, 5); 545 546 /* Disable local APIC just to be sure. */ 547 lapic_disable(); 548 549 /* signal our startup to the BSP. */ 550 mp_naps++; 551 CHECK_WRITE(0x39, 6); 552 553 /* Spin until the BSP releases the AP's. */ 554 while (!aps_ready) 555 ia32_pause(); 556 557 /* BSP may have changed PTD while we were waiting */ 558 invltlb(); 559 for (addr = 0; addr < NKPT * NBPDR - 1; addr += PAGE_SIZE) 560 invlpg(addr); 561 562#if defined(I586_CPU) && !defined(NO_F00F_HACK) 563 lidt(&r_idt); 564#endif 565 566 /* Initialize the PAT MSR if present. */ 567 pmap_init_pat(); 568 569 /* set up CPU registers and state */ 570 cpu_setregs(); 571 572 /* set up FPU state on the AP */ 573 npxinit(__INITIAL_NPXCW__); 574 575 /* set up SSE registers */ 576 enable_sse(); 577 578 /* A quick check from sanity claus */ 579 if (PCPU_GET(apic_id) != lapic_id()) { 580 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid)); 581 printf("SMP: actual apic_id = %d\n", lapic_id()); 582 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id)); 583 printf("PTD[MPPTDI] = %#jx\n", (uintmax_t)PTD[MPPTDI]); 584 panic("cpuid mismatch! boom!!"); 585 } 586 587 /* Initialize curthread. */ 588 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread")); 589 PCPU_SET(curthread, PCPU_GET(idlethread)); 590 591 mtx_lock_spin(&ap_boot_mtx); 592 593 /* Init local apic for irq's */ 594 lapic_setup(); 595 596 /* Set memory range attributes for this CPU to match the BSP */ 597 mem_range_AP_init(); 598 599 smp_cpus++; 600 601 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", PCPU_GET(cpuid)); 602 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid)); 603 604 /* Determine if we are a logical CPU. */ 605 if (logical_cpus > 1 && PCPU_GET(apic_id) % logical_cpus != 0) 606 logical_cpus_mask |= PCPU_GET(cpumask); 607 608 /* Determine if we are a hyperthread. */ 609 if (hyperthreading_cpus > 1 && 610 PCPU_GET(apic_id) % hyperthreading_cpus != 0) 611 hyperthreading_cpus_mask |= PCPU_GET(cpumask); 612 613 /* Build our map of 'other' CPUs. */ 614 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 615 616 if (bootverbose) 617 lapic_dump("AP"); 618 619 if (smp_cpus == mp_ncpus) { 620 /* enable IPI's, tlb shootdown, freezes etc */ 621 atomic_store_rel_int(&smp_started, 1); 622 smp_active = 1; /* historic */ 623 } 624 625 mtx_unlock_spin(&ap_boot_mtx); 626 627 /* wait until all the AP's are up */ 628 while (smp_started == 0) 629 ia32_pause(); 630 631 /* ok, now grab sched_lock and enter the scheduler */ 632 mtx_lock_spin(&sched_lock); 633 634 /* 635 * Correct spinlock nesting. The idle thread context that we are 636 * borrowing was created so that it would start out with a single 637 * spin lock (sched_lock) held in fork_trampoline(). Since we've 638 * explicitly acquired locks in this function, the nesting count 639 * is now 2 rather than 1. Since we are nested, calling 640 * spinlock_exit() will simply adjust the counts without allowing 641 * spin lock using code to interrupt us. 642 */ 643 spinlock_exit(); 644 KASSERT(curthread->td_md.md_spinlock_count == 1, ("invalid count")); 645 646 PCPU_SET(switchtime, cpu_ticks()); 647 PCPU_SET(switchticks, ticks); 648 649 cpu_throw(NULL, choosethread()); /* doesn't return */ 650 651 panic("scheduler returned us to %s", __func__); 652 /* NOTREACHED */ 653} 654 655/******************************************************************* 656 * local functions and data 657 */ 658 659/* 660 * We tell the I/O APIC code about all the CPUs we want to receive 661 * interrupts. If we don't want certain CPUs to receive IRQs we 662 * can simply not tell the I/O APIC code about them in this function. 663 * We also do not tell it about the BSP since it tells itself about 664 * the BSP internally to work with UP kernels and on UP machines. 665 */ 666static void 667set_interrupt_apic_ids(void) 668{ 669 u_int apic_id; 670 671 for (apic_id = 0; apic_id < MAXCPU; apic_id++) { 672 if (!cpu_info[apic_id].cpu_present) 673 continue; 674 if (cpu_info[apic_id].cpu_bsp) 675 continue; 676 677 /* Don't let hyperthreads service interrupts. */ 678 if (hyperthreading_cpus > 1 && 679 apic_id % hyperthreading_cpus != 0) 680 continue; 681 682 intr_add_cpu(apic_id); 683 } 684} 685 686/* 687 * start each AP in our list 688 */ 689static int 690start_all_aps(void) 691{ 692#ifndef PC98 693 u_char mpbiosreason; 694#endif 695 struct pcpu *pc; 696 char *stack; 697 uintptr_t kptbase; 698 u_int32_t mpbioswarmvec; 699 int apic_id, cpu, i, pg; 700 701 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); 702 703 /* install the AP 1st level boot code */ 704 install_ap_tramp(); 705 706 /* save the current value of the warm-start vector */ 707 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF); 708#ifndef PC98 709 outb(CMOS_REG, BIOS_RESET); 710 mpbiosreason = inb(CMOS_DATA); 711#endif 712 713 /* set up temporary P==V mapping for AP boot */ 714 /* XXX this is a hack, we should boot the AP on its own stack/PTD */ 715 kptbase = (uintptr_t)(void *)KPTphys; 716 for (i = 0; i < NKPT; i++) 717 PTD[i] = (pd_entry_t)(PG_V | PG_RW | 718 ((kptbase + i * PAGE_SIZE) & PG_FRAME)); 719 invltlb(); 720 721 /* start each AP */ 722 for (cpu = 0, apic_id = 0; apic_id < MAXCPU; apic_id++) { 723 724 /* Ignore non-existent CPUs and the BSP. */ 725 if (!cpu_info[apic_id].cpu_present || 726 cpu_info[apic_id].cpu_bsp) 727 continue; 728 729 /* Don't use this CPU if it has been disabled by a tunable. */ 730 if (resource_disabled("lapic", apic_id)) { 731 cpu_info[apic_id].cpu_disabled = 1; 732 mp_ncpus--; 733 continue; 734 } 735 736 cpu++; 737 738 /* save APIC ID for this logical ID */ 739 cpu_apic_ids[cpu] = apic_id; 740 741 /* first page of AP's private space */ 742 pg = cpu * i386_btop(sizeof(struct privatespace)); 743 744 /* allocate a new private data page */ 745 pc = (struct pcpu *)kmem_alloc(kernel_map, PAGE_SIZE); 746 747 /* wire it into the private page table page */ 748 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys(pc)); 749 750 /* allocate and set up an idle stack data page */ 751 stack = (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE); /* XXXKSE */ 752 for (i = 0; i < KSTACK_PAGES; i++) 753 SMPpt[pg + 1 + i] = (pt_entry_t) 754 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 755 756 /* prime data page for it to use */ 757 pcpu_init(pc, cpu, sizeof(struct pcpu)); 758 pc->pc_apic_id = apic_id; 759 760 /* setup a vector to our boot code */ 761 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 762 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4); 763#ifndef PC98 764 outb(CMOS_REG, BIOS_RESET); 765 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 766#endif 767 768 bootSTK = &SMP_prvspace[cpu].idlekstack[KSTACK_PAGES * 769 PAGE_SIZE]; 770 bootAP = cpu; 771 772 /* attempt to start the Application Processor */ 773 CHECK_INIT(99); /* setup checkpoints */ 774 if (!start_ap(apic_id)) { 775 printf("AP #%d (PHY# %d) failed!\n", cpu, apic_id); 776 CHECK_PRINT("trace"); /* show checkpoints */ 777 /* better panic as the AP may be running loose */ 778 printf("panic y/n? [y] "); 779 if (cngetc() != 'n') 780 panic("bye-bye"); 781 } 782 CHECK_PRINT("trace"); /* show checkpoints */ 783 784 all_cpus |= (1 << cpu); /* record AP in CPU map */ 785 } 786 787 /* build our map of 'other' CPUs */ 788 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 789 790 /* restore the warmstart vector */ 791 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec; 792 793#ifndef PC98 794 outb(CMOS_REG, BIOS_RESET); 795 outb(CMOS_DATA, mpbiosreason); 796#endif 797 798 /* 799 * Set up the idle context for the BSP. Similar to above except 800 * that some was done by locore, some by pmap.c and some is implicit 801 * because the BSP is cpu#0 and the page is initially zero and also 802 * because we can refer to variables by name on the BSP.. 803 */ 804 805 /* Allocate and setup BSP idle stack */ 806 stack = (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE); 807 for (i = 0; i < KSTACK_PAGES; i++) 808 SMPpt[1 + i] = (pt_entry_t) 809 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 810 811 for (i = 0; i < NKPT; i++) 812 PTD[i] = 0; 813 pmap_invalidate_range(kernel_pmap, 0, NKPT * NBPDR - 1); 814 815 /* number of APs actually started */ 816 return mp_naps; 817} 818 819/* 820 * load the 1st level AP boot code into base memory. 821 */ 822 823/* targets for relocation */ 824extern void bigJump(void); 825extern void bootCodeSeg(void); 826extern void bootDataSeg(void); 827extern void MPentry(void); 828extern u_int MP_GDT; 829extern u_int mp_gdtbase; 830 831static void 832install_ap_tramp(void) 833{ 834 int x; 835 int size = *(int *) ((u_long) & bootMP_size); 836 vm_offset_t va = boot_address + KERNBASE; 837 u_char *src = (u_char *) ((u_long) bootMP); 838 u_char *dst = (u_char *) va; 839 u_int boot_base = (u_int) bootMP; 840 u_int8_t *dst8; 841 u_int16_t *dst16; 842 u_int32_t *dst32; 843 844 KASSERT (size <= PAGE_SIZE, 845 ("'size' do not fit into PAGE_SIZE, as expected.")); 846 pmap_kenter(va, boot_address); 847 pmap_invalidate_page (kernel_pmap, va); 848 for (x = 0; x < size; ++x) 849 *dst++ = *src++; 850 851 /* 852 * modify addresses in code we just moved to basemem. unfortunately we 853 * need fairly detailed info about mpboot.s for this to work. changes 854 * to mpboot.s might require changes here. 855 */ 856 857 /* boot code is located in KERNEL space */ 858 dst = (u_char *) va; 859 860 /* modify the lgdt arg */ 861 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 862 *dst32 = boot_address + ((u_int) & MP_GDT - boot_base); 863 864 /* modify the ljmp target for MPentry() */ 865 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 866 *dst32 = ((u_int) MPentry - KERNBASE); 867 868 /* modify the target for boot code segment */ 869 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 870 dst8 = (u_int8_t *) (dst16 + 1); 871 *dst16 = (u_int) boot_address & 0xffff; 872 *dst8 = ((u_int) boot_address >> 16) & 0xff; 873 874 /* modify the target for boot data segment */ 875 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 876 dst8 = (u_int8_t *) (dst16 + 1); 877 *dst16 = (u_int) boot_address & 0xffff; 878 *dst8 = ((u_int) boot_address >> 16) & 0xff; 879} 880 881/* 882 * This function starts the AP (application processor) identified 883 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 884 * to accomplish this. This is necessary because of the nuances 885 * of the different hardware we might encounter. It isn't pretty, 886 * but it seems to work. 887 */ 888static int 889start_ap(int apic_id) 890{ 891 int vector, ms; 892 int cpus; 893 894 /* calculate the vector */ 895 vector = (boot_address >> 12) & 0xff; 896 897 /* used as a watchpoint to signal AP startup */ 898 cpus = mp_naps; 899 900 /* 901 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 902 * and running the target CPU. OR this INIT IPI might be latched (P5 903 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 904 * ignored. 905 */ 906 907 /* do an INIT IPI: assert RESET */ 908 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 909 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id); 910 911 /* wait for pending status end */ 912 lapic_ipi_wait(-1); 913 914 /* do an INIT IPI: deassert RESET */ 915 lapic_ipi_raw(APIC_DEST_ALLESELF | APIC_TRIGMOD_LEVEL | 916 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, 0); 917 918 /* wait for pending status end */ 919 DELAY(10000); /* wait ~10mS */ 920 lapic_ipi_wait(-1); 921 922 /* 923 * next we do a STARTUP IPI: the previous INIT IPI might still be 924 * latched, (P5 bug) this 1st STARTUP would then terminate 925 * immediately, and the previously started INIT IPI would continue. OR 926 * the previous INIT IPI has already run. and this STARTUP IPI will 927 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 928 * will run. 929 */ 930 931 /* do a STARTUP IPI */ 932 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 933 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 934 vector, apic_id); 935 lapic_ipi_wait(-1); 936 DELAY(200); /* wait ~200uS */ 937 938 /* 939 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 940 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 941 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 942 * recognized after hardware RESET or INIT IPI. 943 */ 944 945 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 946 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 947 vector, apic_id); 948 lapic_ipi_wait(-1); 949 DELAY(200); /* wait ~200uS */ 950 951 /* Wait up to 5 seconds for it to start. */ 952 for (ms = 0; ms < 5000; ms++) { 953 if (mp_naps > cpus) 954 return 1; /* return SUCCESS */ 955 DELAY(1000); 956 } 957 return 0; /* return FAILURE */ 958} 959 960#ifdef COUNT_XINVLTLB_HITS 961u_int xhits_gbl[MAXCPU]; 962u_int xhits_pg[MAXCPU]; 963u_int xhits_rng[MAXCPU]; 964SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, ""); 965SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl, 966 sizeof(xhits_gbl), "IU", ""); 967SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg, 968 sizeof(xhits_pg), "IU", ""); 969SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng, 970 sizeof(xhits_rng), "IU", ""); 971 972u_int ipi_global; 973u_int ipi_page; 974u_int ipi_range; 975u_int ipi_range_size; 976SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, ""); 977SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, ""); 978SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, ""); 979SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size, 980 0, ""); 981 982u_int ipi_masked_global; 983u_int ipi_masked_page; 984u_int ipi_masked_range; 985u_int ipi_masked_range_size; 986SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW, 987 &ipi_masked_global, 0, ""); 988SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW, 989 &ipi_masked_page, 0, ""); 990SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW, 991 &ipi_masked_range, 0, ""); 992SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW, 993 &ipi_masked_range_size, 0, ""); 994#endif /* COUNT_XINVLTLB_HITS */ 995 996/* 997 * Flush the TLB on all other CPU's 998 */ 999static void 1000smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2) 1001{ 1002 u_int ncpu; 1003 1004 ncpu = mp_ncpus - 1; /* does not shootdown self */ 1005 if (ncpu < 1) 1006 return; /* no other cpus */ 1007 mtx_assert(&smp_ipi_mtx, MA_OWNED); 1008 smp_tlb_addr1 = addr1; 1009 smp_tlb_addr2 = addr2; 1010 atomic_store_rel_int(&smp_tlb_wait, 0); 1011 ipi_all_but_self(vector); 1012 while (smp_tlb_wait < ncpu) 1013 ia32_pause(); 1014} 1015 1016static void 1017smp_targeted_tlb_shootdown(u_int mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2) 1018{ 1019 int ncpu, othercpus; 1020 1021 othercpus = mp_ncpus - 1; 1022 if (mask == (u_int)-1) { 1023 ncpu = othercpus; 1024 if (ncpu < 1) 1025 return; 1026 } else { 1027 mask &= ~PCPU_GET(cpumask); 1028 if (mask == 0) 1029 return; 1030 ncpu = bitcount32(mask); 1031 if (ncpu > othercpus) { 1032 /* XXX this should be a panic offence */ 1033 printf("SMP: tlb shootdown to %d other cpus (only have %d)\n", 1034 ncpu, othercpus); 1035 ncpu = othercpus; 1036 } 1037 /* XXX should be a panic, implied by mask == 0 above */ 1038 if (ncpu < 1) 1039 return; 1040 } 1041 mtx_assert(&smp_ipi_mtx, MA_OWNED); 1042 smp_tlb_addr1 = addr1; 1043 smp_tlb_addr2 = addr2; 1044 atomic_store_rel_int(&smp_tlb_wait, 0); 1045 if (mask == (u_int)-1) 1046 ipi_all_but_self(vector); 1047 else 1048 ipi_selected(mask, vector); 1049 while (smp_tlb_wait < ncpu) 1050 ia32_pause(); 1051} 1052 1053void 1054smp_cache_flush(void) 1055{ 1056 1057 if (smp_started) 1058 smp_tlb_shootdown(IPI_INVLCACHE, 0, 0); 1059} 1060 1061void 1062smp_invltlb(void) 1063{ 1064 1065 if (smp_started) { 1066 smp_tlb_shootdown(IPI_INVLTLB, 0, 0); 1067#ifdef COUNT_XINVLTLB_HITS 1068 ipi_global++; 1069#endif 1070 } 1071} 1072 1073void 1074smp_invlpg(vm_offset_t addr) 1075{ 1076 1077 if (smp_started) { 1078 smp_tlb_shootdown(IPI_INVLPG, addr, 0); 1079#ifdef COUNT_XINVLTLB_HITS 1080 ipi_page++; 1081#endif 1082 } 1083} 1084 1085void 1086smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2) 1087{ 1088 1089 if (smp_started) { 1090 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2); 1091#ifdef COUNT_XINVLTLB_HITS 1092 ipi_range++; 1093 ipi_range_size += (addr2 - addr1) / PAGE_SIZE; 1094#endif 1095 } 1096} 1097 1098void 1099smp_masked_invltlb(u_int mask) 1100{ 1101 1102 if (smp_started) { 1103 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0); 1104#ifdef COUNT_XINVLTLB_HITS 1105 ipi_masked_global++; 1106#endif 1107 } 1108} 1109 1110void 1111smp_masked_invlpg(u_int mask, vm_offset_t addr) 1112{ 1113 1114 if (smp_started) { 1115 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0); 1116#ifdef COUNT_XINVLTLB_HITS 1117 ipi_masked_page++; 1118#endif 1119 } 1120} 1121 1122void 1123smp_masked_invlpg_range(u_int mask, vm_offset_t addr1, vm_offset_t addr2) 1124{ 1125 1126 if (smp_started) { 1127 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2); 1128#ifdef COUNT_XINVLTLB_HITS 1129 ipi_masked_range++; 1130 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE; 1131#endif 1132 } 1133} 1134 1135void 1136ipi_bitmap_handler(struct trapframe frame) 1137{ 1138 int cpu = PCPU_GET(cpuid); 1139 u_int ipi_bitmap; 1140 1141 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]); 1142 1143#ifdef IPI_PREEMPTION 1144 if (ipi_bitmap & IPI_PREEMPT) { 1145#ifdef COUNT_IPIS 1146 *ipi_preempt_counts[cpu]++; 1147#endif 1148 mtx_lock_spin(&sched_lock); 1149 /* Don't preempt the idle thread */ 1150 if (curthread->td_priority < PRI_MIN_IDLE) { 1151 struct thread *running_thread = curthread; 1152 if (running_thread->td_critnest > 1) 1153 running_thread->td_owepreempt = 1; 1154 else 1155 mi_switch(SW_INVOL | SW_PREEMPT, NULL); 1156 } 1157 mtx_unlock_spin(&sched_lock); 1158 } 1159#endif 1160 1161 if (ipi_bitmap & IPI_AST) { 1162#ifdef COUNT_IPIS 1163 *ipi_ast_counts[cpu]++; 1164#endif 1165 /* Nothing to do for AST */ 1166 } 1167} 1168 1169/* 1170 * send an IPI to a set of cpus. 1171 */ 1172void 1173ipi_selected(u_int32_t cpus, u_int ipi) 1174{ 1175 int cpu; 1176 u_int bitmap = 0; 1177 u_int old_pending; 1178 u_int new_pending; 1179 1180 if (IPI_IS_BITMAPED(ipi)) { 1181 bitmap = 1 << ipi; 1182 ipi = IPI_BITMAP_VECTOR; 1183 } 1184 1185#ifdef STOP_NMI 1186 if (ipi == IPI_STOP && stop_cpus_with_nmi) { 1187 ipi_nmi_selected(cpus); 1188 return; 1189 } 1190#endif 1191 CTR3(KTR_SMP, "%s: cpus: %x ipi: %x", __func__, cpus, ipi); 1192 while ((cpu = ffs(cpus)) != 0) { 1193 cpu--; 1194 cpus &= ~(1 << cpu); 1195 1196 KASSERT(cpu_apic_ids[cpu] != -1, 1197 ("IPI to non-existent CPU %d", cpu)); 1198 1199 if (bitmap) { 1200 do { 1201 old_pending = cpu_ipi_pending[cpu]; 1202 new_pending = old_pending | bitmap; 1203 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu],old_pending, new_pending)); 1204 1205 if (old_pending) 1206 continue; 1207 } 1208 1209 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]); 1210 } 1211 1212} 1213 1214/* 1215 * send an IPI INTerrupt containing 'vector' to all CPUs, including myself 1216 */ 1217void 1218ipi_all(u_int ipi) 1219{ 1220 1221 if (IPI_IS_BITMAPED(ipi) || (ipi == IPI_STOP && stop_cpus_with_nmi)) { 1222 ipi_selected(all_cpus, ipi); 1223 return; 1224 } 1225 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1226 lapic_ipi_vectored(ipi, APIC_IPI_DEST_ALL); 1227} 1228 1229/* 1230 * send an IPI to all CPUs EXCEPT myself 1231 */ 1232void 1233ipi_all_but_self(u_int ipi) 1234{ 1235 1236 if (IPI_IS_BITMAPED(ipi) || (ipi == IPI_STOP && stop_cpus_with_nmi)) { 1237 ipi_selected(PCPU_GET(other_cpus), ipi); 1238 return; 1239 } 1240 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1241 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS); 1242} 1243 1244/* 1245 * send an IPI to myself 1246 */ 1247void 1248ipi_self(u_int ipi) 1249{ 1250 1251 if (IPI_IS_BITMAPED(ipi) || (ipi == IPI_STOP && stop_cpus_with_nmi)) { 1252 ipi_selected(PCPU_GET(cpumask), ipi); 1253 return; 1254 } 1255 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1256 lapic_ipi_vectored(ipi, APIC_IPI_DEST_SELF); 1257} 1258 1259#ifdef STOP_NMI 1260/* 1261 * send NMI IPI to selected CPUs 1262 */ 1263 1264#define BEFORE_SPIN 1000000 1265 1266void 1267ipi_nmi_selected(u_int32_t cpus) 1268{ 1269 int cpu; 1270 register_t icrlo; 1271 1272 icrlo = APIC_DELMODE_NMI | APIC_DESTMODE_PHY | APIC_LEVEL_ASSERT 1273 | APIC_TRIGMOD_EDGE; 1274 1275 CTR2(KTR_SMP, "%s: cpus: %x nmi", __func__, cpus); 1276 1277 atomic_set_int(&ipi_nmi_pending, cpus); 1278 1279 while ((cpu = ffs(cpus)) != 0) { 1280 cpu--; 1281 cpus &= ~(1 << cpu); 1282 1283 KASSERT(cpu_apic_ids[cpu] != -1, 1284 ("IPI NMI to non-existent CPU %d", cpu)); 1285 1286 /* Wait for an earlier IPI to finish. */ 1287 if (!lapic_ipi_wait(BEFORE_SPIN)) 1288 panic("ipi_nmi_selected: previous IPI has not cleared"); 1289 1290 lapic_ipi_raw(icrlo, cpu_apic_ids[cpu]); 1291 } 1292} 1293 1294int 1295ipi_nmi_handler(void) 1296{ 1297 int cpumask = PCPU_GET(cpumask); 1298 1299 if (!(ipi_nmi_pending & cpumask)) 1300 return 1; 1301 1302 atomic_clear_int(&ipi_nmi_pending, cpumask); 1303 cpustop_handler(); 1304 return 0; 1305} 1306 1307#endif /* STOP_NMI */ 1308 1309/* 1310 * Handle an IPI_STOP by saving our current context and spinning until we 1311 * are resumed. 1312 */ 1313void 1314cpustop_handler(void) 1315{ 1316 int cpu = PCPU_GET(cpuid); 1317 int cpumask = PCPU_GET(cpumask); 1318 1319 savectx(&stoppcbs[cpu]); 1320 1321 /* Indicate that we are stopped */ 1322 atomic_set_int(&stopped_cpus, cpumask); 1323 1324 /* Wait for restart */ 1325 while (!(started_cpus & cpumask)) 1326 ia32_pause(); 1327 1328 atomic_clear_int(&started_cpus, cpumask); 1329 atomic_clear_int(&stopped_cpus, cpumask); 1330 1331 if (cpu == 0 && cpustop_restartfunc != NULL) { 1332 cpustop_restartfunc(); 1333 cpustop_restartfunc = NULL; 1334 } 1335} 1336 1337/* 1338 * This is called once the rest of the system is up and running and we're 1339 * ready to let the AP's out of the pen. 1340 */ 1341static void 1342release_aps(void *dummy __unused) 1343{ 1344 1345 if (mp_ncpus == 1) 1346 return; 1347 mtx_lock_spin(&sched_lock); 1348 atomic_store_rel_int(&aps_ready, 1); 1349 while (smp_started == 0) 1350 ia32_pause(); 1351 mtx_unlock_spin(&sched_lock); 1352} 1353SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL); 1354 1355static int 1356sysctl_hlt_cpus(SYSCTL_HANDLER_ARGS) 1357{ 1358 u_int mask; 1359 int error; 1360 1361 mask = hlt_cpus_mask; 1362 error = sysctl_handle_int(oidp, &mask, 0, req); 1363 if (error || !req->newptr) 1364 return (error); 1365 1366 if (logical_cpus_mask != 0 && 1367 (mask & logical_cpus_mask) == logical_cpus_mask) 1368 hlt_logical_cpus = 1; 1369 else 1370 hlt_logical_cpus = 0; 1371 1372 if (! hyperthreading_allowed) 1373 mask |= hyperthreading_cpus_mask; 1374 1375 if ((mask & all_cpus) == all_cpus) 1376 mask &= ~(1<<0); 1377 hlt_cpus_mask = mask; 1378 return (error); 1379} 1380SYSCTL_PROC(_machdep, OID_AUTO, hlt_cpus, CTLTYPE_INT|CTLFLAG_RW, 1381 0, 0, sysctl_hlt_cpus, "IU", 1382 "Bitmap of CPUs to halt. 101 (binary) will halt CPUs 0 and 2."); 1383 1384static int 1385sysctl_hlt_logical_cpus(SYSCTL_HANDLER_ARGS) 1386{ 1387 int disable, error; 1388 1389 disable = hlt_logical_cpus; 1390 error = sysctl_handle_int(oidp, &disable, 0, req); 1391 if (error || !req->newptr) 1392 return (error); 1393 1394 if (disable) 1395 hlt_cpus_mask |= logical_cpus_mask; 1396 else 1397 hlt_cpus_mask &= ~logical_cpus_mask; 1398 1399 if (! hyperthreading_allowed) 1400 hlt_cpus_mask |= hyperthreading_cpus_mask; 1401 1402 if ((hlt_cpus_mask & all_cpus) == all_cpus) 1403 hlt_cpus_mask &= ~(1<<0); 1404 1405 hlt_logical_cpus = disable; 1406 return (error); 1407} 1408 1409static int 1410sysctl_hyperthreading_allowed(SYSCTL_HANDLER_ARGS) 1411{ 1412 int allowed, error; 1413 1414 allowed = hyperthreading_allowed; 1415 error = sysctl_handle_int(oidp, &allowed, 0, req); 1416 if (error || !req->newptr) 1417 return (error); 1418 1419 if (allowed) 1420 hlt_cpus_mask &= ~hyperthreading_cpus_mask; 1421 else 1422 hlt_cpus_mask |= hyperthreading_cpus_mask; 1423 1424 if (logical_cpus_mask != 0 && 1425 (hlt_cpus_mask & logical_cpus_mask) == logical_cpus_mask) 1426 hlt_logical_cpus = 1; 1427 else 1428 hlt_logical_cpus = 0; 1429 1430 if ((hlt_cpus_mask & all_cpus) == all_cpus) 1431 hlt_cpus_mask &= ~(1<<0); 1432 1433 hyperthreading_allowed = allowed; 1434 return (error); 1435} 1436 1437static void 1438cpu_hlt_setup(void *dummy __unused) 1439{ 1440 1441 if (logical_cpus_mask != 0) { 1442 TUNABLE_INT_FETCH("machdep.hlt_logical_cpus", 1443 &hlt_logical_cpus); 1444 sysctl_ctx_init(&logical_cpu_clist); 1445 SYSCTL_ADD_PROC(&logical_cpu_clist, 1446 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1447 "hlt_logical_cpus", CTLTYPE_INT|CTLFLAG_RW, 0, 0, 1448 sysctl_hlt_logical_cpus, "IU", ""); 1449 SYSCTL_ADD_UINT(&logical_cpu_clist, 1450 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1451 "logical_cpus_mask", CTLTYPE_INT|CTLFLAG_RD, 1452 &logical_cpus_mask, 0, ""); 1453 1454 if (hlt_logical_cpus) 1455 hlt_cpus_mask |= logical_cpus_mask; 1456 1457 /* 1458 * If necessary for security purposes, force 1459 * hyperthreading off, regardless of the value 1460 * of hlt_logical_cpus. 1461 */ 1462 if (hyperthreading_cpus_mask) { 1463 TUNABLE_INT_FETCH("machdep.hyperthreading_allowed", 1464 &hyperthreading_allowed); 1465 SYSCTL_ADD_PROC(&logical_cpu_clist, 1466 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1467 "hyperthreading_allowed", CTLTYPE_INT|CTLFLAG_RW, 1468 0, 0, sysctl_hyperthreading_allowed, "IU", ""); 1469 if (! hyperthreading_allowed) 1470 hlt_cpus_mask |= hyperthreading_cpus_mask; 1471 } 1472 } 1473} 1474SYSINIT(cpu_hlt, SI_SUB_SMP, SI_ORDER_ANY, cpu_hlt_setup, NULL); 1475 1476int 1477mp_grab_cpu_hlt(void) 1478{ 1479 u_int mask = PCPU_GET(cpumask); 1480#ifdef MP_WATCHDOG 1481 u_int cpuid = PCPU_GET(cpuid); 1482#endif 1483 int retval; 1484 1485#ifdef MP_WATCHDOG 1486 ap_watchdog(cpuid); 1487#endif 1488 1489 retval = mask & hlt_cpus_mask; 1490 while (mask & hlt_cpus_mask) 1491 __asm __volatile("sti; hlt" : : : "memory"); 1492 return (retval); 1493} 1494 1495#ifdef COUNT_IPIS 1496/* 1497 * Setup interrupt counters for IPI handlers. 1498 */ 1499static void 1500mp_ipi_intrcnt(void *dummy) 1501{ 1502 char buf[64]; 1503 int i; 1504 1505 for (i = 0; i < mp_maxid; i++) { 1506 if (CPU_ABSENT(i)) 1507 continue; 1508 snprintf(buf, sizeof(buf), "cpu%d: invltlb", i); 1509 intrcnt_add(buf, &ipi_invltlb_counts[i]); 1510 snprintf(buf, sizeof(buf), "cpu%d: invlrng", i); 1511 intrcnt_add(buf, &ipi_invlrng_counts[i]); 1512 snprintf(buf, sizeof(buf), "cpu%d: invlpg", i); 1513 intrcnt_add(buf, &ipi_invlpg_counts[i]); 1514#ifdef IPI_PREEMPTION 1515 snprintf(buf, sizeof(buf), "cpu%d: preempt", i); 1516 intrcnt_add(buf, &ipi_preempt_counts[i]); 1517#endif 1518 snprintf(buf, sizeof(buf), "cpu%d: ast", i); 1519 intrcnt_add(buf, &ipi_ast_counts[i]); 1520 snprintf(buf, sizeof(buf), "cpu%d: rendezvous", i); 1521 intrcnt_add(buf, &ipi_rendezvous_counts[i]); 1522 snprintf(buf, sizeof(buf), "cpu%d: lazypmap", i); 1523 intrcnt_add(buf, &ipi_lazypmap_counts[i]); 1524 } 1525} 1526SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL) 1527#endif 1528