mp_x86.c revision 158007
1/*- 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26#include <sys/cdefs.h> 27__FBSDID("$FreeBSD: head/sys/i386/i386/mp_machdep.c 158007 2006-04-25 00:06:37Z jkim $"); 28 29#include "opt_apic.h" 30#include "opt_cpu.h" 31#include "opt_kstack_pages.h" 32#include "opt_mp_watchdog.h" 33#include "opt_sched.h" 34#include "opt_smp.h" 35 36#if !defined(lint) 37#if !defined(SMP) 38#error How did you get here? 39#endif 40 41#ifndef DEV_APIC 42#error The apic device is required for SMP, add "device apic" to your config file. 43#endif 44#if defined(CPU_DISABLE_CMPXCHG) && !defined(COMPILING_LINT) 45#error SMP not supported with CPU_DISABLE_CMPXCHG 46#endif 47#endif /* not lint */ 48 49#include <sys/param.h> 50#include <sys/systm.h> 51#include <sys/bus.h> 52#include <sys/cons.h> /* cngetc() */ 53#ifdef GPROF 54#include <sys/gmon.h> 55#endif 56#include <sys/kernel.h> 57#include <sys/ktr.h> 58#include <sys/lock.h> 59#include <sys/malloc.h> 60#include <sys/memrange.h> 61#include <sys/mutex.h> 62#include <sys/pcpu.h> 63#include <sys/proc.h> 64#include <sys/smp.h> 65#include <sys/sysctl.h> 66 67#include <vm/vm.h> 68#include <vm/vm_param.h> 69#include <vm/pmap.h> 70#include <vm/vm_kern.h> 71#include <vm/vm_extern.h> 72 73#include <machine/apicreg.h> 74#include <machine/clock.h> 75#include <machine/md_var.h> 76#include <machine/mp_watchdog.h> 77#include <machine/pcb.h> 78#include <machine/smp.h> 79#include <machine/specialreg.h> 80#include <machine/privatespace.h> 81 82#define WARMBOOT_TARGET 0 83#define WARMBOOT_OFF (KERNBASE + 0x0467) 84#define WARMBOOT_SEG (KERNBASE + 0x0469) 85 86#define CMOS_REG (0x70) 87#define CMOS_DATA (0x71) 88#define BIOS_RESET (0x0f) 89#define BIOS_WARM (0x0a) 90 91/* 92 * this code MUST be enabled here and in mpboot.s. 93 * it follows the very early stages of AP boot by placing values in CMOS ram. 94 * it NORMALLY will never be needed and thus the primitive method for enabling. 95 * 96#define CHECK_POINTS 97 */ 98 99#if defined(CHECK_POINTS) && !defined(PC98) 100#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 101#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 102 103#define CHECK_INIT(D); \ 104 CHECK_WRITE(0x34, (D)); \ 105 CHECK_WRITE(0x35, (D)); \ 106 CHECK_WRITE(0x36, (D)); \ 107 CHECK_WRITE(0x37, (D)); \ 108 CHECK_WRITE(0x38, (D)); \ 109 CHECK_WRITE(0x39, (D)); 110 111#define CHECK_PRINT(S); \ 112 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 113 (S), \ 114 CHECK_READ(0x34), \ 115 CHECK_READ(0x35), \ 116 CHECK_READ(0x36), \ 117 CHECK_READ(0x37), \ 118 CHECK_READ(0x38), \ 119 CHECK_READ(0x39)); 120 121#else /* CHECK_POINTS */ 122 123#define CHECK_INIT(D) 124#define CHECK_PRINT(S) 125#define CHECK_WRITE(A, D) 126 127#endif /* CHECK_POINTS */ 128 129/* lock region used by kernel profiling */ 130int mcount_lock; 131 132int mp_naps; /* # of Applications processors */ 133int boot_cpu_id = -1; /* designated BSP */ 134extern int nkpt; 135 136/* 137 * CPU topology map datastructures for HTT. 138 */ 139static struct cpu_group mp_groups[MAXCPU]; 140static struct cpu_top mp_top; 141 142/* AP uses this during bootstrap. Do not staticize. */ 143char *bootSTK; 144static int bootAP; 145 146/* Hotwire a 0->4MB V==P mapping */ 147extern pt_entry_t *KPTphys; 148 149/* SMP page table page */ 150extern pt_entry_t *SMPpt; 151 152struct pcb stoppcbs[MAXCPU]; 153 154/* Variables needed for SMP tlb shootdown. */ 155vm_offset_t smp_tlb_addr1; 156vm_offset_t smp_tlb_addr2; 157volatile int smp_tlb_wait; 158 159#ifdef STOP_NMI 160volatile cpumask_t ipi_nmi_pending; 161 162static void ipi_nmi_selected(u_int32_t cpus); 163#endif 164 165#ifdef COUNT_IPIS 166/* Interrupt counts. */ 167#ifdef IPI_PREEMPTION 168static u_long *ipi_preempt_counts[MAXCPU]; 169#endif 170static u_long *ipi_ast_counts[MAXCPU]; 171u_long *ipi_invltlb_counts[MAXCPU]; 172u_long *ipi_invlrng_counts[MAXCPU]; 173u_long *ipi_invlpg_counts[MAXCPU]; 174u_long *ipi_rendezvous_counts[MAXCPU]; 175u_long *ipi_lazypmap_counts[MAXCPU]; 176#endif 177 178/* 179 * Local data and functions. 180 */ 181 182#ifdef STOP_NMI 183/* 184 * Provide an alternate method of stopping other CPUs. If another CPU has 185 * disabled interrupts the conventional STOP IPI will be blocked. This 186 * NMI-based stop should get through in that case. 187 */ 188static int stop_cpus_with_nmi = 1; 189SYSCTL_INT(_debug, OID_AUTO, stop_cpus_with_nmi, CTLTYPE_INT | CTLFLAG_RW, 190 &stop_cpus_with_nmi, 0, ""); 191TUNABLE_INT("debug.stop_cpus_with_nmi", &stop_cpus_with_nmi); 192#else 193#define stop_cpus_with_nmi 0 194#endif 195 196static u_int logical_cpus; 197 198/* used to hold the AP's until we are ready to release them */ 199static struct mtx ap_boot_mtx; 200 201/* Set to 1 once we're ready to let the APs out of the pen. */ 202static volatile int aps_ready = 0; 203 204/* 205 * Store data from cpu_add() until later in the boot when we actually setup 206 * the APs. 207 */ 208struct cpu_info { 209 int cpu_present:1; 210 int cpu_bsp:1; 211 int cpu_disabled:1; 212} static cpu_info[MAXCPU]; 213static int cpu_apic_ids[MAXCPU]; 214 215/* Holds pending bitmap based IPIs per CPU */ 216static volatile u_int cpu_ipi_pending[MAXCPU]; 217 218static u_int boot_address; 219 220static void set_interrupt_apic_ids(void); 221static int start_all_aps(void); 222static void install_ap_tramp(void); 223static int start_ap(int apic_id); 224static void release_aps(void *dummy); 225 226static int hlt_logical_cpus; 227static u_int hyperthreading_cpus; 228static cpumask_t hyperthreading_cpus_mask; 229static int hyperthreading_allowed = 1; 230static struct sysctl_ctx_list logical_cpu_clist; 231 232static void 233mem_range_AP_init(void) 234{ 235 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP) 236 mem_range_softc.mr_op->initAP(&mem_range_softc); 237} 238 239void 240mp_topology(void) 241{ 242 struct cpu_group *group; 243 u_int regs[4]; 244 int logical_cpus; 245 int apic_id; 246 int groups; 247 int cpu; 248 249 /* Build the smp_topology map. */ 250 /* Nothing to do if there is no HTT support. */ 251 if ((cpu_feature & CPUID_HTT) == 0) 252 return; 253 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 254 if (logical_cpus <= 1) 255 return; 256 /* Nothing to do if reported cores are physical cores. */ 257 if (strcmp(cpu_vendor, "GenuineIntel") == 0 && cpu_high >= 4) { 258 cpuid_count(4, 0, regs); 259 if ((regs[0] & 0x1f) != 0 && 260 logical_cpus <= ((regs[0] >> 26) & 0x3f) + 1) 261 return; 262 } 263 group = &mp_groups[0]; 264 groups = 1; 265 for (cpu = 0, apic_id = 0; apic_id < MAXCPU; apic_id++) { 266 if (!cpu_info[apic_id].cpu_present) 267 continue; 268 /* 269 * If the current group has members and we're not a logical 270 * cpu, create a new group. 271 */ 272 if (group->cg_count != 0 && (apic_id % logical_cpus) == 0) { 273 group++; 274 groups++; 275 } 276 group->cg_count++; 277 group->cg_mask |= 1 << cpu; 278 cpu++; 279 } 280 281 mp_top.ct_count = groups; 282 mp_top.ct_group = mp_groups; 283 smp_topology = &mp_top; 284} 285 286 287/* 288 * Calculate usable address in base memory for AP trampoline code. 289 */ 290u_int 291mp_bootaddress(u_int basemem) 292{ 293 294 boot_address = trunc_page(basemem); /* round down to 4k boundary */ 295 if ((basemem - boot_address) < bootMP_size) 296 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */ 297 298 return boot_address; 299} 300 301void 302cpu_add(u_int apic_id, char boot_cpu) 303{ 304 305 if (apic_id >= MAXCPU) { 306 printf("SMP: CPU %d exceeds maximum CPU %d, ignoring\n", 307 apic_id, MAXCPU - 1); 308 return; 309 } 310 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice", 311 apic_id)); 312 cpu_info[apic_id].cpu_present = 1; 313 if (boot_cpu) { 314 KASSERT(boot_cpu_id == -1, 315 ("CPU %d claims to be BSP, but CPU %d already is", apic_id, 316 boot_cpu_id)); 317 boot_cpu_id = apic_id; 318 cpu_info[apic_id].cpu_bsp = 1; 319 } 320 mp_ncpus++; 321 if (bootverbose) 322 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" : 323 "AP"); 324 325} 326 327void 328cpu_mp_setmaxid(void) 329{ 330 331 mp_maxid = MAXCPU - 1; 332} 333 334int 335cpu_mp_probe(void) 336{ 337 338 /* 339 * Always record BSP in CPU map so that the mbuf init code works 340 * correctly. 341 */ 342 all_cpus = 1; 343 if (mp_ncpus == 0) { 344 /* 345 * No CPUs were found, so this must be a UP system. Setup 346 * the variables to represent a system with a single CPU 347 * with an id of 0. 348 */ 349 mp_ncpus = 1; 350 return (0); 351 } 352 353 /* At least one CPU was found. */ 354 if (mp_ncpus == 1) { 355 /* 356 * One CPU was found, so this must be a UP system with 357 * an I/O APIC. 358 */ 359 return (0); 360 } 361 362 /* At least two CPUs were found. */ 363 return (1); 364} 365 366/* 367 * Initialize the IPI handlers and start up the AP's. 368 */ 369void 370cpu_mp_start(void) 371{ 372 int i; 373 u_int threads_per_cache, p[4]; 374 375 /* Initialize the logical ID to APIC ID table. */ 376 for (i = 0; i < MAXCPU; i++) { 377 cpu_apic_ids[i] = -1; 378 cpu_ipi_pending[i] = 0; 379 } 380 381 /* Install an inter-CPU IPI for TLB invalidation */ 382 setidt(IPI_INVLTLB, IDTVEC(invltlb), 383 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 384 setidt(IPI_INVLPG, IDTVEC(invlpg), 385 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 386 setidt(IPI_INVLRNG, IDTVEC(invlrng), 387 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 388 389 /* Install an inter-CPU IPI for lazy pmap release */ 390 setidt(IPI_LAZYPMAP, IDTVEC(lazypmap), 391 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 392 393 /* Install an inter-CPU IPI for all-CPU rendezvous */ 394 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous), 395 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 396 397 /* Install generic inter-CPU IPI handler */ 398 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler), 399 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 400 401 /* Install an inter-CPU IPI for CPU stop/restart */ 402 setidt(IPI_STOP, IDTVEC(cpustop), 403 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 404 405 406 /* Set boot_cpu_id if needed. */ 407 if (boot_cpu_id == -1) { 408 boot_cpu_id = PCPU_GET(apic_id); 409 cpu_info[boot_cpu_id].cpu_bsp = 1; 410 } else 411 KASSERT(boot_cpu_id == PCPU_GET(apic_id), 412 ("BSP's APIC ID doesn't match boot_cpu_id")); 413 cpu_apic_ids[0] = boot_cpu_id; 414 415 /* Start each Application Processor */ 416 start_all_aps(); 417 418 /* Setup the initial logical CPUs info. */ 419 logical_cpus = logical_cpus_mask = 0; 420 if (cpu_feature & CPUID_HTT) 421 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 422 423 /* 424 * Work out if hyperthreading is *really* enabled. This 425 * is made really ugly by the fact that processors lie: Dual 426 * core processors claim to be hyperthreaded even when they're 427 * not, presumably because they want to be treated the same 428 * way as HTT with respect to per-cpu software licensing. 429 * At the time of writing (May 12, 2005) the only hyperthreaded 430 * cpus are from Intel, and Intel's dual-core processors can be 431 * identified via the "deterministic cache parameters" cpuid 432 * calls. 433 */ 434 /* 435 * First determine if this is an Intel processor which claims 436 * to have hyperthreading support. 437 */ 438 if ((cpu_feature & CPUID_HTT) && 439 (strcmp(cpu_vendor, "GenuineIntel") == 0)) { 440 /* 441 * If the "deterministic cache parameters" cpuid calls 442 * are available, use them. 443 */ 444 if (cpu_high >= 4) { 445 /* Ask the processor about the L1 cache. */ 446 for (i = 0; i < 1; i++) { 447 cpuid_count(4, i, p); 448 threads_per_cache = ((p[0] & 0x3ffc000) >> 14) + 1; 449 if (hyperthreading_cpus < threads_per_cache) 450 hyperthreading_cpus = threads_per_cache; 451 if ((p[0] & 0x1f) == 0) 452 break; 453 } 454 } 455 456 /* 457 * If the deterministic cache parameters are not 458 * available, or if no caches were reported to exist, 459 * just accept what the HTT flag indicated. 460 */ 461 if (hyperthreading_cpus == 0) 462 hyperthreading_cpus = logical_cpus; 463 } 464 465 set_interrupt_apic_ids(); 466} 467 468 469/* 470 * Print various information about the SMP system hardware and setup. 471 */ 472void 473cpu_mp_announce(void) 474{ 475 int i, x; 476 477 /* List CPUs */ 478 printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id); 479 for (i = 1, x = 0; x < MAXCPU; x++) { 480 if (!cpu_info[x].cpu_present || cpu_info[x].cpu_bsp) 481 continue; 482 if (cpu_info[x].cpu_disabled) 483 printf(" cpu (AP): APIC ID: %2d (disabled)\n", x); 484 else { 485 KASSERT(i < mp_ncpus, 486 ("mp_ncpus and actual cpus are out of whack")); 487 printf(" cpu%d (AP): APIC ID: %2d\n", i++, x); 488 } 489 } 490} 491 492/* 493 * AP CPU's call this to initialize themselves. 494 */ 495void 496init_secondary(void) 497{ 498 vm_offset_t addr; 499 int gsel_tss; 500 int x, myid; 501 u_int cr0; 502 503 /* bootAP is set in start_ap() to our ID. */ 504 myid = bootAP; 505 gdt_segs[GPRIV_SEL].ssd_base = (int) &SMP_prvspace[myid]; 506 gdt_segs[GPROC0_SEL].ssd_base = 507 (int) &SMP_prvspace[myid].pcpu.pc_common_tss; 508 SMP_prvspace[myid].pcpu.pc_prvspace = 509 &SMP_prvspace[myid].pcpu; 510 511 for (x = 0; x < NGDT; x++) { 512 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd); 513 } 514 515 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 516 r_gdt.rd_base = (int) &gdt[myid * NGDT]; 517 lgdt(&r_gdt); /* does magic intra-segment return */ 518 519 lidt(&r_idt); 520 521 lldt(_default_ldt); 522 PCPU_SET(currentldt, _default_ldt); 523 524 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 525 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS; 526 PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */ 527 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL)); 528 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16); 529 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd); 530 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt)); 531 ltr(gsel_tss); 532 533 PCPU_SET(fsgs_gdt, &gdt[myid * NGDT + GUFS_SEL].sd); 534 535 /* 536 * Set to a known state: 537 * Set by mpboot.s: CR0_PG, CR0_PE 538 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM 539 */ 540 cr0 = rcr0(); 541 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM); 542 load_cr0(cr0); 543 CHECK_WRITE(0x38, 5); 544 545 /* Disable local APIC just to be sure. */ 546 lapic_disable(); 547 548 /* signal our startup to the BSP. */ 549 mp_naps++; 550 CHECK_WRITE(0x39, 6); 551 552 /* Spin until the BSP releases the AP's. */ 553 while (!aps_ready) 554 ia32_pause(); 555 556 /* BSP may have changed PTD while we were waiting */ 557 invltlb(); 558 for (addr = 0; addr < NKPT * NBPDR - 1; addr += PAGE_SIZE) 559 invlpg(addr); 560 561#if defined(I586_CPU) && !defined(NO_F00F_HACK) 562 lidt(&r_idt); 563#endif 564 565 /* set up CPU registers and state */ 566 cpu_setregs(); 567 568 /* set up FPU state on the AP */ 569 npxinit(__INITIAL_NPXCW__); 570 571 /* set up SSE registers */ 572 enable_sse(); 573 574 /* A quick check from sanity claus */ 575 if (PCPU_GET(apic_id) != lapic_id()) { 576 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid)); 577 printf("SMP: actual apic_id = %d\n", lapic_id()); 578 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id)); 579 printf("PTD[MPPTDI] = %#jx\n", (uintmax_t)PTD[MPPTDI]); 580 panic("cpuid mismatch! boom!!"); 581 } 582 583 /* Initialize curthread. */ 584 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread")); 585 PCPU_SET(curthread, PCPU_GET(idlethread)); 586 587 mtx_lock_spin(&ap_boot_mtx); 588 589 /* Init local apic for irq's */ 590 lapic_setup(); 591 592 /* Set memory range attributes for this CPU to match the BSP */ 593 mem_range_AP_init(); 594 595 smp_cpus++; 596 597 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", PCPU_GET(cpuid)); 598 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid)); 599 600 /* Determine if we are a logical CPU. */ 601 if (logical_cpus > 1 && PCPU_GET(apic_id) % logical_cpus != 0) 602 logical_cpus_mask |= PCPU_GET(cpumask); 603 604 /* Determine if we are a hyperthread. */ 605 if (hyperthreading_cpus > 1 && 606 PCPU_GET(apic_id) % hyperthreading_cpus != 0) 607 hyperthreading_cpus_mask |= PCPU_GET(cpumask); 608 609 /* Build our map of 'other' CPUs. */ 610 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 611 612 if (bootverbose) 613 lapic_dump("AP"); 614 615 if (smp_cpus == mp_ncpus) { 616 /* enable IPI's, tlb shootdown, freezes etc */ 617 atomic_store_rel_int(&smp_started, 1); 618 smp_active = 1; /* historic */ 619 } 620 621 mtx_unlock_spin(&ap_boot_mtx); 622 623 /* wait until all the AP's are up */ 624 while (smp_started == 0) 625 ia32_pause(); 626 627 /* ok, now grab sched_lock and enter the scheduler */ 628 mtx_lock_spin(&sched_lock); 629 630 /* 631 * Correct spinlock nesting. The idle thread context that we are 632 * borrowing was created so that it would start out with a single 633 * spin lock (sched_lock) held in fork_trampoline(). Since we've 634 * explicitly acquired locks in this function, the nesting count 635 * is now 2 rather than 1. Since we are nested, calling 636 * spinlock_exit() will simply adjust the counts without allowing 637 * spin lock using code to interrupt us. 638 */ 639 spinlock_exit(); 640 KASSERT(curthread->td_md.md_spinlock_count == 1, ("invalid count")); 641 642 PCPU_SET(switchtime, cpu_ticks()); 643 PCPU_SET(switchticks, ticks); 644 645 cpu_throw(NULL, choosethread()); /* doesn't return */ 646 647 panic("scheduler returned us to %s", __func__); 648 /* NOTREACHED */ 649} 650 651/******************************************************************* 652 * local functions and data 653 */ 654 655/* 656 * We tell the I/O APIC code about all the CPUs we want to receive 657 * interrupts. If we don't want certain CPUs to receive IRQs we 658 * can simply not tell the I/O APIC code about them in this function. 659 * We also do not tell it about the BSP since it tells itself about 660 * the BSP internally to work with UP kernels and on UP machines. 661 */ 662static void 663set_interrupt_apic_ids(void) 664{ 665 u_int apic_id; 666 667 for (apic_id = 0; apic_id < MAXCPU; apic_id++) { 668 if (!cpu_info[apic_id].cpu_present) 669 continue; 670 if (cpu_info[apic_id].cpu_bsp) 671 continue; 672 673 /* Don't let hyperthreads service interrupts. */ 674 if (hyperthreading_cpus > 1 && 675 apic_id % hyperthreading_cpus != 0) 676 continue; 677 678 intr_add_cpu(apic_id); 679 } 680} 681 682/* 683 * start each AP in our list 684 */ 685static int 686start_all_aps(void) 687{ 688#ifndef PC98 689 u_char mpbiosreason; 690#endif 691 struct pcpu *pc; 692 char *stack; 693 uintptr_t kptbase; 694 u_int32_t mpbioswarmvec; 695 int apic_id, cpu, i, pg; 696 697 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); 698 699 /* install the AP 1st level boot code */ 700 install_ap_tramp(); 701 702 /* save the current value of the warm-start vector */ 703 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF); 704#ifndef PC98 705 outb(CMOS_REG, BIOS_RESET); 706 mpbiosreason = inb(CMOS_DATA); 707#endif 708 709 /* set up temporary P==V mapping for AP boot */ 710 /* XXX this is a hack, we should boot the AP on its own stack/PTD */ 711 kptbase = (uintptr_t)(void *)KPTphys; 712 for (i = 0; i < NKPT; i++) 713 PTD[i] = (pd_entry_t)(PG_V | PG_RW | 714 ((kptbase + i * PAGE_SIZE) & PG_FRAME)); 715 invltlb(); 716 717 /* start each AP */ 718 for (cpu = 0, apic_id = 0; apic_id < MAXCPU; apic_id++) { 719 720 /* Ignore non-existent CPUs and the BSP. */ 721 if (!cpu_info[apic_id].cpu_present || 722 cpu_info[apic_id].cpu_bsp) 723 continue; 724 725 /* Don't use this CPU if it has been disabled by a tunable. */ 726 if (resource_disabled("lapic", apic_id)) { 727 cpu_info[apic_id].cpu_disabled = 1; 728 mp_ncpus--; 729 continue; 730 } 731 732 cpu++; 733 734 /* save APIC ID for this logical ID */ 735 cpu_apic_ids[cpu] = apic_id; 736 737 /* first page of AP's private space */ 738 pg = cpu * i386_btop(sizeof(struct privatespace)); 739 740 /* allocate a new private data page */ 741 pc = (struct pcpu *)kmem_alloc(kernel_map, PAGE_SIZE); 742 743 /* wire it into the private page table page */ 744 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys(pc)); 745 746 /* allocate and set up an idle stack data page */ 747 stack = (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE); /* XXXKSE */ 748 for (i = 0; i < KSTACK_PAGES; i++) 749 SMPpt[pg + 1 + i] = (pt_entry_t) 750 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 751 752 /* prime data page for it to use */ 753 pcpu_init(pc, cpu, sizeof(struct pcpu)); 754 pc->pc_apic_id = apic_id; 755 756 /* setup a vector to our boot code */ 757 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 758 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4); 759#ifndef PC98 760 outb(CMOS_REG, BIOS_RESET); 761 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 762#endif 763 764 bootSTK = &SMP_prvspace[cpu].idlekstack[KSTACK_PAGES * 765 PAGE_SIZE]; 766 bootAP = cpu; 767 768 /* attempt to start the Application Processor */ 769 CHECK_INIT(99); /* setup checkpoints */ 770 if (!start_ap(apic_id)) { 771 printf("AP #%d (PHY# %d) failed!\n", cpu, apic_id); 772 CHECK_PRINT("trace"); /* show checkpoints */ 773 /* better panic as the AP may be running loose */ 774 printf("panic y/n? [y] "); 775 if (cngetc() != 'n') 776 panic("bye-bye"); 777 } 778 CHECK_PRINT("trace"); /* show checkpoints */ 779 780 all_cpus |= (1 << cpu); /* record AP in CPU map */ 781 } 782 783 /* build our map of 'other' CPUs */ 784 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 785 786 /* restore the warmstart vector */ 787 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec; 788 789#ifndef PC98 790 outb(CMOS_REG, BIOS_RESET); 791 outb(CMOS_DATA, mpbiosreason); 792#endif 793 794 /* 795 * Set up the idle context for the BSP. Similar to above except 796 * that some was done by locore, some by pmap.c and some is implicit 797 * because the BSP is cpu#0 and the page is initially zero and also 798 * because we can refer to variables by name on the BSP.. 799 */ 800 801 /* Allocate and setup BSP idle stack */ 802 stack = (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE); 803 for (i = 0; i < KSTACK_PAGES; i++) 804 SMPpt[1 + i] = (pt_entry_t) 805 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 806 807 for (i = 0; i < NKPT; i++) 808 PTD[i] = 0; 809 pmap_invalidate_range(kernel_pmap, 0, NKPT * NBPDR - 1); 810 811 /* number of APs actually started */ 812 return mp_naps; 813} 814 815/* 816 * load the 1st level AP boot code into base memory. 817 */ 818 819/* targets for relocation */ 820extern void bigJump(void); 821extern void bootCodeSeg(void); 822extern void bootDataSeg(void); 823extern void MPentry(void); 824extern u_int MP_GDT; 825extern u_int mp_gdtbase; 826 827static void 828install_ap_tramp(void) 829{ 830 int x; 831 int size = *(int *) ((u_long) & bootMP_size); 832 vm_offset_t va = boot_address + KERNBASE; 833 u_char *src = (u_char *) ((u_long) bootMP); 834 u_char *dst = (u_char *) va; 835 u_int boot_base = (u_int) bootMP; 836 u_int8_t *dst8; 837 u_int16_t *dst16; 838 u_int32_t *dst32; 839 840 KASSERT (size <= PAGE_SIZE, 841 ("'size' do not fit into PAGE_SIZE, as expected.")); 842 pmap_kenter(va, boot_address); 843 pmap_invalidate_page (kernel_pmap, va); 844 for (x = 0; x < size; ++x) 845 *dst++ = *src++; 846 847 /* 848 * modify addresses in code we just moved to basemem. unfortunately we 849 * need fairly detailed info about mpboot.s for this to work. changes 850 * to mpboot.s might require changes here. 851 */ 852 853 /* boot code is located in KERNEL space */ 854 dst = (u_char *) va; 855 856 /* modify the lgdt arg */ 857 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 858 *dst32 = boot_address + ((u_int) & MP_GDT - boot_base); 859 860 /* modify the ljmp target for MPentry() */ 861 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 862 *dst32 = ((u_int) MPentry - KERNBASE); 863 864 /* modify the target for boot code segment */ 865 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 866 dst8 = (u_int8_t *) (dst16 + 1); 867 *dst16 = (u_int) boot_address & 0xffff; 868 *dst8 = ((u_int) boot_address >> 16) & 0xff; 869 870 /* modify the target for boot data segment */ 871 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 872 dst8 = (u_int8_t *) (dst16 + 1); 873 *dst16 = (u_int) boot_address & 0xffff; 874 *dst8 = ((u_int) boot_address >> 16) & 0xff; 875} 876 877/* 878 * This function starts the AP (application processor) identified 879 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 880 * to accomplish this. This is necessary because of the nuances 881 * of the different hardware we might encounter. It isn't pretty, 882 * but it seems to work. 883 */ 884static int 885start_ap(int apic_id) 886{ 887 int vector, ms; 888 int cpus; 889 890 /* calculate the vector */ 891 vector = (boot_address >> 12) & 0xff; 892 893 /* used as a watchpoint to signal AP startup */ 894 cpus = mp_naps; 895 896 /* 897 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 898 * and running the target CPU. OR this INIT IPI might be latched (P5 899 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 900 * ignored. 901 */ 902 903 /* do an INIT IPI: assert RESET */ 904 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 905 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id); 906 907 /* wait for pending status end */ 908 lapic_ipi_wait(-1); 909 910 /* do an INIT IPI: deassert RESET */ 911 lapic_ipi_raw(APIC_DEST_ALLESELF | APIC_TRIGMOD_LEVEL | 912 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, 0); 913 914 /* wait for pending status end */ 915 DELAY(10000); /* wait ~10mS */ 916 lapic_ipi_wait(-1); 917 918 /* 919 * next we do a STARTUP IPI: the previous INIT IPI might still be 920 * latched, (P5 bug) this 1st STARTUP would then terminate 921 * immediately, and the previously started INIT IPI would continue. OR 922 * the previous INIT IPI has already run. and this STARTUP IPI will 923 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 924 * will run. 925 */ 926 927 /* do a STARTUP IPI */ 928 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 929 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 930 vector, apic_id); 931 lapic_ipi_wait(-1); 932 DELAY(200); /* wait ~200uS */ 933 934 /* 935 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 936 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 937 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 938 * recognized after hardware RESET or INIT IPI. 939 */ 940 941 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 942 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 943 vector, apic_id); 944 lapic_ipi_wait(-1); 945 DELAY(200); /* wait ~200uS */ 946 947 /* Wait up to 5 seconds for it to start. */ 948 for (ms = 0; ms < 5000; ms++) { 949 if (mp_naps > cpus) 950 return 1; /* return SUCCESS */ 951 DELAY(1000); 952 } 953 return 0; /* return FAILURE */ 954} 955 956#ifdef COUNT_XINVLTLB_HITS 957u_int xhits_gbl[MAXCPU]; 958u_int xhits_pg[MAXCPU]; 959u_int xhits_rng[MAXCPU]; 960SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, ""); 961SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl, 962 sizeof(xhits_gbl), "IU", ""); 963SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg, 964 sizeof(xhits_pg), "IU", ""); 965SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng, 966 sizeof(xhits_rng), "IU", ""); 967 968u_int ipi_global; 969u_int ipi_page; 970u_int ipi_range; 971u_int ipi_range_size; 972SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, ""); 973SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, ""); 974SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, ""); 975SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size, 976 0, ""); 977 978u_int ipi_masked_global; 979u_int ipi_masked_page; 980u_int ipi_masked_range; 981u_int ipi_masked_range_size; 982SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW, 983 &ipi_masked_global, 0, ""); 984SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW, 985 &ipi_masked_page, 0, ""); 986SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW, 987 &ipi_masked_range, 0, ""); 988SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW, 989 &ipi_masked_range_size, 0, ""); 990#endif /* COUNT_XINVLTLB_HITS */ 991 992/* 993 * Flush the TLB on all other CPU's 994 */ 995static void 996smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2) 997{ 998 u_int ncpu; 999 1000 ncpu = mp_ncpus - 1; /* does not shootdown self */ 1001 if (ncpu < 1) 1002 return; /* no other cpus */ 1003 mtx_assert(&smp_ipi_mtx, MA_OWNED); 1004 smp_tlb_addr1 = addr1; 1005 smp_tlb_addr2 = addr2; 1006 atomic_store_rel_int(&smp_tlb_wait, 0); 1007 ipi_all_but_self(vector); 1008 while (smp_tlb_wait < ncpu) 1009 ia32_pause(); 1010} 1011 1012static void 1013smp_targeted_tlb_shootdown(u_int mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2) 1014{ 1015 int ncpu, othercpus; 1016 1017 othercpus = mp_ncpus - 1; 1018 if (mask == (u_int)-1) { 1019 ncpu = othercpus; 1020 if (ncpu < 1) 1021 return; 1022 } else { 1023 mask &= ~PCPU_GET(cpumask); 1024 if (mask == 0) 1025 return; 1026 ncpu = bitcount32(mask); 1027 if (ncpu > othercpus) { 1028 /* XXX this should be a panic offence */ 1029 printf("SMP: tlb shootdown to %d other cpus (only have %d)\n", 1030 ncpu, othercpus); 1031 ncpu = othercpus; 1032 } 1033 /* XXX should be a panic, implied by mask == 0 above */ 1034 if (ncpu < 1) 1035 return; 1036 } 1037 mtx_assert(&smp_ipi_mtx, MA_OWNED); 1038 smp_tlb_addr1 = addr1; 1039 smp_tlb_addr2 = addr2; 1040 atomic_store_rel_int(&smp_tlb_wait, 0); 1041 if (mask == (u_int)-1) 1042 ipi_all_but_self(vector); 1043 else 1044 ipi_selected(mask, vector); 1045 while (smp_tlb_wait < ncpu) 1046 ia32_pause(); 1047} 1048 1049void 1050smp_invltlb(void) 1051{ 1052 1053 if (smp_started) { 1054 smp_tlb_shootdown(IPI_INVLTLB, 0, 0); 1055#ifdef COUNT_XINVLTLB_HITS 1056 ipi_global++; 1057#endif 1058 } 1059} 1060 1061void 1062smp_invlpg(vm_offset_t addr) 1063{ 1064 1065 if (smp_started) { 1066 smp_tlb_shootdown(IPI_INVLPG, addr, 0); 1067#ifdef COUNT_XINVLTLB_HITS 1068 ipi_page++; 1069#endif 1070 } 1071} 1072 1073void 1074smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2) 1075{ 1076 1077 if (smp_started) { 1078 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2); 1079#ifdef COUNT_XINVLTLB_HITS 1080 ipi_range++; 1081 ipi_range_size += (addr2 - addr1) / PAGE_SIZE; 1082#endif 1083 } 1084} 1085 1086void 1087smp_masked_invltlb(u_int mask) 1088{ 1089 1090 if (smp_started) { 1091 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0); 1092#ifdef COUNT_XINVLTLB_HITS 1093 ipi_masked_global++; 1094#endif 1095 } 1096} 1097 1098void 1099smp_masked_invlpg(u_int mask, vm_offset_t addr) 1100{ 1101 1102 if (smp_started) { 1103 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0); 1104#ifdef COUNT_XINVLTLB_HITS 1105 ipi_masked_page++; 1106#endif 1107 } 1108} 1109 1110void 1111smp_masked_invlpg_range(u_int mask, vm_offset_t addr1, vm_offset_t addr2) 1112{ 1113 1114 if (smp_started) { 1115 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2); 1116#ifdef COUNT_XINVLTLB_HITS 1117 ipi_masked_range++; 1118 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE; 1119#endif 1120 } 1121} 1122 1123void 1124ipi_bitmap_handler(struct trapframe frame) 1125{ 1126 int cpu = PCPU_GET(cpuid); 1127 u_int ipi_bitmap; 1128 1129 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]); 1130 1131#ifdef IPI_PREEMPTION 1132 if (ipi_bitmap & IPI_PREEMPT) { 1133#ifdef COUNT_IPIS 1134 *ipi_preempt_counts[cpu]++; 1135#endif 1136 mtx_lock_spin(&sched_lock); 1137 /* Don't preempt the idle thread */ 1138 if (curthread->td_priority < PRI_MIN_IDLE) { 1139 struct thread *running_thread = curthread; 1140 if (running_thread->td_critnest > 1) 1141 running_thread->td_owepreempt = 1; 1142 else 1143 mi_switch(SW_INVOL | SW_PREEMPT, NULL); 1144 } 1145 mtx_unlock_spin(&sched_lock); 1146 } 1147#endif 1148 1149 if (ipi_bitmap & IPI_AST) { 1150#ifdef COUNT_IPIS 1151 *ipi_ast_counts[cpu]++; 1152#endif 1153 /* Nothing to do for AST */ 1154 } 1155} 1156 1157/* 1158 * send an IPI to a set of cpus. 1159 */ 1160void 1161ipi_selected(u_int32_t cpus, u_int ipi) 1162{ 1163 int cpu; 1164 u_int bitmap = 0; 1165 u_int old_pending; 1166 u_int new_pending; 1167 1168 if (IPI_IS_BITMAPED(ipi)) { 1169 bitmap = 1 << ipi; 1170 ipi = IPI_BITMAP_VECTOR; 1171 } 1172 1173#ifdef STOP_NMI 1174 if (ipi == IPI_STOP && stop_cpus_with_nmi) { 1175 ipi_nmi_selected(cpus); 1176 return; 1177 } 1178#endif 1179 CTR3(KTR_SMP, "%s: cpus: %x ipi: %x", __func__, cpus, ipi); 1180 while ((cpu = ffs(cpus)) != 0) { 1181 cpu--; 1182 cpus &= ~(1 << cpu); 1183 1184 KASSERT(cpu_apic_ids[cpu] != -1, 1185 ("IPI to non-existent CPU %d", cpu)); 1186 1187 if (bitmap) { 1188 do { 1189 old_pending = cpu_ipi_pending[cpu]; 1190 new_pending = old_pending | bitmap; 1191 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu],old_pending, new_pending)); 1192 1193 if (old_pending) 1194 continue; 1195 } 1196 1197 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]); 1198 } 1199 1200} 1201 1202/* 1203 * send an IPI INTerrupt containing 'vector' to all CPUs, including myself 1204 */ 1205void 1206ipi_all(u_int ipi) 1207{ 1208 1209 if (IPI_IS_BITMAPED(ipi) || (ipi == IPI_STOP && stop_cpus_with_nmi)) { 1210 ipi_selected(all_cpus, ipi); 1211 return; 1212 } 1213 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1214 lapic_ipi_vectored(ipi, APIC_IPI_DEST_ALL); 1215} 1216 1217/* 1218 * send an IPI to all CPUs EXCEPT myself 1219 */ 1220void 1221ipi_all_but_self(u_int ipi) 1222{ 1223 1224 if (IPI_IS_BITMAPED(ipi) || (ipi == IPI_STOP && stop_cpus_with_nmi)) { 1225 ipi_selected(PCPU_GET(other_cpus), ipi); 1226 return; 1227 } 1228 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1229 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS); 1230} 1231 1232/* 1233 * send an IPI to myself 1234 */ 1235void 1236ipi_self(u_int ipi) 1237{ 1238 1239 if (IPI_IS_BITMAPED(ipi) || (ipi == IPI_STOP && stop_cpus_with_nmi)) { 1240 ipi_selected(PCPU_GET(cpumask), ipi); 1241 return; 1242 } 1243 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1244 lapic_ipi_vectored(ipi, APIC_IPI_DEST_SELF); 1245} 1246 1247#ifdef STOP_NMI 1248/* 1249 * send NMI IPI to selected CPUs 1250 */ 1251 1252#define BEFORE_SPIN 1000000 1253 1254void 1255ipi_nmi_selected(u_int32_t cpus) 1256{ 1257 int cpu; 1258 register_t icrlo; 1259 1260 icrlo = APIC_DELMODE_NMI | APIC_DESTMODE_PHY | APIC_LEVEL_ASSERT 1261 | APIC_TRIGMOD_EDGE; 1262 1263 CTR2(KTR_SMP, "%s: cpus: %x nmi", __func__, cpus); 1264 1265 atomic_set_int(&ipi_nmi_pending, cpus); 1266 1267 while ((cpu = ffs(cpus)) != 0) { 1268 cpu--; 1269 cpus &= ~(1 << cpu); 1270 1271 KASSERT(cpu_apic_ids[cpu] != -1, 1272 ("IPI NMI to non-existent CPU %d", cpu)); 1273 1274 /* Wait for an earlier IPI to finish. */ 1275 if (!lapic_ipi_wait(BEFORE_SPIN)) 1276 panic("ipi_nmi_selected: previous IPI has not cleared"); 1277 1278 lapic_ipi_raw(icrlo, cpu_apic_ids[cpu]); 1279 } 1280} 1281 1282int 1283ipi_nmi_handler(void) 1284{ 1285 int cpumask = PCPU_GET(cpumask); 1286 1287 if (!(ipi_nmi_pending & cpumask)) 1288 return 1; 1289 1290 atomic_clear_int(&ipi_nmi_pending, cpumask); 1291 cpustop_handler(); 1292 return 0; 1293} 1294 1295#endif /* STOP_NMI */ 1296 1297/* 1298 * Handle an IPI_STOP by saving our current context and spinning until we 1299 * are resumed. 1300 */ 1301void 1302cpustop_handler(void) 1303{ 1304 int cpu = PCPU_GET(cpuid); 1305 int cpumask = PCPU_GET(cpumask); 1306 1307 savectx(&stoppcbs[cpu]); 1308 1309 /* Indicate that we are stopped */ 1310 atomic_set_int(&stopped_cpus, cpumask); 1311 1312 /* Wait for restart */ 1313 while (!(started_cpus & cpumask)) 1314 ia32_pause(); 1315 1316 atomic_clear_int(&started_cpus, cpumask); 1317 atomic_clear_int(&stopped_cpus, cpumask); 1318 1319 if (cpu == 0 && cpustop_restartfunc != NULL) { 1320 cpustop_restartfunc(); 1321 cpustop_restartfunc = NULL; 1322 } 1323} 1324 1325/* 1326 * This is called once the rest of the system is up and running and we're 1327 * ready to let the AP's out of the pen. 1328 */ 1329static void 1330release_aps(void *dummy __unused) 1331{ 1332 1333 if (mp_ncpus == 1) 1334 return; 1335 mtx_lock_spin(&sched_lock); 1336 atomic_store_rel_int(&aps_ready, 1); 1337 while (smp_started == 0) 1338 ia32_pause(); 1339 mtx_unlock_spin(&sched_lock); 1340} 1341SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL); 1342 1343static int 1344sysctl_hlt_cpus(SYSCTL_HANDLER_ARGS) 1345{ 1346 u_int mask; 1347 int error; 1348 1349 mask = hlt_cpus_mask; 1350 error = sysctl_handle_int(oidp, &mask, 0, req); 1351 if (error || !req->newptr) 1352 return (error); 1353 1354 if (logical_cpus_mask != 0 && 1355 (mask & logical_cpus_mask) == logical_cpus_mask) 1356 hlt_logical_cpus = 1; 1357 else 1358 hlt_logical_cpus = 0; 1359 1360 if (! hyperthreading_allowed) 1361 mask |= hyperthreading_cpus_mask; 1362 1363 if ((mask & all_cpus) == all_cpus) 1364 mask &= ~(1<<0); 1365 hlt_cpus_mask = mask; 1366 return (error); 1367} 1368SYSCTL_PROC(_machdep, OID_AUTO, hlt_cpus, CTLTYPE_INT|CTLFLAG_RW, 1369 0, 0, sysctl_hlt_cpus, "IU", 1370 "Bitmap of CPUs to halt. 101 (binary) will halt CPUs 0 and 2."); 1371 1372static int 1373sysctl_hlt_logical_cpus(SYSCTL_HANDLER_ARGS) 1374{ 1375 int disable, error; 1376 1377 disable = hlt_logical_cpus; 1378 error = sysctl_handle_int(oidp, &disable, 0, req); 1379 if (error || !req->newptr) 1380 return (error); 1381 1382 if (disable) 1383 hlt_cpus_mask |= logical_cpus_mask; 1384 else 1385 hlt_cpus_mask &= ~logical_cpus_mask; 1386 1387 if (! hyperthreading_allowed) 1388 hlt_cpus_mask |= hyperthreading_cpus_mask; 1389 1390 if ((hlt_cpus_mask & all_cpus) == all_cpus) 1391 hlt_cpus_mask &= ~(1<<0); 1392 1393 hlt_logical_cpus = disable; 1394 return (error); 1395} 1396 1397static int 1398sysctl_hyperthreading_allowed(SYSCTL_HANDLER_ARGS) 1399{ 1400 int allowed, error; 1401 1402 allowed = hyperthreading_allowed; 1403 error = sysctl_handle_int(oidp, &allowed, 0, req); 1404 if (error || !req->newptr) 1405 return (error); 1406 1407 if (allowed) 1408 hlt_cpus_mask &= ~hyperthreading_cpus_mask; 1409 else 1410 hlt_cpus_mask |= hyperthreading_cpus_mask; 1411 1412 if (logical_cpus_mask != 0 && 1413 (hlt_cpus_mask & logical_cpus_mask) == logical_cpus_mask) 1414 hlt_logical_cpus = 1; 1415 else 1416 hlt_logical_cpus = 0; 1417 1418 if ((hlt_cpus_mask & all_cpus) == all_cpus) 1419 hlt_cpus_mask &= ~(1<<0); 1420 1421 hyperthreading_allowed = allowed; 1422 return (error); 1423} 1424 1425static void 1426cpu_hlt_setup(void *dummy __unused) 1427{ 1428 1429 if (logical_cpus_mask != 0) { 1430 TUNABLE_INT_FETCH("machdep.hlt_logical_cpus", 1431 &hlt_logical_cpus); 1432 sysctl_ctx_init(&logical_cpu_clist); 1433 SYSCTL_ADD_PROC(&logical_cpu_clist, 1434 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1435 "hlt_logical_cpus", CTLTYPE_INT|CTLFLAG_RW, 0, 0, 1436 sysctl_hlt_logical_cpus, "IU", ""); 1437 SYSCTL_ADD_UINT(&logical_cpu_clist, 1438 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1439 "logical_cpus_mask", CTLTYPE_INT|CTLFLAG_RD, 1440 &logical_cpus_mask, 0, ""); 1441 1442 if (hlt_logical_cpus) 1443 hlt_cpus_mask |= logical_cpus_mask; 1444 1445 /* 1446 * If necessary for security purposes, force 1447 * hyperthreading off, regardless of the value 1448 * of hlt_logical_cpus. 1449 */ 1450 if (hyperthreading_cpus_mask) { 1451 TUNABLE_INT_FETCH("machdep.hyperthreading_allowed", 1452 &hyperthreading_allowed); 1453 SYSCTL_ADD_PROC(&logical_cpu_clist, 1454 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1455 "hyperthreading_allowed", CTLTYPE_INT|CTLFLAG_RW, 1456 0, 0, sysctl_hyperthreading_allowed, "IU", ""); 1457 if (! hyperthreading_allowed) 1458 hlt_cpus_mask |= hyperthreading_cpus_mask; 1459 } 1460 } 1461} 1462SYSINIT(cpu_hlt, SI_SUB_SMP, SI_ORDER_ANY, cpu_hlt_setup, NULL); 1463 1464int 1465mp_grab_cpu_hlt(void) 1466{ 1467 u_int mask = PCPU_GET(cpumask); 1468#ifdef MP_WATCHDOG 1469 u_int cpuid = PCPU_GET(cpuid); 1470#endif 1471 int retval; 1472 1473#ifdef MP_WATCHDOG 1474 ap_watchdog(cpuid); 1475#endif 1476 1477 retval = mask & hlt_cpus_mask; 1478 while (mask & hlt_cpus_mask) 1479 __asm __volatile("sti; hlt" : : : "memory"); 1480 return (retval); 1481} 1482 1483#ifdef COUNT_IPIS 1484/* 1485 * Setup interrupt counters for IPI handlers. 1486 */ 1487static void 1488mp_ipi_intrcnt(void *dummy) 1489{ 1490 char buf[64]; 1491 int i; 1492 1493 for (i = 0; i < mp_maxid; i++) { 1494 if (CPU_ABSENT(i)) 1495 continue; 1496 snprintf(buf, sizeof(buf), "cpu%d: invltlb", i); 1497 intrcnt_add(buf, &ipi_invltlb_counts[i]); 1498 snprintf(buf, sizeof(buf), "cpu%d: invlrng", i); 1499 intrcnt_add(buf, &ipi_invlrng_counts[i]); 1500 snprintf(buf, sizeof(buf), "cpu%d: invlpg", i); 1501 intrcnt_add(buf, &ipi_invlpg_counts[i]); 1502#ifdef IPI_PREEMPTION 1503 snprintf(buf, sizeof(buf), "cpu%d: preempt", i); 1504 intrcnt_add(buf, &ipi_preempt_counts[i]); 1505#endif 1506 snprintf(buf, sizeof(buf), "cpu%d: ast", i); 1507 intrcnt_add(buf, &ipi_ast_counts[i]); 1508 snprintf(buf, sizeof(buf), "cpu%d: rendezvous", i); 1509 intrcnt_add(buf, &ipi_rendezvous_counts[i]); 1510 snprintf(buf, sizeof(buf), "cpu%d: lazypmap", i); 1511 intrcnt_add(buf, &ipi_lazypmap_counts[i]); 1512 } 1513} 1514SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL) 1515#endif 1516