mp_x86.c revision 156504
1/*- 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26#include <sys/cdefs.h> 27__FBSDID("$FreeBSD: head/sys/i386/i386/mp_machdep.c 156504 2006-03-09 16:38:52Z jhb $"); 28 29#include "opt_apic.h" 30#include "opt_cpu.h" 31#include "opt_kstack_pages.h" 32#include "opt_mp_watchdog.h" 33#include "opt_sched.h" 34#include "opt_smp.h" 35 36#if !defined(lint) 37#if !defined(SMP) 38#error How did you get here? 39#endif 40 41#ifndef DEV_APIC 42#error The apic device is required for SMP, add "device apic" to your config file. 43#endif 44#if defined(CPU_DISABLE_CMPXCHG) && !defined(COMPILING_LINT) 45#error SMP not supported with CPU_DISABLE_CMPXCHG 46#endif 47#endif /* not lint */ 48 49#include <sys/param.h> 50#include <sys/systm.h> 51#include <sys/bus.h> 52#include <sys/cons.h> /* cngetc() */ 53#ifdef GPROF 54#include <sys/gmon.h> 55#endif 56#include <sys/kernel.h> 57#include <sys/ktr.h> 58#include <sys/lock.h> 59#include <sys/malloc.h> 60#include <sys/memrange.h> 61#include <sys/mutex.h> 62#include <sys/pcpu.h> 63#include <sys/proc.h> 64#include <sys/smp.h> 65#include <sys/sysctl.h> 66 67#include <vm/vm.h> 68#include <vm/vm_param.h> 69#include <vm/pmap.h> 70#include <vm/vm_kern.h> 71#include <vm/vm_extern.h> 72 73#include <machine/apicreg.h> 74#include <machine/clock.h> 75#include <machine/md_var.h> 76#include <machine/mp_watchdog.h> 77#include <machine/pcb.h> 78#include <machine/smp.h> 79#include <machine/specialreg.h> 80#include <machine/privatespace.h> 81 82#define WARMBOOT_TARGET 0 83#define WARMBOOT_OFF (KERNBASE + 0x0467) 84#define WARMBOOT_SEG (KERNBASE + 0x0469) 85 86#define CMOS_REG (0x70) 87#define CMOS_DATA (0x71) 88#define BIOS_RESET (0x0f) 89#define BIOS_WARM (0x0a) 90 91/* 92 * this code MUST be enabled here and in mpboot.s. 93 * it follows the very early stages of AP boot by placing values in CMOS ram. 94 * it NORMALLY will never be needed and thus the primitive method for enabling. 95 * 96#define CHECK_POINTS 97 */ 98 99#if defined(CHECK_POINTS) && !defined(PC98) 100#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 101#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 102 103#define CHECK_INIT(D); \ 104 CHECK_WRITE(0x34, (D)); \ 105 CHECK_WRITE(0x35, (D)); \ 106 CHECK_WRITE(0x36, (D)); \ 107 CHECK_WRITE(0x37, (D)); \ 108 CHECK_WRITE(0x38, (D)); \ 109 CHECK_WRITE(0x39, (D)); 110 111#define CHECK_PRINT(S); \ 112 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 113 (S), \ 114 CHECK_READ(0x34), \ 115 CHECK_READ(0x35), \ 116 CHECK_READ(0x36), \ 117 CHECK_READ(0x37), \ 118 CHECK_READ(0x38), \ 119 CHECK_READ(0x39)); 120 121#else /* CHECK_POINTS */ 122 123#define CHECK_INIT(D) 124#define CHECK_PRINT(S) 125#define CHECK_WRITE(A, D) 126 127#endif /* CHECK_POINTS */ 128 129/* lock region used by kernel profiling */ 130int mcount_lock; 131 132int mp_naps; /* # of Applications processors */ 133int boot_cpu_id = -1; /* designated BSP */ 134extern int nkpt; 135 136/* 137 * CPU topology map datastructures for HTT. 138 */ 139static struct cpu_group mp_groups[MAXCPU]; 140static struct cpu_top mp_top; 141 142/* AP uses this during bootstrap. Do not staticize. */ 143char *bootSTK; 144static int bootAP; 145 146/* Hotwire a 0->4MB V==P mapping */ 147extern pt_entry_t *KPTphys; 148 149/* SMP page table page */ 150extern pt_entry_t *SMPpt; 151 152struct pcb stoppcbs[MAXCPU]; 153 154/* Variables needed for SMP tlb shootdown. */ 155vm_offset_t smp_tlb_addr1; 156vm_offset_t smp_tlb_addr2; 157volatile int smp_tlb_wait; 158 159#ifdef STOP_NMI 160volatile cpumask_t ipi_nmi_pending; 161 162static void ipi_nmi_selected(u_int32_t cpus); 163#endif 164 165#ifdef COUNT_IPIS 166/* Interrupt counts. */ 167#ifdef IPI_PREEMPTION 168static u_long *ipi_preempt_counts[MAXCPU]; 169#endif 170static u_long *ipi_ast_counts[MAXCPU]; 171u_long *ipi_invltlb_counts[MAXCPU]; 172u_long *ipi_invlrng_counts[MAXCPU]; 173u_long *ipi_invlpg_counts[MAXCPU]; 174u_long *ipi_rendezvous_counts[MAXCPU]; 175u_long *ipi_lazypmap_counts[MAXCPU]; 176#endif 177 178/* 179 * Local data and functions. 180 */ 181 182#ifdef STOP_NMI 183/* 184 * Provide an alternate method of stopping other CPUs. If another CPU has 185 * disabled interrupts the conventional STOP IPI will be blocked. This 186 * NMI-based stop should get through in that case. 187 */ 188static int stop_cpus_with_nmi = 1; 189SYSCTL_INT(_debug, OID_AUTO, stop_cpus_with_nmi, CTLTYPE_INT | CTLFLAG_RW, 190 &stop_cpus_with_nmi, 0, ""); 191TUNABLE_INT("debug.stop_cpus_with_nmi", &stop_cpus_with_nmi); 192#else 193#define stop_cpus_with_nmi 0 194#endif 195 196static u_int logical_cpus; 197 198/* used to hold the AP's until we are ready to release them */ 199static struct mtx ap_boot_mtx; 200 201/* Set to 1 once we're ready to let the APs out of the pen. */ 202static volatile int aps_ready = 0; 203 204/* 205 * Store data from cpu_add() until later in the boot when we actually setup 206 * the APs. 207 */ 208struct cpu_info { 209 int cpu_present:1; 210 int cpu_bsp:1; 211 int cpu_disabled:1; 212} static cpu_info[MAXCPU]; 213static int cpu_apic_ids[MAXCPU]; 214 215/* Holds pending bitmap based IPIs per CPU */ 216static volatile u_int cpu_ipi_pending[MAXCPU]; 217 218static u_int boot_address; 219 220static void set_interrupt_apic_ids(void); 221static int start_all_aps(void); 222static void install_ap_tramp(void); 223static int start_ap(int apic_id); 224static void release_aps(void *dummy); 225 226static int hlt_logical_cpus; 227static u_int hyperthreading_cpus; 228static cpumask_t hyperthreading_cpus_mask; 229static int hyperthreading_allowed = 1; 230static struct sysctl_ctx_list logical_cpu_clist; 231 232static void 233mem_range_AP_init(void) 234{ 235 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP) 236 mem_range_softc.mr_op->initAP(&mem_range_softc); 237} 238 239void 240mp_topology(void) 241{ 242 struct cpu_group *group; 243 int logical_cpus; 244 int apic_id; 245 int groups; 246 int cpu; 247 248 /* Build the smp_topology map. */ 249 /* Nothing to do if there is no HTT support. */ 250 if ((cpu_feature & CPUID_HTT) == 0) 251 return; 252 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 253 if (logical_cpus <= 1) 254 return; 255 group = &mp_groups[0]; 256 groups = 1; 257 for (cpu = 0, apic_id = 0; apic_id < MAXCPU; apic_id++) { 258 if (!cpu_info[apic_id].cpu_present) 259 continue; 260 /* 261 * If the current group has members and we're not a logical 262 * cpu, create a new group. 263 */ 264 if (group->cg_count != 0 && (apic_id % logical_cpus) == 0) { 265 group++; 266 groups++; 267 } 268 group->cg_count++; 269 group->cg_mask |= 1 << cpu; 270 cpu++; 271 } 272 273 mp_top.ct_count = groups; 274 mp_top.ct_group = mp_groups; 275 smp_topology = &mp_top; 276} 277 278 279/* 280 * Calculate usable address in base memory for AP trampoline code. 281 */ 282u_int 283mp_bootaddress(u_int basemem) 284{ 285 286 boot_address = trunc_page(basemem); /* round down to 4k boundary */ 287 if ((basemem - boot_address) < bootMP_size) 288 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */ 289 290 return boot_address; 291} 292 293void 294cpu_add(u_int apic_id, char boot_cpu) 295{ 296 297 if (apic_id >= MAXCPU) { 298 printf("SMP: CPU %d exceeds maximum CPU %d, ignoring\n", 299 apic_id, MAXCPU - 1); 300 return; 301 } 302 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice", 303 apic_id)); 304 cpu_info[apic_id].cpu_present = 1; 305 if (boot_cpu) { 306 KASSERT(boot_cpu_id == -1, 307 ("CPU %d claims to be BSP, but CPU %d already is", apic_id, 308 boot_cpu_id)); 309 boot_cpu_id = apic_id; 310 cpu_info[apic_id].cpu_bsp = 1; 311 } 312 mp_ncpus++; 313 if (bootverbose) 314 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" : 315 "AP"); 316 317} 318 319void 320cpu_mp_setmaxid(void) 321{ 322 323 mp_maxid = MAXCPU - 1; 324} 325 326int 327cpu_mp_probe(void) 328{ 329 330 /* 331 * Always record BSP in CPU map so that the mbuf init code works 332 * correctly. 333 */ 334 all_cpus = 1; 335 if (mp_ncpus == 0) { 336 /* 337 * No CPUs were found, so this must be a UP system. Setup 338 * the variables to represent a system with a single CPU 339 * with an id of 0. 340 */ 341 mp_ncpus = 1; 342 return (0); 343 } 344 345 /* At least one CPU was found. */ 346 if (mp_ncpus == 1) { 347 /* 348 * One CPU was found, so this must be a UP system with 349 * an I/O APIC. 350 */ 351 return (0); 352 } 353 354 /* At least two CPUs were found. */ 355 return (1); 356} 357 358/* 359 * Initialize the IPI handlers and start up the AP's. 360 */ 361void 362cpu_mp_start(void) 363{ 364 int i; 365 u_int threads_per_cache, p[4]; 366 367 /* Initialize the logical ID to APIC ID table. */ 368 for (i = 0; i < MAXCPU; i++) { 369 cpu_apic_ids[i] = -1; 370 cpu_ipi_pending[i] = 0; 371 } 372 373 /* Install an inter-CPU IPI for TLB invalidation */ 374 setidt(IPI_INVLTLB, IDTVEC(invltlb), 375 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 376 setidt(IPI_INVLPG, IDTVEC(invlpg), 377 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 378 setidt(IPI_INVLRNG, IDTVEC(invlrng), 379 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 380 381 /* Install an inter-CPU IPI for lazy pmap release */ 382 setidt(IPI_LAZYPMAP, IDTVEC(lazypmap), 383 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 384 385 /* Install an inter-CPU IPI for all-CPU rendezvous */ 386 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous), 387 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 388 389 /* Install generic inter-CPU IPI handler */ 390 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler), 391 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 392 393 /* Install an inter-CPU IPI for CPU stop/restart */ 394 setidt(IPI_STOP, IDTVEC(cpustop), 395 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 396 397 398 /* Set boot_cpu_id if needed. */ 399 if (boot_cpu_id == -1) { 400 boot_cpu_id = PCPU_GET(apic_id); 401 cpu_info[boot_cpu_id].cpu_bsp = 1; 402 } else 403 KASSERT(boot_cpu_id == PCPU_GET(apic_id), 404 ("BSP's APIC ID doesn't match boot_cpu_id")); 405 cpu_apic_ids[0] = boot_cpu_id; 406 407 /* Start each Application Processor */ 408 start_all_aps(); 409 410 /* Setup the initial logical CPUs info. */ 411 logical_cpus = logical_cpus_mask = 0; 412 if (cpu_feature & CPUID_HTT) 413 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 414 415 /* 416 * Work out if hyperthreading is *really* enabled. This 417 * is made really ugly by the fact that processors lie: Dual 418 * core processors claim to be hyperthreaded even when they're 419 * not, presumably because they want to be treated the same 420 * way as HTT with respect to per-cpu software licensing. 421 * At the time of writing (May 12, 2005) the only hyperthreaded 422 * cpus are from Intel, and Intel's dual-core processors can be 423 * identified via the "deterministic cache parameters" cpuid 424 * calls. 425 */ 426 /* 427 * First determine if this is an Intel processor which claims 428 * to have hyperthreading support. 429 */ 430 if ((cpu_feature & CPUID_HTT) && 431 (strcmp(cpu_vendor, "GenuineIntel") == 0)) { 432 /* 433 * If the "deterministic cache parameters" cpuid calls 434 * are available, use them. 435 */ 436 if (cpu_high >= 4) { 437 /* Ask the processor about up to 32 caches. */ 438 for (i = 0; i < 32; i++) { 439 cpuid_count(4, i, p); 440 threads_per_cache = ((p[0] & 0x3ffc000) >> 14) + 1; 441 if (hyperthreading_cpus < threads_per_cache) 442 hyperthreading_cpus = threads_per_cache; 443 if ((p[0] & 0x1f) == 0) 444 break; 445 } 446 } 447 448 /* 449 * If the deterministic cache parameters are not 450 * available, or if no caches were reported to exist, 451 * just accept what the HTT flag indicated. 452 */ 453 if (hyperthreading_cpus == 0) 454 hyperthreading_cpus = logical_cpus; 455 } 456 457 set_interrupt_apic_ids(); 458} 459 460 461/* 462 * Print various information about the SMP system hardware and setup. 463 */ 464void 465cpu_mp_announce(void) 466{ 467 int i, x; 468 469 /* List CPUs */ 470 printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id); 471 for (i = 1, x = 0; x < MAXCPU; x++) { 472 if (!cpu_info[x].cpu_present || cpu_info[x].cpu_bsp) 473 continue; 474 if (cpu_info[x].cpu_disabled) 475 printf(" cpu (AP): APIC ID: %2d (disabled)\n", x); 476 else { 477 KASSERT(i < mp_ncpus, 478 ("mp_ncpus and actual cpus are out of whack")); 479 printf(" cpu%d (AP): APIC ID: %2d\n", i++, x); 480 } 481 } 482} 483 484/* 485 * AP CPU's call this to initialize themselves. 486 */ 487void 488init_secondary(void) 489{ 490 vm_offset_t addr; 491 int gsel_tss; 492 int x, myid; 493 u_int cr0; 494 495 /* bootAP is set in start_ap() to our ID. */ 496 myid = bootAP; 497 gdt_segs[GPRIV_SEL].ssd_base = (int) &SMP_prvspace[myid]; 498 gdt_segs[GPROC0_SEL].ssd_base = 499 (int) &SMP_prvspace[myid].pcpu.pc_common_tss; 500 SMP_prvspace[myid].pcpu.pc_prvspace = 501 &SMP_prvspace[myid].pcpu; 502 503 for (x = 0; x < NGDT; x++) { 504 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd); 505 } 506 507 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 508 r_gdt.rd_base = (int) &gdt[myid * NGDT]; 509 lgdt(&r_gdt); /* does magic intra-segment return */ 510 511 lidt(&r_idt); 512 513 lldt(_default_ldt); 514 PCPU_SET(currentldt, _default_ldt); 515 516 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 517 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS; 518 PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */ 519 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL)); 520 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16); 521 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd); 522 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt)); 523 ltr(gsel_tss); 524 525 PCPU_SET(fsgs_gdt, &gdt[myid * NGDT + GUFS_SEL].sd); 526 527 /* 528 * Set to a known state: 529 * Set by mpboot.s: CR0_PG, CR0_PE 530 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM 531 */ 532 cr0 = rcr0(); 533 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM); 534 load_cr0(cr0); 535 CHECK_WRITE(0x38, 5); 536 537 /* Disable local APIC just to be sure. */ 538 lapic_disable(); 539 540 /* signal our startup to the BSP. */ 541 mp_naps++; 542 CHECK_WRITE(0x39, 6); 543 544 /* Spin until the BSP releases the AP's. */ 545 while (!aps_ready) 546 ia32_pause(); 547 548 /* BSP may have changed PTD while we were waiting */ 549 invltlb(); 550 for (addr = 0; addr < NKPT * NBPDR - 1; addr += PAGE_SIZE) 551 invlpg(addr); 552 553#if defined(I586_CPU) && !defined(NO_F00F_HACK) 554 lidt(&r_idt); 555#endif 556 557 /* set up CPU registers and state */ 558 cpu_setregs(); 559 560 /* set up FPU state on the AP */ 561 npxinit(__INITIAL_NPXCW__); 562 563 /* set up SSE registers */ 564 enable_sse(); 565 566 /* A quick check from sanity claus */ 567 if (PCPU_GET(apic_id) != lapic_id()) { 568 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid)); 569 printf("SMP: actual apic_id = %d\n", lapic_id()); 570 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id)); 571 printf("PTD[MPPTDI] = %#jx\n", (uintmax_t)PTD[MPPTDI]); 572 panic("cpuid mismatch! boom!!"); 573 } 574 575 /* Initialize curthread. */ 576 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread")); 577 PCPU_SET(curthread, PCPU_GET(idlethread)); 578 579 mtx_lock_spin(&ap_boot_mtx); 580 581 /* Init local apic for irq's */ 582 lapic_setup(); 583 584 /* Set memory range attributes for this CPU to match the BSP */ 585 mem_range_AP_init(); 586 587 smp_cpus++; 588 589 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", PCPU_GET(cpuid)); 590 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid)); 591 592 /* Determine if we are a logical CPU. */ 593 if (logical_cpus > 1 && PCPU_GET(apic_id) % logical_cpus != 0) 594 logical_cpus_mask |= PCPU_GET(cpumask); 595 596 /* Determine if we are a hyperthread. */ 597 if (hyperthreading_cpus > 1 && 598 PCPU_GET(apic_id) % hyperthreading_cpus != 0) 599 hyperthreading_cpus_mask |= PCPU_GET(cpumask); 600 601 /* Build our map of 'other' CPUs. */ 602 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 603 604 if (bootverbose) 605 lapic_dump("AP"); 606 607 if (smp_cpus == mp_ncpus) { 608 /* enable IPI's, tlb shootdown, freezes etc */ 609 atomic_store_rel_int(&smp_started, 1); 610 smp_active = 1; /* historic */ 611 } 612 613 mtx_unlock_spin(&ap_boot_mtx); 614 615 /* wait until all the AP's are up */ 616 while (smp_started == 0) 617 ia32_pause(); 618 619 /* ok, now grab sched_lock and enter the scheduler */ 620 mtx_lock_spin(&sched_lock); 621 622 /* 623 * Correct spinlock nesting. The idle thread context that we are 624 * borrowing was created so that it would start out with a single 625 * spin lock (sched_lock) held in fork_trampoline(). Since we've 626 * explicitly acquired locks in this function, the nesting count 627 * is now 2 rather than 1. Since we are nested, calling 628 * spinlock_exit() will simply adjust the counts without allowing 629 * spin lock using code to interrupt us. 630 */ 631 spinlock_exit(); 632 KASSERT(curthread->td_md.md_spinlock_count == 1, ("invalid count")); 633 634 PCPU_SET(switchtime, cpu_ticks()); 635 PCPU_SET(switchticks, ticks); 636 637 cpu_throw(NULL, choosethread()); /* doesn't return */ 638 639 panic("scheduler returned us to %s", __func__); 640 /* NOTREACHED */ 641} 642 643/******************************************************************* 644 * local functions and data 645 */ 646 647/* 648 * We tell the I/O APIC code about all the CPUs we want to receive 649 * interrupts. If we don't want certain CPUs to receive IRQs we 650 * can simply not tell the I/O APIC code about them in this function. 651 * We also do not tell it about the BSP since it tells itself about 652 * the BSP internally to work with UP kernels and on UP machines. 653 */ 654static void 655set_interrupt_apic_ids(void) 656{ 657 u_int apic_id; 658 659 for (apic_id = 0; apic_id < MAXCPU; apic_id++) { 660 if (!cpu_info[apic_id].cpu_present) 661 continue; 662 if (cpu_info[apic_id].cpu_bsp) 663 continue; 664 665 /* Don't let hyperthreads service interrupts. */ 666 if (hyperthreading_cpus > 1 && 667 apic_id % hyperthreading_cpus != 0) 668 continue; 669 670 intr_add_cpu(apic_id); 671 } 672} 673 674/* 675 * start each AP in our list 676 */ 677static int 678start_all_aps(void) 679{ 680#ifndef PC98 681 u_char mpbiosreason; 682#endif 683 struct pcpu *pc; 684 char *stack; 685 uintptr_t kptbase; 686 u_int32_t mpbioswarmvec; 687 int apic_id, cpu, i, pg; 688 689 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); 690 691 /* install the AP 1st level boot code */ 692 install_ap_tramp(); 693 694 /* save the current value of the warm-start vector */ 695 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF); 696#ifndef PC98 697 outb(CMOS_REG, BIOS_RESET); 698 mpbiosreason = inb(CMOS_DATA); 699#endif 700 701 /* set up temporary P==V mapping for AP boot */ 702 /* XXX this is a hack, we should boot the AP on its own stack/PTD */ 703 kptbase = (uintptr_t)(void *)KPTphys; 704 for (i = 0; i < NKPT; i++) 705 PTD[i] = (pd_entry_t)(PG_V | PG_RW | 706 ((kptbase + i * PAGE_SIZE) & PG_FRAME)); 707 invltlb(); 708 709 /* start each AP */ 710 for (cpu = 0, apic_id = 0; apic_id < MAXCPU; apic_id++) { 711 712 /* Ignore non-existent CPUs and the BSP. */ 713 if (!cpu_info[apic_id].cpu_present || 714 cpu_info[apic_id].cpu_bsp) 715 continue; 716 717 /* Don't use this CPU if it has been disabled by a tunable. */ 718 if (resource_disabled("lapic", apic_id)) { 719 cpu_info[apic_id].cpu_disabled = 1; 720 mp_ncpus--; 721 continue; 722 } 723 724 cpu++; 725 726 /* save APIC ID for this logical ID */ 727 cpu_apic_ids[cpu] = apic_id; 728 729 /* first page of AP's private space */ 730 pg = cpu * i386_btop(sizeof(struct privatespace)); 731 732 /* allocate a new private data page */ 733 pc = (struct pcpu *)kmem_alloc(kernel_map, PAGE_SIZE); 734 735 /* wire it into the private page table page */ 736 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys(pc)); 737 738 /* allocate and set up an idle stack data page */ 739 stack = (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE); /* XXXKSE */ 740 for (i = 0; i < KSTACK_PAGES; i++) 741 SMPpt[pg + 1 + i] = (pt_entry_t) 742 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 743 744 /* prime data page for it to use */ 745 pcpu_init(pc, cpu, sizeof(struct pcpu)); 746 pc->pc_apic_id = apic_id; 747 748 /* setup a vector to our boot code */ 749 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 750 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4); 751#ifndef PC98 752 outb(CMOS_REG, BIOS_RESET); 753 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 754#endif 755 756 bootSTK = &SMP_prvspace[cpu].idlekstack[KSTACK_PAGES * 757 PAGE_SIZE]; 758 bootAP = cpu; 759 760 /* attempt to start the Application Processor */ 761 CHECK_INIT(99); /* setup checkpoints */ 762 if (!start_ap(apic_id)) { 763 printf("AP #%d (PHY# %d) failed!\n", cpu, apic_id); 764 CHECK_PRINT("trace"); /* show checkpoints */ 765 /* better panic as the AP may be running loose */ 766 printf("panic y/n? [y] "); 767 if (cngetc() != 'n') 768 panic("bye-bye"); 769 } 770 CHECK_PRINT("trace"); /* show checkpoints */ 771 772 all_cpus |= (1 << cpu); /* record AP in CPU map */ 773 } 774 775 /* build our map of 'other' CPUs */ 776 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 777 778 /* restore the warmstart vector */ 779 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec; 780 781#ifndef PC98 782 outb(CMOS_REG, BIOS_RESET); 783 outb(CMOS_DATA, mpbiosreason); 784#endif 785 786 /* 787 * Set up the idle context for the BSP. Similar to above except 788 * that some was done by locore, some by pmap.c and some is implicit 789 * because the BSP is cpu#0 and the page is initially zero and also 790 * because we can refer to variables by name on the BSP.. 791 */ 792 793 /* Allocate and setup BSP idle stack */ 794 stack = (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE); 795 for (i = 0; i < KSTACK_PAGES; i++) 796 SMPpt[1 + i] = (pt_entry_t) 797 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 798 799 for (i = 0; i < NKPT; i++) 800 PTD[i] = 0; 801 pmap_invalidate_range(kernel_pmap, 0, NKPT * NBPDR - 1); 802 803 /* number of APs actually started */ 804 return mp_naps; 805} 806 807/* 808 * load the 1st level AP boot code into base memory. 809 */ 810 811/* targets for relocation */ 812extern void bigJump(void); 813extern void bootCodeSeg(void); 814extern void bootDataSeg(void); 815extern void MPentry(void); 816extern u_int MP_GDT; 817extern u_int mp_gdtbase; 818 819static void 820install_ap_tramp(void) 821{ 822 int x; 823 int size = *(int *) ((u_long) & bootMP_size); 824 vm_offset_t va = boot_address + KERNBASE; 825 u_char *src = (u_char *) ((u_long) bootMP); 826 u_char *dst = (u_char *) va; 827 u_int boot_base = (u_int) bootMP; 828 u_int8_t *dst8; 829 u_int16_t *dst16; 830 u_int32_t *dst32; 831 832 KASSERT (size <= PAGE_SIZE, 833 ("'size' do not fit into PAGE_SIZE, as expected.")); 834 pmap_kenter(va, boot_address); 835 pmap_invalidate_page (kernel_pmap, va); 836 for (x = 0; x < size; ++x) 837 *dst++ = *src++; 838 839 /* 840 * modify addresses in code we just moved to basemem. unfortunately we 841 * need fairly detailed info about mpboot.s for this to work. changes 842 * to mpboot.s might require changes here. 843 */ 844 845 /* boot code is located in KERNEL space */ 846 dst = (u_char *) va; 847 848 /* modify the lgdt arg */ 849 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 850 *dst32 = boot_address + ((u_int) & MP_GDT - boot_base); 851 852 /* modify the ljmp target for MPentry() */ 853 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 854 *dst32 = ((u_int) MPentry - KERNBASE); 855 856 /* modify the target for boot code segment */ 857 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 858 dst8 = (u_int8_t *) (dst16 + 1); 859 *dst16 = (u_int) boot_address & 0xffff; 860 *dst8 = ((u_int) boot_address >> 16) & 0xff; 861 862 /* modify the target for boot data segment */ 863 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 864 dst8 = (u_int8_t *) (dst16 + 1); 865 *dst16 = (u_int) boot_address & 0xffff; 866 *dst8 = ((u_int) boot_address >> 16) & 0xff; 867} 868 869/* 870 * This function starts the AP (application processor) identified 871 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 872 * to accomplish this. This is necessary because of the nuances 873 * of the different hardware we might encounter. It isn't pretty, 874 * but it seems to work. 875 */ 876static int 877start_ap(int apic_id) 878{ 879 int vector, ms; 880 int cpus; 881 882 /* calculate the vector */ 883 vector = (boot_address >> 12) & 0xff; 884 885 /* used as a watchpoint to signal AP startup */ 886 cpus = mp_naps; 887 888 /* 889 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 890 * and running the target CPU. OR this INIT IPI might be latched (P5 891 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 892 * ignored. 893 */ 894 895 /* do an INIT IPI: assert RESET */ 896 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 897 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id); 898 899 /* wait for pending status end */ 900 lapic_ipi_wait(-1); 901 902 /* do an INIT IPI: deassert RESET */ 903 lapic_ipi_raw(APIC_DEST_ALLESELF | APIC_TRIGMOD_LEVEL | 904 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, 0); 905 906 /* wait for pending status end */ 907 DELAY(10000); /* wait ~10mS */ 908 lapic_ipi_wait(-1); 909 910 /* 911 * next we do a STARTUP IPI: the previous INIT IPI might still be 912 * latched, (P5 bug) this 1st STARTUP would then terminate 913 * immediately, and the previously started INIT IPI would continue. OR 914 * the previous INIT IPI has already run. and this STARTUP IPI will 915 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 916 * will run. 917 */ 918 919 /* do a STARTUP IPI */ 920 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 921 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 922 vector, apic_id); 923 lapic_ipi_wait(-1); 924 DELAY(200); /* wait ~200uS */ 925 926 /* 927 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 928 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 929 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 930 * recognized after hardware RESET or INIT IPI. 931 */ 932 933 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 934 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 935 vector, apic_id); 936 lapic_ipi_wait(-1); 937 DELAY(200); /* wait ~200uS */ 938 939 /* Wait up to 5 seconds for it to start. */ 940 for (ms = 0; ms < 5000; ms++) { 941 if (mp_naps > cpus) 942 return 1; /* return SUCCESS */ 943 DELAY(1000); 944 } 945 return 0; /* return FAILURE */ 946} 947 948#ifdef COUNT_XINVLTLB_HITS 949u_int xhits_gbl[MAXCPU]; 950u_int xhits_pg[MAXCPU]; 951u_int xhits_rng[MAXCPU]; 952SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, ""); 953SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl, 954 sizeof(xhits_gbl), "IU", ""); 955SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg, 956 sizeof(xhits_pg), "IU", ""); 957SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng, 958 sizeof(xhits_rng), "IU", ""); 959 960u_int ipi_global; 961u_int ipi_page; 962u_int ipi_range; 963u_int ipi_range_size; 964SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, ""); 965SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, ""); 966SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, ""); 967SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size, 968 0, ""); 969 970u_int ipi_masked_global; 971u_int ipi_masked_page; 972u_int ipi_masked_range; 973u_int ipi_masked_range_size; 974SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW, 975 &ipi_masked_global, 0, ""); 976SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW, 977 &ipi_masked_page, 0, ""); 978SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW, 979 &ipi_masked_range, 0, ""); 980SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW, 981 &ipi_masked_range_size, 0, ""); 982#endif /* COUNT_XINVLTLB_HITS */ 983 984/* 985 * Flush the TLB on all other CPU's 986 */ 987static void 988smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2) 989{ 990 u_int ncpu; 991 992 ncpu = mp_ncpus - 1; /* does not shootdown self */ 993 if (ncpu < 1) 994 return; /* no other cpus */ 995 mtx_assert(&smp_ipi_mtx, MA_OWNED); 996 smp_tlb_addr1 = addr1; 997 smp_tlb_addr2 = addr2; 998 atomic_store_rel_int(&smp_tlb_wait, 0); 999 ipi_all_but_self(vector); 1000 while (smp_tlb_wait < ncpu) 1001 ia32_pause(); 1002} 1003 1004static void 1005smp_targeted_tlb_shootdown(u_int mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2) 1006{ 1007 int ncpu, othercpus; 1008 1009 othercpus = mp_ncpus - 1; 1010 if (mask == (u_int)-1) { 1011 ncpu = othercpus; 1012 if (ncpu < 1) 1013 return; 1014 } else { 1015 mask &= ~PCPU_GET(cpumask); 1016 if (mask == 0) 1017 return; 1018 ncpu = bitcount32(mask); 1019 if (ncpu > othercpus) { 1020 /* XXX this should be a panic offence */ 1021 printf("SMP: tlb shootdown to %d other cpus (only have %d)\n", 1022 ncpu, othercpus); 1023 ncpu = othercpus; 1024 } 1025 /* XXX should be a panic, implied by mask == 0 above */ 1026 if (ncpu < 1) 1027 return; 1028 } 1029 mtx_assert(&smp_ipi_mtx, MA_OWNED); 1030 smp_tlb_addr1 = addr1; 1031 smp_tlb_addr2 = addr2; 1032 atomic_store_rel_int(&smp_tlb_wait, 0); 1033 if (mask == (u_int)-1) 1034 ipi_all_but_self(vector); 1035 else 1036 ipi_selected(mask, vector); 1037 while (smp_tlb_wait < ncpu) 1038 ia32_pause(); 1039} 1040 1041void 1042smp_invltlb(void) 1043{ 1044 1045 if (smp_started) { 1046 smp_tlb_shootdown(IPI_INVLTLB, 0, 0); 1047#ifdef COUNT_XINVLTLB_HITS 1048 ipi_global++; 1049#endif 1050 } 1051} 1052 1053void 1054smp_invlpg(vm_offset_t addr) 1055{ 1056 1057 if (smp_started) { 1058 smp_tlb_shootdown(IPI_INVLPG, addr, 0); 1059#ifdef COUNT_XINVLTLB_HITS 1060 ipi_page++; 1061#endif 1062 } 1063} 1064 1065void 1066smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2) 1067{ 1068 1069 if (smp_started) { 1070 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2); 1071#ifdef COUNT_XINVLTLB_HITS 1072 ipi_range++; 1073 ipi_range_size += (addr2 - addr1) / PAGE_SIZE; 1074#endif 1075 } 1076} 1077 1078void 1079smp_masked_invltlb(u_int mask) 1080{ 1081 1082 if (smp_started) { 1083 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0); 1084#ifdef COUNT_XINVLTLB_HITS 1085 ipi_masked_global++; 1086#endif 1087 } 1088} 1089 1090void 1091smp_masked_invlpg(u_int mask, vm_offset_t addr) 1092{ 1093 1094 if (smp_started) { 1095 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0); 1096#ifdef COUNT_XINVLTLB_HITS 1097 ipi_masked_page++; 1098#endif 1099 } 1100} 1101 1102void 1103smp_masked_invlpg_range(u_int mask, vm_offset_t addr1, vm_offset_t addr2) 1104{ 1105 1106 if (smp_started) { 1107 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2); 1108#ifdef COUNT_XINVLTLB_HITS 1109 ipi_masked_range++; 1110 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE; 1111#endif 1112 } 1113} 1114 1115void 1116ipi_bitmap_handler(struct trapframe frame) 1117{ 1118 int cpu = PCPU_GET(cpuid); 1119 u_int ipi_bitmap; 1120 1121 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]); 1122 1123#ifdef IPI_PREEMPTION 1124 if (ipi_bitmap & IPI_PREEMPT) { 1125#ifdef COUNT_IPIS 1126 *ipi_preempt_counts[cpu]++; 1127#endif 1128 mtx_lock_spin(&sched_lock); 1129 /* Don't preempt the idle thread */ 1130 if (curthread->td_priority < PRI_MIN_IDLE) { 1131 struct thread *running_thread = curthread; 1132 if (running_thread->td_critnest > 1) 1133 running_thread->td_owepreempt = 1; 1134 else 1135 mi_switch(SW_INVOL | SW_PREEMPT, NULL); 1136 } 1137 mtx_unlock_spin(&sched_lock); 1138 } 1139#endif 1140 1141 if (ipi_bitmap & IPI_AST) { 1142#ifdef COUNT_IPIS 1143 *ipi_ast_counts[cpu]++; 1144#endif 1145 /* Nothing to do for AST */ 1146 } 1147} 1148 1149/* 1150 * send an IPI to a set of cpus. 1151 */ 1152void 1153ipi_selected(u_int32_t cpus, u_int ipi) 1154{ 1155 int cpu; 1156 u_int bitmap = 0; 1157 u_int old_pending; 1158 u_int new_pending; 1159 1160 if (IPI_IS_BITMAPED(ipi)) { 1161 bitmap = 1 << ipi; 1162 ipi = IPI_BITMAP_VECTOR; 1163 } 1164 1165#ifdef STOP_NMI 1166 if (ipi == IPI_STOP && stop_cpus_with_nmi) { 1167 ipi_nmi_selected(cpus); 1168 return; 1169 } 1170#endif 1171 CTR3(KTR_SMP, "%s: cpus: %x ipi: %x", __func__, cpus, ipi); 1172 while ((cpu = ffs(cpus)) != 0) { 1173 cpu--; 1174 cpus &= ~(1 << cpu); 1175 1176 KASSERT(cpu_apic_ids[cpu] != -1, 1177 ("IPI to non-existent CPU %d", cpu)); 1178 1179 if (bitmap) { 1180 do { 1181 old_pending = cpu_ipi_pending[cpu]; 1182 new_pending = old_pending | bitmap; 1183 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu],old_pending, new_pending)); 1184 1185 if (old_pending) 1186 continue; 1187 } 1188 1189 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]); 1190 } 1191 1192} 1193 1194/* 1195 * send an IPI INTerrupt containing 'vector' to all CPUs, including myself 1196 */ 1197void 1198ipi_all(u_int ipi) 1199{ 1200 1201 if (IPI_IS_BITMAPED(ipi) || (ipi == IPI_STOP && stop_cpus_with_nmi)) { 1202 ipi_selected(all_cpus, ipi); 1203 return; 1204 } 1205 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1206 lapic_ipi_vectored(ipi, APIC_IPI_DEST_ALL); 1207} 1208 1209/* 1210 * send an IPI to all CPUs EXCEPT myself 1211 */ 1212void 1213ipi_all_but_self(u_int ipi) 1214{ 1215 1216 if (IPI_IS_BITMAPED(ipi) || (ipi == IPI_STOP && stop_cpus_with_nmi)) { 1217 ipi_selected(PCPU_GET(other_cpus), ipi); 1218 return; 1219 } 1220 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1221 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS); 1222} 1223 1224/* 1225 * send an IPI to myself 1226 */ 1227void 1228ipi_self(u_int ipi) 1229{ 1230 1231 if (IPI_IS_BITMAPED(ipi) || (ipi == IPI_STOP && stop_cpus_with_nmi)) { 1232 ipi_selected(PCPU_GET(cpumask), ipi); 1233 return; 1234 } 1235 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1236 lapic_ipi_vectored(ipi, APIC_IPI_DEST_SELF); 1237} 1238 1239#ifdef STOP_NMI 1240/* 1241 * send NMI IPI to selected CPUs 1242 */ 1243 1244#define BEFORE_SPIN 1000000 1245 1246void 1247ipi_nmi_selected(u_int32_t cpus) 1248{ 1249 int cpu; 1250 register_t icrlo; 1251 1252 icrlo = APIC_DELMODE_NMI | APIC_DESTMODE_PHY | APIC_LEVEL_ASSERT 1253 | APIC_TRIGMOD_EDGE; 1254 1255 CTR2(KTR_SMP, "%s: cpus: %x nmi", __func__, cpus); 1256 1257 atomic_set_int(&ipi_nmi_pending, cpus); 1258 1259 while ((cpu = ffs(cpus)) != 0) { 1260 cpu--; 1261 cpus &= ~(1 << cpu); 1262 1263 KASSERT(cpu_apic_ids[cpu] != -1, 1264 ("IPI NMI to non-existent CPU %d", cpu)); 1265 1266 /* Wait for an earlier IPI to finish. */ 1267 if (!lapic_ipi_wait(BEFORE_SPIN)) 1268 panic("ipi_nmi_selected: previous IPI has not cleared"); 1269 1270 lapic_ipi_raw(icrlo, cpu_apic_ids[cpu]); 1271 } 1272} 1273 1274int 1275ipi_nmi_handler(void) 1276{ 1277 int cpumask = PCPU_GET(cpumask); 1278 1279 if (!(ipi_nmi_pending & cpumask)) 1280 return 1; 1281 1282 atomic_clear_int(&ipi_nmi_pending, cpumask); 1283 cpustop_handler(); 1284 return 0; 1285} 1286 1287#endif /* STOP_NMI */ 1288 1289/* 1290 * Handle an IPI_STOP by saving our current context and spinning until we 1291 * are resumed. 1292 */ 1293void 1294cpustop_handler(void) 1295{ 1296 int cpu = PCPU_GET(cpuid); 1297 int cpumask = PCPU_GET(cpumask); 1298 1299 savectx(&stoppcbs[cpu]); 1300 1301 /* Indicate that we are stopped */ 1302 atomic_set_int(&stopped_cpus, cpumask); 1303 1304 /* Wait for restart */ 1305 while (!(started_cpus & cpumask)) 1306 ia32_pause(); 1307 1308 atomic_clear_int(&started_cpus, cpumask); 1309 atomic_clear_int(&stopped_cpus, cpumask); 1310 1311 if (cpu == 0 && cpustop_restartfunc != NULL) { 1312 cpustop_restartfunc(); 1313 cpustop_restartfunc = NULL; 1314 } 1315} 1316 1317/* 1318 * This is called once the rest of the system is up and running and we're 1319 * ready to let the AP's out of the pen. 1320 */ 1321static void 1322release_aps(void *dummy __unused) 1323{ 1324 1325 if (mp_ncpus == 1) 1326 return; 1327 mtx_lock_spin(&sched_lock); 1328 atomic_store_rel_int(&aps_ready, 1); 1329 while (smp_started == 0) 1330 ia32_pause(); 1331 mtx_unlock_spin(&sched_lock); 1332} 1333SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL); 1334 1335static int 1336sysctl_hlt_cpus(SYSCTL_HANDLER_ARGS) 1337{ 1338 u_int mask; 1339 int error; 1340 1341 mask = hlt_cpus_mask; 1342 error = sysctl_handle_int(oidp, &mask, 0, req); 1343 if (error || !req->newptr) 1344 return (error); 1345 1346 if (logical_cpus_mask != 0 && 1347 (mask & logical_cpus_mask) == logical_cpus_mask) 1348 hlt_logical_cpus = 1; 1349 else 1350 hlt_logical_cpus = 0; 1351 1352 if (! hyperthreading_allowed) 1353 mask |= hyperthreading_cpus_mask; 1354 1355 if ((mask & all_cpus) == all_cpus) 1356 mask &= ~(1<<0); 1357 hlt_cpus_mask = mask; 1358 return (error); 1359} 1360SYSCTL_PROC(_machdep, OID_AUTO, hlt_cpus, CTLTYPE_INT|CTLFLAG_RW, 1361 0, 0, sysctl_hlt_cpus, "IU", 1362 "Bitmap of CPUs to halt. 101 (binary) will halt CPUs 0 and 2."); 1363 1364static int 1365sysctl_hlt_logical_cpus(SYSCTL_HANDLER_ARGS) 1366{ 1367 int disable, error; 1368 1369 disable = hlt_logical_cpus; 1370 error = sysctl_handle_int(oidp, &disable, 0, req); 1371 if (error || !req->newptr) 1372 return (error); 1373 1374 if (disable) 1375 hlt_cpus_mask |= logical_cpus_mask; 1376 else 1377 hlt_cpus_mask &= ~logical_cpus_mask; 1378 1379 if (! hyperthreading_allowed) 1380 hlt_cpus_mask |= hyperthreading_cpus_mask; 1381 1382 if ((hlt_cpus_mask & all_cpus) == all_cpus) 1383 hlt_cpus_mask &= ~(1<<0); 1384 1385 hlt_logical_cpus = disable; 1386 return (error); 1387} 1388 1389static int 1390sysctl_hyperthreading_allowed(SYSCTL_HANDLER_ARGS) 1391{ 1392 int allowed, error; 1393 1394 allowed = hyperthreading_allowed; 1395 error = sysctl_handle_int(oidp, &allowed, 0, req); 1396 if (error || !req->newptr) 1397 return (error); 1398 1399 if (allowed) 1400 hlt_cpus_mask &= ~hyperthreading_cpus_mask; 1401 else 1402 hlt_cpus_mask |= hyperthreading_cpus_mask; 1403 1404 if (logical_cpus_mask != 0 && 1405 (hlt_cpus_mask & logical_cpus_mask) == logical_cpus_mask) 1406 hlt_logical_cpus = 1; 1407 else 1408 hlt_logical_cpus = 0; 1409 1410 if ((hlt_cpus_mask & all_cpus) == all_cpus) 1411 hlt_cpus_mask &= ~(1<<0); 1412 1413 hyperthreading_allowed = allowed; 1414 return (error); 1415} 1416 1417static void 1418cpu_hlt_setup(void *dummy __unused) 1419{ 1420 1421 if (logical_cpus_mask != 0) { 1422 TUNABLE_INT_FETCH("machdep.hlt_logical_cpus", 1423 &hlt_logical_cpus); 1424 sysctl_ctx_init(&logical_cpu_clist); 1425 SYSCTL_ADD_PROC(&logical_cpu_clist, 1426 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1427 "hlt_logical_cpus", CTLTYPE_INT|CTLFLAG_RW, 0, 0, 1428 sysctl_hlt_logical_cpus, "IU", ""); 1429 SYSCTL_ADD_UINT(&logical_cpu_clist, 1430 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1431 "logical_cpus_mask", CTLTYPE_INT|CTLFLAG_RD, 1432 &logical_cpus_mask, 0, ""); 1433 1434 if (hlt_logical_cpus) 1435 hlt_cpus_mask |= logical_cpus_mask; 1436 1437 /* 1438 * If necessary for security purposes, force 1439 * hyperthreading off, regardless of the value 1440 * of hlt_logical_cpus. 1441 */ 1442 if (hyperthreading_cpus_mask) { 1443 TUNABLE_INT_FETCH("machdep.hyperthreading_allowed", 1444 &hyperthreading_allowed); 1445 SYSCTL_ADD_PROC(&logical_cpu_clist, 1446 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1447 "hyperthreading_allowed", CTLTYPE_INT|CTLFLAG_RW, 1448 0, 0, sysctl_hyperthreading_allowed, "IU", ""); 1449 if (! hyperthreading_allowed) 1450 hlt_cpus_mask |= hyperthreading_cpus_mask; 1451 } 1452 } 1453} 1454SYSINIT(cpu_hlt, SI_SUB_SMP, SI_ORDER_ANY, cpu_hlt_setup, NULL); 1455 1456int 1457mp_grab_cpu_hlt(void) 1458{ 1459 u_int mask = PCPU_GET(cpumask); 1460#ifdef MP_WATCHDOG 1461 u_int cpuid = PCPU_GET(cpuid); 1462#endif 1463 int retval; 1464 1465#ifdef MP_WATCHDOG 1466 ap_watchdog(cpuid); 1467#endif 1468 1469 retval = mask & hlt_cpus_mask; 1470 while (mask & hlt_cpus_mask) 1471 __asm __volatile("sti; hlt" : : : "memory"); 1472 return (retval); 1473} 1474 1475#ifdef COUNT_IPIS 1476/* 1477 * Setup interrupt counters for IPI handlers. 1478 */ 1479static void 1480mp_ipi_intrcnt(void *dummy) 1481{ 1482 char buf[64]; 1483 int i; 1484 1485 for (i = 0; i < mp_maxid; i++) { 1486 if (CPU_ABSENT(i)) 1487 continue; 1488 snprintf(buf, sizeof(buf), "cpu%d: invltlb", i); 1489 intrcnt_add(buf, &ipi_invltlb_counts[i]); 1490 snprintf(buf, sizeof(buf), "cpu%d: invlrng", i); 1491 intrcnt_add(buf, &ipi_invlrng_counts[i]); 1492 snprintf(buf, sizeof(buf), "cpu%d: invlpg", i); 1493 intrcnt_add(buf, &ipi_invlpg_counts[i]); 1494#ifdef IPI_PREEMPTION 1495 snprintf(buf, sizeof(buf), "cpu%d: preempt", i); 1496 intrcnt_add(buf, &ipi_preempt_counts[i]); 1497#endif 1498 snprintf(buf, sizeof(buf), "cpu%d: ast", i); 1499 intrcnt_add(buf, &ipi_ast_counts[i]); 1500 snprintf(buf, sizeof(buf), "cpu%d: rendezvous", i); 1501 intrcnt_add(buf, &ipi_rendezvous_counts[i]); 1502 snprintf(buf, sizeof(buf), "cpu%d: lazypmap", i); 1503 intrcnt_add(buf, &ipi_lazypmap_counts[i]); 1504 } 1505} 1506SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL) 1507#endif 1508