mp_x86.c revision 133145
1/*- 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26#include <sys/cdefs.h> 27__FBSDID("$FreeBSD: head/sys/i386/i386/mp_machdep.c 133145 2004-08-05 00:32:08Z rwatson $"); 28 29#include "opt_apic.h" 30#include "opt_cpu.h" 31#include "opt_kstack_pages.h" 32 33#if !defined(lint) 34#if !defined(SMP) 35#error How did you get here? 36#endif 37 38#if defined(I386_CPU) && !defined(COMPILING_LINT) 39#error SMP not supported with I386_CPU 40#endif 41#ifndef DEV_APIC 42#error The apic device is required for SMP, add "device apic" to your config file. 43#endif 44#if defined(CPU_DISABLE_CMPXCHG) && !defined(COMPILING_LINT) 45#error SMP not supported with CPU_DISABLE_CMPXCHG 46#endif 47#endif /* not lint */ 48 49#include <sys/param.h> 50#include <sys/systm.h> 51#include <sys/bus.h> 52#include <sys/cons.h> /* cngetc() */ 53#ifdef GPROF 54#include <sys/gmon.h> 55#endif 56#include <sys/kernel.h> 57#include <sys/ktr.h> 58#include <sys/lock.h> 59#include <sys/malloc.h> 60#include <sys/memrange.h> 61#include <sys/mutex.h> 62#include <sys/pcpu.h> 63#include <sys/proc.h> 64#include <sys/smp.h> 65#include <sys/sysctl.h> 66 67#include <vm/vm.h> 68#include <vm/vm_param.h> 69#include <vm/pmap.h> 70#include <vm/vm_kern.h> 71#include <vm/vm_extern.h> 72 73#include <machine/apicreg.h> 74#include <machine/clock.h> 75#include <machine/md_var.h> 76#include <machine/pcb.h> 77#include <machine/smp.h> 78#include <machine/smptests.h> /** COUNT_XINVLTLB_HITS */ 79#include <machine/specialreg.h> 80#include <machine/privatespace.h> 81 82#define WARMBOOT_TARGET 0 83#define WARMBOOT_OFF (KERNBASE + 0x0467) 84#define WARMBOOT_SEG (KERNBASE + 0x0469) 85 86#define CMOS_REG (0x70) 87#define CMOS_DATA (0x71) 88#define BIOS_RESET (0x0f) 89#define BIOS_WARM (0x0a) 90 91/* 92 * this code MUST be enabled here and in mpboot.s. 93 * it follows the very early stages of AP boot by placing values in CMOS ram. 94 * it NORMALLY will never be needed and thus the primitive method for enabling. 95 * 96#define CHECK_POINTS 97 */ 98 99#if defined(CHECK_POINTS) && !defined(PC98) 100#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 101#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 102 103#define CHECK_INIT(D); \ 104 CHECK_WRITE(0x34, (D)); \ 105 CHECK_WRITE(0x35, (D)); \ 106 CHECK_WRITE(0x36, (D)); \ 107 CHECK_WRITE(0x37, (D)); \ 108 CHECK_WRITE(0x38, (D)); \ 109 CHECK_WRITE(0x39, (D)); 110 111#define CHECK_PRINT(S); \ 112 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 113 (S), \ 114 CHECK_READ(0x34), \ 115 CHECK_READ(0x35), \ 116 CHECK_READ(0x36), \ 117 CHECK_READ(0x37), \ 118 CHECK_READ(0x38), \ 119 CHECK_READ(0x39)); 120 121#else /* CHECK_POINTS */ 122 123#define CHECK_INIT(D) 124#define CHECK_PRINT(S) 125#define CHECK_WRITE(A, D) 126 127#endif /* CHECK_POINTS */ 128 129/* 130 * Values to send to the POST hardware. 131 */ 132#define MP_BOOTADDRESS_POST 0x10 133#define MP_PROBE_POST 0x11 134#define MPTABLE_PASS1_POST 0x12 135 136#define MP_START_POST 0x13 137#define MP_ENABLE_POST 0x14 138#define MPTABLE_PASS2_POST 0x15 139 140#define START_ALL_APS_POST 0x16 141#define INSTALL_AP_TRAMP_POST 0x17 142#define START_AP_POST 0x18 143 144#define MP_ANNOUNCE_POST 0x19 145 146/* lock region used by kernel profiling */ 147int mcount_lock; 148 149/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ 150int current_postcode; 151 152int mp_naps; /* # of Applications processors */ 153int boot_cpu_id = -1; /* designated BSP */ 154extern int nkpt; 155 156/* 157 * CPU topology map datastructures for HTT. 158 */ 159static struct cpu_group mp_groups[MAXCPU]; 160static struct cpu_top mp_top; 161 162/* AP uses this during bootstrap. Do not staticize. */ 163char *bootSTK; 164static int bootAP; 165 166/* Hotwire a 0->4MB V==P mapping */ 167extern pt_entry_t *KPTphys; 168 169/* SMP page table page */ 170extern pt_entry_t *SMPpt; 171 172struct pcb stoppcbs[MAXCPU]; 173 174/* Variables needed for SMP tlb shootdown. */ 175vm_offset_t smp_tlb_addr1; 176vm_offset_t smp_tlb_addr2; 177volatile int smp_tlb_wait; 178struct mtx smp_tlb_mtx; 179 180/* 181 * Local data and functions. 182 */ 183 184static u_int logical_cpus; 185static u_int logical_cpus_mask; 186 187/* used to hold the AP's until we are ready to release them */ 188static struct mtx ap_boot_mtx; 189 190/* Set to 1 once we're ready to let the APs out of the pen. */ 191static volatile int aps_ready = 0; 192 193/* 194 * Store data from cpu_add() until later in the boot when we actually setup 195 * the APs. 196 */ 197struct cpu_info { 198 int cpu_present:1; 199 int cpu_bsp:1; 200} static cpu_info[MAXCPU]; 201static int cpu_apic_ids[MAXCPU]; 202 203static u_int boot_address; 204 205static void set_logical_apic_ids(void); 206static int start_all_aps(void); 207static void install_ap_tramp(void); 208static int start_ap(int apic_id); 209static void release_aps(void *dummy); 210 211static int hlt_cpus_mask; 212static int hlt_logical_cpus; 213static struct sysctl_ctx_list logical_cpu_clist; 214 215static void 216mem_range_AP_init(void) 217{ 218 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP) 219 mem_range_softc.mr_op->initAP(&mem_range_softc); 220} 221 222void 223mp_topology(void) 224{ 225 struct cpu_group *group; 226 int logical_cpus; 227 int apic_id; 228 int groups; 229 int cpu; 230 231 /* Build the smp_topology map. */ 232 /* Nothing to do if there is no HTT support. */ 233 if ((cpu_feature & CPUID_HTT) == 0) 234 return; 235 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 236 if (logical_cpus <= 1) 237 return; 238 group = &mp_groups[0]; 239 groups = 1; 240 for (cpu = 0, apic_id = 0; apic_id < MAXCPU; apic_id++) { 241 if (!cpu_info[apic_id].cpu_present) 242 continue; 243 /* 244 * If the current group has members and we're not a logical 245 * cpu, create a new group. 246 */ 247 if (group->cg_count != 0 && (apic_id % logical_cpus) == 0) { 248 group++; 249 groups++; 250 } 251 group->cg_count++; 252 group->cg_mask |= 1 << cpu; 253 cpu++; 254 } 255 256 mp_top.ct_count = groups; 257 mp_top.ct_group = mp_groups; 258 smp_topology = &mp_top; 259} 260 261 262/* 263 * Calculate usable address in base memory for AP trampoline code. 264 */ 265u_int 266mp_bootaddress(u_int basemem) 267{ 268 POSTCODE(MP_BOOTADDRESS_POST); 269 270 boot_address = trunc_page(basemem); /* round down to 4k boundary */ 271 if ((basemem - boot_address) < bootMP_size) 272 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */ 273 274 return boot_address; 275} 276 277void 278cpu_add(u_int apic_id, char boot_cpu) 279{ 280 281 if (apic_id >= MAXCPU) { 282 printf("SMP: CPU %d exceeds maximum CPU %d, ignoring\n", 283 apic_id, MAXCPU - 1); 284 return; 285 } 286 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice", 287 apic_id)); 288 cpu_info[apic_id].cpu_present = 1; 289 if (boot_cpu) { 290 KASSERT(boot_cpu_id == -1, 291 ("CPU %d claims to be BSP, but CPU %d already is", apic_id, 292 boot_cpu_id)); 293 boot_cpu_id = apic_id; 294 cpu_info[apic_id].cpu_bsp = 1; 295 } 296 mp_ncpus++; 297 if (bootverbose) 298 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" : 299 "AP"); 300 301} 302 303void 304cpu_mp_setmaxid(void) 305{ 306 307 mp_maxid = MAXCPU - 1; 308} 309 310int 311cpu_mp_probe(void) 312{ 313 314 /* 315 * Always record BSP in CPU map so that the mbuf init code works 316 * correctly. 317 */ 318 all_cpus = 1; 319 if (mp_ncpus == 0) { 320 /* 321 * No CPUs were found, so this must be a UP system. Setup 322 * the variables to represent a system with a single CPU 323 * with an id of 0. 324 */ 325 mp_ncpus = 1; 326 return (0); 327 } 328 329 /* At least one CPU was found. */ 330 if (mp_ncpus == 1) { 331 /* 332 * One CPU was found, so this must be a UP system with 333 * an I/O APIC. 334 */ 335 return (0); 336 } 337 338 /* At least two CPUs were found. */ 339 return (1); 340} 341 342/* 343 * Initialize the IPI handlers and start up the AP's. 344 */ 345void 346cpu_mp_start(void) 347{ 348 int i; 349 350 POSTCODE(MP_START_POST); 351 352 /* Initialize the logical ID to APIC ID table. */ 353 for (i = 0; i < MAXCPU; i++) 354 cpu_apic_ids[i] = -1; 355 356 /* Install an inter-CPU IPI for TLB invalidation */ 357 setidt(IPI_INVLTLB, IDTVEC(invltlb), 358 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 359 setidt(IPI_INVLPG, IDTVEC(invlpg), 360 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 361 setidt(IPI_INVLRNG, IDTVEC(invlrng), 362 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 363 364 /* Install an inter-CPU IPI for forwarding hardclock() */ 365 setidt(IPI_HARDCLOCK, IDTVEC(hardclock), 366 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 367 368 /* Install an inter-CPU IPI for forwarding statclock() */ 369 setidt(IPI_STATCLOCK, IDTVEC(statclock), 370 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 371 372 /* Install an inter-CPU IPI for lazy pmap release */ 373 setidt(IPI_LAZYPMAP, IDTVEC(lazypmap), 374 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 375 376 /* Install an inter-CPU IPI for all-CPU rendezvous */ 377 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous), 378 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 379 380 /* Install an inter-CPU IPI for forcing an additional software trap */ 381 setidt(IPI_AST, IDTVEC(cpuast), 382 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 383 384 /* Install an inter-CPU IPI for CPU stop/restart */ 385 setidt(IPI_STOP, IDTVEC(cpustop), 386 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 387 388 mtx_init(&smp_tlb_mtx, "tlb", NULL, MTX_SPIN); 389 390 /* Set boot_cpu_id if needed. */ 391 if (boot_cpu_id == -1) { 392 boot_cpu_id = PCPU_GET(apic_id); 393 cpu_info[boot_cpu_id].cpu_bsp = 1; 394 } else 395 KASSERT(boot_cpu_id == PCPU_GET(apic_id), 396 ("BSP's APIC ID doesn't match boot_cpu_id")); 397 cpu_apic_ids[0] = boot_cpu_id; 398 399 /* Start each Application Processor */ 400 start_all_aps(); 401 402 /* Setup the initial logical CPUs info. */ 403 logical_cpus = logical_cpus_mask = 0; 404 if (cpu_feature & CPUID_HTT) 405 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 406 407 set_logical_apic_ids(); 408} 409 410 411/* 412 * Print various information about the SMP system hardware and setup. 413 */ 414void 415cpu_mp_announce(void) 416{ 417 int i, x; 418 419 POSTCODE(MP_ANNOUNCE_POST); 420 421 /* List CPUs */ 422 printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id); 423 for (i = 1, x = 0; x < MAXCPU; x++) { 424 if (cpu_info[x].cpu_present && !cpu_info[x].cpu_bsp) { 425 KASSERT(i < mp_ncpus, 426 ("mp_ncpus and actual cpus are out of whack")); 427 printf(" cpu%d (AP): APIC ID: %2d\n", i++, x); 428 } 429 } 430} 431 432/* 433 * AP CPU's call this to initialize themselves. 434 */ 435void 436init_secondary(void) 437{ 438 int gsel_tss; 439 int x, myid; 440 u_int cr0; 441 442 /* bootAP is set in start_ap() to our ID. */ 443 myid = bootAP; 444 gdt_segs[GPRIV_SEL].ssd_base = (int) &SMP_prvspace[myid]; 445 gdt_segs[GPROC0_SEL].ssd_base = 446 (int) &SMP_prvspace[myid].pcpu.pc_common_tss; 447 SMP_prvspace[myid].pcpu.pc_prvspace = 448 &SMP_prvspace[myid].pcpu; 449 450 for (x = 0; x < NGDT; x++) { 451 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd); 452 } 453 454 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 455 r_gdt.rd_base = (int) &gdt[myid * NGDT]; 456 lgdt(&r_gdt); /* does magic intra-segment return */ 457 458 lidt(&r_idt); 459 460 lldt(_default_ldt); 461 PCPU_SET(currentldt, _default_ldt); 462 463 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 464 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS; 465 PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */ 466 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL)); 467 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16); 468 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd); 469 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt)); 470 ltr(gsel_tss); 471 472 /* 473 * Set to a known state: 474 * Set by mpboot.s: CR0_PG, CR0_PE 475 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM 476 */ 477 cr0 = rcr0(); 478 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM); 479 load_cr0(cr0); 480 CHECK_WRITE(0x38, 5); 481 482 /* Disable local APIC just to be sure. */ 483 lapic_disable(); 484 485 /* signal our startup to the BSP. */ 486 mp_naps++; 487 CHECK_WRITE(0x39, 6); 488 489 /* Spin until the BSP releases the AP's. */ 490 while (!aps_ready) 491 ia32_pause(); 492 493 /* BSP may have changed PTD while we were waiting */ 494 invltlb(); 495 pmap_invalidate_range(kernel_pmap, 0, NKPT * NBPDR - 1); 496 497#if defined(I586_CPU) && !defined(NO_F00F_HACK) 498 lidt(&r_idt); 499#endif 500 501 /* set up CPU registers and state */ 502 cpu_setregs(); 503 504 /* set up FPU state on the AP */ 505 npxinit(__INITIAL_NPXCW__); 506 507 /* set up SSE registers */ 508 enable_sse(); 509 510 /* A quick check from sanity claus */ 511 if (PCPU_GET(apic_id) != lapic_id()) { 512 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid)); 513 printf("SMP: actual apic_id = %d\n", lapic_id()); 514 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id)); 515 printf("PTD[MPPTDI] = %#jx\n", (uintmax_t)PTD[MPPTDI]); 516 panic("cpuid mismatch! boom!!"); 517 } 518 519 mtx_lock_spin(&ap_boot_mtx); 520 521 /* Init local apic for irq's */ 522 lapic_setup(); 523 524 /* Set memory range attributes for this CPU to match the BSP */ 525 mem_range_AP_init(); 526 527 smp_cpus++; 528 529 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", PCPU_GET(cpuid)); 530 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid)); 531 532 /* Determine if we are a logical CPU. */ 533 if (logical_cpus > 1 && PCPU_GET(apic_id) % logical_cpus != 0) 534 logical_cpus_mask |= PCPU_GET(cpumask); 535 536 /* Build our map of 'other' CPUs. */ 537 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 538 539 if (bootverbose) 540 lapic_dump("AP"); 541 542 if (smp_cpus == mp_ncpus) { 543 /* enable IPI's, tlb shootdown, freezes etc */ 544 atomic_store_rel_int(&smp_started, 1); 545 smp_active = 1; /* historic */ 546 } 547 548 mtx_unlock_spin(&ap_boot_mtx); 549 550 /* wait until all the AP's are up */ 551 while (smp_started == 0) 552 ia32_pause(); 553 554 /* ok, now grab sched_lock and enter the scheduler */ 555 mtx_lock_spin(&sched_lock); 556 557 binuptime(PCPU_PTR(switchtime)); 558 PCPU_SET(switchticks, ticks); 559 560 cpu_throw(NULL, choosethread()); /* doesn't return */ 561 562 panic("scheduler returned us to %s", __func__); 563 /* NOTREACHED */ 564} 565 566/******************************************************************* 567 * local functions and data 568 */ 569 570/* 571 * Set the APIC logical IDs. 572 * 573 * We want to cluster logical CPU's within the same APIC ID cluster. 574 * Since logical CPU's are aligned simply filling in the clusters in 575 * APIC ID order works fine. Note that this does not try to balance 576 * the number of CPU's in each cluster. (XXX?) 577 */ 578static void 579set_logical_apic_ids(void) 580{ 581 u_int apic_id, cluster, cluster_id; 582 583 /* Force us to allocate cluster 0 at the start. */ 584 cluster = -1; 585 cluster_id = APIC_MAX_INTRACLUSTER_ID; 586 for (apic_id = 0; apic_id < MAXCPU; apic_id++) { 587 if (!cpu_info[apic_id].cpu_present) 588 continue; 589 if (cluster_id == APIC_MAX_INTRACLUSTER_ID) { 590 cluster = ioapic_next_logical_cluster(); 591 cluster_id = 0; 592 } else 593 cluster_id++; 594 if (bootverbose) 595 printf("APIC ID: physical %u, logical %u:%u\n", 596 apic_id, cluster, cluster_id); 597 lapic_set_logical_id(apic_id, cluster, cluster_id); 598 } 599} 600 601/* 602 * start each AP in our list 603 */ 604static int 605start_all_aps(void) 606{ 607#ifndef PC98 608 u_char mpbiosreason; 609#endif 610 u_long mpbioswarmvec; 611 struct pcpu *pc; 612 char *stack; 613 uintptr_t kptbase; 614 int i, pg, apic_id, cpu; 615 616 POSTCODE(START_ALL_APS_POST); 617 618 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); 619 620 /* install the AP 1st level boot code */ 621 install_ap_tramp(); 622 623 /* save the current value of the warm-start vector */ 624 mpbioswarmvec = *((u_long *) WARMBOOT_OFF); 625#ifndef PC98 626 outb(CMOS_REG, BIOS_RESET); 627 mpbiosreason = inb(CMOS_DATA); 628#endif 629 630 /* set up temporary P==V mapping for AP boot */ 631 /* XXX this is a hack, we should boot the AP on its own stack/PTD */ 632 kptbase = (uintptr_t)(void *)KPTphys; 633 for (i = 0; i < NKPT; i++) 634 PTD[i] = (pd_entry_t)(PG_V | PG_RW | 635 ((kptbase + i * PAGE_SIZE) & PG_FRAME)); 636 invltlb(); 637 638 /* start each AP */ 639 for (cpu = 0, apic_id = 0; apic_id < MAXCPU; apic_id++) { 640 if (!cpu_info[apic_id].cpu_present || 641 cpu_info[apic_id].cpu_bsp) 642 continue; 643 cpu++; 644 645 /* save APIC ID for this logical ID */ 646 cpu_apic_ids[cpu] = apic_id; 647 648 /* first page of AP's private space */ 649 pg = cpu * i386_btop(sizeof(struct privatespace)); 650 651 /* allocate a new private data page */ 652 pc = (struct pcpu *)kmem_alloc(kernel_map, PAGE_SIZE); 653 654 /* wire it into the private page table page */ 655 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys(pc)); 656 657 /* allocate and set up an idle stack data page */ 658 stack = (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE); /* XXXKSE */ 659 for (i = 0; i < KSTACK_PAGES; i++) 660 SMPpt[pg + 1 + i] = (pt_entry_t) 661 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 662 663 /* prime data page for it to use */ 664 pcpu_init(pc, cpu, sizeof(struct pcpu)); 665 pc->pc_apic_id = apic_id; 666 667 /* setup a vector to our boot code */ 668 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 669 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4); 670#ifndef PC98 671 outb(CMOS_REG, BIOS_RESET); 672 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 673#endif 674 675 bootSTK = &SMP_prvspace[cpu].idlekstack[KSTACK_PAGES * 676 PAGE_SIZE]; 677 bootAP = cpu; 678 679 /* attempt to start the Application Processor */ 680 CHECK_INIT(99); /* setup checkpoints */ 681 if (!start_ap(apic_id)) { 682 printf("AP #%d (PHY# %d) failed!\n", cpu, apic_id); 683 CHECK_PRINT("trace"); /* show checkpoints */ 684 /* better panic as the AP may be running loose */ 685 printf("panic y/n? [y] "); 686 if (cngetc() != 'n') 687 panic("bye-bye"); 688 } 689 CHECK_PRINT("trace"); /* show checkpoints */ 690 691 all_cpus |= (1 << cpu); /* record AP in CPU map */ 692 } 693 694 /* build our map of 'other' CPUs */ 695 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 696 697 /* restore the warmstart vector */ 698 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 699#ifndef PC98 700 outb(CMOS_REG, BIOS_RESET); 701 outb(CMOS_DATA, mpbiosreason); 702#endif 703 704 /* 705 * Set up the idle context for the BSP. Similar to above except 706 * that some was done by locore, some by pmap.c and some is implicit 707 * because the BSP is cpu#0 and the page is initially zero and also 708 * because we can refer to variables by name on the BSP.. 709 */ 710 711 /* Allocate and setup BSP idle stack */ 712 stack = (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE); 713 for (i = 0; i < KSTACK_PAGES; i++) 714 SMPpt[1 + i] = (pt_entry_t) 715 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 716 717 for (i = 0; i < NKPT; i++) 718 PTD[i] = 0; 719 pmap_invalidate_range(kernel_pmap, 0, NKPT * NBPDR - 1); 720 721 /* number of APs actually started */ 722 return mp_naps; 723} 724 725/* 726 * load the 1st level AP boot code into base memory. 727 */ 728 729/* targets for relocation */ 730extern void bigJump(void); 731extern void bootCodeSeg(void); 732extern void bootDataSeg(void); 733extern void MPentry(void); 734extern u_int MP_GDT; 735extern u_int mp_gdtbase; 736 737static void 738install_ap_tramp(void) 739{ 740 int x; 741 int size = *(int *) ((u_long) & bootMP_size); 742 u_char *src = (u_char *) ((u_long) bootMP); 743 u_char *dst = (u_char *) boot_address + KERNBASE; 744 u_int boot_base = (u_int) bootMP; 745 u_int8_t *dst8; 746 u_int16_t *dst16; 747 u_int32_t *dst32; 748 749 POSTCODE(INSTALL_AP_TRAMP_POST); 750 751 pmap_kenter(boot_address + KERNBASE, boot_address); 752 for (x = 0; x < size; ++x) 753 *dst++ = *src++; 754 755 /* 756 * modify addresses in code we just moved to basemem. unfortunately we 757 * need fairly detailed info about mpboot.s for this to work. changes 758 * to mpboot.s might require changes here. 759 */ 760 761 /* boot code is located in KERNEL space */ 762 dst = (u_char *) boot_address + KERNBASE; 763 764 /* modify the lgdt arg */ 765 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 766 *dst32 = boot_address + ((u_int) & MP_GDT - boot_base); 767 768 /* modify the ljmp target for MPentry() */ 769 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 770 *dst32 = ((u_int) MPentry - KERNBASE); 771 772 /* modify the target for boot code segment */ 773 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 774 dst8 = (u_int8_t *) (dst16 + 1); 775 *dst16 = (u_int) boot_address & 0xffff; 776 *dst8 = ((u_int) boot_address >> 16) & 0xff; 777 778 /* modify the target for boot data segment */ 779 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 780 dst8 = (u_int8_t *) (dst16 + 1); 781 *dst16 = (u_int) boot_address & 0xffff; 782 *dst8 = ((u_int) boot_address >> 16) & 0xff; 783} 784 785/* 786 * This function starts the AP (application processor) identified 787 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 788 * to accomplish this. This is necessary because of the nuances 789 * of the different hardware we might encounter. It isn't pretty, 790 * but it seems to work. 791 */ 792static int 793start_ap(int apic_id) 794{ 795 int vector, ms; 796 int cpus; 797 798 POSTCODE(START_AP_POST); 799 800 /* calculate the vector */ 801 vector = (boot_address >> 12) & 0xff; 802 803 /* used as a watchpoint to signal AP startup */ 804 cpus = mp_naps; 805 806 /* 807 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 808 * and running the target CPU. OR this INIT IPI might be latched (P5 809 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 810 * ignored. 811 */ 812 813 /* do an INIT IPI: assert RESET */ 814 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 815 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id); 816 817 /* wait for pending status end */ 818 lapic_ipi_wait(-1); 819 820 /* do an INIT IPI: deassert RESET */ 821 lapic_ipi_raw(APIC_DEST_ALLESELF | APIC_TRIGMOD_LEVEL | 822 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, 0); 823 824 /* wait for pending status end */ 825 DELAY(10000); /* wait ~10mS */ 826 lapic_ipi_wait(-1); 827 828 /* 829 * next we do a STARTUP IPI: the previous INIT IPI might still be 830 * latched, (P5 bug) this 1st STARTUP would then terminate 831 * immediately, and the previously started INIT IPI would continue. OR 832 * the previous INIT IPI has already run. and this STARTUP IPI will 833 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 834 * will run. 835 */ 836 837 /* do a STARTUP IPI */ 838 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 839 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 840 vector, apic_id); 841 lapic_ipi_wait(-1); 842 DELAY(200); /* wait ~200uS */ 843 844 /* 845 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 846 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 847 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 848 * recognized after hardware RESET or INIT IPI. 849 */ 850 851 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 852 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 853 vector, apic_id); 854 lapic_ipi_wait(-1); 855 DELAY(200); /* wait ~200uS */ 856 857 /* Wait up to 5 seconds for it to start. */ 858 for (ms = 0; ms < 5000; ms++) { 859 if (mp_naps > cpus) 860 return 1; /* return SUCCESS */ 861 DELAY(1000); 862 } 863 return 0; /* return FAILURE */ 864} 865 866#ifdef COUNT_XINVLTLB_HITS 867u_int xhits_gbl[MAXCPU]; 868u_int xhits_pg[MAXCPU]; 869u_int xhits_rng[MAXCPU]; 870SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, ""); 871SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl, 872 sizeof(xhits_gbl), "IU", ""); 873SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg, 874 sizeof(xhits_pg), "IU", ""); 875SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng, 876 sizeof(xhits_rng), "IU", ""); 877 878u_int ipi_global; 879u_int ipi_page; 880u_int ipi_range; 881u_int ipi_range_size; 882SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, ""); 883SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, ""); 884SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, ""); 885SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size, 886 0, ""); 887 888u_int ipi_masked_global; 889u_int ipi_masked_page; 890u_int ipi_masked_range; 891u_int ipi_masked_range_size; 892SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW, 893 &ipi_masked_global, 0, ""); 894SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW, 895 &ipi_masked_page, 0, ""); 896SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW, 897 &ipi_masked_range, 0, ""); 898SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW, 899 &ipi_masked_range_size, 0, ""); 900#endif /* COUNT_XINVLTLB_HITS */ 901 902/* 903 * Flush the TLB on all other CPU's 904 */ 905static void 906smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2) 907{ 908 u_int ncpu; 909 910 ncpu = mp_ncpus - 1; /* does not shootdown self */ 911 if (ncpu < 1) 912 return; /* no other cpus */ 913 mtx_assert(&smp_tlb_mtx, MA_OWNED); 914 smp_tlb_addr1 = addr1; 915 smp_tlb_addr2 = addr2; 916 atomic_store_rel_int(&smp_tlb_wait, 0); 917 ipi_all_but_self(vector); 918 while (smp_tlb_wait < ncpu) 919 ia32_pause(); 920} 921 922/* 923 * This is about as magic as it gets. fortune(1) has got similar code 924 * for reversing bits in a word. Who thinks up this stuff?? 925 * 926 * Yes, it does appear to be consistently faster than: 927 * while (i = ffs(m)) { 928 * m >>= i; 929 * bits++; 930 * } 931 * and 932 * while (lsb = (m & -m)) { // This is magic too 933 * m &= ~lsb; // or: m ^= lsb 934 * bits++; 935 * } 936 * Both of these latter forms do some very strange things on gcc-3.1 with 937 * -mcpu=pentiumpro and/or -march=pentiumpro and/or -O or -O2. 938 * There is probably an SSE or MMX popcnt instruction. 939 * 940 * I wonder if this should be in libkern? 941 * 942 * XXX Stop the presses! Another one: 943 * static __inline u_int32_t 944 * popcnt1(u_int32_t v) 945 * { 946 * v -= ((v >> 1) & 0x55555555); 947 * v = (v & 0x33333333) + ((v >> 2) & 0x33333333); 948 * v = (v + (v >> 4)) & 0x0F0F0F0F; 949 * return (v * 0x01010101) >> 24; 950 * } 951 * The downside is that it has a multiply. With a pentium3 with 952 * -mcpu=pentiumpro and -march=pentiumpro then gcc-3.1 will use 953 * an imull, and in that case it is faster. In most other cases 954 * it appears slightly slower. 955 * 956 * Another variant (also from fortune): 957 * #define BITCOUNT(x) (((BX_(x)+(BX_(x)>>4)) & 0x0F0F0F0F) % 255) 958 * #define BX_(x) ((x) - (((x)>>1)&0x77777777) \ 959 * - (((x)>>2)&0x33333333) \ 960 * - (((x)>>3)&0x11111111)) 961 */ 962static __inline u_int32_t 963popcnt(u_int32_t m) 964{ 965 966 m = (m & 0x55555555) + ((m & 0xaaaaaaaa) >> 1); 967 m = (m & 0x33333333) + ((m & 0xcccccccc) >> 2); 968 m = (m & 0x0f0f0f0f) + ((m & 0xf0f0f0f0) >> 4); 969 m = (m & 0x00ff00ff) + ((m & 0xff00ff00) >> 8); 970 m = (m & 0x0000ffff) + ((m & 0xffff0000) >> 16); 971 return m; 972} 973 974static void 975smp_targeted_tlb_shootdown(u_int mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2) 976{ 977 int ncpu, othercpus; 978 979 othercpus = mp_ncpus - 1; 980 if (mask == (u_int)-1) { 981 ncpu = othercpus; 982 if (ncpu < 1) 983 return; 984 } else { 985 mask &= ~PCPU_GET(cpumask); 986 if (mask == 0) 987 return; 988 ncpu = popcnt(mask); 989 if (ncpu > othercpus) { 990 /* XXX this should be a panic offence */ 991 printf("SMP: tlb shootdown to %d other cpus (only have %d)\n", 992 ncpu, othercpus); 993 ncpu = othercpus; 994 } 995 /* XXX should be a panic, implied by mask == 0 above */ 996 if (ncpu < 1) 997 return; 998 } 999 mtx_assert(&smp_tlb_mtx, MA_OWNED); 1000 smp_tlb_addr1 = addr1; 1001 smp_tlb_addr2 = addr2; 1002 atomic_store_rel_int(&smp_tlb_wait, 0); 1003 if (mask == (u_int)-1) 1004 ipi_all_but_self(vector); 1005 else 1006 ipi_selected(mask, vector); 1007 while (smp_tlb_wait < ncpu) 1008 ia32_pause(); 1009} 1010 1011void 1012smp_invltlb(void) 1013{ 1014 if (smp_started) { 1015 smp_tlb_shootdown(IPI_INVLTLB, 0, 0); 1016#ifdef COUNT_XINVLTLB_HITS 1017 ipi_global++; 1018#endif 1019 } 1020} 1021 1022void 1023smp_invlpg(vm_offset_t addr) 1024{ 1025 if (smp_started) { 1026 smp_tlb_shootdown(IPI_INVLPG, addr, 0); 1027#ifdef COUNT_XINVLTLB_HITS 1028 ipi_page++; 1029#endif 1030 } 1031} 1032 1033void 1034smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2) 1035{ 1036 if (smp_started) { 1037 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2); 1038#ifdef COUNT_XINVLTLB_HITS 1039 ipi_range++; 1040 ipi_range_size += (addr2 - addr1) / PAGE_SIZE; 1041#endif 1042 } 1043} 1044 1045void 1046smp_masked_invltlb(u_int mask) 1047{ 1048 if (smp_started) { 1049 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0); 1050#ifdef COUNT_XINVLTLB_HITS 1051 ipi_masked_global++; 1052#endif 1053 } 1054} 1055 1056void 1057smp_masked_invlpg(u_int mask, vm_offset_t addr) 1058{ 1059 if (smp_started) { 1060 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0); 1061#ifdef COUNT_XINVLTLB_HITS 1062 ipi_masked_page++; 1063#endif 1064 } 1065} 1066 1067void 1068smp_masked_invlpg_range(u_int mask, vm_offset_t addr1, vm_offset_t addr2) 1069{ 1070 if (smp_started) { 1071 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2); 1072#ifdef COUNT_XINVLTLB_HITS 1073 ipi_masked_range++; 1074 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE; 1075#endif 1076 } 1077} 1078 1079 1080/* 1081 * For statclock, we send an IPI to all CPU's to have them call this 1082 * function. 1083 */ 1084void 1085forwarded_statclock(struct clockframe frame) 1086{ 1087 struct thread *td; 1088 1089 CTR0(KTR_SMP, "forwarded_statclock"); 1090 td = curthread; 1091 td->td_intr_nesting_level++; 1092 if (profprocs != 0) 1093 profclock(&frame); 1094 if (pscnt == psdiv) 1095 statclock(&frame); 1096 td->td_intr_nesting_level--; 1097} 1098 1099void 1100forward_statclock(void) 1101{ 1102 int map; 1103 1104 CTR0(KTR_SMP, "forward_statclock"); 1105 1106 if (!smp_started || cold || panicstr) 1107 return; 1108 1109 map = PCPU_GET(other_cpus) & ~(stopped_cpus|hlt_cpus_mask); 1110 if (map != 0) 1111 ipi_selected(map, IPI_STATCLOCK); 1112} 1113 1114/* 1115 * For each hardclock(), we send an IPI to all other CPU's to have them 1116 * execute this function. It would be nice to reduce contention on 1117 * sched_lock if we could simply peek at the CPU to determine the user/kernel 1118 * state and call hardclock_process() on the CPU receiving the clock interrupt 1119 * and then just use a simple IPI to handle any ast's if needed. 1120 */ 1121void 1122forwarded_hardclock(struct clockframe frame) 1123{ 1124 struct thread *td; 1125 1126 CTR0(KTR_SMP, "forwarded_hardclock"); 1127 td = curthread; 1128 td->td_intr_nesting_level++; 1129 hardclock_process(&frame); 1130 td->td_intr_nesting_level--; 1131} 1132 1133void 1134forward_hardclock(void) 1135{ 1136 u_int map; 1137 1138 CTR0(KTR_SMP, "forward_hardclock"); 1139 1140 if (!smp_started || cold || panicstr) 1141 return; 1142 1143 map = PCPU_GET(other_cpus) & ~(stopped_cpus|hlt_cpus_mask); 1144 if (map != 0) 1145 ipi_selected(map, IPI_HARDCLOCK); 1146} 1147 1148/* 1149 * send an IPI to a set of cpus. 1150 */ 1151void 1152ipi_selected(u_int32_t cpus, u_int ipi) 1153{ 1154 int cpu; 1155 1156 CTR3(KTR_SMP, "%s: cpus: %x ipi: %x", __func__, cpus, ipi); 1157 while ((cpu = ffs(cpus)) != 0) { 1158 cpu--; 1159 KASSERT(cpu_apic_ids[cpu] != -1, 1160 ("IPI to non-existent CPU %d", cpu)); 1161 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]); 1162 cpus &= ~(1 << cpu); 1163 } 1164} 1165 1166/* 1167 * send an IPI INTerrupt containing 'vector' to all CPUs, including myself 1168 */ 1169void 1170ipi_all(u_int ipi) 1171{ 1172 1173 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1174 lapic_ipi_vectored(ipi, APIC_IPI_DEST_ALL); 1175} 1176 1177/* 1178 * send an IPI to all CPUs EXCEPT myself 1179 */ 1180void 1181ipi_all_but_self(u_int ipi) 1182{ 1183 1184 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1185 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS); 1186} 1187 1188/* 1189 * send an IPI to myself 1190 */ 1191void 1192ipi_self(u_int ipi) 1193{ 1194 1195 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1196 lapic_ipi_vectored(ipi, APIC_IPI_DEST_SELF); 1197} 1198 1199/* 1200 * This is called once the rest of the system is up and running and we're 1201 * ready to let the AP's out of the pen. 1202 */ 1203static void 1204release_aps(void *dummy __unused) 1205{ 1206 1207 if (mp_ncpus == 1) 1208 return; 1209 mtx_lock_spin(&sched_lock); 1210 atomic_store_rel_int(&aps_ready, 1); 1211 while (smp_started == 0) 1212 ia32_pause(); 1213 mtx_unlock_spin(&sched_lock); 1214} 1215SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL); 1216 1217static int 1218sysctl_hlt_cpus(SYSCTL_HANDLER_ARGS) 1219{ 1220 u_int mask; 1221 int error; 1222 1223 mask = hlt_cpus_mask; 1224 error = sysctl_handle_int(oidp, &mask, 0, req); 1225 if (error || !req->newptr) 1226 return (error); 1227 1228 if (logical_cpus_mask != 0 && 1229 (mask & logical_cpus_mask) == logical_cpus_mask) 1230 hlt_logical_cpus = 1; 1231 else 1232 hlt_logical_cpus = 0; 1233 1234 if ((mask & all_cpus) == all_cpus) 1235 mask &= ~(1<<0); 1236 hlt_cpus_mask = mask; 1237 return (error); 1238} 1239SYSCTL_PROC(_machdep, OID_AUTO, hlt_cpus, CTLTYPE_INT|CTLFLAG_RW, 1240 0, 0, sysctl_hlt_cpus, "IU", 1241 "Bitmap of CPUs to halt. 101 (binary) will halt CPUs 0 and 2."); 1242 1243static int 1244sysctl_hlt_logical_cpus(SYSCTL_HANDLER_ARGS) 1245{ 1246 int disable, error; 1247 1248 disable = hlt_logical_cpus; 1249 error = sysctl_handle_int(oidp, &disable, 0, req); 1250 if (error || !req->newptr) 1251 return (error); 1252 1253 if (disable) 1254 hlt_cpus_mask |= logical_cpus_mask; 1255 else 1256 hlt_cpus_mask &= ~logical_cpus_mask; 1257 1258 if ((hlt_cpus_mask & all_cpus) == all_cpus) 1259 hlt_cpus_mask &= ~(1<<0); 1260 1261 hlt_logical_cpus = disable; 1262 return (error); 1263} 1264 1265static void 1266cpu_hlt_setup(void *dummy __unused) 1267{ 1268 1269 if (logical_cpus_mask != 0) { 1270 TUNABLE_INT_FETCH("machdep.hlt_logical_cpus", 1271 &hlt_logical_cpus); 1272 sysctl_ctx_init(&logical_cpu_clist); 1273 SYSCTL_ADD_PROC(&logical_cpu_clist, 1274 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1275 "hlt_logical_cpus", CTLTYPE_INT|CTLFLAG_RW, 0, 0, 1276 sysctl_hlt_logical_cpus, "IU", ""); 1277 SYSCTL_ADD_UINT(&logical_cpu_clist, 1278 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1279 "logical_cpus_mask", CTLTYPE_INT|CTLFLAG_RD, 1280 &logical_cpus_mask, 0, ""); 1281 1282 if (hlt_logical_cpus) 1283 hlt_cpus_mask |= logical_cpus_mask; 1284 } 1285} 1286SYSINIT(cpu_hlt, SI_SUB_SMP, SI_ORDER_ANY, cpu_hlt_setup, NULL); 1287 1288int 1289mp_grab_cpu_hlt(void) 1290{ 1291 u_int mask = PCPU_GET(cpumask); 1292 int retval; 1293 1294 retval = mask & hlt_cpus_mask; 1295 while (mask & hlt_cpus_mask) 1296 __asm __volatile("sti; hlt" : : : "memory"); 1297 return (retval); 1298} 1299