mp_x86.c revision 122438
1/*- 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26#include <sys/cdefs.h> 27__FBSDID("$FreeBSD: head/sys/i386/i386/mp_machdep.c 122438 2003-11-10 21:24:34Z jhb $"); 28 29#include "opt_apic.h" 30#include "opt_cpu.h" 31#include "opt_kstack_pages.h" 32 33#if !defined(lint) 34#if !defined(SMP) 35#error How did you get here? 36#endif 37 38#if defined(I386_CPU) && !defined(COMPILING_LINT) 39#error SMP not supported with I386_CPU 40#endif 41#ifndef DEV_APIC 42#error The apic device is required for SMP, add "device apic" to your config file. 43#endif 44#if defined(CPU_DISABLE_CMPXCHG) && !defined(COMPILING_LINT) 45#error SMP not supported with CPU_DISABLE_CMPXCHG 46#endif 47#endif /* not lint */ 48 49#include <sys/param.h> 50#include <sys/systm.h> 51#include <sys/bus.h> 52#include <sys/cons.h> /* cngetc() */ 53#ifdef GPROF 54#include <sys/gmon.h> 55#endif 56#include <sys/kernel.h> 57#include <sys/ktr.h> 58#include <sys/lock.h> 59#include <sys/malloc.h> 60#include <sys/memrange.h> 61#include <sys/mutex.h> 62#include <sys/pcpu.h> 63#include <sys/proc.h> 64#include <sys/smp.h> 65#include <sys/sysctl.h> 66 67#include <vm/vm.h> 68#include <vm/vm_param.h> 69#include <vm/pmap.h> 70#include <vm/vm_kern.h> 71#include <vm/vm_extern.h> 72 73#include <machine/apicreg.h> 74#include <machine/clock.h> 75#include <machine/md_var.h> 76#include <machine/pcb.h> 77#include <machine/smp.h> 78#include <machine/smptests.h> /** COUNT_XINVLTLB_HITS, USE_COMLOCK */ 79#include <machine/specialreg.h> 80#include <machine/privatespace.h> 81 82#define WARMBOOT_TARGET 0 83#define WARMBOOT_OFF (KERNBASE + 0x0467) 84#define WARMBOOT_SEG (KERNBASE + 0x0469) 85 86#define CMOS_REG (0x70) 87#define CMOS_DATA (0x71) 88#define BIOS_RESET (0x0f) 89#define BIOS_WARM (0x0a) 90 91/* 92 * this code MUST be enabled here and in mpboot.s. 93 * it follows the very early stages of AP boot by placing values in CMOS ram. 94 * it NORMALLY will never be needed and thus the primitive method for enabling. 95 * 96#define CHECK_POINTS 97 */ 98 99#if defined(CHECK_POINTS) && !defined(PC98) 100#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 101#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 102 103#define CHECK_INIT(D); \ 104 CHECK_WRITE(0x34, (D)); \ 105 CHECK_WRITE(0x35, (D)); \ 106 CHECK_WRITE(0x36, (D)); \ 107 CHECK_WRITE(0x37, (D)); \ 108 CHECK_WRITE(0x38, (D)); \ 109 CHECK_WRITE(0x39, (D)); 110 111#define CHECK_PRINT(S); \ 112 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 113 (S), \ 114 CHECK_READ(0x34), \ 115 CHECK_READ(0x35), \ 116 CHECK_READ(0x36), \ 117 CHECK_READ(0x37), \ 118 CHECK_READ(0x38), \ 119 CHECK_READ(0x39)); 120 121#else /* CHECK_POINTS */ 122 123#define CHECK_INIT(D) 124#define CHECK_PRINT(S) 125#define CHECK_WRITE(A, D) 126 127#endif /* CHECK_POINTS */ 128 129/* 130 * Values to send to the POST hardware. 131 */ 132#define MP_BOOTADDRESS_POST 0x10 133#define MP_PROBE_POST 0x11 134#define MPTABLE_PASS1_POST 0x12 135 136#define MP_START_POST 0x13 137#define MP_ENABLE_POST 0x14 138#define MPTABLE_PASS2_POST 0x15 139 140#define START_ALL_APS_POST 0x16 141#define INSTALL_AP_TRAMP_POST 0x17 142#define START_AP_POST 0x18 143 144#define MP_ANNOUNCE_POST 0x19 145 146/* lock region used by kernel profiling */ 147int mcount_lock; 148 149#ifdef USE_COMLOCK 150/* locks com (tty) data/hardware accesses: a FASTINTR() */ 151struct mtx com_mtx; 152#endif 153 154/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ 155int current_postcode; 156 157int mp_naps; /* # of Applications processors */ 158int boot_cpu_id = -1; /* designated BSP */ 159extern int nkpt; 160 161/* 162 * CPU topology map datastructures for HTT. (XXX) 163 */ 164struct cpu_group mp_groups[MAXCPU]; 165struct cpu_top mp_top; 166struct cpu_top *smp_topology; 167 168/* AP uses this during bootstrap. Do not staticize. */ 169char *bootSTK; 170static int bootAP; 171 172/* Hotwire a 0->4MB V==P mapping */ 173extern pt_entry_t *KPTphys; 174 175/* SMP page table page */ 176extern pt_entry_t *SMPpt; 177 178struct pcb stoppcbs[MAXCPU]; 179 180/* Variables needed for SMP tlb shootdown. */ 181vm_offset_t smp_tlb_addr1; 182vm_offset_t smp_tlb_addr2; 183volatile int smp_tlb_wait; 184struct mtx smp_tlb_mtx; 185 186/* 187 * Local data and functions. 188 */ 189 190static u_int logical_cpus; 191static u_int logical_cpus_mask; 192 193/* used to hold the AP's until we are ready to release them */ 194static struct mtx ap_boot_mtx; 195 196/* Set to 1 once we're ready to let the APs out of the pen. */ 197static volatile int aps_ready = 0; 198 199/* 200 * Store data from cpu_add() until later in the boot when we actually setup 201 * the APs. 202 */ 203struct cpu_info { 204 int cpu_present:1; 205 int cpu_bsp:1; 206} static cpu_info[MAXCPU]; 207static int cpu_apic_ids[MAXCPU]; 208 209static u_int boot_address; 210 211static void set_logical_apic_ids(void); 212static int start_all_aps(void); 213static void install_ap_tramp(void); 214static int start_ap(int apic_id); 215static void release_aps(void *dummy); 216 217static int hlt_cpus_mask; 218static int hlt_logical_cpus = 1; 219static struct sysctl_ctx_list logical_cpu_clist; 220 221/* 222 * Calculate usable address in base memory for AP trampoline code. 223 */ 224u_int 225mp_bootaddress(u_int basemem) 226{ 227 POSTCODE(MP_BOOTADDRESS_POST); 228 229 boot_address = trunc_page(basemem); /* round down to 4k boundary */ 230 if ((basemem - boot_address) < bootMP_size) 231 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */ 232 233 return boot_address; 234} 235 236void 237cpu_add(u_int apic_id, char boot_cpu) 238{ 239 240 if (apic_id > MAXCPU) { 241 printf("SMP: CPU %d exceeds maximum CPU %d, ignoring\n", 242 apic_id, MAXCPU); 243 return; 244 } 245 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice", 246 apic_id)); 247 cpu_info[apic_id].cpu_present = 1; 248 if (boot_cpu) { 249 KASSERT(boot_cpu_id == -1, 250 ("CPU %d claims to be BSP, but CPU %d already is", apic_id, 251 boot_cpu_id)); 252 boot_cpu_id = apic_id; 253 cpu_info[apic_id].cpu_bsp = 1; 254 } 255 mp_ncpus++; 256 if (apic_id > mp_maxid) 257 mp_maxid = apic_id; 258 if (bootverbose) 259 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" : 260 "AP"); 261 262} 263 264int 265cpu_mp_probe(void) 266{ 267 268 /* 269 * Always record BSP in CPU map so that the mbuf init code works 270 * correctly. 271 */ 272 all_cpus = 1; 273 if (mp_ncpus == 0) { 274 /* 275 * No CPUs were found, so this must be a UP system. Setup 276 * the variables to represent a system with a single CPU 277 * with an id of 0. 278 */ 279 KASSERT(mp_maxid == 0, 280 ("%s: mp_ncpus is zero, but mp_maxid is not", __func__)); 281 mp_ncpus = 1; 282 return (0); 283 } 284 285 /* At least one CPU was found. */ 286 if (mp_ncpus == 1) { 287 /* 288 * One CPU was found, so this must be a UP system with 289 * an I/O APIC. 290 */ 291 mp_maxid = 0; 292 return (0); 293 } 294 295 /* At least two CPUs were found. */ 296 KASSERT(mp_maxid >= mp_ncpus - 1, 297 ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid, 298 mp_ncpus)); 299 return (1); 300} 301 302/* 303 * Initialize the IPI handlers and start up the AP's. 304 */ 305void 306cpu_mp_start(void) 307{ 308 int i; 309 310 POSTCODE(MP_START_POST); 311 312 /* Initialize the logical ID to APIC ID table. */ 313 for (i = 0; i < MAXCPU; i++) 314 cpu_apic_ids[i] = -1; 315 316 /* Install an inter-CPU IPI for TLB invalidation */ 317 setidt(IPI_INVLTLB, IDTVEC(invltlb), 318 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 319 setidt(IPI_INVLPG, IDTVEC(invlpg), 320 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 321 setidt(IPI_INVLRNG, IDTVEC(invlrng), 322 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 323 324 /* Install an inter-CPU IPI for forwarding hardclock() */ 325 setidt(IPI_HARDCLOCK, IDTVEC(hardclock), 326 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 327 328 /* Install an inter-CPU IPI for forwarding statclock() */ 329 setidt(IPI_STATCLOCK, IDTVEC(statclock), 330 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 331 332 /* Install an inter-CPU IPI for lazy pmap release */ 333 setidt(IPI_LAZYPMAP, IDTVEC(lazypmap), 334 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 335 336 /* Install an inter-CPU IPI for all-CPU rendezvous */ 337 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous), 338 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 339 340 /* Install an inter-CPU IPI for forcing an additional software trap */ 341 setidt(IPI_AST, IDTVEC(cpuast), 342 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 343 344 /* Install an inter-CPU IPI for CPU stop/restart */ 345 setidt(IPI_STOP, IDTVEC(cpustop), 346 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 347 348#ifdef USE_COMLOCK 349 mtx_init(&com_mtx, "com", NULL, MTX_SPIN); 350#endif 351 mtx_init(&smp_tlb_mtx, "tlb", NULL, MTX_SPIN); 352 353 /* Set boot_cpu_id if needed. */ 354 if (boot_cpu_id == -1) { 355 boot_cpu_id = PCPU_GET(apic_id); 356 cpu_info[boot_cpu_id].cpu_bsp = 1; 357 } else 358 KASSERT(boot_cpu_id == PCPU_GET(apic_id), 359 ("BSP's APIC ID doesn't match boot_cpu_id")); 360 cpu_apic_ids[0] = boot_cpu_id; 361 362 /* Start each Application Processor */ 363 start_all_aps(); 364 365 /* Setup the initial logical CPUs info. */ 366 logical_cpus = logical_cpus_mask = 0; 367 if (cpu_feature & CPUID_HTT) 368 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 369 370 set_logical_apic_ids(); 371} 372 373 374/* 375 * Print various information about the SMP system hardware and setup. 376 */ 377void 378cpu_mp_announce(void) 379{ 380 int i, x; 381 382 POSTCODE(MP_ANNOUNCE_POST); 383 384 /* List CPUs */ 385 printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id); 386 for (i = 1, x = 0; x < MAXCPU; x++) { 387 if (cpu_info[x].cpu_present && !cpu_info[x].cpu_bsp) { 388 KASSERT(i < mp_ncpus, 389 ("mp_ncpus and actual cpus are out of whack")); 390 printf(" cpu%d (AP): APIC ID: %2d\n", i++, x); 391 } 392 } 393} 394 395/* 396 * AP CPU's call this to initialize themselves. 397 */ 398void 399init_secondary(void) 400{ 401 int gsel_tss; 402 int x, myid; 403 u_int cr0; 404 405 /* bootAP is set in start_ap() to our ID. */ 406 myid = bootAP; 407 gdt_segs[GPRIV_SEL].ssd_base = (int) &SMP_prvspace[myid]; 408 gdt_segs[GPROC0_SEL].ssd_base = 409 (int) &SMP_prvspace[myid].pcpu.pc_common_tss; 410 SMP_prvspace[myid].pcpu.pc_prvspace = 411 &SMP_prvspace[myid].pcpu; 412 413 for (x = 0; x < NGDT; x++) { 414 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd); 415 } 416 417 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 418 r_gdt.rd_base = (int) &gdt[myid * NGDT]; 419 lgdt(&r_gdt); /* does magic intra-segment return */ 420 421 lidt(&r_idt); 422 423 lldt(_default_ldt); 424 PCPU_SET(currentldt, _default_ldt); 425 426 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 427 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS; 428 PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */ 429 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL)); 430 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16); 431 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd); 432 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt)); 433 ltr(gsel_tss); 434 435 /* 436 * Set to a known state: 437 * Set by mpboot.s: CR0_PG, CR0_PE 438 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM 439 */ 440 cr0 = rcr0(); 441 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM); 442 load_cr0(cr0); 443 CHECK_WRITE(0x38, 5); 444 445 /* Disable local APIC just to be sure. */ 446 lapic_disable(); 447 448 /* signal our startup to the BSP. */ 449 mp_naps++; 450 CHECK_WRITE(0x39, 6); 451 452 /* Spin until the BSP releases the AP's. */ 453 while (!aps_ready) 454 ia32_pause(); 455 456 /* BSP may have changed PTD while we were waiting */ 457 invltlb(); 458 pmap_invalidate_range(kernel_pmap, 0, NKPT * NBPDR - 1); 459 460#if defined(I586_CPU) && !defined(NO_F00F_HACK) 461 lidt(&r_idt); 462#endif 463 464 /* set up CPU registers and state */ 465 cpu_setregs(); 466 467 /* set up FPU state on the AP */ 468 npxinit(__INITIAL_NPXCW__); 469 470 /* set up SSE registers */ 471 enable_sse(); 472 473 /* A quick check from sanity claus */ 474 if (PCPU_GET(apic_id) != lapic_id()) { 475 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid)); 476 printf("SMP: actual apic_id = %d\n", lapic_id()); 477 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id)); 478 printf("PTD[MPPTDI] = %#jx\n", (uintmax_t)PTD[MPPTDI]); 479 panic("cpuid mismatch! boom!!"); 480 } 481 482 mtx_lock_spin(&ap_boot_mtx); 483 484 /* Init local apic for irq's */ 485 lapic_setup(); 486 487 /* Set memory range attributes for this CPU to match the BSP */ 488 mem_range_AP_init(); 489 490 smp_cpus++; 491 492 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", PCPU_GET(cpuid)); 493 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid)); 494 495 /* Determine if we are a logical CPU. */ 496 if (logical_cpus > 1 && PCPU_GET(apic_id) % logical_cpus != 0) 497 logical_cpus_mask |= PCPU_GET(cpumask); 498 499 /* Build our map of 'other' CPUs. */ 500 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 501 502 if (bootverbose) 503 lapic_dump("AP"); 504 505 if (smp_cpus == mp_ncpus) { 506 /* enable IPI's, tlb shootdown, freezes etc */ 507 atomic_store_rel_int(&smp_started, 1); 508 smp_active = 1; /* historic */ 509 } 510 511 mtx_unlock_spin(&ap_boot_mtx); 512 513 /* wait until all the AP's are up */ 514 while (smp_started == 0) 515 ia32_pause(); 516 517 /* ok, now grab sched_lock and enter the scheduler */ 518 mtx_lock_spin(&sched_lock); 519 520 binuptime(PCPU_PTR(switchtime)); 521 PCPU_SET(switchticks, ticks); 522 523 cpu_throw(NULL, choosethread()); /* doesn't return */ 524 525 panic("scheduler returned us to %s", __func__); 526 /* NOTREACHED */ 527} 528 529/******************************************************************* 530 * local functions and data 531 */ 532 533/* 534 * Set the APIC logical IDs. 535 * 536 * We want to cluster logical CPU's within the same APIC ID cluster. 537 * Since logical CPU's are aligned simply filling in the clusters in 538 * APIC ID order works fine. Note that this does not try to balance 539 * the number of CPU's in each cluster. (XXX?) 540 */ 541static void 542set_logical_apic_ids(void) 543{ 544 u_int apic_id, cluster, cluster_id; 545 546 /* Force us to allocate cluster 0 at the start. */ 547 cluster = -1; 548 cluster_id = APIC_MAX_INTRACLUSTER_ID; 549 for (apic_id = 0; apic_id < MAXCPU; apic_id++) { 550 if (!cpu_info[apic_id].cpu_present) 551 continue; 552 if (cluster_id == APIC_MAX_INTRACLUSTER_ID) { 553 cluster = ioapic_next_logical_cluster(); 554 cluster_id = 0; 555 } else 556 cluster_id++; 557 if (bootverbose) 558 printf("APIC ID: physical %u, logical %u:%u\n", 559 apic_id, cluster, cluster_id); 560 lapic_set_logical_id(apic_id, cluster, cluster_id); 561 } 562} 563 564/* 565 * start each AP in our list 566 */ 567static int 568start_all_aps(void) 569{ 570#ifndef PC98 571 u_char mpbiosreason; 572#endif 573 u_long mpbioswarmvec; 574 struct pcpu *pc; 575 char *stack; 576 uintptr_t kptbase; 577 int i, pg, apic_id, cpu; 578 579 POSTCODE(START_ALL_APS_POST); 580 581 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); 582 583 /* install the AP 1st level boot code */ 584 install_ap_tramp(); 585 586 /* save the current value of the warm-start vector */ 587 mpbioswarmvec = *((u_long *) WARMBOOT_OFF); 588#ifndef PC98 589 outb(CMOS_REG, BIOS_RESET); 590 mpbiosreason = inb(CMOS_DATA); 591#endif 592 593 /* set up temporary P==V mapping for AP boot */ 594 /* XXX this is a hack, we should boot the AP on its own stack/PTD */ 595 kptbase = (uintptr_t)(void *)KPTphys; 596 for (i = 0; i < NKPT; i++) 597 PTD[i] = (pd_entry_t)(PG_V | PG_RW | 598 ((kptbase + i * PAGE_SIZE) & PG_FRAME)); 599 invltlb(); 600 601 /* start each AP */ 602 for (cpu = 0, apic_id = 0; apic_id < MAXCPU; apic_id++) { 603 if (!cpu_info[apic_id].cpu_present || 604 cpu_info[apic_id].cpu_bsp) 605 continue; 606 cpu++; 607 608 /* save APIC ID for this logical ID */ 609 cpu_apic_ids[cpu] = apic_id; 610 611 /* first page of AP's private space */ 612 pg = cpu * i386_btop(sizeof(struct privatespace)); 613 614 /* allocate a new private data page */ 615 pc = (struct pcpu *)kmem_alloc(kernel_map, PAGE_SIZE); 616 617 /* wire it into the private page table page */ 618 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys(pc)); 619 620 /* allocate and set up an idle stack data page */ 621 stack = (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE); /* XXXKSE */ 622 for (i = 0; i < KSTACK_PAGES; i++) 623 SMPpt[pg + 1 + i] = (pt_entry_t) 624 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 625 626 /* prime data page for it to use */ 627 pcpu_init(pc, cpu, sizeof(struct pcpu)); 628 pc->pc_apic_id = apic_id; 629 630 /* setup a vector to our boot code */ 631 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 632 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4); 633#ifndef PC98 634 outb(CMOS_REG, BIOS_RESET); 635 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 636#endif 637 638 bootSTK = &SMP_prvspace[cpu].idlekstack[KSTACK_PAGES * 639 PAGE_SIZE]; 640 bootAP = cpu; 641 642 /* attempt to start the Application Processor */ 643 CHECK_INIT(99); /* setup checkpoints */ 644 if (!start_ap(apic_id)) { 645 printf("AP #%d (PHY# %d) failed!\n", cpu, apic_id); 646 CHECK_PRINT("trace"); /* show checkpoints */ 647 /* better panic as the AP may be running loose */ 648 printf("panic y/n? [y] "); 649 if (cngetc() != 'n') 650 panic("bye-bye"); 651 } 652 CHECK_PRINT("trace"); /* show checkpoints */ 653 654 all_cpus |= (1 << cpu); /* record AP in CPU map */ 655 } 656 657 /* build our map of 'other' CPUs */ 658 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 659 660 /* restore the warmstart vector */ 661 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 662#ifndef PC98 663 outb(CMOS_REG, BIOS_RESET); 664 outb(CMOS_DATA, mpbiosreason); 665#endif 666 667 /* 668 * Set up the idle context for the BSP. Similar to above except 669 * that some was done by locore, some by pmap.c and some is implicit 670 * because the BSP is cpu#0 and the page is initially zero and also 671 * because we can refer to variables by name on the BSP.. 672 */ 673 674 /* Allocate and setup BSP idle stack */ 675 stack = (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE); 676 for (i = 0; i < KSTACK_PAGES; i++) 677 SMPpt[1 + i] = (pt_entry_t) 678 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 679 680 for (i = 0; i < NKPT; i++) 681 PTD[i] = 0; 682 pmap_invalidate_range(kernel_pmap, 0, NKPT * NBPDR - 1); 683 684 /* number of APs actually started */ 685 return mp_naps; 686} 687 688/* 689 * load the 1st level AP boot code into base memory. 690 */ 691 692/* targets for relocation */ 693extern void bigJump(void); 694extern void bootCodeSeg(void); 695extern void bootDataSeg(void); 696extern void MPentry(void); 697extern u_int MP_GDT; 698extern u_int mp_gdtbase; 699 700static void 701install_ap_tramp(void) 702{ 703 int x; 704 int size = *(int *) ((u_long) & bootMP_size); 705 u_char *src = (u_char *) ((u_long) bootMP); 706 u_char *dst = (u_char *) boot_address + KERNBASE; 707 u_int boot_base = (u_int) bootMP; 708 u_int8_t *dst8; 709 u_int16_t *dst16; 710 u_int32_t *dst32; 711 712 POSTCODE(INSTALL_AP_TRAMP_POST); 713 714 pmap_kenter(boot_address + KERNBASE, boot_address); 715 for (x = 0; x < size; ++x) 716 *dst++ = *src++; 717 718 /* 719 * modify addresses in code we just moved to basemem. unfortunately we 720 * need fairly detailed info about mpboot.s for this to work. changes 721 * to mpboot.s might require changes here. 722 */ 723 724 /* boot code is located in KERNEL space */ 725 dst = (u_char *) boot_address + KERNBASE; 726 727 /* modify the lgdt arg */ 728 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 729 *dst32 = boot_address + ((u_int) & MP_GDT - boot_base); 730 731 /* modify the ljmp target for MPentry() */ 732 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 733 *dst32 = ((u_int) MPentry - KERNBASE); 734 735 /* modify the target for boot code segment */ 736 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 737 dst8 = (u_int8_t *) (dst16 + 1); 738 *dst16 = (u_int) boot_address & 0xffff; 739 *dst8 = ((u_int) boot_address >> 16) & 0xff; 740 741 /* modify the target for boot data segment */ 742 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 743 dst8 = (u_int8_t *) (dst16 + 1); 744 *dst16 = (u_int) boot_address & 0xffff; 745 *dst8 = ((u_int) boot_address >> 16) & 0xff; 746} 747 748/* 749 * This function starts the AP (application processor) identified 750 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 751 * to accomplish this. This is necessary because of the nuances 752 * of the different hardware we might encounter. It isn't pretty, 753 * but it seems to work. 754 */ 755static int 756start_ap(int apic_id) 757{ 758 int vector, ms; 759 int cpus; 760 761 POSTCODE(START_AP_POST); 762 763 /* calculate the vector */ 764 vector = (boot_address >> 12) & 0xff; 765 766 /* used as a watchpoint to signal AP startup */ 767 cpus = mp_naps; 768 769 /* 770 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 771 * and running the target CPU. OR this INIT IPI might be latched (P5 772 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 773 * ignored. 774 */ 775 776 /* do an INIT IPI: assert RESET */ 777 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 778 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id); 779 780 /* wait for pending status end */ 781 lapic_ipi_wait(-1); 782 783 /* do an INIT IPI: deassert RESET */ 784 lapic_ipi_raw(APIC_DEST_ALLESELF | APIC_TRIGMOD_LEVEL | 785 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, 0); 786 787 /* wait for pending status end */ 788 DELAY(10000); /* wait ~10mS */ 789 lapic_ipi_wait(-1); 790 791 /* 792 * next we do a STARTUP IPI: the previous INIT IPI might still be 793 * latched, (P5 bug) this 1st STARTUP would then terminate 794 * immediately, and the previously started INIT IPI would continue. OR 795 * the previous INIT IPI has already run. and this STARTUP IPI will 796 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 797 * will run. 798 */ 799 800 /* do a STARTUP IPI */ 801 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 802 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 803 vector, apic_id); 804 lapic_ipi_wait(-1); 805 DELAY(200); /* wait ~200uS */ 806 807 /* 808 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 809 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 810 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 811 * recognized after hardware RESET or INIT IPI. 812 */ 813 814 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 815 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 816 vector, apic_id); 817 lapic_ipi_wait(-1); 818 DELAY(200); /* wait ~200uS */ 819 820 /* Wait up to 5 seconds for it to start. */ 821 for (ms = 0; ms < 5000; ms++) { 822 if (mp_naps > cpus) 823 return 1; /* return SUCCESS */ 824 DELAY(1000); 825 } 826 return 0; /* return FAILURE */ 827} 828 829#ifdef COUNT_XINVLTLB_HITS 830u_int xhits_gbl[MAXCPU]; 831u_int xhits_pg[MAXCPU]; 832u_int xhits_rng[MAXCPU]; 833SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, ""); 834SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl, 835 sizeof(xhits_gbl), "IU", ""); 836SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg, 837 sizeof(xhits_pg), "IU", ""); 838SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng, 839 sizeof(xhits_rng), "IU", ""); 840 841u_int ipi_global; 842u_int ipi_page; 843u_int ipi_range; 844u_int ipi_range_size; 845SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, ""); 846SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, ""); 847SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, ""); 848SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size, 849 0, ""); 850 851u_int ipi_masked_global; 852u_int ipi_masked_page; 853u_int ipi_masked_range; 854u_int ipi_masked_range_size; 855SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW, 856 &ipi_masked_global, 0, ""); 857SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW, 858 &ipi_masked_page, 0, ""); 859SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW, 860 &ipi_masked_range, 0, ""); 861SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW, 862 &ipi_masked_range_size, 0, ""); 863#endif /* COUNT_XINVLTLB_HITS */ 864 865/* 866 * Flush the TLB on all other CPU's 867 */ 868static void 869smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2) 870{ 871 u_int ncpu; 872 873 ncpu = mp_ncpus - 1; /* does not shootdown self */ 874 if (ncpu < 1) 875 return; /* no other cpus */ 876 mtx_assert(&smp_tlb_mtx, MA_OWNED); 877 smp_tlb_addr1 = addr1; 878 smp_tlb_addr2 = addr2; 879 atomic_store_rel_int(&smp_tlb_wait, 0); 880 ipi_all_but_self(vector); 881 while (smp_tlb_wait < ncpu) 882 ia32_pause(); 883} 884 885/* 886 * This is about as magic as it gets. fortune(1) has got similar code 887 * for reversing bits in a word. Who thinks up this stuff?? 888 * 889 * Yes, it does appear to be consistently faster than: 890 * while (i = ffs(m)) { 891 * m >>= i; 892 * bits++; 893 * } 894 * and 895 * while (lsb = (m & -m)) { // This is magic too 896 * m &= ~lsb; // or: m ^= lsb 897 * bits++; 898 * } 899 * Both of these latter forms do some very strange things on gcc-3.1 with 900 * -mcpu=pentiumpro and/or -march=pentiumpro and/or -O or -O2. 901 * There is probably an SSE or MMX popcnt instruction. 902 * 903 * I wonder if this should be in libkern? 904 * 905 * XXX Stop the presses! Another one: 906 * static __inline u_int32_t 907 * popcnt1(u_int32_t v) 908 * { 909 * v -= ((v >> 1) & 0x55555555); 910 * v = (v & 0x33333333) + ((v >> 2) & 0x33333333); 911 * v = (v + (v >> 4)) & 0x0F0F0F0F; 912 * return (v * 0x01010101) >> 24; 913 * } 914 * The downside is that it has a multiply. With a pentium3 with 915 * -mcpu=pentiumpro and -march=pentiumpro then gcc-3.1 will use 916 * an imull, and in that case it is faster. In most other cases 917 * it appears slightly slower. 918 * 919 * Another variant (also from fortune): 920 * #define BITCOUNT(x) (((BX_(x)+(BX_(x)>>4)) & 0x0F0F0F0F) % 255) 921 * #define BX_(x) ((x) - (((x)>>1)&0x77777777) \ 922 * - (((x)>>2)&0x33333333) \ 923 * - (((x)>>3)&0x11111111)) 924 */ 925static __inline u_int32_t 926popcnt(u_int32_t m) 927{ 928 929 m = (m & 0x55555555) + ((m & 0xaaaaaaaa) >> 1); 930 m = (m & 0x33333333) + ((m & 0xcccccccc) >> 2); 931 m = (m & 0x0f0f0f0f) + ((m & 0xf0f0f0f0) >> 4); 932 m = (m & 0x00ff00ff) + ((m & 0xff00ff00) >> 8); 933 m = (m & 0x0000ffff) + ((m & 0xffff0000) >> 16); 934 return m; 935} 936 937static void 938smp_targeted_tlb_shootdown(u_int mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2) 939{ 940 int ncpu, othercpus; 941 942 othercpus = mp_ncpus - 1; 943 if (mask == (u_int)-1) { 944 ncpu = othercpus; 945 if (ncpu < 1) 946 return; 947 } else { 948 mask &= ~PCPU_GET(cpumask); 949 if (mask == 0) 950 return; 951 ncpu = popcnt(mask); 952 if (ncpu > othercpus) { 953 /* XXX this should be a panic offence */ 954 printf("SMP: tlb shootdown to %d other cpus (only have %d)\n", 955 ncpu, othercpus); 956 ncpu = othercpus; 957 } 958 /* XXX should be a panic, implied by mask == 0 above */ 959 if (ncpu < 1) 960 return; 961 } 962 mtx_assert(&smp_tlb_mtx, MA_OWNED); 963 smp_tlb_addr1 = addr1; 964 smp_tlb_addr2 = addr2; 965 atomic_store_rel_int(&smp_tlb_wait, 0); 966 if (mask == (u_int)-1) 967 ipi_all_but_self(vector); 968 else 969 ipi_selected(mask, vector); 970 while (smp_tlb_wait < ncpu) 971 ia32_pause(); 972} 973 974void 975smp_invltlb(void) 976{ 977 if (smp_started) { 978 smp_tlb_shootdown(IPI_INVLTLB, 0, 0); 979#ifdef COUNT_XINVLTLB_HITS 980 ipi_global++; 981#endif 982 } 983} 984 985void 986smp_invlpg(vm_offset_t addr) 987{ 988 if (smp_started) { 989 smp_tlb_shootdown(IPI_INVLPG, addr, 0); 990#ifdef COUNT_XINVLTLB_HITS 991 ipi_page++; 992#endif 993 } 994} 995 996void 997smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2) 998{ 999 if (smp_started) { 1000 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2); 1001#ifdef COUNT_XINVLTLB_HITS 1002 ipi_range++; 1003 ipi_range_size += (addr2 - addr1) / PAGE_SIZE; 1004#endif 1005 } 1006} 1007 1008void 1009smp_masked_invltlb(u_int mask) 1010{ 1011 if (smp_started) { 1012 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0); 1013#ifdef COUNT_XINVLTLB_HITS 1014 ipi_masked_global++; 1015#endif 1016 } 1017} 1018 1019void 1020smp_masked_invlpg(u_int mask, vm_offset_t addr) 1021{ 1022 if (smp_started) { 1023 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0); 1024#ifdef COUNT_XINVLTLB_HITS 1025 ipi_masked_page++; 1026#endif 1027 } 1028} 1029 1030void 1031smp_masked_invlpg_range(u_int mask, vm_offset_t addr1, vm_offset_t addr2) 1032{ 1033 if (smp_started) { 1034 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2); 1035#ifdef COUNT_XINVLTLB_HITS 1036 ipi_masked_range++; 1037 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE; 1038#endif 1039 } 1040} 1041 1042 1043/* 1044 * For statclock, we send an IPI to all CPU's to have them call this 1045 * function. 1046 */ 1047void 1048forwarded_statclock(struct clockframe frame) 1049{ 1050 1051 CTR0(KTR_SMP, "forwarded_statclock"); 1052 if (profprocs != 0) 1053 profclock(&frame); 1054 if (pscnt == psdiv) 1055 statclock(&frame); 1056} 1057 1058void 1059forward_statclock(void) 1060{ 1061 int map; 1062 1063 CTR0(KTR_SMP, "forward_statclock"); 1064 1065 if (!smp_started || cold || panicstr) 1066 return; 1067 1068 map = PCPU_GET(other_cpus) & ~(stopped_cpus|hlt_cpus_mask); 1069 if (map != 0) 1070 ipi_selected(map, IPI_STATCLOCK); 1071} 1072 1073/* 1074 * For each hardclock(), we send an IPI to all other CPU's to have them 1075 * execute this function. It would be nice to reduce contention on 1076 * sched_lock if we could simply peek at the CPU to determine the user/kernel 1077 * state and call hardclock_process() on the CPU receiving the clock interrupt 1078 * and then just use a simple IPI to handle any ast's if needed. 1079 */ 1080void 1081forwarded_hardclock(struct clockframe frame) 1082{ 1083 1084 CTR0(KTR_SMP, "forwarded_hardclock"); 1085 hardclock_process(&frame); 1086} 1087 1088void 1089forward_hardclock(void) 1090{ 1091 u_int map; 1092 1093 CTR0(KTR_SMP, "forward_hardclock"); 1094 1095 if (!smp_started || cold || panicstr) 1096 return; 1097 1098 map = PCPU_GET(other_cpus) & ~(stopped_cpus|hlt_cpus_mask); 1099 if (map != 0) 1100 ipi_selected(map, IPI_HARDCLOCK); 1101} 1102 1103/* 1104 * send an IPI to a set of cpus. 1105 */ 1106void 1107ipi_selected(u_int32_t cpus, u_int ipi) 1108{ 1109 int cpu; 1110 1111 CTR3(KTR_SMP, "%s: cpus: %x ipi: %x", __func__, cpus, ipi); 1112 while ((cpu = ffs(cpus)) != 0) { 1113 cpu--; 1114 KASSERT(cpu_apic_ids[cpu] != -1, 1115 ("IPI to non-existent CPU %d", cpu)); 1116 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]); 1117 cpus &= ~(1 << cpu); 1118 } 1119} 1120 1121/* 1122 * send an IPI INTerrupt containing 'vector' to all CPUs, including myself 1123 */ 1124void 1125ipi_all(u_int ipi) 1126{ 1127 1128 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1129 lapic_ipi_vectored(ipi, APIC_IPI_DEST_ALL); 1130} 1131 1132/* 1133 * send an IPI to all CPUs EXCEPT myself 1134 */ 1135void 1136ipi_all_but_self(u_int ipi) 1137{ 1138 1139 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1140 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS); 1141} 1142 1143/* 1144 * send an IPI to myself 1145 */ 1146void 1147ipi_self(u_int ipi) 1148{ 1149 1150 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1151 lapic_ipi_vectored(ipi, APIC_IPI_DEST_SELF); 1152} 1153 1154/* 1155 * This is called once the rest of the system is up and running and we're 1156 * ready to let the AP's out of the pen. 1157 */ 1158static void 1159release_aps(void *dummy __unused) 1160{ 1161 1162 if (mp_ncpus == 1) 1163 return; 1164 mtx_lock_spin(&sched_lock); 1165 atomic_store_rel_int(&aps_ready, 1); 1166 while (smp_started == 0) 1167 ia32_pause(); 1168 mtx_unlock_spin(&sched_lock); 1169} 1170SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL); 1171 1172static int 1173sysctl_hlt_cpus(SYSCTL_HANDLER_ARGS) 1174{ 1175 u_int mask; 1176 int error; 1177 1178 mask = hlt_cpus_mask; 1179 error = sysctl_handle_int(oidp, &mask, 0, req); 1180 if (error || !req->newptr) 1181 return (error); 1182 1183 if (logical_cpus_mask != 0 && 1184 (mask & logical_cpus_mask) == logical_cpus_mask) 1185 hlt_logical_cpus = 1; 1186 else 1187 hlt_logical_cpus = 0; 1188 1189 if ((mask & all_cpus) == all_cpus) 1190 mask &= ~(1<<0); 1191 hlt_cpus_mask = mask; 1192 return (error); 1193} 1194SYSCTL_PROC(_machdep, OID_AUTO, hlt_cpus, CTLTYPE_INT|CTLFLAG_RW, 1195 0, 0, sysctl_hlt_cpus, "IU", ""); 1196 1197static int 1198sysctl_hlt_logical_cpus(SYSCTL_HANDLER_ARGS) 1199{ 1200 int disable, error; 1201 1202 disable = hlt_logical_cpus; 1203 error = sysctl_handle_int(oidp, &disable, 0, req); 1204 if (error || !req->newptr) 1205 return (error); 1206 1207 if (disable) 1208 hlt_cpus_mask |= logical_cpus_mask; 1209 else 1210 hlt_cpus_mask &= ~logical_cpus_mask; 1211 1212 if ((hlt_cpus_mask & all_cpus) == all_cpus) 1213 hlt_cpus_mask &= ~(1<<0); 1214 1215 hlt_logical_cpus = disable; 1216 return (error); 1217} 1218 1219static void 1220cpu_hlt_setup(void *dummy __unused) 1221{ 1222 1223 if (logical_cpus_mask != 0) { 1224 TUNABLE_INT_FETCH("machdep.hlt_logical_cpus", 1225 &hlt_logical_cpus); 1226 sysctl_ctx_init(&logical_cpu_clist); 1227 SYSCTL_ADD_PROC(&logical_cpu_clist, 1228 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1229 "hlt_logical_cpus", CTLTYPE_INT|CTLFLAG_RW, 0, 0, 1230 sysctl_hlt_logical_cpus, "IU", ""); 1231 SYSCTL_ADD_UINT(&logical_cpu_clist, 1232 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1233 "logical_cpus_mask", CTLTYPE_INT|CTLFLAG_RD, 1234 &logical_cpus_mask, 0, ""); 1235 1236 if (hlt_logical_cpus) 1237 hlt_cpus_mask |= logical_cpus_mask; 1238 } 1239} 1240SYSINIT(cpu_hlt, SI_SUB_SMP, SI_ORDER_ANY, cpu_hlt_setup, NULL); 1241 1242int 1243mp_grab_cpu_hlt(void) 1244{ 1245 u_int mask = PCPU_GET(cpumask); 1246 int retval; 1247 1248 retval = mask & hlt_cpus_mask; 1249 while (mask & hlt_cpus_mask) 1250 __asm __volatile("sti; hlt" : : : "memory"); 1251 return (retval); 1252} 1253