mp_x86.c revision 112687
1/* 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: head/sys/i386/i386/mp_machdep.c 112687 2003-03-26 19:49:34Z ps $ 26 */ 27 28#include "opt_cpu.h" 29#include "opt_kstack_pages.h" 30 31#ifdef SMP 32#include <machine/smptests.h> 33#else 34#error 35#endif 36 37#include <sys/param.h> 38#include <sys/systm.h> 39#include <sys/bus.h> 40#include <sys/cons.h> /* cngetc() */ 41#ifdef GPROF 42#include <sys/gmon.h> 43#endif 44#include <sys/kernel.h> 45#include <sys/ktr.h> 46#include <sys/lock.h> 47#include <sys/malloc.h> 48#include <sys/memrange.h> 49#include <sys/mutex.h> 50#include <sys/pcpu.h> 51#include <sys/proc.h> 52#include <sys/smp.h> 53#include <sys/sysctl.h> 54#include <sys/user.h> 55 56#include <vm/vm.h> 57#include <vm/vm_param.h> 58#include <vm/pmap.h> 59#include <vm/vm_kern.h> 60#include <vm/vm_extern.h> 61#include <vm/vm_map.h> 62 63#include <machine/apic.h> 64#include <machine/atomic.h> 65#include <machine/clock.h> 66#include <machine/cpu.h> 67#include <machine/cpufunc.h> 68#include <machine/mpapic.h> 69#include <machine/psl.h> 70#include <machine/segments.h> 71#include <machine/smp.h> 72#include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */ 73#include <machine/tss.h> 74#include <machine/specialreg.h> 75#include <machine/privatespace.h> 76 77#if defined(APIC_IO) 78#include <machine/md_var.h> /* setidt() */ 79#include <i386/isa/icu.h> /* IPIs */ 80#include <i386/isa/intr_machdep.h> /* IPIs */ 81#endif /* APIC_IO */ 82 83#if defined(TEST_DEFAULT_CONFIG) 84#define MPFPS_MPFB1 TEST_DEFAULT_CONFIG 85#else 86#define MPFPS_MPFB1 mpfps->mpfb1 87#endif /* TEST_DEFAULT_CONFIG */ 88 89#define WARMBOOT_TARGET 0 90#define WARMBOOT_OFF (KERNBASE + 0x0467) 91#define WARMBOOT_SEG (KERNBASE + 0x0469) 92 93#ifdef PC98 94#define BIOS_BASE (0xe8000) 95#define BIOS_SIZE (0x18000) 96#else 97#define BIOS_BASE (0xf0000) 98#define BIOS_SIZE (0x10000) 99#endif 100#define BIOS_COUNT (BIOS_SIZE/4) 101 102#define CMOS_REG (0x70) 103#define CMOS_DATA (0x71) 104#define BIOS_RESET (0x0f) 105#define BIOS_WARM (0x0a) 106 107#define PROCENTRY_FLAG_EN 0x01 108#define PROCENTRY_FLAG_BP 0x02 109#define IOAPICENTRY_FLAG_EN 0x01 110 111 112/* MP Floating Pointer Structure */ 113typedef struct MPFPS { 114 char signature[4]; 115 void *pap; 116 u_char length; 117 u_char spec_rev; 118 u_char checksum; 119 u_char mpfb1; 120 u_char mpfb2; 121 u_char mpfb3; 122 u_char mpfb4; 123 u_char mpfb5; 124} *mpfps_t; 125 126/* MP Configuration Table Header */ 127typedef struct MPCTH { 128 char signature[4]; 129 u_short base_table_length; 130 u_char spec_rev; 131 u_char checksum; 132 u_char oem_id[8]; 133 u_char product_id[12]; 134 void *oem_table_pointer; 135 u_short oem_table_size; 136 u_short entry_count; 137 void *apic_address; 138 u_short extended_table_length; 139 u_char extended_table_checksum; 140 u_char reserved; 141} *mpcth_t; 142 143 144typedef struct PROCENTRY { 145 u_char type; 146 u_char apic_id; 147 u_char apic_version; 148 u_char cpu_flags; 149 u_long cpu_signature; 150 u_long feature_flags; 151 u_long reserved1; 152 u_long reserved2; 153} *proc_entry_ptr; 154 155typedef struct BUSENTRY { 156 u_char type; 157 u_char bus_id; 158 char bus_type[6]; 159} *bus_entry_ptr; 160 161typedef struct IOAPICENTRY { 162 u_char type; 163 u_char apic_id; 164 u_char apic_version; 165 u_char apic_flags; 166 void *apic_address; 167} *io_apic_entry_ptr; 168 169typedef struct INTENTRY { 170 u_char type; 171 u_char int_type; 172 u_short int_flags; 173 u_char src_bus_id; 174 u_char src_bus_irq; 175 u_char dst_apic_id; 176 u_char dst_apic_int; 177} *int_entry_ptr; 178 179/* descriptions of MP basetable entries */ 180typedef struct BASETABLE_ENTRY { 181 u_char type; 182 u_char length; 183 char name[16]; 184} basetable_entry; 185 186/* 187 * this code MUST be enabled here and in mpboot.s. 188 * it follows the very early stages of AP boot by placing values in CMOS ram. 189 * it NORMALLY will never be needed and thus the primitive method for enabling. 190 * 191#define CHECK_POINTS 192 */ 193 194#if defined(CHECK_POINTS) && !defined(PC98) 195#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 196#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 197 198#define CHECK_INIT(D); \ 199 CHECK_WRITE(0x34, (D)); \ 200 CHECK_WRITE(0x35, (D)); \ 201 CHECK_WRITE(0x36, (D)); \ 202 CHECK_WRITE(0x37, (D)); \ 203 CHECK_WRITE(0x38, (D)); \ 204 CHECK_WRITE(0x39, (D)); 205 206#define CHECK_PRINT(S); \ 207 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 208 (S), \ 209 CHECK_READ(0x34), \ 210 CHECK_READ(0x35), \ 211 CHECK_READ(0x36), \ 212 CHECK_READ(0x37), \ 213 CHECK_READ(0x38), \ 214 CHECK_READ(0x39)); 215 216#else /* CHECK_POINTS */ 217 218#define CHECK_INIT(D) 219#define CHECK_PRINT(S) 220 221#endif /* CHECK_POINTS */ 222 223/* 224 * Values to send to the POST hardware. 225 */ 226#define MP_BOOTADDRESS_POST 0x10 227#define MP_PROBE_POST 0x11 228#define MPTABLE_PASS1_POST 0x12 229 230#define MP_START_POST 0x13 231#define MP_ENABLE_POST 0x14 232#define MPTABLE_PASS2_POST 0x15 233 234#define START_ALL_APS_POST 0x16 235#define INSTALL_AP_TRAMP_POST 0x17 236#define START_AP_POST 0x18 237 238#define MP_ANNOUNCE_POST 0x19 239 240static int need_hyperthreading_fixup; 241static u_int logical_cpus; 242static u_int logical_cpus_mask; 243 244/* used to hold the AP's until we are ready to release them */ 245static struct mtx ap_boot_mtx; 246 247/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ 248int current_postcode; 249 250/** XXX FIXME: what system files declare these??? */ 251extern struct region_descriptor r_gdt, r_idt; 252 253int bsp_apic_ready = 0; /* flags useability of BSP apic */ 254int mp_naps; /* # of Applications processors */ 255int mp_nbusses; /* # of busses */ 256int mp_napics; /* # of IO APICs */ 257int boot_cpu_id; /* designated BSP */ 258vm_offset_t cpu_apic_address; 259vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */ 260extern int nkpt; 261 262u_int32_t cpu_apic_versions[MAXCPU]; 263u_int32_t *io_apic_versions; 264 265#ifdef APIC_INTR_REORDER 266struct { 267 volatile int *location; 268 int bit; 269} apic_isrbit_location[32]; 270#endif 271 272struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE]; 273 274/* 275 * APIC ID logical/physical mapping structures. 276 * We oversize these to simplify boot-time config. 277 */ 278int cpu_num_to_apic_id[NAPICID]; 279int io_num_to_apic_id[NAPICID]; 280int apic_id_to_logical[NAPICID]; 281 282 283/* AP uses this during bootstrap. Do not staticize. */ 284char *bootSTK; 285static int bootAP; 286 287/* Hotwire a 0->4MB V==P mapping */ 288extern pt_entry_t *KPTphys; 289 290/* SMP page table page */ 291extern pt_entry_t *SMPpt; 292 293struct pcb stoppcbs[MAXCPU]; 294 295#ifdef APIC_IO 296/* Variables needed for SMP tlb shootdown. */ 297vm_offset_t smp_tlb_addr1; 298vm_offset_t smp_tlb_addr2; 299volatile int smp_tlb_wait; 300static struct mtx smp_tlb_mtx; 301#endif 302 303/* 304 * Local data and functions. 305 */ 306 307/* Set to 1 once we're ready to let the APs out of the pen. */ 308static volatile int aps_ready = 0; 309 310static int mp_capable; 311static u_int boot_address; 312static u_int base_memory; 313 314static int picmode; /* 0: virtual wire mode, 1: PIC mode */ 315static mpfps_t mpfps; 316static int search_for_sig(u_int32_t target, int count); 317static void mp_enable(u_int boot_addr); 318 319static void mptable_hyperthread_fixup(u_int id_mask); 320static void mptable_pass1(void); 321static int mptable_pass2(void); 322static void default_mp_table(int type); 323static void fix_mp_table(void); 324static void setup_apic_irq_mapping(void); 325static void init_locks(void); 326static int start_all_aps(u_int boot_addr); 327static void install_ap_tramp(u_int boot_addr); 328static int start_ap(int logicalCpu, u_int boot_addr); 329void ap_init(void); 330static int apic_int_is_bus_type(int intr, int bus_type); 331static void release_aps(void *dummy); 332 333/* 334 * initialize all the SMP locks 335 */ 336 337/* lock region used by kernel profiling */ 338int mcount_lock; 339 340#ifdef USE_COMLOCK 341/* locks com (tty) data/hardware accesses: a FASTINTR() */ 342struct mtx com_mtx; 343#endif /* USE_COMLOCK */ 344 345static void 346init_locks(void) 347{ 348 349#ifdef USE_COMLOCK 350 mtx_init(&com_mtx, "com", NULL, MTX_SPIN); 351#endif /* USE_COMLOCK */ 352#ifdef APIC_IO 353 mtx_init(&smp_tlb_mtx, "tlb", NULL, MTX_SPIN); 354#endif 355} 356 357/* 358 * Calculate usable address in base memory for AP trampoline code. 359 */ 360u_int 361mp_bootaddress(u_int basemem) 362{ 363 POSTCODE(MP_BOOTADDRESS_POST); 364 365 base_memory = basemem * 1024; /* convert to bytes */ 366 367 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ 368 if ((base_memory - boot_address) < bootMP_size) 369 boot_address -= 4096; /* not enough, lower by 4k */ 370 371 return boot_address; 372} 373 374 375/* 376 * Look for an Intel MP spec table (ie, SMP capable hardware). 377 */ 378void 379i386_mp_probe(void) 380{ 381 int x; 382 u_long segment; 383 u_int32_t target; 384 385 POSTCODE(MP_PROBE_POST); 386 387 /* see if EBDA exists */ 388 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) { 389 /* search first 1K of EBDA */ 390 target = (u_int32_t) (segment << 4); 391 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 392 goto found; 393 } else { 394 /* last 1K of base memory, effective 'top of base' passed in */ 395 target = (u_int32_t) (base_memory - 0x400); 396 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 397 goto found; 398 } 399 400 /* search the BIOS */ 401 target = (u_int32_t) BIOS_BASE; 402 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) 403 goto found; 404 405 /* nothing found */ 406 mpfps = (mpfps_t)0; 407 mp_capable = 0; 408 return; 409 410found: 411 /* calculate needed resources */ 412 mpfps = (mpfps_t)x; 413 mptable_pass1(); 414 415 /* flag fact that we are running multiple processors */ 416 mp_capable = 1; 417} 418 419int 420cpu_mp_probe(void) 421{ 422 /* 423 * Record BSP in CPU map 424 * This is done here so that MBUF init code works correctly. 425 */ 426 all_cpus = 1; 427 428 return (mp_capable); 429} 430 431/* 432 * Initialize the SMP hardware and the APIC and start up the AP's. 433 */ 434void 435cpu_mp_start(void) 436{ 437 POSTCODE(MP_START_POST); 438 439 /* look for MP capable motherboard */ 440 if (mp_capable) 441 mp_enable(boot_address); 442 else 443 panic("MP hardware not found!"); 444 445 cpu_setregs(); 446} 447 448 449/* 450 * Print various information about the SMP system hardware and setup. 451 */ 452void 453cpu_mp_announce(void) 454{ 455 int x; 456 457 POSTCODE(MP_ANNOUNCE_POST); 458 459 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0)); 460 printf(", version: 0x%08x", cpu_apic_versions[0]); 461 printf(", at 0x%08x\n", cpu_apic_address); 462 for (x = 1; x <= mp_naps; ++x) { 463 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x)); 464 printf(", version: 0x%08x", cpu_apic_versions[x]); 465 printf(", at 0x%08x\n", cpu_apic_address); 466 } 467 468#if defined(APIC_IO) 469 for (x = 0; x < mp_napics; ++x) { 470 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x)); 471 printf(", version: 0x%08x", io_apic_versions[x]); 472 printf(", at 0x%08x\n", io_apic_address[x]); 473 } 474#else 475 printf(" Warning: APIC I/O disabled\n"); 476#endif /* APIC_IO */ 477} 478 479/* 480 * AP cpu's call this to sync up protected mode. 481 */ 482void 483init_secondary(void) 484{ 485 int gsel_tss; 486 int x, myid = bootAP; 487 u_int cr0; 488 489 gdt_segs[GPRIV_SEL].ssd_base = (int) &SMP_prvspace[myid]; 490 gdt_segs[GPROC0_SEL].ssd_base = 491 (int) &SMP_prvspace[myid].pcpu.pc_common_tss; 492 SMP_prvspace[myid].pcpu.pc_prvspace = 493 &SMP_prvspace[myid].pcpu; 494 495 for (x = 0; x < NGDT; x++) { 496 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd); 497 } 498 499 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 500 r_gdt.rd_base = (int) &gdt[myid * NGDT]; 501 lgdt(&r_gdt); /* does magic intra-segment return */ 502 503 lidt(&r_idt); 504 505 lldt(_default_ldt); 506 PCPU_SET(currentldt, _default_ldt); 507 508 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 509 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS; 510 PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */ 511 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL)); 512 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16); 513 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd); 514 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt)); 515 ltr(gsel_tss); 516 517 /* 518 * Set to a known state: 519 * Set by mpboot.s: CR0_PG, CR0_PE 520 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM 521 */ 522 cr0 = rcr0(); 523 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM); 524 load_cr0(cr0); 525 526 pmap_set_opt(); 527} 528 529 530#if defined(APIC_IO) 531/* 532 * Final configuration of the BSP's local APIC: 533 * - disable 'pic mode'. 534 * - disable 'virtual wire mode'. 535 * - enable NMI. 536 */ 537void 538bsp_apic_configure(void) 539{ 540 u_char byte; 541 u_int32_t temp; 542 543 /* leave 'pic mode' if necessary */ 544 if (picmode) { 545 outb(0x22, 0x70); /* select IMCR */ 546 byte = inb(0x23); /* current contents */ 547 byte |= 0x01; /* mask external INTR */ 548 outb(0x23, byte); /* disconnect 8259s/NMI */ 549 } 550 551 /* mask lint0 (the 8259 'virtual wire' connection) */ 552 temp = lapic.lvt_lint0; 553 temp |= APIC_LVT_M; /* set the mask */ 554 lapic.lvt_lint0 = temp; 555 556 /* setup lint1 to handle NMI */ 557 temp = lapic.lvt_lint1; 558 temp &= ~APIC_LVT_M; /* clear the mask */ 559 lapic.lvt_lint1 = temp; 560 561 if (bootverbose) 562 apic_dump("bsp_apic_configure()"); 563} 564#endif /* APIC_IO */ 565 566 567/******************************************************************* 568 * local functions and data 569 */ 570 571/* 572 * start the SMP system 573 */ 574static void 575mp_enable(u_int boot_addr) 576{ 577 int x; 578#if defined(APIC_IO) 579 int apic; 580 u_int ux; 581#endif /* APIC_IO */ 582 583 POSTCODE(MP_ENABLE_POST); 584 585 /* turn on 4MB of V == P addressing so we can get to MP table */ 586 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME); 587 invltlb(); 588 589 /* examine the MP table for needed info, uses physical addresses */ 590 x = mptable_pass2(); 591 592 *(int *)PTD = 0; 593 invltlb(); 594 595 /* can't process default configs till the CPU APIC is pmapped */ 596 if (x) 597 default_mp_table(x); 598 599 /* post scan cleanup */ 600 fix_mp_table(); 601 setup_apic_irq_mapping(); 602 603#if defined(APIC_IO) 604 605 /* fill the LOGICAL io_apic_versions table */ 606 for (apic = 0; apic < mp_napics; ++apic) { 607 ux = io_apic_read(apic, IOAPIC_VER); 608 io_apic_versions[apic] = ux; 609 io_apic_set_id(apic, IO_TO_ID(apic)); 610 } 611 612 /* program each IO APIC in the system */ 613 for (apic = 0; apic < mp_napics; ++apic) 614 if (io_apic_setup(apic) < 0) 615 panic("IO APIC setup failure"); 616 617 /* install a 'Spurious INTerrupt' vector */ 618 setidt(XSPURIOUSINT_OFFSET, Xspuriousint, 619 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 620 621 /* install an inter-CPU IPI for TLB invalidation */ 622 setidt(XINVLTLB_OFFSET, Xinvltlb, 623 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 624 setidt(XINVLPG_OFFSET, Xinvlpg, 625 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 626 setidt(XINVLRNG_OFFSET, Xinvlrng, 627 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 628 629 /* install an inter-CPU IPI for forwarding hardclock() */ 630 setidt(XHARDCLOCK_OFFSET, Xhardclock, 631 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 632 633 /* install an inter-CPU IPI for forwarding statclock() */ 634 setidt(XSTATCLOCK_OFFSET, Xstatclock, 635 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 636 637 /* install an inter-CPU IPI for all-CPU rendezvous */ 638 setidt(XRENDEZVOUS_OFFSET, Xrendezvous, 639 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 640 641 /* install an inter-CPU IPI for forcing an additional software trap */ 642 setidt(XCPUAST_OFFSET, Xcpuast, 643 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 644 645 /* install an inter-CPU IPI for CPU stop/restart */ 646 setidt(XCPUSTOP_OFFSET, Xcpustop, 647 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 648 649#if defined(TEST_TEST1) 650 /* install a "fake hardware INTerrupt" vector */ 651 setidt(XTEST1_OFFSET, Xtest1, 652 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 653#endif /** TEST_TEST1 */ 654 655#endif /* APIC_IO */ 656 657 /* initialize all SMP locks */ 658 init_locks(); 659 660 /* start each Application Processor */ 661 start_all_aps(boot_addr); 662} 663 664 665/* 666 * look for the MP spec signature 667 */ 668 669/* string defined by the Intel MP Spec as identifying the MP table */ 670#define MP_SIG 0x5f504d5f /* _MP_ */ 671#define NEXT(X) ((X) += 4) 672static int 673search_for_sig(u_int32_t target, int count) 674{ 675 int x; 676 u_int32_t *addr = (u_int32_t *) (KERNBASE + target); 677 678 for (x = 0; x < count; NEXT(x)) 679 if (addr[x] == MP_SIG) 680 /* make array index a byte index */ 681 return (target + (x * sizeof(u_int32_t))); 682 683 return -1; 684} 685 686 687static basetable_entry basetable_entry_types[] = 688{ 689 {0, 20, "Processor"}, 690 {1, 8, "Bus"}, 691 {2, 8, "I/O APIC"}, 692 {3, 8, "I/O INT"}, 693 {4, 8, "Local INT"} 694}; 695 696typedef struct BUSDATA { 697 u_char bus_id; 698 enum busTypes bus_type; 699} bus_datum; 700 701typedef struct INTDATA { 702 u_char int_type; 703 u_short int_flags; 704 u_char src_bus_id; 705 u_char src_bus_irq; 706 u_char dst_apic_id; 707 u_char dst_apic_int; 708 u_char int_vector; 709} io_int, local_int; 710 711typedef struct BUSTYPENAME { 712 u_char type; 713 char name[7]; 714} bus_type_name; 715 716static bus_type_name bus_type_table[] = 717{ 718 {CBUS, "CBUS"}, 719 {CBUSII, "CBUSII"}, 720 {EISA, "EISA"}, 721 {MCA, "MCA"}, 722 {UNKNOWN_BUSTYPE, "---"}, 723 {ISA, "ISA"}, 724 {MCA, "MCA"}, 725 {UNKNOWN_BUSTYPE, "---"}, 726 {UNKNOWN_BUSTYPE, "---"}, 727 {UNKNOWN_BUSTYPE, "---"}, 728 {UNKNOWN_BUSTYPE, "---"}, 729 {UNKNOWN_BUSTYPE, "---"}, 730 {PCI, "PCI"}, 731 {UNKNOWN_BUSTYPE, "---"}, 732 {UNKNOWN_BUSTYPE, "---"}, 733 {UNKNOWN_BUSTYPE, "---"}, 734 {UNKNOWN_BUSTYPE, "---"}, 735 {XPRESS, "XPRESS"}, 736 {UNKNOWN_BUSTYPE, "---"} 737}; 738/* from MP spec v1.4, table 5-1 */ 739static int default_data[7][5] = 740{ 741/* nbus, id0, type0, id1, type1 */ 742 {1, 0, ISA, 255, 255}, 743 {1, 0, EISA, 255, 255}, 744 {1, 0, EISA, 255, 255}, 745 {1, 0, MCA, 255, 255}, 746 {2, 0, ISA, 1, PCI}, 747 {2, 0, EISA, 1, PCI}, 748 {2, 0, MCA, 1, PCI} 749}; 750 751 752/* the bus data */ 753static bus_datum *bus_data; 754 755/* the IO INT data, one entry per possible APIC INTerrupt */ 756static io_int *io_apic_ints; 757 758static int nintrs; 759 760static int processor_entry(proc_entry_ptr entry, int cpu); 761static int bus_entry(bus_entry_ptr entry, int bus); 762static int io_apic_entry(io_apic_entry_ptr entry, int apic); 763static int int_entry(int_entry_ptr entry, int intr); 764static int lookup_bus_type(char *name); 765 766 767/* 768 * 1st pass on motherboard's Intel MP specification table. 769 * 770 * initializes: 771 * mp_ncpus = 1 772 * 773 * determines: 774 * cpu_apic_address (common to all CPUs) 775 * io_apic_address[N] 776 * mp_naps 777 * mp_nbusses 778 * mp_napics 779 * nintrs 780 */ 781static void 782mptable_pass1(void) 783{ 784 int x; 785 mpcth_t cth; 786 int totalSize; 787 void* position; 788 int count; 789 int type; 790 u_int id_mask; 791 792 POSTCODE(MPTABLE_PASS1_POST); 793 794 /* clear various tables */ 795 for (x = 0; x < NAPICID; ++x) { 796 io_apic_address[x] = ~0; /* IO APIC address table */ 797 } 798 799 /* init everything to empty */ 800 mp_naps = 0; 801 mp_nbusses = 0; 802 mp_napics = 0; 803 nintrs = 0; 804 id_mask = 0; 805 806 /* check for use of 'default' configuration */ 807 if (MPFPS_MPFB1 != 0) { 808 /* use default addresses */ 809 cpu_apic_address = DEFAULT_APIC_BASE; 810 io_apic_address[0] = DEFAULT_IO_APIC_BASE; 811 812 /* fill in with defaults */ 813 mp_naps = 2; /* includes BSP */ 814 mp_maxid = 1; 815 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0]; 816#if defined(APIC_IO) 817 mp_napics = 1; 818 nintrs = 16; 819#endif /* APIC_IO */ 820 } 821 else { 822 if ((cth = mpfps->pap) == 0) 823 panic("MP Configuration Table Header MISSING!"); 824 825 cpu_apic_address = (vm_offset_t) cth->apic_address; 826 827 /* walk the table, recording info of interest */ 828 totalSize = cth->base_table_length - sizeof(struct MPCTH); 829 position = (u_char *) cth + sizeof(struct MPCTH); 830 count = cth->entry_count; 831 832 while (count--) { 833 switch (type = *(u_char *) position) { 834 case 0: /* processor_entry */ 835 if (((proc_entry_ptr)position)->cpu_flags 836 & PROCENTRY_FLAG_EN) { 837 ++mp_naps; 838 mp_maxid++; 839 id_mask |= 1 << 840 ((proc_entry_ptr)position)->apic_id; 841 } 842 break; 843 case 1: /* bus_entry */ 844 ++mp_nbusses; 845 break; 846 case 2: /* io_apic_entry */ 847 if (((io_apic_entry_ptr)position)->apic_flags 848 & IOAPICENTRY_FLAG_EN) 849 io_apic_address[mp_napics++] = 850 (vm_offset_t)((io_apic_entry_ptr) 851 position)->apic_address; 852 break; 853 case 3: /* int_entry */ 854 ++nintrs; 855 break; 856 case 4: /* int_entry */ 857 break; 858 default: 859 panic("mpfps Base Table HOSED!"); 860 /* NOTREACHED */ 861 } 862 863 totalSize -= basetable_entry_types[type].length; 864 (u_char*)position += basetable_entry_types[type].length; 865 } 866 } 867 868 /* qualify the numbers */ 869 if (mp_naps > MAXCPU) { 870 printf("Warning: only using %d of %d available CPUs!\n", 871 MAXCPU, mp_naps); 872 mp_naps = MAXCPU; 873 } 874 875 /* See if we need to fixup HT logical CPUs. */ 876 mptable_hyperthread_fixup(id_mask); 877 878 /* 879 * Count the BSP. 880 * This is also used as a counter while starting the APs. 881 */ 882 mp_ncpus = 1; 883 884 --mp_naps; /* subtract the BSP */ 885} 886 887 888/* 889 * 2nd pass on motherboard's Intel MP specification table. 890 * 891 * sets: 892 * boot_cpu_id 893 * ID_TO_IO(N), phy APIC ID to log CPU/IO table 894 * CPU_TO_ID(N), logical CPU to APIC ID table 895 * IO_TO_ID(N), logical IO to APIC ID table 896 * bus_data[N] 897 * io_apic_ints[N] 898 */ 899static int 900mptable_pass2(void) 901{ 902 struct PROCENTRY proc; 903 int x; 904 mpcth_t cth; 905 int totalSize; 906 void* position; 907 int count; 908 int type; 909 int apic, bus, cpu, intr; 910 int i, j; 911 int pgeflag; 912 913 POSTCODE(MPTABLE_PASS2_POST); 914 915 /* Initialize fake proc entry for use with HT fixup. */ 916 bzero(&proc, sizeof(proc)); 917 proc.type = 0; 918 proc.cpu_flags = PROCENTRY_FLAG_EN; 919 920 pgeflag = 0; /* XXX - Not used under SMP yet. */ 921 922 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics, 923 M_DEVBUF, M_WAITOK); 924 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics, 925 M_DEVBUF, M_WAITOK); 926 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + 1), 927 M_DEVBUF, M_WAITOK); 928 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses, 929 M_DEVBUF, M_WAITOK); 930 931 bzero(ioapic, sizeof(ioapic_t *) * mp_napics); 932 933 for (i = 0; i < mp_napics; i++) { 934 for (j = 0; j < mp_napics; j++) { 935 /* same page frame as a previous IO apic? */ 936 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) == 937 (io_apic_address[i] & PG_FRAME)) { 938 ioapic[i] = (ioapic_t *)((u_int)SMP_prvspace 939 + (NPTEPG-2-j) * PAGE_SIZE 940 + (io_apic_address[i] & PAGE_MASK)); 941 break; 942 } 943 /* use this slot if available */ 944 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) == 0) { 945 SMPpt[NPTEPG-2-j] = (pt_entry_t)(PG_V | PG_RW | 946 pgeflag | (io_apic_address[i] & PG_FRAME)); 947 ioapic[i] = (ioapic_t *)((u_int)SMP_prvspace 948 + (NPTEPG-2-j) * PAGE_SIZE 949 + (io_apic_address[i] & PAGE_MASK)); 950 break; 951 } 952 } 953 } 954 955 /* clear various tables */ 956 for (x = 0; x < NAPICID; ++x) { 957 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */ 958 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */ 959 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */ 960 } 961 962 /* clear bus data table */ 963 for (x = 0; x < mp_nbusses; ++x) 964 bus_data[x].bus_id = 0xff; 965 966 /* clear IO APIC INT table */ 967 for (x = 0; x < (nintrs + 1); ++x) { 968 io_apic_ints[x].int_type = 0xff; 969 io_apic_ints[x].int_vector = 0xff; 970 } 971 972 /* setup the cpu/apic mapping arrays */ 973 boot_cpu_id = -1; 974 975 /* record whether PIC or virtual-wire mode */ 976 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0; 977 978 /* check for use of 'default' configuration */ 979 if (MPFPS_MPFB1 != 0) 980 return MPFPS_MPFB1; /* return default configuration type */ 981 982 if ((cth = mpfps->pap) == 0) 983 panic("MP Configuration Table Header MISSING!"); 984 985 /* walk the table, recording info of interest */ 986 totalSize = cth->base_table_length - sizeof(struct MPCTH); 987 position = (u_char *) cth + sizeof(struct MPCTH); 988 count = cth->entry_count; 989 apic = bus = intr = 0; 990 cpu = 1; /* pre-count the BSP */ 991 992 while (count--) { 993 switch (type = *(u_char *) position) { 994 case 0: 995 if (processor_entry(position, cpu)) 996 ++cpu; 997 998 if (need_hyperthreading_fixup) { 999 /* 1000 * Create fake mptable processor entries 1001 * and feed them to processor_entry() to 1002 * enumerate the logical CPUs. 1003 */ 1004 proc.apic_id = ((proc_entry_ptr)position)->apic_id; 1005 for (i = 1; i < logical_cpus; i++) { 1006 proc.apic_id++; 1007 (void)processor_entry(&proc, cpu); 1008 logical_cpus_mask |= (1 << cpu); 1009 cpu++; 1010 } 1011 } 1012 break; 1013 case 1: 1014 if (bus_entry(position, bus)) 1015 ++bus; 1016 break; 1017 case 2: 1018 if (io_apic_entry(position, apic)) 1019 ++apic; 1020 break; 1021 case 3: 1022 if (int_entry(position, intr)) 1023 ++intr; 1024 break; 1025 case 4: 1026 /* int_entry(position); */ 1027 break; 1028 default: 1029 panic("mpfps Base Table HOSED!"); 1030 /* NOTREACHED */ 1031 } 1032 1033 totalSize -= basetable_entry_types[type].length; 1034 (u_char *) position += basetable_entry_types[type].length; 1035 } 1036 1037 if (boot_cpu_id == -1) 1038 panic("NO BSP found!"); 1039 1040 /* report fact that its NOT a default configuration */ 1041 return 0; 1042} 1043 1044/* 1045 * Check if we should perform a hyperthreading "fix-up" to 1046 * enumerate any logical CPU's that aren't already listed 1047 * in the table. 1048 * 1049 * XXX: We assume that all of the physical CPUs in the 1050 * system have the same number of logical CPUs. 1051 * 1052 * XXX: We assume that APIC ID's are allocated such that 1053 * the APIC ID's for a physical processor are aligned 1054 * with the number of logical CPU's in the processor. 1055 */ 1056static void 1057mptable_hyperthread_fixup(u_int id_mask) 1058{ 1059 u_int i, id; 1060 1061 /* Nothing to do if there is no HTT support. */ 1062 if ((cpu_feature & CPUID_HTT) == 0) 1063 return; 1064 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 1065 if (logical_cpus <= 1) 1066 return; 1067 1068 /* 1069 * For each APIC ID of a CPU that is set in the mask, 1070 * scan the other candidate APIC ID's for this 1071 * physical processor. If any of those ID's are 1072 * already in the table, then kill the fixup. 1073 */ 1074 for (id = 0; id <= MAXCPU; id++) { 1075 if ((id_mask & 1 << id) == 0) 1076 continue; 1077 /* First, make sure we are on a logical_cpus boundary. */ 1078 if (id % logical_cpus != 0) 1079 return; 1080 for (i = id + 1; i < id + logical_cpus; i++) 1081 if ((id_mask & 1 << i) != 0) 1082 return; 1083 } 1084 1085 /* 1086 * Ok, the ID's checked out, so enable the fixup. We have to fixup 1087 * mp_naps and mp_maxid right now. 1088 */ 1089 need_hyperthreading_fixup = 1; 1090 mp_maxid *= logical_cpus; 1091 mp_naps *= logical_cpus; 1092} 1093 1094void 1095assign_apic_irq(int apic, int intpin, int irq) 1096{ 1097 int x; 1098 1099 if (int_to_apicintpin[irq].ioapic != -1) 1100 panic("assign_apic_irq: inconsistent table"); 1101 1102 int_to_apicintpin[irq].ioapic = apic; 1103 int_to_apicintpin[irq].int_pin = intpin; 1104 int_to_apicintpin[irq].apic_address = ioapic[apic]; 1105 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin; 1106 1107 for (x = 0; x < nintrs; x++) { 1108 if ((io_apic_ints[x].int_type == 0 || 1109 io_apic_ints[x].int_type == 3) && 1110 io_apic_ints[x].int_vector == 0xff && 1111 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) && 1112 io_apic_ints[x].dst_apic_int == intpin) 1113 io_apic_ints[x].int_vector = irq; 1114 } 1115} 1116 1117void 1118revoke_apic_irq(int irq) 1119{ 1120 int x; 1121 int oldapic; 1122 int oldintpin; 1123 1124 if (int_to_apicintpin[irq].ioapic == -1) 1125 panic("revoke_apic_irq: inconsistent table"); 1126 1127 oldapic = int_to_apicintpin[irq].ioapic; 1128 oldintpin = int_to_apicintpin[irq].int_pin; 1129 1130 int_to_apicintpin[irq].ioapic = -1; 1131 int_to_apicintpin[irq].int_pin = 0; 1132 int_to_apicintpin[irq].apic_address = NULL; 1133 int_to_apicintpin[irq].redirindex = 0; 1134 1135 for (x = 0; x < nintrs; x++) { 1136 if ((io_apic_ints[x].int_type == 0 || 1137 io_apic_ints[x].int_type == 3) && 1138 io_apic_ints[x].int_vector != 0xff && 1139 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) && 1140 io_apic_ints[x].dst_apic_int == oldintpin) 1141 io_apic_ints[x].int_vector = 0xff; 1142 } 1143} 1144 1145 1146static void 1147allocate_apic_irq(int intr) 1148{ 1149 int apic; 1150 int intpin; 1151 int irq; 1152 1153 if (io_apic_ints[intr].int_vector != 0xff) 1154 return; /* Interrupt handler already assigned */ 1155 1156 if (io_apic_ints[intr].int_type != 0 && 1157 (io_apic_ints[intr].int_type != 3 || 1158 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) && 1159 io_apic_ints[intr].dst_apic_int == 0))) 1160 return; /* Not INT or ExtInt on != (0, 0) */ 1161 1162 irq = 0; 1163 while (irq < APIC_INTMAPSIZE && 1164 int_to_apicintpin[irq].ioapic != -1) 1165 irq++; 1166 1167 if (irq >= APIC_INTMAPSIZE) 1168 return; /* No free interrupt handlers */ 1169 1170 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id); 1171 intpin = io_apic_ints[intr].dst_apic_int; 1172 1173 assign_apic_irq(apic, intpin, irq); 1174 io_apic_setup_intpin(apic, intpin); 1175} 1176 1177 1178static void 1179swap_apic_id(int apic, int oldid, int newid) 1180{ 1181 int x; 1182 int oapic; 1183 1184 1185 if (oldid == newid) 1186 return; /* Nothing to do */ 1187 1188 printf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n", 1189 apic, oldid, newid); 1190 1191 /* Swap physical APIC IDs in interrupt entries */ 1192 for (x = 0; x < nintrs; x++) { 1193 if (io_apic_ints[x].dst_apic_id == oldid) 1194 io_apic_ints[x].dst_apic_id = newid; 1195 else if (io_apic_ints[x].dst_apic_id == newid) 1196 io_apic_ints[x].dst_apic_id = oldid; 1197 } 1198 1199 /* Swap physical APIC IDs in IO_TO_ID mappings */ 1200 for (oapic = 0; oapic < mp_napics; oapic++) 1201 if (IO_TO_ID(oapic) == newid) 1202 break; 1203 1204 if (oapic < mp_napics) { 1205 printf("Changing APIC ID for IO APIC #%d from " 1206 "%d to %d in MP table\n", 1207 oapic, newid, oldid); 1208 IO_TO_ID(oapic) = oldid; 1209 } 1210 IO_TO_ID(apic) = newid; 1211} 1212 1213 1214static void 1215fix_id_to_io_mapping(void) 1216{ 1217 int x; 1218 1219 for (x = 0; x < NAPICID; x++) 1220 ID_TO_IO(x) = -1; 1221 1222 for (x = 0; x <= mp_naps; x++) 1223 if (CPU_TO_ID(x) < NAPICID) 1224 ID_TO_IO(CPU_TO_ID(x)) = x; 1225 1226 for (x = 0; x < mp_napics; x++) 1227 if (IO_TO_ID(x) < NAPICID) 1228 ID_TO_IO(IO_TO_ID(x)) = x; 1229} 1230 1231 1232static int 1233first_free_apic_id(void) 1234{ 1235 int freeid, x; 1236 1237 for (freeid = 0; freeid < NAPICID; freeid++) { 1238 for (x = 0; x <= mp_naps; x++) 1239 if (CPU_TO_ID(x) == freeid) 1240 break; 1241 if (x <= mp_naps) 1242 continue; 1243 for (x = 0; x < mp_napics; x++) 1244 if (IO_TO_ID(x) == freeid) 1245 break; 1246 if (x < mp_napics) 1247 continue; 1248 return freeid; 1249 } 1250 return freeid; 1251} 1252 1253 1254static int 1255io_apic_id_acceptable(int apic, int id) 1256{ 1257 int cpu; /* Logical CPU number */ 1258 int oapic; /* Logical IO APIC number for other IO APIC */ 1259 1260 if (id >= NAPICID) 1261 return 0; /* Out of range */ 1262 1263 for (cpu = 0; cpu <= mp_naps; cpu++) 1264 if (CPU_TO_ID(cpu) == id) 1265 return 0; /* Conflict with CPU */ 1266 1267 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++) 1268 if (IO_TO_ID(oapic) == id) 1269 return 0; /* Conflict with other APIC */ 1270 1271 return 1; /* ID is acceptable for IO APIC */ 1272} 1273 1274 1275/* 1276 * parse an Intel MP specification table 1277 */ 1278static void 1279fix_mp_table(void) 1280{ 1281 int x; 1282 int id; 1283 int bus_0 = 0; /* Stop GCC warning */ 1284 int bus_pci = 0; /* Stop GCC warning */ 1285 int num_pci_bus; 1286 int apic; /* IO APIC unit number */ 1287 int freeid; /* Free physical APIC ID */ 1288 int physid; /* Current physical IO APIC ID */ 1289 1290 /* 1291 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS 1292 * did it wrong. The MP spec says that when more than 1 PCI bus 1293 * exists the BIOS must begin with bus entries for the PCI bus and use 1294 * actual PCI bus numbering. This implies that when only 1 PCI bus 1295 * exists the BIOS can choose to ignore this ordering, and indeed many 1296 * MP motherboards do ignore it. This causes a problem when the PCI 1297 * sub-system makes requests of the MP sub-system based on PCI bus 1298 * numbers. So here we look for the situation and renumber the 1299 * busses and associated INTs in an effort to "make it right". 1300 */ 1301 1302 /* find bus 0, PCI bus, count the number of PCI busses */ 1303 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { 1304 if (bus_data[x].bus_id == 0) { 1305 bus_0 = x; 1306 } 1307 if (bus_data[x].bus_type == PCI) { 1308 ++num_pci_bus; 1309 bus_pci = x; 1310 } 1311 } 1312 /* 1313 * bus_0 == slot of bus with ID of 0 1314 * bus_pci == slot of last PCI bus encountered 1315 */ 1316 1317 /* check the 1 PCI bus case for sanity */ 1318 /* if it is number 0 all is well */ 1319 if (num_pci_bus == 1 && 1320 bus_data[bus_pci].bus_id != 0) { 1321 1322 /* mis-numbered, swap with whichever bus uses slot 0 */ 1323 1324 /* swap the bus entry types */ 1325 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type; 1326 bus_data[bus_0].bus_type = PCI; 1327 1328 /* swap each relavant INTerrupt entry */ 1329 id = bus_data[bus_pci].bus_id; 1330 for (x = 0; x < nintrs; ++x) { 1331 if (io_apic_ints[x].src_bus_id == id) { 1332 io_apic_ints[x].src_bus_id = 0; 1333 } 1334 else if (io_apic_ints[x].src_bus_id == 0) { 1335 io_apic_ints[x].src_bus_id = id; 1336 } 1337 } 1338 } 1339 1340 /* Assign IO APIC IDs. 1341 * 1342 * First try the existing ID. If a conflict is detected, try 1343 * the ID in the MP table. If a conflict is still detected, find 1344 * a free id. 1345 * 1346 * We cannot use the ID_TO_IO table before all conflicts has been 1347 * resolved and the table has been corrected. 1348 */ 1349 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */ 1350 1351 /* First try to use the value set by the BIOS */ 1352 physid = io_apic_get_id(apic); 1353 if (io_apic_id_acceptable(apic, physid)) { 1354 if (IO_TO_ID(apic) != physid) 1355 swap_apic_id(apic, IO_TO_ID(apic), physid); 1356 continue; 1357 } 1358 1359 /* Then check if the value in the MP table is acceptable */ 1360 if (io_apic_id_acceptable(apic, IO_TO_ID(apic))) 1361 continue; 1362 1363 /* Last resort, find a free APIC ID and use it */ 1364 freeid = first_free_apic_id(); 1365 if (freeid >= NAPICID) 1366 panic("No free physical APIC IDs found"); 1367 1368 if (io_apic_id_acceptable(apic, freeid)) { 1369 swap_apic_id(apic, IO_TO_ID(apic), freeid); 1370 continue; 1371 } 1372 panic("Free physical APIC ID not usable"); 1373 } 1374 fix_id_to_io_mapping(); 1375 1376 /* detect and fix broken Compaq MP table */ 1377 if (apic_int_type(0, 0) == -1) { 1378 printf("APIC_IO: MP table broken: 8259->APIC entry missing!\n"); 1379 io_apic_ints[nintrs].int_type = 3; /* ExtInt */ 1380 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */ 1381 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */ 1382 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0); 1383 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */ 1384 nintrs++; 1385 } 1386} 1387 1388 1389/* Assign low level interrupt handlers */ 1390static void 1391setup_apic_irq_mapping(void) 1392{ 1393 int x; 1394 int int_vector; 1395 1396 /* Clear array */ 1397 for (x = 0; x < APIC_INTMAPSIZE; x++) { 1398 int_to_apicintpin[x].ioapic = -1; 1399 int_to_apicintpin[x].int_pin = 0; 1400 int_to_apicintpin[x].apic_address = NULL; 1401 int_to_apicintpin[x].redirindex = 0; 1402 } 1403 1404 /* First assign ISA/EISA interrupts */ 1405 for (x = 0; x < nintrs; x++) { 1406 int_vector = io_apic_ints[x].src_bus_irq; 1407 if (int_vector < APIC_INTMAPSIZE && 1408 io_apic_ints[x].int_vector == 0xff && 1409 int_to_apicintpin[int_vector].ioapic == -1 && 1410 (apic_int_is_bus_type(x, ISA) || 1411 apic_int_is_bus_type(x, EISA)) && 1412 io_apic_ints[x].int_type == 0) { 1413 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id), 1414 io_apic_ints[x].dst_apic_int, 1415 int_vector); 1416 } 1417 } 1418 1419 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */ 1420 for (x = 0; x < nintrs; x++) { 1421 if (io_apic_ints[x].dst_apic_int == 0 && 1422 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) && 1423 io_apic_ints[x].int_vector == 0xff && 1424 int_to_apicintpin[0].ioapic == -1 && 1425 io_apic_ints[x].int_type == 3) { 1426 assign_apic_irq(0, 0, 0); 1427 break; 1428 } 1429 } 1430 /* PCI interrupt assignment is deferred */ 1431} 1432 1433 1434static int 1435processor_entry(proc_entry_ptr entry, int cpu) 1436{ 1437 /* check for usability */ 1438 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN)) 1439 return 0; 1440 1441 if(entry->apic_id >= NAPICID) 1442 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1); 1443 /* check for BSP flag */ 1444 if (entry->cpu_flags & PROCENTRY_FLAG_BP) { 1445 boot_cpu_id = entry->apic_id; 1446 CPU_TO_ID(0) = entry->apic_id; 1447 ID_TO_CPU(entry->apic_id) = 0; 1448 return 0; /* its already been counted */ 1449 } 1450 1451 /* add another AP to list, if less than max number of CPUs */ 1452 else if (cpu < MAXCPU) { 1453 CPU_TO_ID(cpu) = entry->apic_id; 1454 ID_TO_CPU(entry->apic_id) = cpu; 1455 return 1; 1456 } 1457 1458 return 0; 1459} 1460 1461 1462static int 1463bus_entry(bus_entry_ptr entry, int bus) 1464{ 1465 int x; 1466 char c, name[8]; 1467 1468 /* encode the name into an index */ 1469 for (x = 0; x < 6; ++x) { 1470 if ((c = entry->bus_type[x]) == ' ') 1471 break; 1472 name[x] = c; 1473 } 1474 name[x] = '\0'; 1475 1476 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) 1477 panic("unknown bus type: '%s'", name); 1478 1479 bus_data[bus].bus_id = entry->bus_id; 1480 bus_data[bus].bus_type = x; 1481 1482 return 1; 1483} 1484 1485 1486static int 1487io_apic_entry(io_apic_entry_ptr entry, int apic) 1488{ 1489 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) 1490 return 0; 1491 1492 IO_TO_ID(apic) = entry->apic_id; 1493 if (entry->apic_id < NAPICID) 1494 ID_TO_IO(entry->apic_id) = apic; 1495 1496 return 1; 1497} 1498 1499 1500static int 1501lookup_bus_type(char *name) 1502{ 1503 int x; 1504 1505 for (x = 0; x < MAX_BUSTYPE; ++x) 1506 if (strcmp(bus_type_table[x].name, name) == 0) 1507 return bus_type_table[x].type; 1508 1509 return UNKNOWN_BUSTYPE; 1510} 1511 1512 1513static int 1514int_entry(int_entry_ptr entry, int intr) 1515{ 1516 int apic; 1517 1518 io_apic_ints[intr].int_type = entry->int_type; 1519 io_apic_ints[intr].int_flags = entry->int_flags; 1520 io_apic_ints[intr].src_bus_id = entry->src_bus_id; 1521 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq; 1522 if (entry->dst_apic_id == 255) { 1523 /* This signal goes to all IO APICS. Select an IO APIC 1524 with sufficient number of interrupt pins */ 1525 for (apic = 0; apic < mp_napics; apic++) 1526 if (((io_apic_read(apic, IOAPIC_VER) & 1527 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >= 1528 entry->dst_apic_int) 1529 break; 1530 if (apic < mp_napics) 1531 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic); 1532 else 1533 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; 1534 } else 1535 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; 1536 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int; 1537 1538 return 1; 1539} 1540 1541 1542static int 1543apic_int_is_bus_type(int intr, int bus_type) 1544{ 1545 int bus; 1546 1547 for (bus = 0; bus < mp_nbusses; ++bus) 1548 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) 1549 && ((int) bus_data[bus].bus_type == bus_type)) 1550 return 1; 1551 1552 return 0; 1553} 1554 1555 1556/* 1557 * Given a traditional ISA INT mask, return an APIC mask. 1558 */ 1559u_int 1560isa_apic_mask(u_int isa_mask) 1561{ 1562 int isa_irq; 1563 int apic_pin; 1564 1565#if defined(SKIP_IRQ15_REDIRECT) 1566 if (isa_mask == (1 << 15)) { 1567 printf("skipping ISA IRQ15 redirect\n"); 1568 return isa_mask; 1569 } 1570#endif /* SKIP_IRQ15_REDIRECT */ 1571 1572 isa_irq = ffs(isa_mask); /* find its bit position */ 1573 if (isa_irq == 0) /* doesn't exist */ 1574 return 0; 1575 --isa_irq; /* make it zero based */ 1576 1577 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */ 1578 if (apic_pin == -1) 1579 return 0; 1580 1581 return (1 << apic_pin); /* convert pin# to a mask */ 1582} 1583 1584 1585/* 1586 * Determine which APIC pin an ISA/EISA INT is attached to. 1587 */ 1588#define INTTYPE(I) (io_apic_ints[(I)].int_type) 1589#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) 1590#define INTIRQ(I) (io_apic_ints[(I)].int_vector) 1591#define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id)) 1592 1593#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) 1594int 1595isa_apic_irq(int isa_irq) 1596{ 1597 int intr; 1598 1599 for (intr = 0; intr < nintrs; ++intr) { /* check each record */ 1600 if (INTTYPE(intr) == 0) { /* standard INT */ 1601 if (SRCBUSIRQ(intr) == isa_irq) { 1602 if (apic_int_is_bus_type(intr, ISA) || 1603 apic_int_is_bus_type(intr, EISA)) { 1604 if (INTIRQ(intr) == 0xff) 1605 return -1; /* unassigned */ 1606 return INTIRQ(intr); /* found */ 1607 } 1608 } 1609 } 1610 } 1611 return -1; /* NOT found */ 1612} 1613 1614 1615/* 1616 * Determine which APIC pin a PCI INT is attached to. 1617 */ 1618#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) 1619#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) 1620#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) 1621int 1622pci_apic_irq(int pciBus, int pciDevice, int pciInt) 1623{ 1624 int intr; 1625 1626 --pciInt; /* zero based */ 1627 1628 for (intr = 0; intr < nintrs; ++intr) /* check each record */ 1629 if ((INTTYPE(intr) == 0) /* standard INT */ 1630 && (SRCBUSID(intr) == pciBus) 1631 && (SRCBUSDEVICE(intr) == pciDevice) 1632 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ 1633 if (apic_int_is_bus_type(intr, PCI)) { 1634 if (INTIRQ(intr) == 0xff) 1635 allocate_apic_irq(intr); 1636 if (INTIRQ(intr) == 0xff) 1637 return -1; /* unassigned */ 1638 return INTIRQ(intr); /* exact match */ 1639 } 1640 1641 return -1; /* NOT found */ 1642} 1643 1644int 1645next_apic_irq(int irq) 1646{ 1647 int intr, ointr; 1648 int bus, bustype; 1649 1650 bus = 0; 1651 bustype = 0; 1652 for (intr = 0; intr < nintrs; intr++) { 1653 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0) 1654 continue; 1655 bus = SRCBUSID(intr); 1656 bustype = apic_bus_type(bus); 1657 if (bustype != ISA && 1658 bustype != EISA && 1659 bustype != PCI) 1660 continue; 1661 break; 1662 } 1663 if (intr >= nintrs) { 1664 return -1; 1665 } 1666 for (ointr = intr + 1; ointr < nintrs; ointr++) { 1667 if (INTTYPE(ointr) != 0) 1668 continue; 1669 if (bus != SRCBUSID(ointr)) 1670 continue; 1671 if (bustype == PCI) { 1672 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr)) 1673 continue; 1674 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr)) 1675 continue; 1676 } 1677 if (bustype == ISA || bustype == EISA) { 1678 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr)) 1679 continue; 1680 } 1681 if (INTPIN(intr) == INTPIN(ointr)) 1682 continue; 1683 break; 1684 } 1685 if (ointr >= nintrs) { 1686 return -1; 1687 } 1688 return INTIRQ(ointr); 1689} 1690#undef SRCBUSLINE 1691#undef SRCBUSDEVICE 1692#undef SRCBUSID 1693#undef SRCBUSIRQ 1694 1695#undef INTPIN 1696#undef INTIRQ 1697#undef INTAPIC 1698#undef INTTYPE 1699 1700 1701/* 1702 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt. 1703 * 1704 * XXX FIXME: 1705 * Exactly what this means is unclear at this point. It is a solution 1706 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard 1707 * could route any of the ISA INTs to upper (>15) IRQ values. But most would 1708 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an 1709 * option. 1710 */ 1711int 1712undirect_isa_irq(int rirq) 1713{ 1714#if defined(READY) 1715 if (bootverbose) 1716 printf("Freeing redirected ISA irq %d.\n", rirq); 1717 /** FIXME: tickle the MB redirector chip */ 1718 return -1; 1719#else 1720 if (bootverbose) 1721 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq); 1722 return 0; 1723#endif /* READY */ 1724} 1725 1726 1727/* 1728 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt 1729 */ 1730int 1731undirect_pci_irq(int rirq) 1732{ 1733#if defined(READY) 1734 if (bootverbose) 1735 printf("Freeing redirected PCI irq %d.\n", rirq); 1736 1737 /** FIXME: tickle the MB redirector chip */ 1738 return -1; 1739#else 1740 if (bootverbose) 1741 printf("Freeing (NOT implemented) redirected PCI irq %d.\n", 1742 rirq); 1743 return 0; 1744#endif /* READY */ 1745} 1746 1747 1748/* 1749 * given a bus ID, return: 1750 * the bus type if found 1751 * -1 if NOT found 1752 */ 1753int 1754apic_bus_type(int id) 1755{ 1756 int x; 1757 1758 for (x = 0; x < mp_nbusses; ++x) 1759 if (bus_data[x].bus_id == id) 1760 return bus_data[x].bus_type; 1761 1762 return -1; 1763} 1764 1765 1766/* 1767 * given a LOGICAL APIC# and pin#, return: 1768 * the associated src bus ID if found 1769 * -1 if NOT found 1770 */ 1771int 1772apic_src_bus_id(int apic, int pin) 1773{ 1774 int x; 1775 1776 /* search each of the possible INTerrupt sources */ 1777 for (x = 0; x < nintrs; ++x) 1778 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1779 (pin == io_apic_ints[x].dst_apic_int)) 1780 return (io_apic_ints[x].src_bus_id); 1781 1782 return -1; /* NOT found */ 1783} 1784 1785 1786/* 1787 * given a LOGICAL APIC# and pin#, return: 1788 * the associated src bus IRQ if found 1789 * -1 if NOT found 1790 */ 1791int 1792apic_src_bus_irq(int apic, int pin) 1793{ 1794 int x; 1795 1796 for (x = 0; x < nintrs; x++) 1797 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1798 (pin == io_apic_ints[x].dst_apic_int)) 1799 return (io_apic_ints[x].src_bus_irq); 1800 1801 return -1; /* NOT found */ 1802} 1803 1804 1805/* 1806 * given a LOGICAL APIC# and pin#, return: 1807 * the associated INTerrupt type if found 1808 * -1 if NOT found 1809 */ 1810int 1811apic_int_type(int apic, int pin) 1812{ 1813 int x; 1814 1815 /* search each of the possible INTerrupt sources */ 1816 for (x = 0; x < nintrs; ++x) 1817 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1818 (pin == io_apic_ints[x].dst_apic_int)) 1819 return (io_apic_ints[x].int_type); 1820 1821 return -1; /* NOT found */ 1822} 1823 1824int 1825apic_irq(int apic, int pin) 1826{ 1827 int x; 1828 int res; 1829 1830 for (x = 0; x < nintrs; ++x) 1831 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1832 (pin == io_apic_ints[x].dst_apic_int)) { 1833 res = io_apic_ints[x].int_vector; 1834 if (res == 0xff) 1835 return -1; 1836 if (apic != int_to_apicintpin[res].ioapic) 1837 panic("apic_irq: inconsistent table"); 1838 if (pin != int_to_apicintpin[res].int_pin) 1839 panic("apic_irq inconsistent table (2)"); 1840 return res; 1841 } 1842 return -1; 1843} 1844 1845 1846/* 1847 * given a LOGICAL APIC# and pin#, return: 1848 * the associated trigger mode if found 1849 * -1 if NOT found 1850 */ 1851int 1852apic_trigger(int apic, int pin) 1853{ 1854 int x; 1855 1856 /* search each of the possible INTerrupt sources */ 1857 for (x = 0; x < nintrs; ++x) 1858 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1859 (pin == io_apic_ints[x].dst_apic_int)) 1860 return ((io_apic_ints[x].int_flags >> 2) & 0x03); 1861 1862 return -1; /* NOT found */ 1863} 1864 1865 1866/* 1867 * given a LOGICAL APIC# and pin#, return: 1868 * the associated 'active' level if found 1869 * -1 if NOT found 1870 */ 1871int 1872apic_polarity(int apic, int pin) 1873{ 1874 int x; 1875 1876 /* search each of the possible INTerrupt sources */ 1877 for (x = 0; x < nintrs; ++x) 1878 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1879 (pin == io_apic_ints[x].dst_apic_int)) 1880 return (io_apic_ints[x].int_flags & 0x03); 1881 1882 return -1; /* NOT found */ 1883} 1884 1885 1886/* 1887 * set data according to MP defaults 1888 * FIXME: probably not complete yet... 1889 */ 1890static void 1891default_mp_table(int type) 1892{ 1893 int ap_cpu_id; 1894#if defined(APIC_IO) 1895 int io_apic_id; 1896 int pin; 1897#endif /* APIC_IO */ 1898 1899#if 0 1900 printf(" MP default config type: %d\n", type); 1901 switch (type) { 1902 case 1: 1903 printf(" bus: ISA, APIC: 82489DX\n"); 1904 break; 1905 case 2: 1906 printf(" bus: EISA, APIC: 82489DX\n"); 1907 break; 1908 case 3: 1909 printf(" bus: EISA, APIC: 82489DX\n"); 1910 break; 1911 case 4: 1912 printf(" bus: MCA, APIC: 82489DX\n"); 1913 break; 1914 case 5: 1915 printf(" bus: ISA+PCI, APIC: Integrated\n"); 1916 break; 1917 case 6: 1918 printf(" bus: EISA+PCI, APIC: Integrated\n"); 1919 break; 1920 case 7: 1921 printf(" bus: MCA+PCI, APIC: Integrated\n"); 1922 break; 1923 default: 1924 printf(" future type\n"); 1925 break; 1926 /* NOTREACHED */ 1927 } 1928#endif /* 0 */ 1929 1930 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24; 1931 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; 1932 1933 /* BSP */ 1934 CPU_TO_ID(0) = boot_cpu_id; 1935 ID_TO_CPU(boot_cpu_id) = 0; 1936 1937 /* one and only AP */ 1938 CPU_TO_ID(1) = ap_cpu_id; 1939 ID_TO_CPU(ap_cpu_id) = 1; 1940 1941#if defined(APIC_IO) 1942 /* one and only IO APIC */ 1943 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; 1944 1945 /* 1946 * sanity check, refer to MP spec section 3.6.6, last paragraph 1947 * necessary as some hardware isn't properly setting up the IO APIC 1948 */ 1949#if defined(REALLY_ANAL_IOAPICID_VALUE) 1950 if (io_apic_id != 2) { 1951#else 1952 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { 1953#endif /* REALLY_ANAL_IOAPICID_VALUE */ 1954 io_apic_set_id(0, 2); 1955 io_apic_id = 2; 1956 } 1957 IO_TO_ID(0) = io_apic_id; 1958 ID_TO_IO(io_apic_id) = 0; 1959#endif /* APIC_IO */ 1960 1961 /* fill out bus entries */ 1962 switch (type) { 1963 case 1: 1964 case 2: 1965 case 3: 1966 case 4: 1967 case 5: 1968 case 6: 1969 case 7: 1970 bus_data[0].bus_id = default_data[type - 1][1]; 1971 bus_data[0].bus_type = default_data[type - 1][2]; 1972 bus_data[1].bus_id = default_data[type - 1][3]; 1973 bus_data[1].bus_type = default_data[type - 1][4]; 1974 break; 1975 1976 /* case 4: case 7: MCA NOT supported */ 1977 default: /* illegal/reserved */ 1978 panic("BAD default MP config: %d", type); 1979 /* NOTREACHED */ 1980 } 1981 1982#if defined(APIC_IO) 1983 /* general cases from MP v1.4, table 5-2 */ 1984 for (pin = 0; pin < 16; ++pin) { 1985 io_apic_ints[pin].int_type = 0; 1986 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */ 1987 io_apic_ints[pin].src_bus_id = 0; 1988 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */ 1989 io_apic_ints[pin].dst_apic_id = io_apic_id; 1990 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */ 1991 } 1992 1993 /* special cases from MP v1.4, table 5-2 */ 1994 if (type == 2) { 1995 io_apic_ints[2].int_type = 0xff; /* N/C */ 1996 io_apic_ints[13].int_type = 0xff; /* N/C */ 1997#if !defined(APIC_MIXED_MODE) 1998 /** FIXME: ??? */ 1999 panic("sorry, can't support type 2 default yet"); 2000#endif /* APIC_MIXED_MODE */ 2001 } 2002 else 2003 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ 2004 2005 if (type == 7) 2006 io_apic_ints[0].int_type = 0xff; /* N/C */ 2007 else 2008 io_apic_ints[0].int_type = 3; /* vectored 8259 */ 2009#endif /* APIC_IO */ 2010} 2011 2012 2013/* 2014 * start each AP in our list 2015 */ 2016static int 2017start_all_aps(u_int boot_addr) 2018{ 2019 int x, i, pg; 2020#ifndef PC98 2021 u_char mpbiosreason; 2022#endif 2023 u_long mpbioswarmvec; 2024 struct pcpu *pc; 2025 char *stack; 2026 uintptr_t kptbase; 2027 2028 POSTCODE(START_ALL_APS_POST); 2029 2030 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); 2031 2032 /* initialize BSP's local APIC */ 2033 apic_initialize(); 2034 bsp_apic_ready = 1; 2035 2036 /* install the AP 1st level boot code */ 2037 install_ap_tramp(boot_addr); 2038 2039 2040 /* save the current value of the warm-start vector */ 2041 mpbioswarmvec = *((u_long *) WARMBOOT_OFF); 2042#ifndef PC98 2043 outb(CMOS_REG, BIOS_RESET); 2044 mpbiosreason = inb(CMOS_DATA); 2045#endif 2046 2047 /* set up temporary P==V mapping for AP boot */ 2048 /* XXX this is a hack, we should boot the AP on its own stack/PTD */ 2049 kptbase = (uintptr_t)(void *)KPTphys; 2050 for (x = 0; x < NKPT; x++) 2051 PTD[x] = (pd_entry_t)(PG_V | PG_RW | 2052 ((kptbase + x * PAGE_SIZE) & PG_FRAME)); 2053 invltlb(); 2054 2055 /* start each AP */ 2056 for (x = 1; x <= mp_naps; ++x) { 2057 2058 /* This is a bit verbose, it will go away soon. */ 2059 2060 /* first page of AP's private space */ 2061 pg = x * i386_btop(sizeof(struct privatespace)); 2062 2063 /* allocate a new private data page */ 2064 pc = (struct pcpu *)kmem_alloc(kernel_map, PAGE_SIZE); 2065 2066 /* wire it into the private page table page */ 2067 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys(pc)); 2068 2069 /* allocate and set up an idle stack data page */ 2070 stack = (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE); /* XXXKSE */ 2071 for (i = 0; i < KSTACK_PAGES; i++) 2072 SMPpt[pg + 1 + i] = (pt_entry_t) 2073 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 2074 2075 /* prime data page for it to use */ 2076 pcpu_init(pc, x, sizeof(struct pcpu)); 2077 2078 /* setup a vector to our boot code */ 2079 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 2080 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); 2081#ifndef PC98 2082 outb(CMOS_REG, BIOS_RESET); 2083 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 2084#endif 2085 2086 bootSTK = &SMP_prvspace[x].idlekstack[KSTACK_PAGES * PAGE_SIZE]; 2087 bootAP = x; 2088 2089 /* attempt to start the Application Processor */ 2090 CHECK_INIT(99); /* setup checkpoints */ 2091 if (!start_ap(x, boot_addr)) { 2092 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); 2093 CHECK_PRINT("trace"); /* show checkpoints */ 2094 /* better panic as the AP may be running loose */ 2095 printf("panic y/n? [y] "); 2096 if (cngetc() != 'n') 2097 panic("bye-bye"); 2098 } 2099 CHECK_PRINT("trace"); /* show checkpoints */ 2100 2101 /* record its version info */ 2102 cpu_apic_versions[x] = cpu_apic_versions[0]; 2103 2104 all_cpus |= (1 << x); /* record AP in CPU map */ 2105 } 2106 2107 /* build our map of 'other' CPUs */ 2108 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 2109 2110 /* fill in our (BSP) APIC version */ 2111 cpu_apic_versions[0] = lapic.version; 2112 2113 /* restore the warmstart vector */ 2114 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 2115#ifndef PC98 2116 outb(CMOS_REG, BIOS_RESET); 2117 outb(CMOS_DATA, mpbiosreason); 2118#endif 2119 2120 /* 2121 * Set up the idle context for the BSP. Similar to above except 2122 * that some was done by locore, some by pmap.c and some is implicit 2123 * because the BSP is cpu#0 and the page is initially zero, and also 2124 * because we can refer to variables by name on the BSP.. 2125 */ 2126 2127 /* Allocate and setup BSP idle stack */ 2128 stack = (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE); 2129 for (i = 0; i < KSTACK_PAGES; i++) 2130 SMPpt[1 + i] = (pt_entry_t) 2131 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 2132 2133 for (x = 0; x < NKPT; x++) 2134 PTD[x] = 0; 2135 pmap_set_opt(); 2136 2137 /* number of APs actually started */ 2138 return mp_ncpus - 1; 2139} 2140 2141 2142/* 2143 * load the 1st level AP boot code into base memory. 2144 */ 2145 2146/* targets for relocation */ 2147extern void bigJump(void); 2148extern void bootCodeSeg(void); 2149extern void bootDataSeg(void); 2150extern void MPentry(void); 2151extern u_int MP_GDT; 2152extern u_int mp_gdtbase; 2153 2154static void 2155install_ap_tramp(u_int boot_addr) 2156{ 2157 int x; 2158 int size = *(int *) ((u_long) & bootMP_size); 2159 u_char *src = (u_char *) ((u_long) bootMP); 2160 u_char *dst = (u_char *) boot_addr + KERNBASE; 2161 u_int boot_base = (u_int) bootMP; 2162 u_int8_t *dst8; 2163 u_int16_t *dst16; 2164 u_int32_t *dst32; 2165 2166 POSTCODE(INSTALL_AP_TRAMP_POST); 2167 2168 for (x = 0; x < size; ++x) 2169 *dst++ = *src++; 2170 2171 /* 2172 * modify addresses in code we just moved to basemem. unfortunately we 2173 * need fairly detailed info about mpboot.s for this to work. changes 2174 * to mpboot.s might require changes here. 2175 */ 2176 2177 /* boot code is located in KERNEL space */ 2178 dst = (u_char *) boot_addr + KERNBASE; 2179 2180 /* modify the lgdt arg */ 2181 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 2182 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); 2183 2184 /* modify the ljmp target for MPentry() */ 2185 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 2186 *dst32 = ((u_int) MPentry - KERNBASE); 2187 2188 /* modify the target for boot code segment */ 2189 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 2190 dst8 = (u_int8_t *) (dst16 + 1); 2191 *dst16 = (u_int) boot_addr & 0xffff; 2192 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 2193 2194 /* modify the target for boot data segment */ 2195 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 2196 dst8 = (u_int8_t *) (dst16 + 1); 2197 *dst16 = (u_int) boot_addr & 0xffff; 2198 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 2199} 2200 2201 2202/* 2203 * this function starts the AP (application processor) identified 2204 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 2205 * to accomplish this. This is necessary because of the nuances 2206 * of the different hardware we might encounter. It ain't pretty, 2207 * but it seems to work. 2208 */ 2209static int 2210start_ap(int logical_cpu, u_int boot_addr) 2211{ 2212 int physical_cpu; 2213 int vector; 2214 int cpus; 2215 u_long icr_lo, icr_hi; 2216 2217 POSTCODE(START_AP_POST); 2218 2219 /* get the PHYSICAL APIC ID# */ 2220 physical_cpu = CPU_TO_ID(logical_cpu); 2221 2222 /* calculate the vector */ 2223 vector = (boot_addr >> 12) & 0xff; 2224 2225 /* used as a watchpoint to signal AP startup */ 2226 cpus = mp_ncpus; 2227 2228 /* 2229 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 2230 * and running the target CPU. OR this INIT IPI might be latched (P5 2231 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 2232 * ignored. 2233 */ 2234 2235 /* setup the address for the target AP */ 2236 icr_hi = lapic.icr_hi & ~APIC_ID_MASK; 2237 icr_hi |= (physical_cpu << 24); 2238 lapic.icr_hi = icr_hi; 2239 2240 /* do an INIT IPI: assert RESET */ 2241 icr_lo = lapic.icr_lo & 0xfff00000; 2242 lapic.icr_lo = icr_lo | 0x0000c500; 2243 2244 /* wait for pending status end */ 2245 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2246 /* spin */ ; 2247 2248 /* do an INIT IPI: deassert RESET */ 2249 lapic.icr_lo = icr_lo | 0x00008500; 2250 2251 /* wait for pending status end */ 2252 u_sleep(10000); /* wait ~10mS */ 2253 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2254 /* spin */ ; 2255 2256 /* 2257 * next we do a STARTUP IPI: the previous INIT IPI might still be 2258 * latched, (P5 bug) this 1st STARTUP would then terminate 2259 * immediately, and the previously started INIT IPI would continue. OR 2260 * the previous INIT IPI has already run. and this STARTUP IPI will 2261 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 2262 * will run. 2263 */ 2264 2265 /* do a STARTUP IPI */ 2266 lapic.icr_lo = icr_lo | 0x00000600 | vector; 2267 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2268 /* spin */ ; 2269 u_sleep(200); /* wait ~200uS */ 2270 2271 /* 2272 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 2273 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 2274 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 2275 * recognized after hardware RESET or INIT IPI. 2276 */ 2277 2278 lapic.icr_lo = icr_lo | 0x00000600 | vector; 2279 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2280 /* spin */ ; 2281 u_sleep(200); /* wait ~200uS */ 2282 2283 /* wait for it to start */ 2284 set_apic_timer(5000000);/* == 5 seconds */ 2285 while (read_apic_timer()) 2286 if (mp_ncpus > cpus) 2287 return 1; /* return SUCCESS */ 2288 2289 return 0; /* return FAILURE */ 2290} 2291 2292#if defined(APIC_IO) 2293 2294#ifdef COUNT_XINVLTLB_HITS 2295u_int xhits_gbl[MAXCPU]; 2296u_int xhits_pg[MAXCPU]; 2297u_int xhits_rng[MAXCPU]; 2298SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, ""); 2299SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl, 2300 sizeof(xhits_gbl), "IU", ""); 2301SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg, 2302 sizeof(xhits_pg), "IU", ""); 2303SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng, 2304 sizeof(xhits_rng), "IU", ""); 2305 2306u_int ipi_global; 2307u_int ipi_page; 2308u_int ipi_range; 2309u_int ipi_range_size; 2310SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, ""); 2311SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, ""); 2312SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, ""); 2313SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size, 2314 0, ""); 2315 2316u_int ipi_masked_global; 2317u_int ipi_masked_page; 2318u_int ipi_masked_range; 2319u_int ipi_masked_range_size; 2320SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW, 2321 &ipi_masked_global, 0, ""); 2322SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW, 2323 &ipi_masked_page, 0, ""); 2324SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW, 2325 &ipi_masked_range, 0, ""); 2326SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW, 2327 &ipi_masked_range_size, 0, ""); 2328#endif 2329 2330/* 2331 * Flush the TLB on all other CPU's 2332 */ 2333static void 2334smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2) 2335{ 2336 u_int ncpu; 2337 register_t eflags; 2338 2339 ncpu = mp_ncpus - 1; /* does not shootdown self */ 2340 if (ncpu < 1) 2341 return; /* no other cpus */ 2342 eflags = read_eflags(); 2343 if ((eflags & PSL_I) == 0) 2344 panic("absolutely cannot call smp_ipi_shootdown with interrupts already disabled"); 2345 mtx_lock_spin(&smp_tlb_mtx); 2346 smp_tlb_addr1 = addr1; 2347 smp_tlb_addr2 = addr2; 2348 atomic_store_rel_int(&smp_tlb_wait, 0); 2349 ipi_all_but_self(vector); 2350 while (smp_tlb_wait < ncpu) 2351 ia32_pause(); 2352 mtx_unlock_spin(&smp_tlb_mtx); 2353} 2354 2355/* 2356 * This is about as magic as it gets. fortune(1) has got similar code 2357 * for reversing bits in a word. Who thinks up this stuff?? 2358 * 2359 * Yes, it does appear to be consistently faster than: 2360 * while (i = ffs(m)) { 2361 * m >>= i; 2362 * bits++; 2363 * } 2364 * and 2365 * while (lsb = (m & -m)) { // This is magic too 2366 * m &= ~lsb; // or: m ^= lsb 2367 * bits++; 2368 * } 2369 * Both of these latter forms do some very strange things on gcc-3.1 with 2370 * -mcpu=pentiumpro and/or -march=pentiumpro and/or -O or -O2. 2371 * There is probably an SSE or MMX popcnt instruction. 2372 * 2373 * I wonder if this should be in libkern? 2374 * 2375 * XXX Stop the presses! Another one: 2376 * static __inline u_int32_t 2377 * popcnt1(u_int32_t v) 2378 * { 2379 * v -= ((v >> 1) & 0x55555555); 2380 * v = (v & 0x33333333) + ((v >> 2) & 0x33333333); 2381 * v = (v + (v >> 4)) & 0x0F0F0F0F; 2382 * return (v * 0x01010101) >> 24; 2383 * } 2384 * The downside is that it has a multiply. With a pentium3 with 2385 * -mcpu=pentiumpro and -march=pentiumpro then gcc-3.1 will use 2386 * an imull, and in that case it is faster. In most other cases 2387 * it appears slightly slower. 2388 */ 2389static __inline u_int32_t 2390popcnt(u_int32_t m) 2391{ 2392 2393 m = (m & 0x55555555) + ((m & 0xaaaaaaaa) >> 1); 2394 m = (m & 0x33333333) + ((m & 0xcccccccc) >> 2); 2395 m = (m & 0x0f0f0f0f) + ((m & 0xf0f0f0f0) >> 4); 2396 m = (m & 0x00ff00ff) + ((m & 0xff00ff00) >> 8); 2397 m = (m & 0x0000ffff) + ((m & 0xffff0000) >> 16); 2398 return m; 2399} 2400 2401static void 2402smp_targeted_tlb_shootdown(u_int mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2) 2403{ 2404 int ncpu, othercpus; 2405 register_t eflags; 2406 2407 othercpus = mp_ncpus - 1; 2408 if (mask == (u_int)-1) { 2409 ncpu = othercpus; 2410 if (ncpu < 1) 2411 return; 2412 } else { 2413 /* XXX there should be a pcpu self mask */ 2414 mask &= ~(1 << PCPU_GET(cpuid)); 2415 if (mask == 0) 2416 return; 2417 ncpu = popcnt(mask); 2418 if (ncpu > othercpus) { 2419 /* XXX this should be a panic offence */ 2420 printf("SMP: tlb shootdown to %d other cpus (only have %d)\n", 2421 ncpu, othercpus); 2422 ncpu = othercpus; 2423 } 2424 /* XXX should be a panic, implied by mask == 0 above */ 2425 if (ncpu < 1) 2426 return; 2427 } 2428 eflags = read_eflags(); 2429 if ((eflags & PSL_I) == 0) 2430 panic("absolutely cannot call smp_targeted_ipi_shootdown with interrupts already disabled"); 2431 mtx_lock_spin(&smp_tlb_mtx); 2432 smp_tlb_addr1 = addr1; 2433 smp_tlb_addr2 = addr2; 2434 atomic_store_rel_int(&smp_tlb_wait, 0); 2435 if (mask == (u_int)-1) 2436 ipi_all_but_self(vector); 2437 else 2438 ipi_selected(mask, vector); 2439 while (smp_tlb_wait < ncpu) 2440 ia32_pause(); 2441 mtx_unlock_spin(&smp_tlb_mtx); 2442} 2443#endif 2444 2445void 2446smp_invltlb(void) 2447{ 2448#if defined(APIC_IO) 2449 if (smp_started) { 2450 smp_tlb_shootdown(IPI_INVLTLB, 0, 0); 2451#ifdef COUNT_XINVLTLB_HITS 2452 ipi_global++; 2453#endif 2454 } 2455#endif /* APIC_IO */ 2456} 2457 2458void 2459smp_invlpg(vm_offset_t addr) 2460{ 2461#if defined(APIC_IO) 2462 if (smp_started) { 2463 smp_tlb_shootdown(IPI_INVLPG, addr, 0); 2464#ifdef COUNT_XINVLTLB_HITS 2465 ipi_page++; 2466#endif 2467 } 2468#endif /* APIC_IO */ 2469} 2470 2471void 2472smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2) 2473{ 2474#if defined(APIC_IO) 2475 if (smp_started) { 2476 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2); 2477#ifdef COUNT_XINVLTLB_HITS 2478 ipi_range++; 2479 ipi_range_size += (addr2 - addr1) / PAGE_SIZE; 2480#endif 2481 } 2482#endif /* APIC_IO */ 2483} 2484 2485void 2486smp_masked_invltlb(u_int mask) 2487{ 2488#if defined(APIC_IO) 2489 if (smp_started) { 2490 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0); 2491#ifdef COUNT_XINVLTLB_HITS 2492 ipi_masked_global++; 2493#endif 2494 } 2495#endif /* APIC_IO */ 2496} 2497 2498void 2499smp_masked_invlpg(u_int mask, vm_offset_t addr) 2500{ 2501#if defined(APIC_IO) 2502 if (smp_started) { 2503 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0); 2504#ifdef COUNT_XINVLTLB_HITS 2505 ipi_masked_page++; 2506#endif 2507 } 2508#endif /* APIC_IO */ 2509} 2510 2511void 2512smp_masked_invlpg_range(u_int mask, vm_offset_t addr1, vm_offset_t addr2) 2513{ 2514#if defined(APIC_IO) 2515 if (smp_started) { 2516 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2); 2517#ifdef COUNT_XINVLTLB_HITS 2518 ipi_masked_range++; 2519 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE; 2520#endif 2521 } 2522#endif /* APIC_IO */ 2523} 2524 2525 2526/* 2527 * This is called once the rest of the system is up and running and we're 2528 * ready to let the AP's out of the pen. 2529 */ 2530void 2531ap_init(void) 2532{ 2533 u_int apic_id; 2534 2535 /* spin until all the AP's are ready */ 2536 while (!aps_ready) 2537 ia32_pause(); 2538 2539 /* BSP may have changed PTD while we were waiting */ 2540 invltlb(); 2541 2542#if defined(I586_CPU) && !defined(NO_F00F_HACK) 2543 lidt(&r_idt); 2544#endif 2545 2546 /* set up CPU registers and state */ 2547 cpu_setregs(); 2548 2549 /* set up FPU state on the AP */ 2550 npxinit(__INITIAL_NPXCW__); 2551 2552 /* set up SSE registers */ 2553 enable_sse(); 2554 2555 /* A quick check from sanity claus */ 2556 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]); 2557 if (PCPU_GET(cpuid) != apic_id) { 2558 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid)); 2559 printf("SMP: apic_id = %d\n", apic_id); 2560 printf("PTD[MPPTDI] = %#jx\n", (uintmax_t)PTD[MPPTDI]); 2561 panic("cpuid mismatch! boom!!"); 2562 } 2563 2564 /* Init local apic for irq's */ 2565 apic_initialize(); 2566 2567 /* Set memory range attributes for this CPU to match the BSP */ 2568 mem_range_AP_init(); 2569 2570 mtx_lock_spin(&ap_boot_mtx); 2571 2572 smp_cpus++; 2573 2574 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", PCPU_GET(cpuid)); 2575 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid)); 2576 2577 /* Build our map of 'other' CPUs. */ 2578 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 2579 2580 if (bootverbose) 2581 apic_dump("ap_init()"); 2582 2583 if (smp_cpus == mp_ncpus) { 2584 /* enable IPI's, tlb shootdown, freezes etc */ 2585 atomic_store_rel_int(&smp_started, 1); 2586 smp_active = 1; /* historic */ 2587 } 2588 2589 mtx_unlock_spin(&ap_boot_mtx); 2590 2591 /* wait until all the AP's are up */ 2592 while (smp_started == 0) 2593 ia32_pause(); 2594 2595 /* ok, now grab sched_lock and enter the scheduler */ 2596 mtx_lock_spin(&sched_lock); 2597 2598 binuptime(PCPU_PTR(switchtime)); 2599 PCPU_SET(switchticks, ticks); 2600 2601 cpu_throw(); /* doesn't return */ 2602 2603 panic("scheduler returned us to %s", __func__); 2604} 2605 2606/* 2607 * For statclock, we send an IPI to all CPU's to have them call this 2608 * function. 2609 * 2610 * WARNING! unpend() will call statclock() directly and skip this 2611 * routine. 2612 */ 2613void 2614forwarded_statclock(struct clockframe frame) 2615{ 2616 2617 if (profprocs != 0) 2618 profclock(&frame); 2619 if (pscnt == psdiv) 2620 statclock(&frame); 2621} 2622 2623void 2624forward_statclock(void) 2625{ 2626 int map; 2627 2628 CTR0(KTR_SMP, "forward_statclock"); 2629 2630 if (!smp_started || cold || panicstr) 2631 return; 2632 2633 map = PCPU_GET(other_cpus) & ~stopped_cpus ; 2634 if (map != 0) 2635 ipi_selected(map, IPI_STATCLOCK); 2636} 2637 2638/* 2639 * For each hardclock(), we send an IPI to all other CPU's to have them 2640 * execute this function. It would be nice to reduce contention on 2641 * sched_lock if we could simply peek at the CPU to determine the user/kernel 2642 * state and call hardclock_process() on the CPU receiving the clock interrupt 2643 * and then just use a simple IPI to handle any ast's if needed. 2644 * 2645 * WARNING! unpend() will call hardclock_process() directly and skip this 2646 * routine. 2647 */ 2648void 2649forwarded_hardclock(struct clockframe frame) 2650{ 2651 2652 hardclock_process(&frame); 2653} 2654 2655void 2656forward_hardclock(void) 2657{ 2658 u_int map; 2659 2660 CTR0(KTR_SMP, "forward_hardclock"); 2661 2662 if (!smp_started || cold || panicstr) 2663 return; 2664 2665 map = PCPU_GET(other_cpus) & ~stopped_cpus ; 2666 if (map != 0) 2667 ipi_selected(map, IPI_HARDCLOCK); 2668} 2669 2670#ifdef APIC_INTR_REORDER 2671/* 2672 * Maintain mapping from softintr vector to isr bit in local apic. 2673 */ 2674void 2675set_lapic_isrloc(int intr, int vector) 2676{ 2677 if (intr < 0 || intr > 32) 2678 panic("set_apic_isrloc: bad intr argument: %d",intr); 2679 if (vector < ICU_OFFSET || vector > 255) 2680 panic("set_apic_isrloc: bad vector argument: %d",vector); 2681 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2); 2682 apic_isrbit_location[intr].bit = (1<<(vector & 31)); 2683} 2684#endif 2685 2686/* 2687 * send an IPI to a set of cpus. 2688 */ 2689void 2690ipi_selected(u_int32_t cpus, u_int ipi) 2691{ 2692 2693 CTR3(KTR_SMP, "%s: cpus: %x ipi: %x", __func__, cpus, ipi); 2694 selected_apic_ipi(cpus, ipi, APIC_DELMODE_FIXED); 2695} 2696 2697/* 2698 * send an IPI INTerrupt containing 'vector' to all CPUs, including myself 2699 */ 2700void 2701ipi_all(u_int ipi) 2702{ 2703 2704 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 2705 apic_ipi(APIC_DEST_ALLISELF, ipi, APIC_DELMODE_FIXED); 2706} 2707 2708/* 2709 * send an IPI to all CPUs EXCEPT myself 2710 */ 2711void 2712ipi_all_but_self(u_int ipi) 2713{ 2714 2715 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 2716 apic_ipi(APIC_DEST_ALLESELF, ipi, APIC_DELMODE_FIXED); 2717} 2718 2719/* 2720 * send an IPI to myself 2721 */ 2722void 2723ipi_self(u_int ipi) 2724{ 2725 2726 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 2727 apic_ipi(APIC_DEST_SELF, ipi, APIC_DELMODE_FIXED); 2728} 2729 2730static void 2731release_aps(void *dummy __unused) 2732{ 2733 2734 if (mp_ncpus == 1) 2735 return; 2736 mtx_lock_spin(&sched_lock); 2737 atomic_store_rel_int(&aps_ready, 1); 2738 while (smp_started == 0) 2739 ia32_pause(); 2740 mtx_unlock_spin(&sched_lock); 2741} 2742 2743SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL); 2744 2745static int hlt_cpus_mask; 2746static int hlt_logical_cpus = 1; 2747static struct sysctl_ctx_list logical_cpu_clist; 2748 2749static int 2750sysctl_hlt_cpus(SYSCTL_HANDLER_ARGS) 2751{ 2752 u_int mask; 2753 int error; 2754 2755 mask = hlt_cpus_mask; 2756 error = sysctl_handle_int(oidp, &mask, 0, req); 2757 if (error || !req->newptr) 2758 return (error); 2759 2760 if (logical_cpus_mask != 0 && 2761 (mask & logical_cpus_mask) == logical_cpus_mask) 2762 hlt_logical_cpus = 1; 2763 else 2764 hlt_logical_cpus = 0; 2765 2766 if ((mask & all_cpus) == all_cpus) 2767 mask &= ~(1<<0); 2768 hlt_cpus_mask = mask; 2769 return (error); 2770} 2771SYSCTL_PROC(_machdep, OID_AUTO, hlt_cpus, CTLTYPE_INT|CTLFLAG_RW, 2772 0, 0, sysctl_hlt_cpus, "IU", ""); 2773 2774static int 2775sysctl_hlt_logical_cpus(SYSCTL_HANDLER_ARGS) 2776{ 2777 int disable, error; 2778 2779 disable = hlt_logical_cpus; 2780 error = sysctl_handle_int(oidp, &disable, 0, req); 2781 if (error || !req->newptr) 2782 return (error); 2783 2784 if (disable) 2785 hlt_cpus_mask |= logical_cpus_mask; 2786 else 2787 hlt_cpus_mask &= ~logical_cpus_mask; 2788 2789 if ((hlt_cpus_mask & all_cpus) == all_cpus) 2790 hlt_cpus_mask &= ~(1<<0); 2791 2792 hlt_logical_cpus = disable; 2793 return (error); 2794} 2795 2796static void 2797cpu_hlt_setup(void *dummy __unused) 2798{ 2799 2800 if (logical_cpus_mask != 0) { 2801 TUNABLE_INT_FETCH("machdep.hlt_logical_cpus", 2802 &hlt_logical_cpus); 2803 sysctl_ctx_init(&logical_cpu_clist); 2804 SYSCTL_ADD_PROC(&logical_cpu_clist, 2805 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 2806 "hlt_logical_cpus", CTLTYPE_INT|CTLFLAG_RW, 0, 0, 2807 sysctl_hlt_logical_cpus, "IU", ""); 2808 SYSCTL_ADD_UINT(&logical_cpu_clist, 2809 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 2810 "logical_cpus_mask", CTLTYPE_INT|CTLFLAG_RD, 2811 &logical_cpus_mask, 0, ""); 2812 2813 if (hlt_logical_cpus) 2814 hlt_cpus_mask |= logical_cpus_mask; 2815 } 2816} 2817SYSINIT(cpu_hlt, SI_SUB_SMP, SI_ORDER_ANY, cpu_hlt_setup, NULL); 2818 2819int 2820mp_grab_cpu_hlt(void) 2821{ 2822 u_int mask = PCPU_GET(cpumask); 2823 int retval; 2824 2825 retval = mask & hlt_cpus_mask; 2826 while (mask & hlt_cpus_mask) 2827 __asm __volatile("sti; hlt" : : : "memory"); 2828 return (retval); 2829} 2830