identcpu.c revision 347947
1/*- 2 * Copyright (c) 1992 Terrence R. Lambert. 3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 4 * Copyright (c) 1997 KATO Takenori. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp 39 */ 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: stable/11/sys/x86/x86/identcpu.c 347947 2019-05-17 22:14:30Z kib $"); 43 44#include "opt_cpu.h" 45 46#include <sys/param.h> 47#include <sys/bus.h> 48#include <sys/cpu.h> 49#include <sys/eventhandler.h> 50#include <sys/limits.h> 51#include <sys/systm.h> 52#include <sys/kernel.h> 53#include <sys/sysctl.h> 54#include <sys/power.h> 55 56#include <machine/asmacros.h> 57#include <machine/clock.h> 58#include <machine/cputypes.h> 59#include <machine/frame.h> 60#include <machine/intr_machdep.h> 61#include <machine/md_var.h> 62#include <machine/segments.h> 63#include <machine/specialreg.h> 64 65#include <amd64/vmm/intel/vmx_controls.h> 66#include <x86/isa/icu.h> 67#include <x86/vmware.h> 68 69#ifdef __i386__ 70#define IDENTBLUE_CYRIX486 0 71#define IDENTBLUE_IBMCPU 1 72#define IDENTBLUE_CYRIXM2 2 73 74static void identifycyrix(void); 75static void print_transmeta_info(void); 76#endif 77static u_int find_cpu_vendor_id(void); 78static void print_AMD_info(void); 79static void print_INTEL_info(void); 80static void print_INTEL_TLB(u_int data); 81static void print_hypervisor_info(void); 82static void print_svm_info(void); 83static void print_via_padlock_info(void); 84static void print_vmx_info(void); 85 86#ifdef __i386__ 87int cpu; /* Are we 386, 386sx, 486, etc? */ 88int cpu_class; 89#endif 90u_int cpu_feature; /* Feature flags */ 91u_int cpu_feature2; /* Feature flags */ 92u_int amd_feature; /* AMD feature flags */ 93u_int amd_feature2; /* AMD feature flags */ 94u_int amd_pminfo; /* AMD advanced power management info */ 95u_int amd_extended_feature_extensions; 96u_int via_feature_rng; /* VIA RNG features */ 97u_int via_feature_xcrypt; /* VIA ACE features */ 98u_int cpu_high; /* Highest arg to CPUID */ 99u_int cpu_exthigh; /* Highest arg to extended CPUID */ 100u_int cpu_id; /* Stepping ID */ 101u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */ 102u_int cpu_procinfo2; /* Multicore info */ 103char cpu_vendor[20]; /* CPU Origin code */ 104u_int cpu_vendor_id; /* CPU vendor ID */ 105u_int cpu_fxsr; /* SSE enabled */ 106u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */ 107u_int cpu_clflush_line_size = 32; 108u_int cpu_stdext_feature; /* %ebx */ 109u_int cpu_stdext_feature2; /* %ecx */ 110u_int cpu_stdext_feature3; /* %edx */ 111uint64_t cpu_ia32_arch_caps; 112u_int cpu_max_ext_state_size; 113u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */ 114u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */ 115u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */ 116u_int cpu_maxphyaddr; /* Max phys addr width in bits */ 117char machine[] = MACHINE; 118 119SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD, 120 &via_feature_rng, 0, 121 "VIA RNG feature available in CPU"); 122SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD, 123 &via_feature_xcrypt, 0, 124 "VIA xcrypt feature available in CPU"); 125 126#ifdef __amd64__ 127#ifdef SCTL_MASK32 128extern int adaptive_machine_arch; 129#endif 130 131static int 132sysctl_hw_machine(SYSCTL_HANDLER_ARGS) 133{ 134#ifdef SCTL_MASK32 135 static const char machine32[] = "i386"; 136#endif 137 int error; 138 139#ifdef SCTL_MASK32 140 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch) 141 error = SYSCTL_OUT(req, machine32, sizeof(machine32)); 142 else 143#endif 144 error = SYSCTL_OUT(req, machine, sizeof(machine)); 145 return (error); 146 147} 148SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD | 149 CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class"); 150#else 151SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 152 machine, 0, "Machine class"); 153#endif 154 155static char cpu_model[128]; 156SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_MPSAFE, 157 cpu_model, 0, "Machine model"); 158 159static int hw_clockrate; 160SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 161 &hw_clockrate, 0, "CPU instruction clock rate"); 162 163u_int hv_high; 164char hv_vendor[16]; 165SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD | CTLFLAG_MPSAFE, hv_vendor, 166 0, "Hypervisor vendor"); 167 168static eventhandler_tag tsc_post_tag; 169 170static char cpu_brand[48]; 171 172#ifdef __i386__ 173#define MAX_BRAND_INDEX 8 174 175static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = { 176 NULL, /* No brand */ 177 "Intel Celeron", 178 "Intel Pentium III", 179 "Intel Pentium III Xeon", 180 NULL, 181 NULL, 182 NULL, 183 NULL, 184 "Intel Pentium 4" 185}; 186 187static struct { 188 char *cpu_name; 189 int cpu_class; 190} cpus[] = { 191 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */ 192 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */ 193 { "i386DX", CPUCLASS_386 }, /* CPU_386 */ 194 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */ 195 { "i486DX", CPUCLASS_486 }, /* CPU_486 */ 196 { "Pentium", CPUCLASS_586 }, /* CPU_586 */ 197 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */ 198 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */ 199 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */ 200 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */ 201 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */ 202 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */ 203 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */ 204 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */ 205 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */ 206 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */ 207 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */ 208}; 209#endif 210 211static struct { 212 char *vendor; 213 u_int vendor_id; 214} cpu_vendors[] = { 215 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */ 216 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */ 217 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */ 218#ifdef __i386__ 219 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */ 220 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */ 221 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */ 222 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */ 223 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */ 224 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */ 225 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */ 226#if 0 227 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */ 228 { "TransmetaCPU", CPU_VENDOR_TRANSMETA }, 229#endif 230#endif 231}; 232 233void 234printcpuinfo(void) 235{ 236 u_int regs[4], i; 237 char *brand; 238 239 printf("CPU: "); 240#ifdef __i386__ 241 cpu_class = cpus[cpu].cpu_class; 242 strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model)); 243#else 244 strncpy(cpu_model, "Hammer", sizeof (cpu_model)); 245#endif 246 247 /* Check for extended CPUID information and a processor name. */ 248 if (cpu_exthigh >= 0x80000004) { 249 brand = cpu_brand; 250 for (i = 0x80000002; i < 0x80000005; i++) { 251 do_cpuid(i, regs); 252 memcpy(brand, regs, sizeof(regs)); 253 brand += sizeof(regs); 254 } 255 } 256 257 switch (cpu_vendor_id) { 258 case CPU_VENDOR_INTEL: 259#ifdef __i386__ 260 if ((cpu_id & 0xf00) > 0x300) { 261 u_int brand_index; 262 263 cpu_model[0] = '\0'; 264 265 switch (cpu_id & 0x3000) { 266 case 0x1000: 267 strcpy(cpu_model, "Overdrive "); 268 break; 269 case 0x2000: 270 strcpy(cpu_model, "Dual "); 271 break; 272 } 273 274 switch (cpu_id & 0xf00) { 275 case 0x400: 276 strcat(cpu_model, "i486 "); 277 /* Check the particular flavor of 486 */ 278 switch (cpu_id & 0xf0) { 279 case 0x00: 280 case 0x10: 281 strcat(cpu_model, "DX"); 282 break; 283 case 0x20: 284 strcat(cpu_model, "SX"); 285 break; 286 case 0x30: 287 strcat(cpu_model, "DX2"); 288 break; 289 case 0x40: 290 strcat(cpu_model, "SL"); 291 break; 292 case 0x50: 293 strcat(cpu_model, "SX2"); 294 break; 295 case 0x70: 296 strcat(cpu_model, 297 "DX2 Write-Back Enhanced"); 298 break; 299 case 0x80: 300 strcat(cpu_model, "DX4"); 301 break; 302 } 303 break; 304 case 0x500: 305 /* Check the particular flavor of 586 */ 306 strcat(cpu_model, "Pentium"); 307 switch (cpu_id & 0xf0) { 308 case 0x00: 309 strcat(cpu_model, " A-step"); 310 break; 311 case 0x10: 312 strcat(cpu_model, "/P5"); 313 break; 314 case 0x20: 315 strcat(cpu_model, "/P54C"); 316 break; 317 case 0x30: 318 strcat(cpu_model, "/P24T"); 319 break; 320 case 0x40: 321 strcat(cpu_model, "/P55C"); 322 break; 323 case 0x70: 324 strcat(cpu_model, "/P54C"); 325 break; 326 case 0x80: 327 strcat(cpu_model, "/P55C (quarter-micron)"); 328 break; 329 default: 330 /* nothing */ 331 break; 332 } 333#if defined(I586_CPU) && !defined(NO_F00F_HACK) 334 /* 335 * XXX - If/when Intel fixes the bug, this 336 * should also check the version of the 337 * CPU, not just that it's a Pentium. 338 */ 339 has_f00f_bug = 1; 340#endif 341 break; 342 case 0x600: 343 /* Check the particular flavor of 686 */ 344 switch (cpu_id & 0xf0) { 345 case 0x00: 346 strcat(cpu_model, "Pentium Pro A-step"); 347 break; 348 case 0x10: 349 strcat(cpu_model, "Pentium Pro"); 350 break; 351 case 0x30: 352 case 0x50: 353 case 0x60: 354 strcat(cpu_model, 355 "Pentium II/Pentium II Xeon/Celeron"); 356 cpu = CPU_PII; 357 break; 358 case 0x70: 359 case 0x80: 360 case 0xa0: 361 case 0xb0: 362 strcat(cpu_model, 363 "Pentium III/Pentium III Xeon/Celeron"); 364 cpu = CPU_PIII; 365 break; 366 default: 367 strcat(cpu_model, "Unknown 80686"); 368 break; 369 } 370 break; 371 case 0xf00: 372 strcat(cpu_model, "Pentium 4"); 373 cpu = CPU_P4; 374 break; 375 default: 376 strcat(cpu_model, "unknown"); 377 break; 378 } 379 380 /* 381 * If we didn't get a brand name from the extended 382 * CPUID, try to look it up in the brand table. 383 */ 384 if (cpu_high > 0 && *cpu_brand == '\0') { 385 brand_index = cpu_procinfo & CPUID_BRAND_INDEX; 386 if (brand_index <= MAX_BRAND_INDEX && 387 cpu_brandtable[brand_index] != NULL) 388 strcpy(cpu_brand, 389 cpu_brandtable[brand_index]); 390 } 391 } 392#else 393 /* Please make up your mind folks! */ 394 strcat(cpu_model, "EM64T"); 395#endif 396 break; 397 case CPU_VENDOR_AMD: 398 /* 399 * Values taken from AMD Processor Recognition 400 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf 401 * (also describes ``Features'' encodings. 402 */ 403 strcpy(cpu_model, "AMD "); 404#ifdef __i386__ 405 switch (cpu_id & 0xFF0) { 406 case 0x410: 407 strcat(cpu_model, "Standard Am486DX"); 408 break; 409 case 0x430: 410 strcat(cpu_model, "Enhanced Am486DX2 Write-Through"); 411 break; 412 case 0x470: 413 strcat(cpu_model, "Enhanced Am486DX2 Write-Back"); 414 break; 415 case 0x480: 416 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through"); 417 break; 418 case 0x490: 419 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back"); 420 break; 421 case 0x4E0: 422 strcat(cpu_model, "Am5x86 Write-Through"); 423 break; 424 case 0x4F0: 425 strcat(cpu_model, "Am5x86 Write-Back"); 426 break; 427 case 0x500: 428 strcat(cpu_model, "K5 model 0"); 429 break; 430 case 0x510: 431 strcat(cpu_model, "K5 model 1"); 432 break; 433 case 0x520: 434 strcat(cpu_model, "K5 PR166 (model 2)"); 435 break; 436 case 0x530: 437 strcat(cpu_model, "K5 PR200 (model 3)"); 438 break; 439 case 0x560: 440 strcat(cpu_model, "K6"); 441 break; 442 case 0x570: 443 strcat(cpu_model, "K6 266 (model 1)"); 444 break; 445 case 0x580: 446 strcat(cpu_model, "K6-2"); 447 break; 448 case 0x590: 449 strcat(cpu_model, "K6-III"); 450 break; 451 case 0x5a0: 452 strcat(cpu_model, "Geode LX"); 453 break; 454 default: 455 strcat(cpu_model, "Unknown"); 456 break; 457 } 458#else 459 if ((cpu_id & 0xf00) == 0xf00) 460 strcat(cpu_model, "AMD64 Processor"); 461 else 462 strcat(cpu_model, "Unknown"); 463#endif 464 break; 465#ifdef __i386__ 466 case CPU_VENDOR_CYRIX: 467 strcpy(cpu_model, "Cyrix "); 468 switch (cpu_id & 0xff0) { 469 case 0x440: 470 strcat(cpu_model, "MediaGX"); 471 break; 472 case 0x520: 473 strcat(cpu_model, "6x86"); 474 break; 475 case 0x540: 476 cpu_class = CPUCLASS_586; 477 strcat(cpu_model, "GXm"); 478 break; 479 case 0x600: 480 strcat(cpu_model, "6x86MX"); 481 break; 482 default: 483 /* 484 * Even though CPU supports the cpuid 485 * instruction, it can be disabled. 486 * Therefore, this routine supports all Cyrix 487 * CPUs. 488 */ 489 switch (cyrix_did & 0xf0) { 490 case 0x00: 491 switch (cyrix_did & 0x0f) { 492 case 0x00: 493 strcat(cpu_model, "486SLC"); 494 break; 495 case 0x01: 496 strcat(cpu_model, "486DLC"); 497 break; 498 case 0x02: 499 strcat(cpu_model, "486SLC2"); 500 break; 501 case 0x03: 502 strcat(cpu_model, "486DLC2"); 503 break; 504 case 0x04: 505 strcat(cpu_model, "486SRx"); 506 break; 507 case 0x05: 508 strcat(cpu_model, "486DRx"); 509 break; 510 case 0x06: 511 strcat(cpu_model, "486SRx2"); 512 break; 513 case 0x07: 514 strcat(cpu_model, "486DRx2"); 515 break; 516 case 0x08: 517 strcat(cpu_model, "486SRu"); 518 break; 519 case 0x09: 520 strcat(cpu_model, "486DRu"); 521 break; 522 case 0x0a: 523 strcat(cpu_model, "486SRu2"); 524 break; 525 case 0x0b: 526 strcat(cpu_model, "486DRu2"); 527 break; 528 default: 529 strcat(cpu_model, "Unknown"); 530 break; 531 } 532 break; 533 case 0x10: 534 switch (cyrix_did & 0x0f) { 535 case 0x00: 536 strcat(cpu_model, "486S"); 537 break; 538 case 0x01: 539 strcat(cpu_model, "486S2"); 540 break; 541 case 0x02: 542 strcat(cpu_model, "486Se"); 543 break; 544 case 0x03: 545 strcat(cpu_model, "486S2e"); 546 break; 547 case 0x0a: 548 strcat(cpu_model, "486DX"); 549 break; 550 case 0x0b: 551 strcat(cpu_model, "486DX2"); 552 break; 553 case 0x0f: 554 strcat(cpu_model, "486DX4"); 555 break; 556 default: 557 strcat(cpu_model, "Unknown"); 558 break; 559 } 560 break; 561 case 0x20: 562 if ((cyrix_did & 0x0f) < 8) 563 strcat(cpu_model, "6x86"); /* Where did you get it? */ 564 else 565 strcat(cpu_model, "5x86"); 566 break; 567 case 0x30: 568 strcat(cpu_model, "6x86"); 569 break; 570 case 0x40: 571 if ((cyrix_did & 0xf000) == 0x3000) { 572 cpu_class = CPUCLASS_586; 573 strcat(cpu_model, "GXm"); 574 } else 575 strcat(cpu_model, "MediaGX"); 576 break; 577 case 0x50: 578 strcat(cpu_model, "6x86MX"); 579 break; 580 case 0xf0: 581 switch (cyrix_did & 0x0f) { 582 case 0x0d: 583 strcat(cpu_model, "Overdrive CPU"); 584 break; 585 case 0x0e: 586 strcpy(cpu_model, "Texas Instruments 486SXL"); 587 break; 588 case 0x0f: 589 strcat(cpu_model, "486SLC/DLC"); 590 break; 591 default: 592 strcat(cpu_model, "Unknown"); 593 break; 594 } 595 break; 596 default: 597 strcat(cpu_model, "Unknown"); 598 break; 599 } 600 break; 601 } 602 break; 603 case CPU_VENDOR_RISE: 604 strcpy(cpu_model, "Rise "); 605 switch (cpu_id & 0xff0) { 606 case 0x500: /* 6401 and 6441 (Kirin) */ 607 case 0x520: /* 6510 (Lynx) */ 608 strcat(cpu_model, "mP6"); 609 break; 610 default: 611 strcat(cpu_model, "Unknown"); 612 } 613 break; 614#endif 615 case CPU_VENDOR_CENTAUR: 616#ifdef __i386__ 617 switch (cpu_id & 0xff0) { 618 case 0x540: 619 strcpy(cpu_model, "IDT WinChip C6"); 620 break; 621 case 0x580: 622 strcpy(cpu_model, "IDT WinChip 2"); 623 break; 624 case 0x590: 625 strcpy(cpu_model, "IDT WinChip 3"); 626 break; 627 case 0x660: 628 strcpy(cpu_model, "VIA C3 Samuel"); 629 break; 630 case 0x670: 631 if (cpu_id & 0x8) 632 strcpy(cpu_model, "VIA C3 Ezra"); 633 else 634 strcpy(cpu_model, "VIA C3 Samuel 2"); 635 break; 636 case 0x680: 637 strcpy(cpu_model, "VIA C3 Ezra-T"); 638 break; 639 case 0x690: 640 strcpy(cpu_model, "VIA C3 Nehemiah"); 641 break; 642 case 0x6a0: 643 case 0x6d0: 644 strcpy(cpu_model, "VIA C7 Esther"); 645 break; 646 case 0x6f0: 647 strcpy(cpu_model, "VIA Nano"); 648 break; 649 default: 650 strcpy(cpu_model, "VIA/IDT Unknown"); 651 } 652#else 653 strcpy(cpu_model, "VIA "); 654 if ((cpu_id & 0xff0) == 0x6f0) 655 strcat(cpu_model, "Nano Processor"); 656 else 657 strcat(cpu_model, "Unknown"); 658#endif 659 break; 660#ifdef __i386__ 661 case CPU_VENDOR_IBM: 662 strcpy(cpu_model, "Blue Lightning CPU"); 663 break; 664 case CPU_VENDOR_NSC: 665 switch (cpu_id & 0xff0) { 666 case 0x540: 667 strcpy(cpu_model, "Geode SC1100"); 668 cpu = CPU_GEODE1100; 669 break; 670 default: 671 strcpy(cpu_model, "Geode/NSC unknown"); 672 break; 673 } 674 break; 675#endif 676 default: 677 strcat(cpu_model, "Unknown"); 678 break; 679 } 680 681 /* 682 * Replace cpu_model with cpu_brand minus leading spaces if 683 * we have one. 684 */ 685 brand = cpu_brand; 686 while (*brand == ' ') 687 ++brand; 688 if (*brand != '\0') 689 strcpy(cpu_model, brand); 690 691 printf("%s (", cpu_model); 692 if (tsc_freq != 0) { 693 hw_clockrate = (tsc_freq + 5000) / 1000000; 694 printf("%jd.%02d-MHz ", 695 (intmax_t)(tsc_freq + 4999) / 1000000, 696 (u_int)((tsc_freq + 4999) / 10000) % 100); 697 } 698#ifdef __i386__ 699 switch(cpu_class) { 700 case CPUCLASS_286: 701 printf("286"); 702 break; 703 case CPUCLASS_386: 704 printf("386"); 705 break; 706#if defined(I486_CPU) 707 case CPUCLASS_486: 708 printf("486"); 709 break; 710#endif 711#if defined(I586_CPU) 712 case CPUCLASS_586: 713 printf("586"); 714 break; 715#endif 716#if defined(I686_CPU) 717 case CPUCLASS_686: 718 printf("686"); 719 break; 720#endif 721 default: 722 printf("Unknown"); /* will panic below... */ 723 } 724#else 725 printf("K8"); 726#endif 727 printf("-class CPU)\n"); 728 if (*cpu_vendor) 729 printf(" Origin=\"%s\"", cpu_vendor); 730 if (cpu_id) 731 printf(" Id=0x%x", cpu_id); 732 733 if (cpu_vendor_id == CPU_VENDOR_INTEL || 734 cpu_vendor_id == CPU_VENDOR_AMD || 735 cpu_vendor_id == CPU_VENDOR_CENTAUR || 736#ifdef __i386__ 737 cpu_vendor_id == CPU_VENDOR_TRANSMETA || 738 cpu_vendor_id == CPU_VENDOR_RISE || 739 cpu_vendor_id == CPU_VENDOR_NSC || 740 (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) || 741#endif 742 0) { 743 printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id)); 744 printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id)); 745 printf(" Stepping=%u", cpu_id & CPUID_STEPPING); 746#ifdef __i386__ 747 if (cpu_vendor_id == CPU_VENDOR_CYRIX) 748 printf("\n DIR=0x%04x", cyrix_did); 749#endif 750 751 /* 752 * AMD CPUID Specification 753 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf 754 * 755 * Intel Processor Identification and CPUID Instruction 756 * http://www.intel.com/assets/pdf/appnote/241618.pdf 757 */ 758 if (cpu_high > 0) { 759 760 /* 761 * Here we should probably set up flags indicating 762 * whether or not various features are available. 763 * The interesting ones are probably VME, PSE, PAE, 764 * and PGE. The code already assumes without bothering 765 * to check that all CPUs >= Pentium have a TSC and 766 * MSRs. 767 */ 768 printf("\n Features=0x%b", cpu_feature, 769 "\020" 770 "\001FPU" /* Integral FPU */ 771 "\002VME" /* Extended VM86 mode support */ 772 "\003DE" /* Debugging Extensions (CR4.DE) */ 773 "\004PSE" /* 4MByte page tables */ 774 "\005TSC" /* Timestamp counter */ 775 "\006MSR" /* Machine specific registers */ 776 "\007PAE" /* Physical address extension */ 777 "\010MCE" /* Machine Check support */ 778 "\011CX8" /* CMPEXCH8 instruction */ 779 "\012APIC" /* SMP local APIC */ 780 "\013oldMTRR" /* Previous implementation of MTRR */ 781 "\014SEP" /* Fast System Call */ 782 "\015MTRR" /* Memory Type Range Registers */ 783 "\016PGE" /* PG_G (global bit) support */ 784 "\017MCA" /* Machine Check Architecture */ 785 "\020CMOV" /* CMOV instruction */ 786 "\021PAT" /* Page attributes table */ 787 "\022PSE36" /* 36 bit address space support */ 788 "\023PN" /* Processor Serial number */ 789 "\024CLFLUSH" /* Has the CLFLUSH instruction */ 790 "\025<b20>" 791 "\026DTS" /* Debug Trace Store */ 792 "\027ACPI" /* ACPI support */ 793 "\030MMX" /* MMX instructions */ 794 "\031FXSR" /* FXSAVE/FXRSTOR */ 795 "\032SSE" /* Streaming SIMD Extensions */ 796 "\033SSE2" /* Streaming SIMD Extensions #2 */ 797 "\034SS" /* Self snoop */ 798 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */ 799 "\036TM" /* Thermal Monitor clock slowdown */ 800 "\037IA64" /* CPU can execute IA64 instructions */ 801 "\040PBE" /* Pending Break Enable */ 802 ); 803 804 if (cpu_feature2 != 0) { 805 printf("\n Features2=0x%b", cpu_feature2, 806 "\020" 807 "\001SSE3" /* SSE3 */ 808 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */ 809 "\003DTES64" /* 64-bit Debug Trace */ 810 "\004MON" /* MONITOR/MWAIT Instructions */ 811 "\005DS_CPL" /* CPL Qualified Debug Store */ 812 "\006VMX" /* Virtual Machine Extensions */ 813 "\007SMX" /* Safer Mode Extensions */ 814 "\010EST" /* Enhanced SpeedStep */ 815 "\011TM2" /* Thermal Monitor 2 */ 816 "\012SSSE3" /* SSSE3 */ 817 "\013CNXT-ID" /* L1 context ID available */ 818 "\014SDBG" /* IA32 silicon debug */ 819 "\015FMA" /* Fused Multiply Add */ 820 "\016CX16" /* CMPXCHG16B Instruction */ 821 "\017xTPR" /* Send Task Priority Messages*/ 822 "\020PDCM" /* Perf/Debug Capability MSR */ 823 "\021<b16>" 824 "\022PCID" /* Process-context Identifiers*/ 825 "\023DCA" /* Direct Cache Access */ 826 "\024SSE4.1" /* SSE 4.1 */ 827 "\025SSE4.2" /* SSE 4.2 */ 828 "\026x2APIC" /* xAPIC Extensions */ 829 "\027MOVBE" /* MOVBE Instruction */ 830 "\030POPCNT" /* POPCNT Instruction */ 831 "\031TSCDLT" /* TSC-Deadline Timer */ 832 "\032AESNI" /* AES Crypto */ 833 "\033XSAVE" /* XSAVE/XRSTOR States */ 834 "\034OSXSAVE" /* OS-Enabled State Management*/ 835 "\035AVX" /* Advanced Vector Extensions */ 836 "\036F16C" /* Half-precision conversions */ 837 "\037RDRAND" /* RDRAND Instruction */ 838 "\040HV" /* Hypervisor */ 839 ); 840 } 841 842 if (amd_feature != 0) { 843 printf("\n AMD Features=0x%b", amd_feature, 844 "\020" /* in hex */ 845 "\001<s0>" /* Same */ 846 "\002<s1>" /* Same */ 847 "\003<s2>" /* Same */ 848 "\004<s3>" /* Same */ 849 "\005<s4>" /* Same */ 850 "\006<s5>" /* Same */ 851 "\007<s6>" /* Same */ 852 "\010<s7>" /* Same */ 853 "\011<s8>" /* Same */ 854 "\012<s9>" /* Same */ 855 "\013<b10>" /* Undefined */ 856 "\014SYSCALL" /* Have SYSCALL/SYSRET */ 857 "\015<s12>" /* Same */ 858 "\016<s13>" /* Same */ 859 "\017<s14>" /* Same */ 860 "\020<s15>" /* Same */ 861 "\021<s16>" /* Same */ 862 "\022<s17>" /* Same */ 863 "\023<b18>" /* Reserved, unknown */ 864 "\024MP" /* Multiprocessor Capable */ 865 "\025NX" /* Has EFER.NXE, NX */ 866 "\026<b21>" /* Undefined */ 867 "\027MMX+" /* AMD MMX Extensions */ 868 "\030<s23>" /* Same */ 869 "\031<s24>" /* Same */ 870 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */ 871 "\033Page1GB" /* 1-GB large page support */ 872 "\034RDTSCP" /* RDTSCP */ 873 "\035<b28>" /* Undefined */ 874 "\036LM" /* 64 bit long mode */ 875 "\0373DNow!+" /* AMD 3DNow! Extensions */ 876 "\0403DNow!" /* AMD 3DNow! */ 877 ); 878 } 879 880 if (amd_feature2 != 0) { 881 printf("\n AMD Features2=0x%b", amd_feature2, 882 "\020" 883 "\001LAHF" /* LAHF/SAHF in long mode */ 884 "\002CMP" /* CMP legacy */ 885 "\003SVM" /* Secure Virtual Mode */ 886 "\004ExtAPIC" /* Extended APIC register */ 887 "\005CR8" /* CR8 in legacy mode */ 888 "\006ABM" /* LZCNT instruction */ 889 "\007SSE4A" /* SSE4A */ 890 "\010MAS" /* Misaligned SSE mode */ 891 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ 892 "\012OSVW" /* OS visible workaround */ 893 "\013IBS" /* Instruction based sampling */ 894 "\014XOP" /* XOP extended instructions */ 895 "\015SKINIT" /* SKINIT/STGI */ 896 "\016WDT" /* Watchdog timer */ 897 "\017<b14>" 898 "\020LWP" /* Lightweight Profiling */ 899 "\021FMA4" /* 4-operand FMA instructions */ 900 "\022TCE" /* Translation Cache Extension */ 901 "\023<b18>" 902 "\024NodeId" /* NodeId MSR support */ 903 "\025<b20>" 904 "\026TBM" /* Trailing Bit Manipulation */ 905 "\027Topology" /* Topology Extensions */ 906 "\030PCXC" /* Core perf count */ 907 "\031PNXC" /* NB perf count */ 908 "\032<b25>" 909 "\033DBE" /* Data Breakpoint extension */ 910 "\034PTSC" /* Performance TSC */ 911 "\035PL2I" /* L2I perf count */ 912 "\036MWAITX" /* MONITORX/MWAITX instructions */ 913 "\037<b30>" 914 "\040<b31>" 915 ); 916 } 917 918 if (cpu_stdext_feature != 0) { 919 printf("\n Structured Extended Features=0x%b", 920 cpu_stdext_feature, 921 "\020" 922 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ 923 "\001FSGSBASE" 924 "\002TSCADJ" 925 "\003SGX" 926 /* Bit Manipulation Instructions */ 927 "\004BMI1" 928 /* Hardware Lock Elision */ 929 "\005HLE" 930 /* Advanced Vector Instructions 2 */ 931 "\006AVX2" 932 /* FDP_EXCPTN_ONLY */ 933 "\007FDPEXC" 934 /* Supervisor Mode Execution Prot. */ 935 "\010SMEP" 936 /* Bit Manipulation Instructions */ 937 "\011BMI2" 938 "\012ERMS" 939 /* Invalidate Processor Context ID */ 940 "\013INVPCID" 941 /* Restricted Transactional Memory */ 942 "\014RTM" 943 "\015PQM" 944 "\016NFPUSG" 945 /* Intel Memory Protection Extensions */ 946 "\017MPX" 947 "\020PQE" 948 /* AVX512 Foundation */ 949 "\021AVX512F" 950 "\022AVX512DQ" 951 /* Enhanced NRBG */ 952 "\023RDSEED" 953 /* ADCX + ADOX */ 954 "\024ADX" 955 /* Supervisor Mode Access Prevention */ 956 "\025SMAP" 957 "\026AVX512IFMA" 958 "\027PCOMMIT" 959 "\030CLFLUSHOPT" 960 "\031CLWB" 961 "\032PROCTRACE" 962 "\033AVX512PF" 963 "\034AVX512ER" 964 "\035AVX512CD" 965 "\036SHA" 966 "\037AVX512BW" 967 "\040AVX512VL" 968 ); 969 } 970 971 if (cpu_stdext_feature2 != 0) { 972 printf("\n Structured Extended Features2=0x%b", 973 cpu_stdext_feature2, 974 "\020" 975 "\001PREFETCHWT1" 976 "\002AVX512VBMI" 977 "\003UMIP" 978 "\004PKU" 979 "\005OSPKE" 980 "\006WAITPKG" 981 "\011GFNI" 982 "\027RDPID" 983 "\032CLDEMOTE" 984 "\034MOVDIRI" 985 "\035MOVDIRI64B" 986 "\037SGXLC" 987 ); 988 } 989 990 if (cpu_stdext_feature3 != 0) { 991 printf("\n Structured Extended Features3=0x%b", 992 cpu_stdext_feature3, 993 "\020" 994 "\013MD_CLEAR" 995 "\016TSXFA" 996 "\033IBPB" 997 "\034STIBP" 998 "\035L1DFL" 999 "\036ARCH_CAP" 1000 "\037CORE_CAP" 1001 "\040SSBD" 1002 ); 1003 } 1004 1005 if ((cpu_feature2 & CPUID2_XSAVE) != 0) { 1006 cpuid_count(0xd, 0x1, regs); 1007 if (regs[0] != 0) { 1008 printf("\n XSAVE Features=0x%b", 1009 regs[0], 1010 "\020" 1011 "\001XSAVEOPT" 1012 "\002XSAVEC" 1013 "\003XINUSE" 1014 "\004XSAVES"); 1015 } 1016 } 1017 1018 if (cpu_ia32_arch_caps != 0) { 1019 printf("\n IA32_ARCH_CAPS=0x%b", 1020 (u_int)cpu_ia32_arch_caps, 1021 "\020" 1022 "\001RDCL_NO" 1023 "\002IBRS_ALL" 1024 "\003RSBA" 1025 "\004SKIP_L1DFL_VME" 1026 "\005SSB_NO" 1027 ); 1028 } 1029 1030 if (amd_extended_feature_extensions != 0) { 1031 printf("\n " 1032 "AMD Extended Feature Extensions ID EBX=" 1033 "0x%b", amd_extended_feature_extensions, 1034 "\020" 1035 "\001CLZERO" 1036 "\002IRPerf" 1037 "\003XSaveErPtr"); 1038 } 1039 1040 if (via_feature_rng != 0 || via_feature_xcrypt != 0) 1041 print_via_padlock_info(); 1042 1043 if (cpu_feature2 & CPUID2_VMX) 1044 print_vmx_info(); 1045 1046 if (amd_feature2 & AMDID2_SVM) 1047 print_svm_info(); 1048 1049 if ((cpu_feature & CPUID_HTT) && 1050 cpu_vendor_id == CPU_VENDOR_AMD) 1051 cpu_feature &= ~CPUID_HTT; 1052 1053 /* 1054 * If this CPU supports P-state invariant TSC then 1055 * mention the capability. 1056 */ 1057 if (tsc_is_invariant) { 1058 printf("\n TSC: P-state invariant"); 1059 if (tsc_perf_stat) 1060 printf(", performance statistics"); 1061 } 1062 } 1063#ifdef __i386__ 1064 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 1065 printf(" DIR=0x%04x", cyrix_did); 1066 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12); 1067 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8); 1068#ifndef CYRIX_CACHE_REALLY_WORKS 1069 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700) 1070 printf("\n CPU cache: write-through mode"); 1071#endif 1072#endif 1073 } 1074 1075 /* Avoid ugly blank lines: only print newline when we have to. */ 1076 if (*cpu_vendor || cpu_id) 1077 printf("\n"); 1078 1079 if (bootverbose) { 1080 if (cpu_vendor_id == CPU_VENDOR_AMD) 1081 print_AMD_info(); 1082 else if (cpu_vendor_id == CPU_VENDOR_INTEL) 1083 print_INTEL_info(); 1084#ifdef __i386__ 1085 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA) 1086 print_transmeta_info(); 1087#endif 1088 } 1089 1090 print_hypervisor_info(); 1091} 1092 1093#ifdef __i386__ 1094void 1095panicifcpuunsupported(void) 1096{ 1097 1098#if !defined(lint) 1099#if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU) 1100#error This kernel is not configured for one of the supported CPUs 1101#endif 1102#else /* lint */ 1103#endif /* lint */ 1104 /* 1105 * Now that we have told the user what they have, 1106 * let them know if that machine type isn't configured. 1107 */ 1108 switch (cpu_class) { 1109 case CPUCLASS_286: /* a 286 should not make it this far, anyway */ 1110 case CPUCLASS_386: 1111#if !defined(I486_CPU) 1112 case CPUCLASS_486: 1113#endif 1114#if !defined(I586_CPU) 1115 case CPUCLASS_586: 1116#endif 1117#if !defined(I686_CPU) 1118 case CPUCLASS_686: 1119#endif 1120 panic("CPU class not configured"); 1121 default: 1122 break; 1123 } 1124} 1125 1126static volatile u_int trap_by_rdmsr; 1127 1128/* 1129 * Special exception 6 handler. 1130 * The rdmsr instruction generates invalid opcodes fault on 486-class 1131 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the 1132 * function identblue() when this handler is called. Stacked eip should 1133 * be advanced. 1134 */ 1135inthand_t bluetrap6; 1136#ifdef __GNUCLIKE_ASM 1137__asm 1138(" \n\ 1139 .text \n\ 1140 .p2align 2,0x90 \n\ 1141 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\ 1142" __XSTRING(CNAME(bluetrap6)) ": \n\ 1143 ss \n\ 1144 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 1145 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 1146 iret \n\ 1147"); 1148#endif 1149 1150/* 1151 * Special exception 13 handler. 1152 * Accessing non-existent MSR generates general protection fault. 1153 */ 1154inthand_t bluetrap13; 1155#ifdef __GNUCLIKE_ASM 1156__asm 1157(" \n\ 1158 .text \n\ 1159 .p2align 2,0x90 \n\ 1160 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\ 1161" __XSTRING(CNAME(bluetrap13)) ": \n\ 1162 ss \n\ 1163 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 1164 popl %eax /* discard error code */ \n\ 1165 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 1166 iret \n\ 1167"); 1168#endif 1169 1170/* 1171 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not 1172 * support cpuid instruction. This function should be called after 1173 * loading interrupt descriptor table register. 1174 * 1175 * I don't like this method that handles fault, but I couldn't get 1176 * information for any other methods. Does blue giant know? 1177 */ 1178static int 1179identblue(void) 1180{ 1181 1182 trap_by_rdmsr = 0; 1183 1184 /* 1185 * Cyrix 486-class CPU does not support rdmsr instruction. 1186 * The rdmsr instruction generates invalid opcode fault, and exception 1187 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The 1188 * bluetrap6() set the magic number to trap_by_rdmsr. 1189 */ 1190 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL, 1191 GSEL(GCODE_SEL, SEL_KPL)); 1192 1193 /* 1194 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU. 1195 * In this case, rdmsr generates general protection fault, and 1196 * exception will be trapped by bluetrap13(). 1197 */ 1198 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL, 1199 GSEL(GCODE_SEL, SEL_KPL)); 1200 1201 rdmsr(0x1002); /* Cyrix CPU generates fault. */ 1202 1203 if (trap_by_rdmsr == 0xa8c1d) 1204 return IDENTBLUE_CYRIX486; 1205 else if (trap_by_rdmsr == 0xa89c4) 1206 return IDENTBLUE_CYRIXM2; 1207 return IDENTBLUE_IBMCPU; 1208} 1209 1210 1211/* 1212 * identifycyrix() set lower 16 bits of cyrix_did as follows: 1213 * 1214 * F E D C B A 9 8 7 6 5 4 3 2 1 0 1215 * +-------+-------+---------------+ 1216 * | SID | RID | Device ID | 1217 * | (DIR 1) | (DIR 0) | 1218 * +-------+-------+---------------+ 1219 */ 1220static void 1221identifycyrix(void) 1222{ 1223 register_t saveintr; 1224 int ccr2_test = 0, dir_test = 0; 1225 u_char ccr2, ccr3; 1226 1227 saveintr = intr_disable(); 1228 1229 ccr2 = read_cyrix_reg(CCR2); 1230 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW); 1231 read_cyrix_reg(CCR2); 1232 if (read_cyrix_reg(CCR2) != ccr2) 1233 ccr2_test = 1; 1234 write_cyrix_reg(CCR2, ccr2); 1235 1236 ccr3 = read_cyrix_reg(CCR3); 1237 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3); 1238 read_cyrix_reg(CCR3); 1239 if (read_cyrix_reg(CCR3) != ccr3) 1240 dir_test = 1; /* CPU supports DIRs. */ 1241 write_cyrix_reg(CCR3, ccr3); 1242 1243 if (dir_test) { 1244 /* Device ID registers are available. */ 1245 cyrix_did = read_cyrix_reg(DIR1) << 8; 1246 cyrix_did += read_cyrix_reg(DIR0); 1247 } else if (ccr2_test) 1248 cyrix_did = 0x0010; /* 486S A-step */ 1249 else 1250 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */ 1251 1252 intr_restore(saveintr); 1253} 1254#endif 1255 1256/* Update TSC freq with the value indicated by the caller. */ 1257static void 1258tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status) 1259{ 1260 1261 /* If there was an error during the transition, don't do anything. */ 1262 if (status != 0) 1263 return; 1264 1265 /* Total setting for this level gives the new frequency in MHz. */ 1266 hw_clockrate = level->total_set.freq; 1267} 1268 1269static void 1270hook_tsc_freq(void *arg __unused) 1271{ 1272 1273 if (tsc_is_invariant) 1274 return; 1275 1276 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change, 1277 tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY); 1278} 1279 1280SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL); 1281 1282static const char *const vm_bnames[] = { 1283 "QEMU", /* QEMU */ 1284 "Plex86", /* Plex86 */ 1285 "Bochs", /* Bochs */ 1286 "Xen", /* Xen */ 1287 "BHYVE", /* bhyve */ 1288 "Seabios", /* KVM */ 1289 NULL 1290}; 1291 1292static const char *const vm_pnames[] = { 1293 "VMware Virtual Platform", /* VMWare VM */ 1294 "Virtual Machine", /* Microsoft VirtualPC */ 1295 "VirtualBox", /* Sun xVM VirtualBox */ 1296 "Parallels Virtual Platform", /* Parallels VM */ 1297 "KVM", /* KVM */ 1298 NULL 1299}; 1300 1301void 1302identify_hypervisor(void) 1303{ 1304 u_int regs[4]; 1305 char *p; 1306 int i; 1307 1308 /* 1309 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1310 * http://lkml.org/lkml/2008/10/1/246 1311 * 1312 * KB1009458: Mechanisms to determine if software is running in 1313 * a VMware virtual machine 1314 * http://kb.vmware.com/kb/1009458 1315 */ 1316 if (cpu_feature2 & CPUID2_HV) { 1317 vm_guest = VM_GUEST_VM; 1318 do_cpuid(0x40000000, regs); 1319 1320 /* 1321 * KVM from Linux kernels prior to commit 1322 * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax 1323 * to 0 rather than a valid hv_high value. Check for 1324 * the KVM signature bytes and fixup %eax to the 1325 * highest supported leaf in that case. 1326 */ 1327 if (regs[0] == 0 && regs[1] == 0x4b4d564b && 1328 regs[2] == 0x564b4d56 && regs[3] == 0x0000004d) 1329 regs[0] = 0x40000001; 1330 1331 if (regs[0] >= 0x40000000) { 1332 hv_high = regs[0]; 1333 ((u_int *)&hv_vendor)[0] = regs[1]; 1334 ((u_int *)&hv_vendor)[1] = regs[2]; 1335 ((u_int *)&hv_vendor)[2] = regs[3]; 1336 hv_vendor[12] = '\0'; 1337 if (strcmp(hv_vendor, "VMwareVMware") == 0) 1338 vm_guest = VM_GUEST_VMWARE; 1339 else if (strcmp(hv_vendor, "Microsoft Hv") == 0) 1340 vm_guest = VM_GUEST_HV; 1341 else if (strcmp(hv_vendor, "KVMKVMKVM") == 0) 1342 vm_guest = VM_GUEST_KVM; 1343 else if (strcmp(hv_vendor, "bhyve bhyve") == 0) 1344 vm_guest = VM_GUEST_BHYVE; 1345 } 1346 return; 1347 } 1348 1349 /* 1350 * Examine SMBIOS strings for older hypervisors. 1351 */ 1352 p = kern_getenv("smbios.system.serial"); 1353 if (p != NULL) { 1354 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) { 1355 vmware_hvcall(VMW_HVCMD_GETVERSION, regs); 1356 if (regs[1] == VMW_HVMAGIC) { 1357 vm_guest = VM_GUEST_VMWARE; 1358 freeenv(p); 1359 return; 1360 } 1361 } 1362 freeenv(p); 1363 } 1364 1365 /* 1366 * XXX: Some of these entries may not be needed since they were 1367 * added to FreeBSD before the checks above. 1368 */ 1369 p = kern_getenv("smbios.bios.vendor"); 1370 if (p != NULL) { 1371 for (i = 0; vm_bnames[i] != NULL; i++) 1372 if (strcmp(p, vm_bnames[i]) == 0) { 1373 vm_guest = VM_GUEST_VM; 1374 freeenv(p); 1375 return; 1376 } 1377 freeenv(p); 1378 } 1379 p = kern_getenv("smbios.system.product"); 1380 if (p != NULL) { 1381 for (i = 0; vm_pnames[i] != NULL; i++) 1382 if (strcmp(p, vm_pnames[i]) == 0) { 1383 vm_guest = VM_GUEST_VM; 1384 freeenv(p); 1385 return; 1386 } 1387 freeenv(p); 1388 } 1389} 1390 1391bool 1392fix_cpuid(void) 1393{ 1394 uint64_t msr; 1395 1396 /* 1397 * Clear "Limit CPUID Maxval" bit and return true if the caller should 1398 * get the largest standard CPUID function number again if it is set 1399 * from BIOS. It is necessary for probing correct CPU topology later 1400 * and for the correct operation of the AVX-aware userspace. 1401 */ 1402 if (cpu_vendor_id == CPU_VENDOR_INTEL && 1403 ((CPUID_TO_FAMILY(cpu_id) == 0xf && 1404 CPUID_TO_MODEL(cpu_id) >= 0x3) || 1405 (CPUID_TO_FAMILY(cpu_id) == 0x6 && 1406 CPUID_TO_MODEL(cpu_id) >= 0xe))) { 1407 msr = rdmsr(MSR_IA32_MISC_ENABLE); 1408 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) { 1409 msr &= ~IA32_MISC_EN_LIMCPUID; 1410 wrmsr(MSR_IA32_MISC_ENABLE, msr); 1411 return (true); 1412 } 1413 } 1414 1415 /* 1416 * Re-enable AMD Topology Extension that could be disabled by BIOS 1417 * on some notebook processors. Without the extension it's really 1418 * hard to determine the correct CPU cache topology. 1419 * See BIOS and Kernel Developer���s Guide (BKDG) for AMD Family 15h 1420 * Models 60h-6Fh Processors, Publication # 50742. 1421 */ 1422 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD && 1423 CPUID_TO_FAMILY(cpu_id) == 0x15) { 1424 msr = rdmsr(MSR_EXTFEATURES); 1425 if ((msr & ((uint64_t)1 << 54)) == 0) { 1426 msr |= (uint64_t)1 << 54; 1427 wrmsr(MSR_EXTFEATURES, msr); 1428 return (true); 1429 } 1430 } 1431 return (false); 1432} 1433 1434void 1435identify_cpu1(void) 1436{ 1437 u_int regs[4]; 1438 1439 do_cpuid(0, regs); 1440 cpu_high = regs[0]; 1441 ((u_int *)&cpu_vendor)[0] = regs[1]; 1442 ((u_int *)&cpu_vendor)[1] = regs[3]; 1443 ((u_int *)&cpu_vendor)[2] = regs[2]; 1444 cpu_vendor[12] = '\0'; 1445 1446 do_cpuid(1, regs); 1447 cpu_id = regs[0]; 1448 cpu_procinfo = regs[1]; 1449 cpu_feature = regs[3]; 1450 cpu_feature2 = regs[2]; 1451} 1452 1453void 1454identify_cpu2(void) 1455{ 1456 u_int regs[4], cpu_stdext_disable; 1457 1458 if (cpu_high >= 7) { 1459 cpuid_count(7, 0, regs); 1460 cpu_stdext_feature = regs[1]; 1461 1462 /* 1463 * Some hypervisors failed to filter out unsupported 1464 * extended features. Allow to disable the 1465 * extensions, activation of which requires setting a 1466 * bit in CR4, and which VM monitors do not support. 1467 */ 1468 cpu_stdext_disable = 0; 1469 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable); 1470 cpu_stdext_feature &= ~cpu_stdext_disable; 1471 1472 cpu_stdext_feature2 = regs[2]; 1473 cpu_stdext_feature3 = regs[3]; 1474 1475 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0) 1476 cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP); 1477 } 1478} 1479 1480/* 1481 * Final stage of CPU identification. 1482 */ 1483void 1484finishidentcpu(void) 1485{ 1486 u_int regs[4]; 1487#ifdef __i386__ 1488 u_char ccr3; 1489#endif 1490 1491 cpu_vendor_id = find_cpu_vendor_id(); 1492 1493 if (fix_cpuid()) { 1494 do_cpuid(0, regs); 1495 cpu_high = regs[0]; 1496 } 1497 1498 if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) { 1499 do_cpuid(5, regs); 1500 cpu_mon_mwait_flags = regs[2]; 1501 cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE; 1502 cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE; 1503 } 1504 1505 identify_cpu2(); 1506 1507#ifdef __i386__ 1508 if (cpu_high > 0 && 1509 (cpu_vendor_id == CPU_VENDOR_INTEL || 1510 cpu_vendor_id == CPU_VENDOR_AMD || 1511 cpu_vendor_id == CPU_VENDOR_TRANSMETA || 1512 cpu_vendor_id == CPU_VENDOR_CENTAUR || 1513 cpu_vendor_id == CPU_VENDOR_NSC)) { 1514 do_cpuid(0x80000000, regs); 1515 if (regs[0] >= 0x80000000) 1516 cpu_exthigh = regs[0]; 1517 } 1518#else 1519 if (cpu_vendor_id == CPU_VENDOR_INTEL || 1520 cpu_vendor_id == CPU_VENDOR_AMD || 1521 cpu_vendor_id == CPU_VENDOR_CENTAUR) { 1522 do_cpuid(0x80000000, regs); 1523 cpu_exthigh = regs[0]; 1524 } 1525#endif 1526 if (cpu_exthigh >= 0x80000001) { 1527 do_cpuid(0x80000001, regs); 1528 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); 1529 amd_feature2 = regs[2]; 1530 } 1531 if (cpu_exthigh >= 0x80000007) { 1532 do_cpuid(0x80000007, regs); 1533 amd_pminfo = regs[3]; 1534 } 1535 if (cpu_exthigh >= 0x80000008) { 1536 do_cpuid(0x80000008, regs); 1537 cpu_maxphyaddr = regs[0] & 0xff; 1538 amd_extended_feature_extensions = regs[1]; 1539 cpu_procinfo2 = regs[2]; 1540 } else { 1541 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32; 1542 } 1543 1544#ifdef __i386__ 1545 if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 1546 if (cpu == CPU_486) { 1547 /* 1548 * These conditions are equivalent to: 1549 * - CPU does not support cpuid instruction. 1550 * - Cyrix/IBM CPU is detected. 1551 */ 1552 if (identblue() == IDENTBLUE_IBMCPU) { 1553 strcpy(cpu_vendor, "IBM"); 1554 cpu_vendor_id = CPU_VENDOR_IBM; 1555 cpu = CPU_BLUE; 1556 return; 1557 } 1558 } 1559 switch (cpu_id & 0xf00) { 1560 case 0x600: 1561 /* 1562 * Cyrix's datasheet does not describe DIRs. 1563 * Therefor, I assume it does not have them 1564 * and use the result of the cpuid instruction. 1565 * XXX they seem to have it for now at least. -Peter 1566 */ 1567 identifycyrix(); 1568 cpu = CPU_M2; 1569 break; 1570 default: 1571 identifycyrix(); 1572 /* 1573 * This routine contains a trick. 1574 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now. 1575 */ 1576 switch (cyrix_did & 0x00f0) { 1577 case 0x00: 1578 case 0xf0: 1579 cpu = CPU_486DLC; 1580 break; 1581 case 0x10: 1582 cpu = CPU_CY486DX; 1583 break; 1584 case 0x20: 1585 if ((cyrix_did & 0x000f) < 8) 1586 cpu = CPU_M1; 1587 else 1588 cpu = CPU_M1SC; 1589 break; 1590 case 0x30: 1591 cpu = CPU_M1; 1592 break; 1593 case 0x40: 1594 /* MediaGX CPU */ 1595 cpu = CPU_M1SC; 1596 break; 1597 default: 1598 /* M2 and later CPUs are treated as M2. */ 1599 cpu = CPU_M2; 1600 1601 /* 1602 * enable cpuid instruction. 1603 */ 1604 ccr3 = read_cyrix_reg(CCR3); 1605 write_cyrix_reg(CCR3, CCR3_MAPEN0); 1606 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID); 1607 write_cyrix_reg(CCR3, ccr3); 1608 1609 do_cpuid(0, regs); 1610 cpu_high = regs[0]; /* eax */ 1611 do_cpuid(1, regs); 1612 cpu_id = regs[0]; /* eax */ 1613 cpu_feature = regs[3]; /* edx */ 1614 break; 1615 } 1616 } 1617 } else if (cpu == CPU_486 && *cpu_vendor == '\0') { 1618 /* 1619 * There are BlueLightning CPUs that do not change 1620 * undefined flags by dividing 5 by 2. In this case, 1621 * the CPU identification routine in locore.s leaves 1622 * cpu_vendor null string and puts CPU_486 into the 1623 * cpu. 1624 */ 1625 if (identblue() == IDENTBLUE_IBMCPU) { 1626 strcpy(cpu_vendor, "IBM"); 1627 cpu_vendor_id = CPU_VENDOR_IBM; 1628 cpu = CPU_BLUE; 1629 return; 1630 } 1631 } 1632#endif 1633} 1634 1635int 1636pti_get_default(void) 1637{ 1638 1639 if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0) 1640 return (0); 1641 if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0) 1642 return (0); 1643 return (1); 1644} 1645 1646static u_int 1647find_cpu_vendor_id(void) 1648{ 1649 int i; 1650 1651 for (i = 0; i < nitems(cpu_vendors); i++) 1652 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0) 1653 return (cpu_vendors[i].vendor_id); 1654 return (0); 1655} 1656 1657static void 1658print_AMD_assoc(int i) 1659{ 1660 if (i == 255) 1661 printf(", fully associative\n"); 1662 else 1663 printf(", %d-way associative\n", i); 1664} 1665 1666static void 1667print_AMD_l2_assoc(int i) 1668{ 1669 switch (i & 0x0f) { 1670 case 0: printf(", disabled/not present\n"); break; 1671 case 1: printf(", direct mapped\n"); break; 1672 case 2: printf(", 2-way associative\n"); break; 1673 case 4: printf(", 4-way associative\n"); break; 1674 case 6: printf(", 8-way associative\n"); break; 1675 case 8: printf(", 16-way associative\n"); break; 1676 case 15: printf(", fully associative\n"); break; 1677 default: printf(", reserved configuration\n"); break; 1678 } 1679} 1680 1681static void 1682print_AMD_info(void) 1683{ 1684#ifdef __i386__ 1685 uint64_t amd_whcr; 1686#endif 1687 u_int regs[4]; 1688 1689 if (cpu_exthigh >= 0x80000005) { 1690 do_cpuid(0x80000005, regs); 1691 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff); 1692 print_AMD_assoc(regs[0] >> 24); 1693 1694 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff); 1695 print_AMD_assoc((regs[0] >> 8) & 0xff); 1696 1697 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff); 1698 print_AMD_assoc(regs[1] >> 24); 1699 1700 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff); 1701 print_AMD_assoc((regs[1] >> 8) & 0xff); 1702 1703 printf("L1 data cache: %d kbytes", regs[2] >> 24); 1704 printf(", %d bytes/line", regs[2] & 0xff); 1705 printf(", %d lines/tag", (regs[2] >> 8) & 0xff); 1706 print_AMD_assoc((regs[2] >> 16) & 0xff); 1707 1708 printf("L1 instruction cache: %d kbytes", regs[3] >> 24); 1709 printf(", %d bytes/line", regs[3] & 0xff); 1710 printf(", %d lines/tag", (regs[3] >> 8) & 0xff); 1711 print_AMD_assoc((regs[3] >> 16) & 0xff); 1712 } 1713 1714 if (cpu_exthigh >= 0x80000006) { 1715 do_cpuid(0x80000006, regs); 1716 if ((regs[0] >> 16) != 0) { 1717 printf("L2 2MB data TLB: %d entries", 1718 (regs[0] >> 16) & 0xfff); 1719 print_AMD_l2_assoc(regs[0] >> 28); 1720 printf("L2 2MB instruction TLB: %d entries", 1721 regs[0] & 0xfff); 1722 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 1723 } else { 1724 printf("L2 2MB unified TLB: %d entries", 1725 regs[0] & 0xfff); 1726 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 1727 } 1728 if ((regs[1] >> 16) != 0) { 1729 printf("L2 4KB data TLB: %d entries", 1730 (regs[1] >> 16) & 0xfff); 1731 print_AMD_l2_assoc(regs[1] >> 28); 1732 1733 printf("L2 4KB instruction TLB: %d entries", 1734 (regs[1] >> 16) & 0xfff); 1735 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 1736 } else { 1737 printf("L2 4KB unified TLB: %d entries", 1738 (regs[1] >> 16) & 0xfff); 1739 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 1740 } 1741 printf("L2 unified cache: %d kbytes", regs[2] >> 16); 1742 printf(", %d bytes/line", regs[2] & 0xff); 1743 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); 1744 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f); 1745 } 1746 1747#ifdef __i386__ 1748 if (((cpu_id & 0xf00) == 0x500) 1749 && (((cpu_id & 0x0f0) > 0x80) 1750 || (((cpu_id & 0x0f0) == 0x80) 1751 && (cpu_id & 0x00f) > 0x07))) { 1752 /* K6-2(new core [Stepping 8-F]), K6-III or later */ 1753 amd_whcr = rdmsr(0xc0000082); 1754 if (!(amd_whcr & (0x3ff << 22))) { 1755 printf("Write Allocate Disable\n"); 1756 } else { 1757 printf("Write Allocate Enable Limit: %dM bytes\n", 1758 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4); 1759 printf("Write Allocate 15-16M bytes: %s\n", 1760 (amd_whcr & (1 << 16)) ? "Enable" : "Disable"); 1761 } 1762 } else if (((cpu_id & 0xf00) == 0x500) 1763 && ((cpu_id & 0x0f0) > 0x50)) { 1764 /* K6, K6-2(old core) */ 1765 amd_whcr = rdmsr(0xc0000082); 1766 if (!(amd_whcr & (0x7f << 1))) { 1767 printf("Write Allocate Disable\n"); 1768 } else { 1769 printf("Write Allocate Enable Limit: %dM bytes\n", 1770 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4); 1771 printf("Write Allocate 15-16M bytes: %s\n", 1772 (amd_whcr & 0x0001) ? "Enable" : "Disable"); 1773 printf("Hardware Write Allocate Control: %s\n", 1774 (amd_whcr & 0x0100) ? "Enable" : "Disable"); 1775 } 1776 } 1777#endif 1778 /* 1779 * Opteron Rev E shows a bug as in very rare occasions a read memory 1780 * barrier is not performed as expected if it is followed by a 1781 * non-atomic read-modify-write instruction. 1782 * As long as that bug pops up very rarely (intensive machine usage 1783 * on other operating systems generally generates one unexplainable 1784 * crash any 2 months) and as long as a model specific fix would be 1785 * impractical at this stage, print out a warning string if the broken 1786 * model and family are identified. 1787 */ 1788 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 && 1789 CPUID_TO_MODEL(cpu_id) <= 0x3f) 1790 printf("WARNING: This architecture revision has known SMP " 1791 "hardware bugs which may cause random instability\n"); 1792} 1793 1794static void 1795print_INTEL_info(void) 1796{ 1797 u_int regs[4]; 1798 u_int rounds, regnum; 1799 u_int nwaycode, nway; 1800 1801 if (cpu_high >= 2) { 1802 rounds = 0; 1803 do { 1804 do_cpuid(0x2, regs); 1805 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0) 1806 break; /* we have a buggy CPU */ 1807 1808 for (regnum = 0; regnum <= 3; ++regnum) { 1809 if (regs[regnum] & (1<<31)) 1810 continue; 1811 if (regnum != 0) 1812 print_INTEL_TLB(regs[regnum] & 0xff); 1813 print_INTEL_TLB((regs[regnum] >> 8) & 0xff); 1814 print_INTEL_TLB((regs[regnum] >> 16) & 0xff); 1815 print_INTEL_TLB((regs[regnum] >> 24) & 0xff); 1816 } 1817 } while (--rounds > 0); 1818 } 1819 1820 if (cpu_exthigh >= 0x80000006) { 1821 do_cpuid(0x80000006, regs); 1822 nwaycode = (regs[2] >> 12) & 0x0f; 1823 if (nwaycode >= 0x02 && nwaycode <= 0x08) 1824 nway = 1 << (nwaycode / 2); 1825 else 1826 nway = 0; 1827 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n", 1828 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff); 1829 } 1830} 1831 1832static void 1833print_INTEL_TLB(u_int data) 1834{ 1835 switch (data) { 1836 case 0x0: 1837 case 0x40: 1838 default: 1839 break; 1840 case 0x1: 1841 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n"); 1842 break; 1843 case 0x2: 1844 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n"); 1845 break; 1846 case 0x3: 1847 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n"); 1848 break; 1849 case 0x4: 1850 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n"); 1851 break; 1852 case 0x6: 1853 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n"); 1854 break; 1855 case 0x8: 1856 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n"); 1857 break; 1858 case 0x9: 1859 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n"); 1860 break; 1861 case 0xa: 1862 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n"); 1863 break; 1864 case 0xb: 1865 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n"); 1866 break; 1867 case 0xc: 1868 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n"); 1869 break; 1870 case 0xd: 1871 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size"); 1872 break; 1873 case 0xe: 1874 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n"); 1875 break; 1876 case 0x1d: 1877 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n"); 1878 break; 1879 case 0x21: 1880 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n"); 1881 break; 1882 case 0x22: 1883 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1884 break; 1885 case 0x23: 1886 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1887 break; 1888 case 0x24: 1889 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n"); 1890 break; 1891 case 0x25: 1892 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1893 break; 1894 case 0x29: 1895 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1896 break; 1897 case 0x2c: 1898 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n"); 1899 break; 1900 case 0x30: 1901 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n"); 1902 break; 1903 case 0x39: /* De-listed in SDM rev. 54 */ 1904 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1905 break; 1906 case 0x3b: /* De-listed in SDM rev. 54 */ 1907 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n"); 1908 break; 1909 case 0x3c: /* De-listed in SDM rev. 54 */ 1910 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1911 break; 1912 case 0x41: 1913 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n"); 1914 break; 1915 case 0x42: 1916 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n"); 1917 break; 1918 case 0x43: 1919 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n"); 1920 break; 1921 case 0x44: 1922 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n"); 1923 break; 1924 case 0x45: 1925 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n"); 1926 break; 1927 case 0x46: 1928 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n"); 1929 break; 1930 case 0x47: 1931 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n"); 1932 break; 1933 case 0x48: 1934 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n"); 1935 break; 1936 case 0x49: 1937 if (CPUID_TO_FAMILY(cpu_id) == 0xf && 1938 CPUID_TO_MODEL(cpu_id) == 0x6) 1939 printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n"); 1940 else 1941 printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size"); 1942 break; 1943 case 0x4a: 1944 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n"); 1945 break; 1946 case 0x4b: 1947 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n"); 1948 break; 1949 case 0x4c: 1950 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n"); 1951 break; 1952 case 0x4d: 1953 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n"); 1954 break; 1955 case 0x4e: 1956 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n"); 1957 break; 1958 case 0x4f: 1959 printf("Instruction TLB: 4 KByte pages, 32 entries\n"); 1960 break; 1961 case 0x50: 1962 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n"); 1963 break; 1964 case 0x51: 1965 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n"); 1966 break; 1967 case 0x52: 1968 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n"); 1969 break; 1970 case 0x55: 1971 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n"); 1972 break; 1973 case 0x56: 1974 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n"); 1975 break; 1976 case 0x57: 1977 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n"); 1978 break; 1979 case 0x59: 1980 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n"); 1981 break; 1982 case 0x5a: 1983 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n"); 1984 break; 1985 case 0x5b: 1986 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n"); 1987 break; 1988 case 0x5c: 1989 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n"); 1990 break; 1991 case 0x5d: 1992 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n"); 1993 break; 1994 case 0x60: 1995 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 1996 break; 1997 case 0x61: 1998 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n"); 1999 break; 2000 case 0x63: 2001 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n"); 2002 break; 2003 case 0x64: 2004 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n"); 2005 break; 2006 case 0x66: 2007 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2008 break; 2009 case 0x67: 2010 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2011 break; 2012 case 0x68: 2013 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n"); 2014 break; 2015 case 0x6a: 2016 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n"); 2017 break; 2018 case 0x6b: 2019 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n"); 2020 break; 2021 case 0x6c: 2022 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n"); 2023 break; 2024 case 0x6d: 2025 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n"); 2026 break; 2027 case 0x70: 2028 printf("Trace cache: 12K-uops, 8-way set associative\n"); 2029 break; 2030 case 0x71: 2031 printf("Trace cache: 16K-uops, 8-way set associative\n"); 2032 break; 2033 case 0x72: 2034 printf("Trace cache: 32K-uops, 8-way set associative\n"); 2035 break; 2036 case 0x76: 2037 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n"); 2038 break; 2039 case 0x78: 2040 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n"); 2041 break; 2042 case 0x79: 2043 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2044 break; 2045 case 0x7a: 2046 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2047 break; 2048 case 0x7b: 2049 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2050 break; 2051 case 0x7c: 2052 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 2053 break; 2054 case 0x7d: 2055 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n"); 2056 break; 2057 case 0x7f: 2058 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n"); 2059 break; 2060 case 0x80: 2061 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n"); 2062 break; 2063 case 0x82: 2064 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n"); 2065 break; 2066 case 0x83: 2067 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n"); 2068 break; 2069 case 0x84: 2070 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n"); 2071 break; 2072 case 0x85: 2073 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n"); 2074 break; 2075 case 0x86: 2076 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n"); 2077 break; 2078 case 0x87: 2079 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n"); 2080 break; 2081 case 0xa0: 2082 printf("DTLB: 4k pages, fully associative, 32 entries\n"); 2083 break; 2084 case 0xb0: 2085 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); 2086 break; 2087 case 0xb1: 2088 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n"); 2089 break; 2090 case 0xb2: 2091 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n"); 2092 break; 2093 case 0xb3: 2094 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); 2095 break; 2096 case 0xb4: 2097 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n"); 2098 break; 2099 case 0xb5: 2100 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n"); 2101 break; 2102 case 0xb6: 2103 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n"); 2104 break; 2105 case 0xba: 2106 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n"); 2107 break; 2108 case 0xc0: 2109 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n"); 2110 break; 2111 case 0xc1: 2112 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n"); 2113 break; 2114 case 0xc2: 2115 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n"); 2116 break; 2117 case 0xc3: 2118 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n"); 2119 break; 2120 case 0xc4: 2121 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n"); 2122 break; 2123 case 0xca: 2124 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n"); 2125 break; 2126 case 0xd0: 2127 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n"); 2128 break; 2129 case 0xd1: 2130 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n"); 2131 break; 2132 case 0xd2: 2133 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n"); 2134 break; 2135 case 0xd6: 2136 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n"); 2137 break; 2138 case 0xd7: 2139 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n"); 2140 break; 2141 case 0xd8: 2142 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n"); 2143 break; 2144 case 0xdc: 2145 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n"); 2146 break; 2147 case 0xdd: 2148 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n"); 2149 break; 2150 case 0xde: 2151 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n"); 2152 break; 2153 case 0xe2: 2154 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n"); 2155 break; 2156 case 0xe3: 2157 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n"); 2158 break; 2159 case 0xe4: 2160 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n"); 2161 break; 2162 case 0xea: 2163 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n"); 2164 break; 2165 case 0xeb: 2166 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n"); 2167 break; 2168 case 0xec: 2169 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n"); 2170 break; 2171 case 0xf0: 2172 printf("64-Byte prefetching\n"); 2173 break; 2174 case 0xf1: 2175 printf("128-Byte prefetching\n"); 2176 break; 2177 } 2178} 2179 2180static void 2181print_svm_info(void) 2182{ 2183 u_int features, regs[4]; 2184 uint64_t msr; 2185 int comma; 2186 2187 printf("\n SVM: "); 2188 do_cpuid(0x8000000A, regs); 2189 features = regs[3]; 2190 2191 msr = rdmsr(MSR_VM_CR); 2192 if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS) 2193 printf("(disabled in BIOS) "); 2194 2195 if (!bootverbose) { 2196 comma = 0; 2197 if (features & (1 << 0)) { 2198 printf("%sNP", comma ? "," : ""); 2199 comma = 1; 2200 } 2201 if (features & (1 << 3)) { 2202 printf("%sNRIP", comma ? "," : ""); 2203 comma = 1; 2204 } 2205 if (features & (1 << 5)) { 2206 printf("%sVClean", comma ? "," : ""); 2207 comma = 1; 2208 } 2209 if (features & (1 << 6)) { 2210 printf("%sAFlush", comma ? "," : ""); 2211 comma = 1; 2212 } 2213 if (features & (1 << 7)) { 2214 printf("%sDAssist", comma ? "," : ""); 2215 comma = 1; 2216 } 2217 printf("%sNAsids=%d", comma ? "," : "", regs[1]); 2218 return; 2219 } 2220 2221 printf("Features=0x%b", features, 2222 "\020" 2223 "\001NP" /* Nested paging */ 2224 "\002LbrVirt" /* LBR virtualization */ 2225 "\003SVML" /* SVM lock */ 2226 "\004NRIPS" /* NRIP save */ 2227 "\005TscRateMsr" /* MSR based TSC rate control */ 2228 "\006VmcbClean" /* VMCB clean bits */ 2229 "\007FlushByAsid" /* Flush by ASID */ 2230 "\010DecodeAssist" /* Decode assist */ 2231 "\011<b8>" 2232 "\012<b9>" 2233 "\013PauseFilter" /* PAUSE intercept filter */ 2234 "\014<b11>" 2235 "\015PauseFilterThreshold" /* PAUSE filter threshold */ 2236 "\016AVIC" /* virtual interrupt controller */ 2237 ); 2238 printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]); 2239} 2240 2241#ifdef __i386__ 2242static void 2243print_transmeta_info(void) 2244{ 2245 u_int regs[4], nreg = 0; 2246 2247 do_cpuid(0x80860000, regs); 2248 nreg = regs[0]; 2249 if (nreg >= 0x80860001) { 2250 do_cpuid(0x80860001, regs); 2251 printf(" Processor revision %u.%u.%u.%u\n", 2252 (regs[1] >> 24) & 0xff, 2253 (regs[1] >> 16) & 0xff, 2254 (regs[1] >> 8) & 0xff, 2255 regs[1] & 0xff); 2256 } 2257 if (nreg >= 0x80860002) { 2258 do_cpuid(0x80860002, regs); 2259 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n", 2260 (regs[1] >> 24) & 0xff, 2261 (regs[1] >> 16) & 0xff, 2262 (regs[1] >> 8) & 0xff, 2263 regs[1] & 0xff, 2264 regs[2]); 2265 } 2266 if (nreg >= 0x80860006) { 2267 char info[65]; 2268 do_cpuid(0x80860003, (u_int*) &info[0]); 2269 do_cpuid(0x80860004, (u_int*) &info[16]); 2270 do_cpuid(0x80860005, (u_int*) &info[32]); 2271 do_cpuid(0x80860006, (u_int*) &info[48]); 2272 info[64] = 0; 2273 printf(" %s\n", info); 2274 } 2275} 2276#endif 2277 2278static void 2279print_via_padlock_info(void) 2280{ 2281 u_int regs[4]; 2282 2283 do_cpuid(0xc0000001, regs); 2284 printf("\n VIA Padlock Features=0x%b", regs[3], 2285 "\020" 2286 "\003RNG" /* RNG */ 2287 "\007AES" /* ACE */ 2288 "\011AES-CTR" /* ACE2 */ 2289 "\013SHA1,SHA256" /* PHE */ 2290 "\015RSA" /* PMM */ 2291 ); 2292} 2293 2294static uint32_t 2295vmx_settable(uint64_t basic, int msr, int true_msr) 2296{ 2297 uint64_t val; 2298 2299 if (basic & (1ULL << 55)) 2300 val = rdmsr(true_msr); 2301 else 2302 val = rdmsr(msr); 2303 2304 /* Just report the controls that can be set to 1. */ 2305 return (val >> 32); 2306} 2307 2308static void 2309print_vmx_info(void) 2310{ 2311 uint64_t basic, msr; 2312 uint32_t entry, exit, mask, pin, proc, proc2; 2313 int comma; 2314 2315 printf("\n VT-x: "); 2316 msr = rdmsr(MSR_IA32_FEATURE_CONTROL); 2317 if (!(msr & IA32_FEATURE_CONTROL_VMX_EN)) 2318 printf("(disabled in BIOS) "); 2319 basic = rdmsr(MSR_VMX_BASIC); 2320 pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS, 2321 MSR_VMX_TRUE_PINBASED_CTLS); 2322 proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS, 2323 MSR_VMX_TRUE_PROCBASED_CTLS); 2324 if (proc & PROCBASED_SECONDARY_CONTROLS) 2325 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2, 2326 MSR_VMX_PROCBASED_CTLS2); 2327 else 2328 proc2 = 0; 2329 exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS); 2330 entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS); 2331 2332 if (!bootverbose) { 2333 comma = 0; 2334 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT && 2335 entry & VM_ENTRY_LOAD_PAT) { 2336 printf("%sPAT", comma ? "," : ""); 2337 comma = 1; 2338 } 2339 if (proc & PROCBASED_HLT_EXITING) { 2340 printf("%sHLT", comma ? "," : ""); 2341 comma = 1; 2342 } 2343 if (proc & PROCBASED_MTF) { 2344 printf("%sMTF", comma ? "," : ""); 2345 comma = 1; 2346 } 2347 if (proc & PROCBASED_PAUSE_EXITING) { 2348 printf("%sPAUSE", comma ? "," : ""); 2349 comma = 1; 2350 } 2351 if (proc2 & PROCBASED2_ENABLE_EPT) { 2352 printf("%sEPT", comma ? "," : ""); 2353 comma = 1; 2354 } 2355 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) { 2356 printf("%sUG", comma ? "," : ""); 2357 comma = 1; 2358 } 2359 if (proc2 & PROCBASED2_ENABLE_VPID) { 2360 printf("%sVPID", comma ? "," : ""); 2361 comma = 1; 2362 } 2363 if (proc & PROCBASED_USE_TPR_SHADOW && 2364 proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES && 2365 proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE && 2366 proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION && 2367 proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) { 2368 printf("%sVID", comma ? "," : ""); 2369 comma = 1; 2370 if (pin & PINBASED_POSTED_INTERRUPT) 2371 printf(",PostIntr"); 2372 } 2373 return; 2374 } 2375 2376 mask = basic >> 32; 2377 printf("Basic Features=0x%b", mask, 2378 "\020" 2379 "\02132PA" /* 32-bit physical addresses */ 2380 "\022SMM" /* SMM dual-monitor */ 2381 "\027INS/OUTS" /* VM-exit info for INS and OUTS */ 2382 "\030TRUE" /* TRUE_CTLS MSRs */ 2383 ); 2384 printf("\n Pin-Based Controls=0x%b", pin, 2385 "\020" 2386 "\001ExtINT" /* External-interrupt exiting */ 2387 "\004NMI" /* NMI exiting */ 2388 "\006VNMI" /* Virtual NMIs */ 2389 "\007PreTmr" /* Activate VMX-preemption timer */ 2390 "\010PostIntr" /* Process posted interrupts */ 2391 ); 2392 printf("\n Primary Processor Controls=0x%b", proc, 2393 "\020" 2394 "\003INTWIN" /* Interrupt-window exiting */ 2395 "\004TSCOff" /* Use TSC offsetting */ 2396 "\010HLT" /* HLT exiting */ 2397 "\012INVLPG" /* INVLPG exiting */ 2398 "\013MWAIT" /* MWAIT exiting */ 2399 "\014RDPMC" /* RDPMC exiting */ 2400 "\015RDTSC" /* RDTSC exiting */ 2401 "\020CR3-LD" /* CR3-load exiting */ 2402 "\021CR3-ST" /* CR3-store exiting */ 2403 "\024CR8-LD" /* CR8-load exiting */ 2404 "\025CR8-ST" /* CR8-store exiting */ 2405 "\026TPR" /* Use TPR shadow */ 2406 "\027NMIWIN" /* NMI-window exiting */ 2407 "\030MOV-DR" /* MOV-DR exiting */ 2408 "\031IO" /* Unconditional I/O exiting */ 2409 "\032IOmap" /* Use I/O bitmaps */ 2410 "\034MTF" /* Monitor trap flag */ 2411 "\035MSRmap" /* Use MSR bitmaps */ 2412 "\036MONITOR" /* MONITOR exiting */ 2413 "\037PAUSE" /* PAUSE exiting */ 2414 ); 2415 if (proc & PROCBASED_SECONDARY_CONTROLS) 2416 printf("\n Secondary Processor Controls=0x%b", proc2, 2417 "\020" 2418 "\001APIC" /* Virtualize APIC accesses */ 2419 "\002EPT" /* Enable EPT */ 2420 "\003DT" /* Descriptor-table exiting */ 2421 "\004RDTSCP" /* Enable RDTSCP */ 2422 "\005x2APIC" /* Virtualize x2APIC mode */ 2423 "\006VPID" /* Enable VPID */ 2424 "\007WBINVD" /* WBINVD exiting */ 2425 "\010UG" /* Unrestricted guest */ 2426 "\011APIC-reg" /* APIC-register virtualization */ 2427 "\012VID" /* Virtual-interrupt delivery */ 2428 "\013PAUSE-loop" /* PAUSE-loop exiting */ 2429 "\014RDRAND" /* RDRAND exiting */ 2430 "\015INVPCID" /* Enable INVPCID */ 2431 "\016VMFUNC" /* Enable VM functions */ 2432 "\017VMCS" /* VMCS shadowing */ 2433 "\020EPT#VE" /* EPT-violation #VE */ 2434 "\021XSAVES" /* Enable XSAVES/XRSTORS */ 2435 ); 2436 printf("\n Exit Controls=0x%b", mask, 2437 "\020" 2438 "\003DR" /* Save debug controls */ 2439 /* Ignore Host address-space size */ 2440 "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */ 2441 "\020AckInt" /* Acknowledge interrupt on exit */ 2442 "\023PAT-SV" /* Save MSR_PAT */ 2443 "\024PAT-LD" /* Load MSR_PAT */ 2444 "\025EFER-SV" /* Save MSR_EFER */ 2445 "\026EFER-LD" /* Load MSR_EFER */ 2446 "\027PTMR-SV" /* Save VMX-preemption timer value */ 2447 ); 2448 printf("\n Entry Controls=0x%b", mask, 2449 "\020" 2450 "\003DR" /* Save debug controls */ 2451 /* Ignore IA-32e mode guest */ 2452 /* Ignore Entry to SMM */ 2453 /* Ignore Deactivate dual-monitor treatment */ 2454 "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */ 2455 "\017PAT" /* Load MSR_PAT */ 2456 "\020EFER" /* Load MSR_EFER */ 2457 ); 2458 if (proc & PROCBASED_SECONDARY_CONTROLS && 2459 (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) { 2460 msr = rdmsr(MSR_VMX_EPT_VPID_CAP); 2461 mask = msr; 2462 printf("\n EPT Features=0x%b", mask, 2463 "\020" 2464 "\001XO" /* Execute-only translations */ 2465 "\007PW4" /* Page-walk length of 4 */ 2466 "\011UC" /* EPT paging-structure mem can be UC */ 2467 "\017WB" /* EPT paging-structure mem can be WB */ 2468 "\0212M" /* EPT PDE can map a 2-Mbyte page */ 2469 "\0221G" /* EPT PDPTE can map a 1-Gbyte page */ 2470 "\025INVEPT" /* INVEPT is supported */ 2471 "\026AD" /* Accessed and dirty flags for EPT */ 2472 "\032single" /* INVEPT single-context type */ 2473 "\033all" /* INVEPT all-context type */ 2474 ); 2475 mask = msr >> 32; 2476 printf("\n VPID Features=0x%b", mask, 2477 "\020" 2478 "\001INVVPID" /* INVVPID is supported */ 2479 "\011individual" /* INVVPID individual-address type */ 2480 "\012single" /* INVVPID single-context type */ 2481 "\013all" /* INVVPID all-context type */ 2482 /* INVVPID single-context-retaining-globals type */ 2483 "\014single-globals" 2484 ); 2485 } 2486} 2487 2488static void 2489print_hypervisor_info(void) 2490{ 2491 2492 if (*hv_vendor) 2493 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor); 2494} 2495