identcpu.c revision 315927
1/*- 2 * Copyright (c) 1992 Terrence R. Lambert. 3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 4 * Copyright (c) 1997 KATO Takenori. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp 39 */ 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: stable/11/sys/x86/x86/identcpu.c 315927 2017-03-25 05:05:12Z grehan $"); 43 44#include "opt_cpu.h" 45 46#include <sys/param.h> 47#include <sys/bus.h> 48#include <sys/cpu.h> 49#include <sys/eventhandler.h> 50#include <sys/limits.h> 51#include <sys/systm.h> 52#include <sys/kernel.h> 53#include <sys/sysctl.h> 54#include <sys/power.h> 55 56#include <machine/asmacros.h> 57#include <machine/clock.h> 58#include <machine/cputypes.h> 59#include <machine/frame.h> 60#include <machine/intr_machdep.h> 61#include <machine/md_var.h> 62#include <machine/segments.h> 63#include <machine/specialreg.h> 64 65#include <amd64/vmm/intel/vmx_controls.h> 66#include <x86/isa/icu.h> 67#include <x86/vmware.h> 68 69#ifdef __i386__ 70#define IDENTBLUE_CYRIX486 0 71#define IDENTBLUE_IBMCPU 1 72#define IDENTBLUE_CYRIXM2 2 73 74static void identifycyrix(void); 75static void print_transmeta_info(void); 76#endif 77static u_int find_cpu_vendor_id(void); 78static void print_AMD_info(void); 79static void print_INTEL_info(void); 80static void print_INTEL_TLB(u_int data); 81static void print_hypervisor_info(void); 82static void print_svm_info(void); 83static void print_via_padlock_info(void); 84static void print_vmx_info(void); 85 86#ifdef __i386__ 87int cpu; /* Are we 386, 386sx, 486, etc? */ 88int cpu_class; 89#endif 90u_int cpu_feature; /* Feature flags */ 91u_int cpu_feature2; /* Feature flags */ 92u_int amd_feature; /* AMD feature flags */ 93u_int amd_feature2; /* AMD feature flags */ 94u_int amd_pminfo; /* AMD advanced power management info */ 95u_int via_feature_rng; /* VIA RNG features */ 96u_int via_feature_xcrypt; /* VIA ACE features */ 97u_int cpu_high; /* Highest arg to CPUID */ 98u_int cpu_exthigh; /* Highest arg to extended CPUID */ 99u_int cpu_id; /* Stepping ID */ 100u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */ 101u_int cpu_procinfo2; /* Multicore info */ 102char cpu_vendor[20]; /* CPU Origin code */ 103u_int cpu_vendor_id; /* CPU vendor ID */ 104u_int cpu_fxsr; /* SSE enabled */ 105u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */ 106u_int cpu_clflush_line_size = 32; 107u_int cpu_stdext_feature; 108u_int cpu_stdext_feature2; 109u_int cpu_max_ext_state_size; 110u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */ 111u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */ 112u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */ 113u_int cpu_maxphyaddr; /* Max phys addr width in bits */ 114char machine[] = MACHINE; 115 116SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD, 117 &via_feature_rng, 0, 118 "VIA RNG feature available in CPU"); 119SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD, 120 &via_feature_xcrypt, 0, 121 "VIA xcrypt feature available in CPU"); 122 123#ifdef __amd64__ 124#ifdef SCTL_MASK32 125extern int adaptive_machine_arch; 126#endif 127 128static int 129sysctl_hw_machine(SYSCTL_HANDLER_ARGS) 130{ 131#ifdef SCTL_MASK32 132 static const char machine32[] = "i386"; 133#endif 134 int error; 135 136#ifdef SCTL_MASK32 137 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch) 138 error = SYSCTL_OUT(req, machine32, sizeof(machine32)); 139 else 140#endif 141 error = SYSCTL_OUT(req, machine, sizeof(machine)); 142 return (error); 143 144} 145SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD | 146 CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class"); 147#else 148SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 149 machine, 0, "Machine class"); 150#endif 151 152static char cpu_model[128]; 153SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_MPSAFE, 154 cpu_model, 0, "Machine model"); 155 156static int hw_clockrate; 157SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 158 &hw_clockrate, 0, "CPU instruction clock rate"); 159 160u_int hv_high; 161char hv_vendor[16]; 162SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD | CTLFLAG_MPSAFE, hv_vendor, 163 0, "Hypervisor vendor"); 164 165static eventhandler_tag tsc_post_tag; 166 167static char cpu_brand[48]; 168 169#ifdef __i386__ 170#define MAX_BRAND_INDEX 8 171 172static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = { 173 NULL, /* No brand */ 174 "Intel Celeron", 175 "Intel Pentium III", 176 "Intel Pentium III Xeon", 177 NULL, 178 NULL, 179 NULL, 180 NULL, 181 "Intel Pentium 4" 182}; 183 184static struct { 185 char *cpu_name; 186 int cpu_class; 187} cpus[] = { 188 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */ 189 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */ 190 { "i386DX", CPUCLASS_386 }, /* CPU_386 */ 191 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */ 192 { "i486DX", CPUCLASS_486 }, /* CPU_486 */ 193 { "Pentium", CPUCLASS_586 }, /* CPU_586 */ 194 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */ 195 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */ 196 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */ 197 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */ 198 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */ 199 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */ 200 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */ 201 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */ 202 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */ 203 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */ 204 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */ 205}; 206#endif 207 208static struct { 209 char *vendor; 210 u_int vendor_id; 211} cpu_vendors[] = { 212 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */ 213 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */ 214 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */ 215#ifdef __i386__ 216 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */ 217 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */ 218 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */ 219 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */ 220 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */ 221 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */ 222 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */ 223#if 0 224 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */ 225 { "TransmetaCPU", CPU_VENDOR_TRANSMETA }, 226#endif 227#endif 228}; 229 230void 231printcpuinfo(void) 232{ 233 u_int regs[4], i; 234 char *brand; 235 236 printf("CPU: "); 237#ifdef __i386__ 238 cpu_class = cpus[cpu].cpu_class; 239 strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model)); 240#else 241 strncpy(cpu_model, "Hammer", sizeof (cpu_model)); 242#endif 243 244 /* Check for extended CPUID information and a processor name. */ 245 if (cpu_exthigh >= 0x80000004) { 246 brand = cpu_brand; 247 for (i = 0x80000002; i < 0x80000005; i++) { 248 do_cpuid(i, regs); 249 memcpy(brand, regs, sizeof(regs)); 250 brand += sizeof(regs); 251 } 252 } 253 254 switch (cpu_vendor_id) { 255 case CPU_VENDOR_INTEL: 256#ifdef __i386__ 257 if ((cpu_id & 0xf00) > 0x300) { 258 u_int brand_index; 259 260 cpu_model[0] = '\0'; 261 262 switch (cpu_id & 0x3000) { 263 case 0x1000: 264 strcpy(cpu_model, "Overdrive "); 265 break; 266 case 0x2000: 267 strcpy(cpu_model, "Dual "); 268 break; 269 } 270 271 switch (cpu_id & 0xf00) { 272 case 0x400: 273 strcat(cpu_model, "i486 "); 274 /* Check the particular flavor of 486 */ 275 switch (cpu_id & 0xf0) { 276 case 0x00: 277 case 0x10: 278 strcat(cpu_model, "DX"); 279 break; 280 case 0x20: 281 strcat(cpu_model, "SX"); 282 break; 283 case 0x30: 284 strcat(cpu_model, "DX2"); 285 break; 286 case 0x40: 287 strcat(cpu_model, "SL"); 288 break; 289 case 0x50: 290 strcat(cpu_model, "SX2"); 291 break; 292 case 0x70: 293 strcat(cpu_model, 294 "DX2 Write-Back Enhanced"); 295 break; 296 case 0x80: 297 strcat(cpu_model, "DX4"); 298 break; 299 } 300 break; 301 case 0x500: 302 /* Check the particular flavor of 586 */ 303 strcat(cpu_model, "Pentium"); 304 switch (cpu_id & 0xf0) { 305 case 0x00: 306 strcat(cpu_model, " A-step"); 307 break; 308 case 0x10: 309 strcat(cpu_model, "/P5"); 310 break; 311 case 0x20: 312 strcat(cpu_model, "/P54C"); 313 break; 314 case 0x30: 315 strcat(cpu_model, "/P24T"); 316 break; 317 case 0x40: 318 strcat(cpu_model, "/P55C"); 319 break; 320 case 0x70: 321 strcat(cpu_model, "/P54C"); 322 break; 323 case 0x80: 324 strcat(cpu_model, "/P55C (quarter-micron)"); 325 break; 326 default: 327 /* nothing */ 328 break; 329 } 330#if defined(I586_CPU) && !defined(NO_F00F_HACK) 331 /* 332 * XXX - If/when Intel fixes the bug, this 333 * should also check the version of the 334 * CPU, not just that it's a Pentium. 335 */ 336 has_f00f_bug = 1; 337#endif 338 break; 339 case 0x600: 340 /* Check the particular flavor of 686 */ 341 switch (cpu_id & 0xf0) { 342 case 0x00: 343 strcat(cpu_model, "Pentium Pro A-step"); 344 break; 345 case 0x10: 346 strcat(cpu_model, "Pentium Pro"); 347 break; 348 case 0x30: 349 case 0x50: 350 case 0x60: 351 strcat(cpu_model, 352 "Pentium II/Pentium II Xeon/Celeron"); 353 cpu = CPU_PII; 354 break; 355 case 0x70: 356 case 0x80: 357 case 0xa0: 358 case 0xb0: 359 strcat(cpu_model, 360 "Pentium III/Pentium III Xeon/Celeron"); 361 cpu = CPU_PIII; 362 break; 363 default: 364 strcat(cpu_model, "Unknown 80686"); 365 break; 366 } 367 break; 368 case 0xf00: 369 strcat(cpu_model, "Pentium 4"); 370 cpu = CPU_P4; 371 break; 372 default: 373 strcat(cpu_model, "unknown"); 374 break; 375 } 376 377 /* 378 * If we didn't get a brand name from the extended 379 * CPUID, try to look it up in the brand table. 380 */ 381 if (cpu_high > 0 && *cpu_brand == '\0') { 382 brand_index = cpu_procinfo & CPUID_BRAND_INDEX; 383 if (brand_index <= MAX_BRAND_INDEX && 384 cpu_brandtable[brand_index] != NULL) 385 strcpy(cpu_brand, 386 cpu_brandtable[brand_index]); 387 } 388 } 389#else 390 /* Please make up your mind folks! */ 391 strcat(cpu_model, "EM64T"); 392#endif 393 break; 394 case CPU_VENDOR_AMD: 395 /* 396 * Values taken from AMD Processor Recognition 397 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf 398 * (also describes ``Features'' encodings. 399 */ 400 strcpy(cpu_model, "AMD "); 401#ifdef __i386__ 402 switch (cpu_id & 0xFF0) { 403 case 0x410: 404 strcat(cpu_model, "Standard Am486DX"); 405 break; 406 case 0x430: 407 strcat(cpu_model, "Enhanced Am486DX2 Write-Through"); 408 break; 409 case 0x470: 410 strcat(cpu_model, "Enhanced Am486DX2 Write-Back"); 411 break; 412 case 0x480: 413 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through"); 414 break; 415 case 0x490: 416 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back"); 417 break; 418 case 0x4E0: 419 strcat(cpu_model, "Am5x86 Write-Through"); 420 break; 421 case 0x4F0: 422 strcat(cpu_model, "Am5x86 Write-Back"); 423 break; 424 case 0x500: 425 strcat(cpu_model, "K5 model 0"); 426 break; 427 case 0x510: 428 strcat(cpu_model, "K5 model 1"); 429 break; 430 case 0x520: 431 strcat(cpu_model, "K5 PR166 (model 2)"); 432 break; 433 case 0x530: 434 strcat(cpu_model, "K5 PR200 (model 3)"); 435 break; 436 case 0x560: 437 strcat(cpu_model, "K6"); 438 break; 439 case 0x570: 440 strcat(cpu_model, "K6 266 (model 1)"); 441 break; 442 case 0x580: 443 strcat(cpu_model, "K6-2"); 444 break; 445 case 0x590: 446 strcat(cpu_model, "K6-III"); 447 break; 448 case 0x5a0: 449 strcat(cpu_model, "Geode LX"); 450 break; 451 default: 452 strcat(cpu_model, "Unknown"); 453 break; 454 } 455#else 456 if ((cpu_id & 0xf00) == 0xf00) 457 strcat(cpu_model, "AMD64 Processor"); 458 else 459 strcat(cpu_model, "Unknown"); 460#endif 461 break; 462#ifdef __i386__ 463 case CPU_VENDOR_CYRIX: 464 strcpy(cpu_model, "Cyrix "); 465 switch (cpu_id & 0xff0) { 466 case 0x440: 467 strcat(cpu_model, "MediaGX"); 468 break; 469 case 0x520: 470 strcat(cpu_model, "6x86"); 471 break; 472 case 0x540: 473 cpu_class = CPUCLASS_586; 474 strcat(cpu_model, "GXm"); 475 break; 476 case 0x600: 477 strcat(cpu_model, "6x86MX"); 478 break; 479 default: 480 /* 481 * Even though CPU supports the cpuid 482 * instruction, it can be disabled. 483 * Therefore, this routine supports all Cyrix 484 * CPUs. 485 */ 486 switch (cyrix_did & 0xf0) { 487 case 0x00: 488 switch (cyrix_did & 0x0f) { 489 case 0x00: 490 strcat(cpu_model, "486SLC"); 491 break; 492 case 0x01: 493 strcat(cpu_model, "486DLC"); 494 break; 495 case 0x02: 496 strcat(cpu_model, "486SLC2"); 497 break; 498 case 0x03: 499 strcat(cpu_model, "486DLC2"); 500 break; 501 case 0x04: 502 strcat(cpu_model, "486SRx"); 503 break; 504 case 0x05: 505 strcat(cpu_model, "486DRx"); 506 break; 507 case 0x06: 508 strcat(cpu_model, "486SRx2"); 509 break; 510 case 0x07: 511 strcat(cpu_model, "486DRx2"); 512 break; 513 case 0x08: 514 strcat(cpu_model, "486SRu"); 515 break; 516 case 0x09: 517 strcat(cpu_model, "486DRu"); 518 break; 519 case 0x0a: 520 strcat(cpu_model, "486SRu2"); 521 break; 522 case 0x0b: 523 strcat(cpu_model, "486DRu2"); 524 break; 525 default: 526 strcat(cpu_model, "Unknown"); 527 break; 528 } 529 break; 530 case 0x10: 531 switch (cyrix_did & 0x0f) { 532 case 0x00: 533 strcat(cpu_model, "486S"); 534 break; 535 case 0x01: 536 strcat(cpu_model, "486S2"); 537 break; 538 case 0x02: 539 strcat(cpu_model, "486Se"); 540 break; 541 case 0x03: 542 strcat(cpu_model, "486S2e"); 543 break; 544 case 0x0a: 545 strcat(cpu_model, "486DX"); 546 break; 547 case 0x0b: 548 strcat(cpu_model, "486DX2"); 549 break; 550 case 0x0f: 551 strcat(cpu_model, "486DX4"); 552 break; 553 default: 554 strcat(cpu_model, "Unknown"); 555 break; 556 } 557 break; 558 case 0x20: 559 if ((cyrix_did & 0x0f) < 8) 560 strcat(cpu_model, "6x86"); /* Where did you get it? */ 561 else 562 strcat(cpu_model, "5x86"); 563 break; 564 case 0x30: 565 strcat(cpu_model, "6x86"); 566 break; 567 case 0x40: 568 if ((cyrix_did & 0xf000) == 0x3000) { 569 cpu_class = CPUCLASS_586; 570 strcat(cpu_model, "GXm"); 571 } else 572 strcat(cpu_model, "MediaGX"); 573 break; 574 case 0x50: 575 strcat(cpu_model, "6x86MX"); 576 break; 577 case 0xf0: 578 switch (cyrix_did & 0x0f) { 579 case 0x0d: 580 strcat(cpu_model, "Overdrive CPU"); 581 break; 582 case 0x0e: 583 strcpy(cpu_model, "Texas Instruments 486SXL"); 584 break; 585 case 0x0f: 586 strcat(cpu_model, "486SLC/DLC"); 587 break; 588 default: 589 strcat(cpu_model, "Unknown"); 590 break; 591 } 592 break; 593 default: 594 strcat(cpu_model, "Unknown"); 595 break; 596 } 597 break; 598 } 599 break; 600 case CPU_VENDOR_RISE: 601 strcpy(cpu_model, "Rise "); 602 switch (cpu_id & 0xff0) { 603 case 0x500: /* 6401 and 6441 (Kirin) */ 604 case 0x520: /* 6510 (Lynx) */ 605 strcat(cpu_model, "mP6"); 606 break; 607 default: 608 strcat(cpu_model, "Unknown"); 609 } 610 break; 611#endif 612 case CPU_VENDOR_CENTAUR: 613#ifdef __i386__ 614 switch (cpu_id & 0xff0) { 615 case 0x540: 616 strcpy(cpu_model, "IDT WinChip C6"); 617 break; 618 case 0x580: 619 strcpy(cpu_model, "IDT WinChip 2"); 620 break; 621 case 0x590: 622 strcpy(cpu_model, "IDT WinChip 3"); 623 break; 624 case 0x660: 625 strcpy(cpu_model, "VIA C3 Samuel"); 626 break; 627 case 0x670: 628 if (cpu_id & 0x8) 629 strcpy(cpu_model, "VIA C3 Ezra"); 630 else 631 strcpy(cpu_model, "VIA C3 Samuel 2"); 632 break; 633 case 0x680: 634 strcpy(cpu_model, "VIA C3 Ezra-T"); 635 break; 636 case 0x690: 637 strcpy(cpu_model, "VIA C3 Nehemiah"); 638 break; 639 case 0x6a0: 640 case 0x6d0: 641 strcpy(cpu_model, "VIA C7 Esther"); 642 break; 643 case 0x6f0: 644 strcpy(cpu_model, "VIA Nano"); 645 break; 646 default: 647 strcpy(cpu_model, "VIA/IDT Unknown"); 648 } 649#else 650 strcpy(cpu_model, "VIA "); 651 if ((cpu_id & 0xff0) == 0x6f0) 652 strcat(cpu_model, "Nano Processor"); 653 else 654 strcat(cpu_model, "Unknown"); 655#endif 656 break; 657#ifdef __i386__ 658 case CPU_VENDOR_IBM: 659 strcpy(cpu_model, "Blue Lightning CPU"); 660 break; 661 case CPU_VENDOR_NSC: 662 switch (cpu_id & 0xff0) { 663 case 0x540: 664 strcpy(cpu_model, "Geode SC1100"); 665 cpu = CPU_GEODE1100; 666 break; 667 default: 668 strcpy(cpu_model, "Geode/NSC unknown"); 669 break; 670 } 671 break; 672#endif 673 default: 674 strcat(cpu_model, "Unknown"); 675 break; 676 } 677 678 /* 679 * Replace cpu_model with cpu_brand minus leading spaces if 680 * we have one. 681 */ 682 brand = cpu_brand; 683 while (*brand == ' ') 684 ++brand; 685 if (*brand != '\0') 686 strcpy(cpu_model, brand); 687 688 printf("%s (", cpu_model); 689 if (tsc_freq != 0) { 690 hw_clockrate = (tsc_freq + 5000) / 1000000; 691 printf("%jd.%02d-MHz ", 692 (intmax_t)(tsc_freq + 4999) / 1000000, 693 (u_int)((tsc_freq + 4999) / 10000) % 100); 694 } 695#ifdef __i386__ 696 switch(cpu_class) { 697 case CPUCLASS_286: 698 printf("286"); 699 break; 700 case CPUCLASS_386: 701 printf("386"); 702 break; 703#if defined(I486_CPU) 704 case CPUCLASS_486: 705 printf("486"); 706 break; 707#endif 708#if defined(I586_CPU) 709 case CPUCLASS_586: 710 printf("586"); 711 break; 712#endif 713#if defined(I686_CPU) 714 case CPUCLASS_686: 715 printf("686"); 716 break; 717#endif 718 default: 719 printf("Unknown"); /* will panic below... */ 720 } 721#else 722 printf("K8"); 723#endif 724 printf("-class CPU)\n"); 725 if (*cpu_vendor) 726 printf(" Origin=\"%s\"", cpu_vendor); 727 if (cpu_id) 728 printf(" Id=0x%x", cpu_id); 729 730 if (cpu_vendor_id == CPU_VENDOR_INTEL || 731 cpu_vendor_id == CPU_VENDOR_AMD || 732 cpu_vendor_id == CPU_VENDOR_CENTAUR || 733#ifdef __i386__ 734 cpu_vendor_id == CPU_VENDOR_TRANSMETA || 735 cpu_vendor_id == CPU_VENDOR_RISE || 736 cpu_vendor_id == CPU_VENDOR_NSC || 737 (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) || 738#endif 739 0) { 740 printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id)); 741 printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id)); 742 printf(" Stepping=%u", cpu_id & CPUID_STEPPING); 743#ifdef __i386__ 744 if (cpu_vendor_id == CPU_VENDOR_CYRIX) 745 printf("\n DIR=0x%04x", cyrix_did); 746#endif 747 748 /* 749 * AMD CPUID Specification 750 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf 751 * 752 * Intel Processor Identification and CPUID Instruction 753 * http://www.intel.com/assets/pdf/appnote/241618.pdf 754 */ 755 if (cpu_high > 0) { 756 757 /* 758 * Here we should probably set up flags indicating 759 * whether or not various features are available. 760 * The interesting ones are probably VME, PSE, PAE, 761 * and PGE. The code already assumes without bothering 762 * to check that all CPUs >= Pentium have a TSC and 763 * MSRs. 764 */ 765 printf("\n Features=0x%b", cpu_feature, 766 "\020" 767 "\001FPU" /* Integral FPU */ 768 "\002VME" /* Extended VM86 mode support */ 769 "\003DE" /* Debugging Extensions (CR4.DE) */ 770 "\004PSE" /* 4MByte page tables */ 771 "\005TSC" /* Timestamp counter */ 772 "\006MSR" /* Machine specific registers */ 773 "\007PAE" /* Physical address extension */ 774 "\010MCE" /* Machine Check support */ 775 "\011CX8" /* CMPEXCH8 instruction */ 776 "\012APIC" /* SMP local APIC */ 777 "\013oldMTRR" /* Previous implementation of MTRR */ 778 "\014SEP" /* Fast System Call */ 779 "\015MTRR" /* Memory Type Range Registers */ 780 "\016PGE" /* PG_G (global bit) support */ 781 "\017MCA" /* Machine Check Architecture */ 782 "\020CMOV" /* CMOV instruction */ 783 "\021PAT" /* Page attributes table */ 784 "\022PSE36" /* 36 bit address space support */ 785 "\023PN" /* Processor Serial number */ 786 "\024CLFLUSH" /* Has the CLFLUSH instruction */ 787 "\025<b20>" 788 "\026DTS" /* Debug Trace Store */ 789 "\027ACPI" /* ACPI support */ 790 "\030MMX" /* MMX instructions */ 791 "\031FXSR" /* FXSAVE/FXRSTOR */ 792 "\032SSE" /* Streaming SIMD Extensions */ 793 "\033SSE2" /* Streaming SIMD Extensions #2 */ 794 "\034SS" /* Self snoop */ 795 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */ 796 "\036TM" /* Thermal Monitor clock slowdown */ 797 "\037IA64" /* CPU can execute IA64 instructions */ 798 "\040PBE" /* Pending Break Enable */ 799 ); 800 801 if (cpu_feature2 != 0) { 802 printf("\n Features2=0x%b", cpu_feature2, 803 "\020" 804 "\001SSE3" /* SSE3 */ 805 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */ 806 "\003DTES64" /* 64-bit Debug Trace */ 807 "\004MON" /* MONITOR/MWAIT Instructions */ 808 "\005DS_CPL" /* CPL Qualified Debug Store */ 809 "\006VMX" /* Virtual Machine Extensions */ 810 "\007SMX" /* Safer Mode Extensions */ 811 "\010EST" /* Enhanced SpeedStep */ 812 "\011TM2" /* Thermal Monitor 2 */ 813 "\012SSSE3" /* SSSE3 */ 814 "\013CNXT-ID" /* L1 context ID available */ 815 "\014SDBG" /* IA32 silicon debug */ 816 "\015FMA" /* Fused Multiply Add */ 817 "\016CX16" /* CMPXCHG16B Instruction */ 818 "\017xTPR" /* Send Task Priority Messages*/ 819 "\020PDCM" /* Perf/Debug Capability MSR */ 820 "\021<b16>" 821 "\022PCID" /* Process-context Identifiers*/ 822 "\023DCA" /* Direct Cache Access */ 823 "\024SSE4.1" /* SSE 4.1 */ 824 "\025SSE4.2" /* SSE 4.2 */ 825 "\026x2APIC" /* xAPIC Extensions */ 826 "\027MOVBE" /* MOVBE Instruction */ 827 "\030POPCNT" /* POPCNT Instruction */ 828 "\031TSCDLT" /* TSC-Deadline Timer */ 829 "\032AESNI" /* AES Crypto */ 830 "\033XSAVE" /* XSAVE/XRSTOR States */ 831 "\034OSXSAVE" /* OS-Enabled State Management*/ 832 "\035AVX" /* Advanced Vector Extensions */ 833 "\036F16C" /* Half-precision conversions */ 834 "\037RDRAND" /* RDRAND Instruction */ 835 "\040HV" /* Hypervisor */ 836 ); 837 } 838 839 if (amd_feature != 0) { 840 printf("\n AMD Features=0x%b", amd_feature, 841 "\020" /* in hex */ 842 "\001<s0>" /* Same */ 843 "\002<s1>" /* Same */ 844 "\003<s2>" /* Same */ 845 "\004<s3>" /* Same */ 846 "\005<s4>" /* Same */ 847 "\006<s5>" /* Same */ 848 "\007<s6>" /* Same */ 849 "\010<s7>" /* Same */ 850 "\011<s8>" /* Same */ 851 "\012<s9>" /* Same */ 852 "\013<b10>" /* Undefined */ 853 "\014SYSCALL" /* Have SYSCALL/SYSRET */ 854 "\015<s12>" /* Same */ 855 "\016<s13>" /* Same */ 856 "\017<s14>" /* Same */ 857 "\020<s15>" /* Same */ 858 "\021<s16>" /* Same */ 859 "\022<s17>" /* Same */ 860 "\023<b18>" /* Reserved, unknown */ 861 "\024MP" /* Multiprocessor Capable */ 862 "\025NX" /* Has EFER.NXE, NX */ 863 "\026<b21>" /* Undefined */ 864 "\027MMX+" /* AMD MMX Extensions */ 865 "\030<s23>" /* Same */ 866 "\031<s24>" /* Same */ 867 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */ 868 "\033Page1GB" /* 1-GB large page support */ 869 "\034RDTSCP" /* RDTSCP */ 870 "\035<b28>" /* Undefined */ 871 "\036LM" /* 64 bit long mode */ 872 "\0373DNow!+" /* AMD 3DNow! Extensions */ 873 "\0403DNow!" /* AMD 3DNow! */ 874 ); 875 } 876 877 if (amd_feature2 != 0) { 878 printf("\n AMD Features2=0x%b", amd_feature2, 879 "\020" 880 "\001LAHF" /* LAHF/SAHF in long mode */ 881 "\002CMP" /* CMP legacy */ 882 "\003SVM" /* Secure Virtual Mode */ 883 "\004ExtAPIC" /* Extended APIC register */ 884 "\005CR8" /* CR8 in legacy mode */ 885 "\006ABM" /* LZCNT instruction */ 886 "\007SSE4A" /* SSE4A */ 887 "\010MAS" /* Misaligned SSE mode */ 888 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ 889 "\012OSVW" /* OS visible workaround */ 890 "\013IBS" /* Instruction based sampling */ 891 "\014XOP" /* XOP extended instructions */ 892 "\015SKINIT" /* SKINIT/STGI */ 893 "\016WDT" /* Watchdog timer */ 894 "\017<b14>" 895 "\020LWP" /* Lightweight Profiling */ 896 "\021FMA4" /* 4-operand FMA instructions */ 897 "\022TCE" /* Translation Cache Extension */ 898 "\023<b18>" 899 "\024NodeId" /* NodeId MSR support */ 900 "\025<b20>" 901 "\026TBM" /* Trailing Bit Manipulation */ 902 "\027Topology" /* Topology Extensions */ 903 "\030PCXC" /* Core perf count */ 904 "\031PNXC" /* NB perf count */ 905 "\032<b25>" 906 "\033DBE" /* Data Breakpoint extension */ 907 "\034PTSC" /* Performance TSC */ 908 "\035PL2I" /* L2I perf count */ 909 "\036MWAITX" /* MONITORX/MWAITX instructions */ 910 "\037<b30>" 911 "\040<b31>" 912 ); 913 } 914 915 if (cpu_stdext_feature != 0) { 916 printf("\n Structured Extended Features=0x%b", 917 cpu_stdext_feature, 918 "\020" 919 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ 920 "\001FSGSBASE" 921 "\002TSCADJ" 922 "\003SGX" 923 /* Bit Manipulation Instructions */ 924 "\004BMI1" 925 /* Hardware Lock Elision */ 926 "\005HLE" 927 /* Advanced Vector Instructions 2 */ 928 "\006AVX2" 929 /* FDP_EXCPTN_ONLY */ 930 "\007FDPEXC" 931 /* Supervisor Mode Execution Prot. */ 932 "\010SMEP" 933 /* Bit Manipulation Instructions */ 934 "\011BMI2" 935 "\012ERMS" 936 /* Invalidate Processor Context ID */ 937 "\013INVPCID" 938 /* Restricted Transactional Memory */ 939 "\014RTM" 940 "\015PQM" 941 "\016NFPUSG" 942 /* Intel Memory Protection Extensions */ 943 "\017MPX" 944 "\020PQE" 945 /* AVX512 Foundation */ 946 "\021AVX512F" 947 "\022AVX512DQ" 948 /* Enhanced NRBG */ 949 "\023RDSEED" 950 /* ADCX + ADOX */ 951 "\024ADX" 952 /* Supervisor Mode Access Prevention */ 953 "\025SMAP" 954 "\026AVX512IFMA" 955 "\027PCOMMIT" 956 "\030CLFLUSHOPT" 957 "\031CLWB" 958 "\032PROCTRACE" 959 "\033AVX512PF" 960 "\034AVX512ER" 961 "\035AVX512CD" 962 "\036SHA" 963 "\037AVX512BW" 964 ); 965 } 966 967 if (cpu_stdext_feature2 != 0) { 968 printf("\n Structured Extended Features2=0x%b", 969 cpu_stdext_feature2, 970 "\020" 971 "\001PREFETCHWT1" 972 "\002AVX512VBMI" 973 "\003UMIP" 974 "\004PKU" 975 "\005OSPKE" 976 "\027RDPID" 977 "\037SGXLC" 978 ); 979 } 980 981 if ((cpu_feature2 & CPUID2_XSAVE) != 0) { 982 cpuid_count(0xd, 0x1, regs); 983 if (regs[0] != 0) { 984 printf("\n XSAVE Features=0x%b", 985 regs[0], 986 "\020" 987 "\001XSAVEOPT" 988 "\002XSAVEC" 989 "\003XINUSE" 990 "\004XSAVES"); 991 } 992 } 993 994 if (via_feature_rng != 0 || via_feature_xcrypt != 0) 995 print_via_padlock_info(); 996 997 if (cpu_feature2 & CPUID2_VMX) 998 print_vmx_info(); 999 1000 if (amd_feature2 & AMDID2_SVM) 1001 print_svm_info(); 1002 1003 if ((cpu_feature & CPUID_HTT) && 1004 cpu_vendor_id == CPU_VENDOR_AMD) 1005 cpu_feature &= ~CPUID_HTT; 1006 1007 /* 1008 * If this CPU supports P-state invariant TSC then 1009 * mention the capability. 1010 */ 1011 if (tsc_is_invariant) { 1012 printf("\n TSC: P-state invariant"); 1013 if (tsc_perf_stat) 1014 printf(", performance statistics"); 1015 } 1016 } 1017#ifdef __i386__ 1018 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 1019 printf(" DIR=0x%04x", cyrix_did); 1020 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12); 1021 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8); 1022#ifndef CYRIX_CACHE_REALLY_WORKS 1023 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700) 1024 printf("\n CPU cache: write-through mode"); 1025#endif 1026#endif 1027 } 1028 1029 /* Avoid ugly blank lines: only print newline when we have to. */ 1030 if (*cpu_vendor || cpu_id) 1031 printf("\n"); 1032 1033 if (bootverbose) { 1034 if (cpu_vendor_id == CPU_VENDOR_AMD) 1035 print_AMD_info(); 1036 else if (cpu_vendor_id == CPU_VENDOR_INTEL) 1037 print_INTEL_info(); 1038#ifdef __i386__ 1039 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA) 1040 print_transmeta_info(); 1041#endif 1042 } 1043 1044 print_hypervisor_info(); 1045} 1046 1047#ifdef __i386__ 1048void 1049panicifcpuunsupported(void) 1050{ 1051 1052#if !defined(lint) 1053#if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU) 1054#error This kernel is not configured for one of the supported CPUs 1055#endif 1056#else /* lint */ 1057#endif /* lint */ 1058 /* 1059 * Now that we have told the user what they have, 1060 * let them know if that machine type isn't configured. 1061 */ 1062 switch (cpu_class) { 1063 case CPUCLASS_286: /* a 286 should not make it this far, anyway */ 1064 case CPUCLASS_386: 1065#if !defined(I486_CPU) 1066 case CPUCLASS_486: 1067#endif 1068#if !defined(I586_CPU) 1069 case CPUCLASS_586: 1070#endif 1071#if !defined(I686_CPU) 1072 case CPUCLASS_686: 1073#endif 1074 panic("CPU class not configured"); 1075 default: 1076 break; 1077 } 1078} 1079 1080static volatile u_int trap_by_rdmsr; 1081 1082/* 1083 * Special exception 6 handler. 1084 * The rdmsr instruction generates invalid opcodes fault on 486-class 1085 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the 1086 * function identblue() when this handler is called. Stacked eip should 1087 * be advanced. 1088 */ 1089inthand_t bluetrap6; 1090#ifdef __GNUCLIKE_ASM 1091__asm 1092(" \n\ 1093 .text \n\ 1094 .p2align 2,0x90 \n\ 1095 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\ 1096" __XSTRING(CNAME(bluetrap6)) ": \n\ 1097 ss \n\ 1098 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 1099 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 1100 iret \n\ 1101"); 1102#endif 1103 1104/* 1105 * Special exception 13 handler. 1106 * Accessing non-existent MSR generates general protection fault. 1107 */ 1108inthand_t bluetrap13; 1109#ifdef __GNUCLIKE_ASM 1110__asm 1111(" \n\ 1112 .text \n\ 1113 .p2align 2,0x90 \n\ 1114 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\ 1115" __XSTRING(CNAME(bluetrap13)) ": \n\ 1116 ss \n\ 1117 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 1118 popl %eax /* discard error code */ \n\ 1119 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 1120 iret \n\ 1121"); 1122#endif 1123 1124/* 1125 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not 1126 * support cpuid instruction. This function should be called after 1127 * loading interrupt descriptor table register. 1128 * 1129 * I don't like this method that handles fault, but I couldn't get 1130 * information for any other methods. Does blue giant know? 1131 */ 1132static int 1133identblue(void) 1134{ 1135 1136 trap_by_rdmsr = 0; 1137 1138 /* 1139 * Cyrix 486-class CPU does not support rdmsr instruction. 1140 * The rdmsr instruction generates invalid opcode fault, and exception 1141 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The 1142 * bluetrap6() set the magic number to trap_by_rdmsr. 1143 */ 1144 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL, 1145 GSEL(GCODE_SEL, SEL_KPL)); 1146 1147 /* 1148 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU. 1149 * In this case, rdmsr generates general protection fault, and 1150 * exception will be trapped by bluetrap13(). 1151 */ 1152 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL, 1153 GSEL(GCODE_SEL, SEL_KPL)); 1154 1155 rdmsr(0x1002); /* Cyrix CPU generates fault. */ 1156 1157 if (trap_by_rdmsr == 0xa8c1d) 1158 return IDENTBLUE_CYRIX486; 1159 else if (trap_by_rdmsr == 0xa89c4) 1160 return IDENTBLUE_CYRIXM2; 1161 return IDENTBLUE_IBMCPU; 1162} 1163 1164 1165/* 1166 * identifycyrix() set lower 16 bits of cyrix_did as follows: 1167 * 1168 * F E D C B A 9 8 7 6 5 4 3 2 1 0 1169 * +-------+-------+---------------+ 1170 * | SID | RID | Device ID | 1171 * | (DIR 1) | (DIR 0) | 1172 * +-------+-------+---------------+ 1173 */ 1174static void 1175identifycyrix(void) 1176{ 1177 register_t saveintr; 1178 int ccr2_test = 0, dir_test = 0; 1179 u_char ccr2, ccr3; 1180 1181 saveintr = intr_disable(); 1182 1183 ccr2 = read_cyrix_reg(CCR2); 1184 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW); 1185 read_cyrix_reg(CCR2); 1186 if (read_cyrix_reg(CCR2) != ccr2) 1187 ccr2_test = 1; 1188 write_cyrix_reg(CCR2, ccr2); 1189 1190 ccr3 = read_cyrix_reg(CCR3); 1191 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3); 1192 read_cyrix_reg(CCR3); 1193 if (read_cyrix_reg(CCR3) != ccr3) 1194 dir_test = 1; /* CPU supports DIRs. */ 1195 write_cyrix_reg(CCR3, ccr3); 1196 1197 if (dir_test) { 1198 /* Device ID registers are available. */ 1199 cyrix_did = read_cyrix_reg(DIR1) << 8; 1200 cyrix_did += read_cyrix_reg(DIR0); 1201 } else if (ccr2_test) 1202 cyrix_did = 0x0010; /* 486S A-step */ 1203 else 1204 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */ 1205 1206 intr_restore(saveintr); 1207} 1208#endif 1209 1210/* Update TSC freq with the value indicated by the caller. */ 1211static void 1212tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status) 1213{ 1214 1215 /* If there was an error during the transition, don't do anything. */ 1216 if (status != 0) 1217 return; 1218 1219 /* Total setting for this level gives the new frequency in MHz. */ 1220 hw_clockrate = level->total_set.freq; 1221} 1222 1223static void 1224hook_tsc_freq(void *arg __unused) 1225{ 1226 1227 if (tsc_is_invariant) 1228 return; 1229 1230 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change, 1231 tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY); 1232} 1233 1234SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL); 1235 1236static const char *const vm_bnames[] = { 1237 "QEMU", /* QEMU */ 1238 "Plex86", /* Plex86 */ 1239 "Bochs", /* Bochs */ 1240 "Xen", /* Xen */ 1241 "BHYVE", /* bhyve */ 1242 "Seabios", /* KVM */ 1243 NULL 1244}; 1245 1246static const char *const vm_pnames[] = { 1247 "VMware Virtual Platform", /* VMWare VM */ 1248 "Virtual Machine", /* Microsoft VirtualPC */ 1249 "VirtualBox", /* Sun xVM VirtualBox */ 1250 "Parallels Virtual Platform", /* Parallels VM */ 1251 "KVM", /* KVM */ 1252 NULL 1253}; 1254 1255static void 1256identify_hypervisor(void) 1257{ 1258 u_int regs[4]; 1259 char *p; 1260 int i; 1261 1262 /* 1263 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1264 * http://lkml.org/lkml/2008/10/1/246 1265 * 1266 * KB1009458: Mechanisms to determine if software is running in 1267 * a VMware virtual machine 1268 * http://kb.vmware.com/kb/1009458 1269 */ 1270 if (cpu_feature2 & CPUID2_HV) { 1271 vm_guest = VM_GUEST_VM; 1272 do_cpuid(0x40000000, regs); 1273 if (regs[0] >= 0x40000000) { 1274 hv_high = regs[0]; 1275 ((u_int *)&hv_vendor)[0] = regs[1]; 1276 ((u_int *)&hv_vendor)[1] = regs[2]; 1277 ((u_int *)&hv_vendor)[2] = regs[3]; 1278 hv_vendor[12] = '\0'; 1279 if (strcmp(hv_vendor, "VMwareVMware") == 0) 1280 vm_guest = VM_GUEST_VMWARE; 1281 else if (strcmp(hv_vendor, "Microsoft Hv") == 0) 1282 vm_guest = VM_GUEST_HV; 1283 else if (strcmp(hv_vendor, "KVMKVMKVM") == 0) 1284 vm_guest = VM_GUEST_KVM; 1285 } 1286 return; 1287 } 1288 1289 /* 1290 * Examine SMBIOS strings for older hypervisors. 1291 */ 1292 p = kern_getenv("smbios.system.serial"); 1293 if (p != NULL) { 1294 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) { 1295 vmware_hvcall(VMW_HVCMD_GETVERSION, regs); 1296 if (regs[1] == VMW_HVMAGIC) { 1297 vm_guest = VM_GUEST_VMWARE; 1298 freeenv(p); 1299 return; 1300 } 1301 } 1302 freeenv(p); 1303 } 1304 1305 /* 1306 * XXX: Some of these entries may not be needed since they were 1307 * added to FreeBSD before the checks above. 1308 */ 1309 p = kern_getenv("smbios.bios.vendor"); 1310 if (p != NULL) { 1311 for (i = 0; vm_bnames[i] != NULL; i++) 1312 if (strcmp(p, vm_bnames[i]) == 0) { 1313 vm_guest = VM_GUEST_VM; 1314 freeenv(p); 1315 return; 1316 } 1317 freeenv(p); 1318 } 1319 p = kern_getenv("smbios.system.product"); 1320 if (p != NULL) { 1321 for (i = 0; vm_pnames[i] != NULL; i++) 1322 if (strcmp(p, vm_pnames[i]) == 0) { 1323 vm_guest = VM_GUEST_VM; 1324 freeenv(p); 1325 return; 1326 } 1327 freeenv(p); 1328 } 1329} 1330 1331bool 1332fix_cpuid(void) 1333{ 1334 uint64_t msr; 1335 1336 /* 1337 * Clear "Limit CPUID Maxval" bit and return true if the caller should 1338 * get the largest standard CPUID function number again if it is set 1339 * from BIOS. It is necessary for probing correct CPU topology later 1340 * and for the correct operation of the AVX-aware userspace. 1341 */ 1342 if (cpu_vendor_id == CPU_VENDOR_INTEL && 1343 ((CPUID_TO_FAMILY(cpu_id) == 0xf && 1344 CPUID_TO_MODEL(cpu_id) >= 0x3) || 1345 (CPUID_TO_FAMILY(cpu_id) == 0x6 && 1346 CPUID_TO_MODEL(cpu_id) >= 0xe))) { 1347 msr = rdmsr(MSR_IA32_MISC_ENABLE); 1348 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) { 1349 msr &= ~IA32_MISC_EN_LIMCPUID; 1350 wrmsr(MSR_IA32_MISC_ENABLE, msr); 1351 return (true); 1352 } 1353 } 1354 1355 /* 1356 * Re-enable AMD Topology Extension that could be disabled by BIOS 1357 * on some notebook processors. Without the extension it's really 1358 * hard to determine the correct CPU cache topology. 1359 * See BIOS and Kernel Developer���s Guide (BKDG) for AMD Family 15h 1360 * Models 60h-6Fh Processors, Publication # 50742. 1361 */ 1362 if (cpu_vendor_id == CPU_VENDOR_AMD && CPUID_TO_FAMILY(cpu_id) == 0x15) { 1363 msr = rdmsr(MSR_EXTFEATURES); 1364 if ((msr & ((uint64_t)1 << 54)) == 0) { 1365 msr |= (uint64_t)1 << 54; 1366 wrmsr(MSR_EXTFEATURES, msr); 1367 return (true); 1368 } 1369 } 1370 return (false); 1371} 1372 1373/* 1374 * Final stage of CPU identification. 1375 */ 1376#ifdef __i386__ 1377void 1378finishidentcpu(void) 1379#else 1380void 1381identify_cpu(void) 1382#endif 1383{ 1384 u_int regs[4], cpu_stdext_disable; 1385#ifdef __i386__ 1386 u_char ccr3; 1387#endif 1388 1389#ifdef __amd64__ 1390 do_cpuid(0, regs); 1391 cpu_high = regs[0]; 1392 ((u_int *)&cpu_vendor)[0] = regs[1]; 1393 ((u_int *)&cpu_vendor)[1] = regs[3]; 1394 ((u_int *)&cpu_vendor)[2] = regs[2]; 1395 cpu_vendor[12] = '\0'; 1396 1397 do_cpuid(1, regs); 1398 cpu_id = regs[0]; 1399 cpu_procinfo = regs[1]; 1400 cpu_feature = regs[3]; 1401 cpu_feature2 = regs[2]; 1402#endif 1403 1404 identify_hypervisor(); 1405 cpu_vendor_id = find_cpu_vendor_id(); 1406 1407 if (fix_cpuid()) { 1408 do_cpuid(0, regs); 1409 cpu_high = regs[0]; 1410 } 1411 1412 if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) { 1413 do_cpuid(5, regs); 1414 cpu_mon_mwait_flags = regs[2]; 1415 cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE; 1416 cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE; 1417 } 1418 1419 if (cpu_high >= 7) { 1420 cpuid_count(7, 0, regs); 1421 cpu_stdext_feature = regs[1]; 1422 1423 /* 1424 * Some hypervisors fail to filter out unsupported 1425 * extended features. For now, disable the 1426 * extensions, activation of which requires setting a 1427 * bit in CR4, and which VM monitors do not support. 1428 */ 1429 if (cpu_feature2 & CPUID2_HV) { 1430 cpu_stdext_disable = CPUID_STDEXT_FSGSBASE | 1431 CPUID_STDEXT_SMEP; 1432 } else 1433 cpu_stdext_disable = 0; 1434 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable); 1435 cpu_stdext_feature &= ~cpu_stdext_disable; 1436 cpu_stdext_feature2 = regs[2]; 1437 } 1438 1439#ifdef __i386__ 1440 if (cpu_high > 0 && 1441 (cpu_vendor_id == CPU_VENDOR_INTEL || 1442 cpu_vendor_id == CPU_VENDOR_AMD || 1443 cpu_vendor_id == CPU_VENDOR_TRANSMETA || 1444 cpu_vendor_id == CPU_VENDOR_CENTAUR || 1445 cpu_vendor_id == CPU_VENDOR_NSC)) { 1446 do_cpuid(0x80000000, regs); 1447 if (regs[0] >= 0x80000000) 1448 cpu_exthigh = regs[0]; 1449 } 1450#else 1451 if (cpu_vendor_id == CPU_VENDOR_INTEL || 1452 cpu_vendor_id == CPU_VENDOR_AMD || 1453 cpu_vendor_id == CPU_VENDOR_CENTAUR) { 1454 do_cpuid(0x80000000, regs); 1455 cpu_exthigh = regs[0]; 1456 } 1457#endif 1458 if (cpu_exthigh >= 0x80000001) { 1459 do_cpuid(0x80000001, regs); 1460 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); 1461 amd_feature2 = regs[2]; 1462 } 1463 if (cpu_exthigh >= 0x80000007) { 1464 do_cpuid(0x80000007, regs); 1465 amd_pminfo = regs[3]; 1466 } 1467 if (cpu_exthigh >= 0x80000008) { 1468 do_cpuid(0x80000008, regs); 1469 cpu_maxphyaddr = regs[0] & 0xff; 1470 cpu_procinfo2 = regs[2]; 1471 } else { 1472 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32; 1473 } 1474 1475#ifdef __i386__ 1476 if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 1477 if (cpu == CPU_486) { 1478 /* 1479 * These conditions are equivalent to: 1480 * - CPU does not support cpuid instruction. 1481 * - Cyrix/IBM CPU is detected. 1482 */ 1483 if (identblue() == IDENTBLUE_IBMCPU) { 1484 strcpy(cpu_vendor, "IBM"); 1485 cpu_vendor_id = CPU_VENDOR_IBM; 1486 cpu = CPU_BLUE; 1487 return; 1488 } 1489 } 1490 switch (cpu_id & 0xf00) { 1491 case 0x600: 1492 /* 1493 * Cyrix's datasheet does not describe DIRs. 1494 * Therefor, I assume it does not have them 1495 * and use the result of the cpuid instruction. 1496 * XXX they seem to have it for now at least. -Peter 1497 */ 1498 identifycyrix(); 1499 cpu = CPU_M2; 1500 break; 1501 default: 1502 identifycyrix(); 1503 /* 1504 * This routine contains a trick. 1505 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now. 1506 */ 1507 switch (cyrix_did & 0x00f0) { 1508 case 0x00: 1509 case 0xf0: 1510 cpu = CPU_486DLC; 1511 break; 1512 case 0x10: 1513 cpu = CPU_CY486DX; 1514 break; 1515 case 0x20: 1516 if ((cyrix_did & 0x000f) < 8) 1517 cpu = CPU_M1; 1518 else 1519 cpu = CPU_M1SC; 1520 break; 1521 case 0x30: 1522 cpu = CPU_M1; 1523 break; 1524 case 0x40: 1525 /* MediaGX CPU */ 1526 cpu = CPU_M1SC; 1527 break; 1528 default: 1529 /* M2 and later CPUs are treated as M2. */ 1530 cpu = CPU_M2; 1531 1532 /* 1533 * enable cpuid instruction. 1534 */ 1535 ccr3 = read_cyrix_reg(CCR3); 1536 write_cyrix_reg(CCR3, CCR3_MAPEN0); 1537 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID); 1538 write_cyrix_reg(CCR3, ccr3); 1539 1540 do_cpuid(0, regs); 1541 cpu_high = regs[0]; /* eax */ 1542 do_cpuid(1, regs); 1543 cpu_id = regs[0]; /* eax */ 1544 cpu_feature = regs[3]; /* edx */ 1545 break; 1546 } 1547 } 1548 } else if (cpu == CPU_486 && *cpu_vendor == '\0') { 1549 /* 1550 * There are BlueLightning CPUs that do not change 1551 * undefined flags by dividing 5 by 2. In this case, 1552 * the CPU identification routine in locore.s leaves 1553 * cpu_vendor null string and puts CPU_486 into the 1554 * cpu. 1555 */ 1556 if (identblue() == IDENTBLUE_IBMCPU) { 1557 strcpy(cpu_vendor, "IBM"); 1558 cpu_vendor_id = CPU_VENDOR_IBM; 1559 cpu = CPU_BLUE; 1560 return; 1561 } 1562 } 1563#endif 1564} 1565 1566static u_int 1567find_cpu_vendor_id(void) 1568{ 1569 int i; 1570 1571 for (i = 0; i < nitems(cpu_vendors); i++) 1572 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0) 1573 return (cpu_vendors[i].vendor_id); 1574 return (0); 1575} 1576 1577static void 1578print_AMD_assoc(int i) 1579{ 1580 if (i == 255) 1581 printf(", fully associative\n"); 1582 else 1583 printf(", %d-way associative\n", i); 1584} 1585 1586static void 1587print_AMD_l2_assoc(int i) 1588{ 1589 switch (i & 0x0f) { 1590 case 0: printf(", disabled/not present\n"); break; 1591 case 1: printf(", direct mapped\n"); break; 1592 case 2: printf(", 2-way associative\n"); break; 1593 case 4: printf(", 4-way associative\n"); break; 1594 case 6: printf(", 8-way associative\n"); break; 1595 case 8: printf(", 16-way associative\n"); break; 1596 case 15: printf(", fully associative\n"); break; 1597 default: printf(", reserved configuration\n"); break; 1598 } 1599} 1600 1601static void 1602print_AMD_info(void) 1603{ 1604#ifdef __i386__ 1605 uint64_t amd_whcr; 1606#endif 1607 u_int regs[4]; 1608 1609 if (cpu_exthigh >= 0x80000005) { 1610 do_cpuid(0x80000005, regs); 1611 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff); 1612 print_AMD_assoc(regs[0] >> 24); 1613 1614 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff); 1615 print_AMD_assoc((regs[0] >> 8) & 0xff); 1616 1617 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff); 1618 print_AMD_assoc(regs[1] >> 24); 1619 1620 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff); 1621 print_AMD_assoc((regs[1] >> 8) & 0xff); 1622 1623 printf("L1 data cache: %d kbytes", regs[2] >> 24); 1624 printf(", %d bytes/line", regs[2] & 0xff); 1625 printf(", %d lines/tag", (regs[2] >> 8) & 0xff); 1626 print_AMD_assoc((regs[2] >> 16) & 0xff); 1627 1628 printf("L1 instruction cache: %d kbytes", regs[3] >> 24); 1629 printf(", %d bytes/line", regs[3] & 0xff); 1630 printf(", %d lines/tag", (regs[3] >> 8) & 0xff); 1631 print_AMD_assoc((regs[3] >> 16) & 0xff); 1632 } 1633 1634 if (cpu_exthigh >= 0x80000006) { 1635 do_cpuid(0x80000006, regs); 1636 if ((regs[0] >> 16) != 0) { 1637 printf("L2 2MB data TLB: %d entries", 1638 (regs[0] >> 16) & 0xfff); 1639 print_AMD_l2_assoc(regs[0] >> 28); 1640 printf("L2 2MB instruction TLB: %d entries", 1641 regs[0] & 0xfff); 1642 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 1643 } else { 1644 printf("L2 2MB unified TLB: %d entries", 1645 regs[0] & 0xfff); 1646 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 1647 } 1648 if ((regs[1] >> 16) != 0) { 1649 printf("L2 4KB data TLB: %d entries", 1650 (regs[1] >> 16) & 0xfff); 1651 print_AMD_l2_assoc(regs[1] >> 28); 1652 1653 printf("L2 4KB instruction TLB: %d entries", 1654 (regs[1] >> 16) & 0xfff); 1655 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 1656 } else { 1657 printf("L2 4KB unified TLB: %d entries", 1658 (regs[1] >> 16) & 0xfff); 1659 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 1660 } 1661 printf("L2 unified cache: %d kbytes", regs[2] >> 16); 1662 printf(", %d bytes/line", regs[2] & 0xff); 1663 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); 1664 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f); 1665 } 1666 1667#ifdef __i386__ 1668 if (((cpu_id & 0xf00) == 0x500) 1669 && (((cpu_id & 0x0f0) > 0x80) 1670 || (((cpu_id & 0x0f0) == 0x80) 1671 && (cpu_id & 0x00f) > 0x07))) { 1672 /* K6-2(new core [Stepping 8-F]), K6-III or later */ 1673 amd_whcr = rdmsr(0xc0000082); 1674 if (!(amd_whcr & (0x3ff << 22))) { 1675 printf("Write Allocate Disable\n"); 1676 } else { 1677 printf("Write Allocate Enable Limit: %dM bytes\n", 1678 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4); 1679 printf("Write Allocate 15-16M bytes: %s\n", 1680 (amd_whcr & (1 << 16)) ? "Enable" : "Disable"); 1681 } 1682 } else if (((cpu_id & 0xf00) == 0x500) 1683 && ((cpu_id & 0x0f0) > 0x50)) { 1684 /* K6, K6-2(old core) */ 1685 amd_whcr = rdmsr(0xc0000082); 1686 if (!(amd_whcr & (0x7f << 1))) { 1687 printf("Write Allocate Disable\n"); 1688 } else { 1689 printf("Write Allocate Enable Limit: %dM bytes\n", 1690 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4); 1691 printf("Write Allocate 15-16M bytes: %s\n", 1692 (amd_whcr & 0x0001) ? "Enable" : "Disable"); 1693 printf("Hardware Write Allocate Control: %s\n", 1694 (amd_whcr & 0x0100) ? "Enable" : "Disable"); 1695 } 1696 } 1697#endif 1698 /* 1699 * Opteron Rev E shows a bug as in very rare occasions a read memory 1700 * barrier is not performed as expected if it is followed by a 1701 * non-atomic read-modify-write instruction. 1702 * As long as that bug pops up very rarely (intensive machine usage 1703 * on other operating systems generally generates one unexplainable 1704 * crash any 2 months) and as long as a model specific fix would be 1705 * impractical at this stage, print out a warning string if the broken 1706 * model and family are identified. 1707 */ 1708 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 && 1709 CPUID_TO_MODEL(cpu_id) <= 0x3f) 1710 printf("WARNING: This architecture revision has known SMP " 1711 "hardware bugs which may cause random instability\n"); 1712} 1713 1714static void 1715print_INTEL_info(void) 1716{ 1717 u_int regs[4]; 1718 u_int rounds, regnum; 1719 u_int nwaycode, nway; 1720 1721 if (cpu_high >= 2) { 1722 rounds = 0; 1723 do { 1724 do_cpuid(0x2, regs); 1725 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0) 1726 break; /* we have a buggy CPU */ 1727 1728 for (regnum = 0; regnum <= 3; ++regnum) { 1729 if (regs[regnum] & (1<<31)) 1730 continue; 1731 if (regnum != 0) 1732 print_INTEL_TLB(regs[regnum] & 0xff); 1733 print_INTEL_TLB((regs[regnum] >> 8) & 0xff); 1734 print_INTEL_TLB((regs[regnum] >> 16) & 0xff); 1735 print_INTEL_TLB((regs[regnum] >> 24) & 0xff); 1736 } 1737 } while (--rounds > 0); 1738 } 1739 1740 if (cpu_exthigh >= 0x80000006) { 1741 do_cpuid(0x80000006, regs); 1742 nwaycode = (regs[2] >> 12) & 0x0f; 1743 if (nwaycode >= 0x02 && nwaycode <= 0x08) 1744 nway = 1 << (nwaycode / 2); 1745 else 1746 nway = 0; 1747 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n", 1748 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff); 1749 } 1750} 1751 1752static void 1753print_INTEL_TLB(u_int data) 1754{ 1755 switch (data) { 1756 case 0x0: 1757 case 0x40: 1758 default: 1759 break; 1760 case 0x1: 1761 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n"); 1762 break; 1763 case 0x2: 1764 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n"); 1765 break; 1766 case 0x3: 1767 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n"); 1768 break; 1769 case 0x4: 1770 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n"); 1771 break; 1772 case 0x6: 1773 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n"); 1774 break; 1775 case 0x8: 1776 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n"); 1777 break; 1778 case 0x9: 1779 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n"); 1780 break; 1781 case 0xa: 1782 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n"); 1783 break; 1784 case 0xb: 1785 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n"); 1786 break; 1787 case 0xc: 1788 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n"); 1789 break; 1790 case 0xd: 1791 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size"); 1792 break; 1793 case 0xe: 1794 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n"); 1795 break; 1796 case 0x1d: 1797 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n"); 1798 break; 1799 case 0x21: 1800 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n"); 1801 break; 1802 case 0x22: 1803 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1804 break; 1805 case 0x23: 1806 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1807 break; 1808 case 0x24: 1809 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n"); 1810 break; 1811 case 0x25: 1812 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1813 break; 1814 case 0x29: 1815 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1816 break; 1817 case 0x2c: 1818 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n"); 1819 break; 1820 case 0x30: 1821 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n"); 1822 break; 1823 case 0x39: /* De-listed in SDM rev. 54 */ 1824 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1825 break; 1826 case 0x3b: /* De-listed in SDM rev. 54 */ 1827 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n"); 1828 break; 1829 case 0x3c: /* De-listed in SDM rev. 54 */ 1830 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1831 break; 1832 case 0x41: 1833 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n"); 1834 break; 1835 case 0x42: 1836 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n"); 1837 break; 1838 case 0x43: 1839 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n"); 1840 break; 1841 case 0x44: 1842 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n"); 1843 break; 1844 case 0x45: 1845 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n"); 1846 break; 1847 case 0x46: 1848 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n"); 1849 break; 1850 case 0x47: 1851 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n"); 1852 break; 1853 case 0x48: 1854 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n"); 1855 break; 1856 case 0x49: 1857 if (CPUID_TO_FAMILY(cpu_id) == 0xf && 1858 CPUID_TO_MODEL(cpu_id) == 0x6) 1859 printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n"); 1860 else 1861 printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size"); 1862 break; 1863 case 0x4a: 1864 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n"); 1865 break; 1866 case 0x4b: 1867 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n"); 1868 break; 1869 case 0x4c: 1870 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n"); 1871 break; 1872 case 0x4d: 1873 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n"); 1874 break; 1875 case 0x4e: 1876 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n"); 1877 break; 1878 case 0x4f: 1879 printf("Instruction TLB: 4 KByte pages, 32 entries\n"); 1880 break; 1881 case 0x50: 1882 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n"); 1883 break; 1884 case 0x51: 1885 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n"); 1886 break; 1887 case 0x52: 1888 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n"); 1889 break; 1890 case 0x55: 1891 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n"); 1892 break; 1893 case 0x56: 1894 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n"); 1895 break; 1896 case 0x57: 1897 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n"); 1898 break; 1899 case 0x59: 1900 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n"); 1901 break; 1902 case 0x5a: 1903 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n"); 1904 break; 1905 case 0x5b: 1906 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n"); 1907 break; 1908 case 0x5c: 1909 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n"); 1910 break; 1911 case 0x5d: 1912 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n"); 1913 break; 1914 case 0x60: 1915 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 1916 break; 1917 case 0x61: 1918 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n"); 1919 break; 1920 case 0x63: 1921 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n"); 1922 break; 1923 case 0x64: 1924 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n"); 1925 break; 1926 case 0x66: 1927 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1928 break; 1929 case 0x67: 1930 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1931 break; 1932 case 0x68: 1933 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n"); 1934 break; 1935 case 0x6a: 1936 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n"); 1937 break; 1938 case 0x6b: 1939 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n"); 1940 break; 1941 case 0x6c: 1942 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n"); 1943 break; 1944 case 0x6d: 1945 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n"); 1946 break; 1947 case 0x70: 1948 printf("Trace cache: 12K-uops, 8-way set associative\n"); 1949 break; 1950 case 0x71: 1951 printf("Trace cache: 16K-uops, 8-way set associative\n"); 1952 break; 1953 case 0x72: 1954 printf("Trace cache: 32K-uops, 8-way set associative\n"); 1955 break; 1956 case 0x76: 1957 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n"); 1958 break; 1959 case 0x78: 1960 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n"); 1961 break; 1962 case 0x79: 1963 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 1964 break; 1965 case 0x7a: 1966 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 1967 break; 1968 case 0x7b: 1969 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 1970 break; 1971 case 0x7c: 1972 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1973 break; 1974 case 0x7d: 1975 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n"); 1976 break; 1977 case 0x7f: 1978 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n"); 1979 break; 1980 case 0x80: 1981 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n"); 1982 break; 1983 case 0x82: 1984 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n"); 1985 break; 1986 case 0x83: 1987 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n"); 1988 break; 1989 case 0x84: 1990 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n"); 1991 break; 1992 case 0x85: 1993 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n"); 1994 break; 1995 case 0x86: 1996 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n"); 1997 break; 1998 case 0x87: 1999 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n"); 2000 break; 2001 case 0xa0: 2002 printf("DTLB: 4k pages, fully associative, 32 entries\n"); 2003 break; 2004 case 0xb0: 2005 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); 2006 break; 2007 case 0xb1: 2008 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n"); 2009 break; 2010 case 0xb2: 2011 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n"); 2012 break; 2013 case 0xb3: 2014 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); 2015 break; 2016 case 0xb4: 2017 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n"); 2018 break; 2019 case 0xb5: 2020 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n"); 2021 break; 2022 case 0xb6: 2023 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n"); 2024 break; 2025 case 0xba: 2026 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n"); 2027 break; 2028 case 0xc0: 2029 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n"); 2030 break; 2031 case 0xc1: 2032 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n"); 2033 break; 2034 case 0xc2: 2035 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n"); 2036 break; 2037 case 0xc3: 2038 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n"); 2039 break; 2040 case 0xc4: 2041 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n"); 2042 break; 2043 case 0xca: 2044 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n"); 2045 break; 2046 case 0xd0: 2047 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n"); 2048 break; 2049 case 0xd1: 2050 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n"); 2051 break; 2052 case 0xd2: 2053 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n"); 2054 break; 2055 case 0xd6: 2056 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n"); 2057 break; 2058 case 0xd7: 2059 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n"); 2060 break; 2061 case 0xd8: 2062 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n"); 2063 break; 2064 case 0xdc: 2065 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n"); 2066 break; 2067 case 0xdd: 2068 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n"); 2069 break; 2070 case 0xde: 2071 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n"); 2072 break; 2073 case 0xe2: 2074 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n"); 2075 break; 2076 case 0xe3: 2077 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n"); 2078 break; 2079 case 0xe4: 2080 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n"); 2081 break; 2082 case 0xea: 2083 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n"); 2084 break; 2085 case 0xeb: 2086 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n"); 2087 break; 2088 case 0xec: 2089 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n"); 2090 break; 2091 case 0xf0: 2092 printf("64-Byte prefetching\n"); 2093 break; 2094 case 0xf1: 2095 printf("128-Byte prefetching\n"); 2096 break; 2097 } 2098} 2099 2100static void 2101print_svm_info(void) 2102{ 2103 u_int features, regs[4]; 2104 uint64_t msr; 2105 int comma; 2106 2107 printf("\n SVM: "); 2108 do_cpuid(0x8000000A, regs); 2109 features = regs[3]; 2110 2111 msr = rdmsr(MSR_VM_CR); 2112 if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS) 2113 printf("(disabled in BIOS) "); 2114 2115 if (!bootverbose) { 2116 comma = 0; 2117 if (features & (1 << 0)) { 2118 printf("%sNP", comma ? "," : ""); 2119 comma = 1; 2120 } 2121 if (features & (1 << 3)) { 2122 printf("%sNRIP", comma ? "," : ""); 2123 comma = 1; 2124 } 2125 if (features & (1 << 5)) { 2126 printf("%sVClean", comma ? "," : ""); 2127 comma = 1; 2128 } 2129 if (features & (1 << 6)) { 2130 printf("%sAFlush", comma ? "," : ""); 2131 comma = 1; 2132 } 2133 if (features & (1 << 7)) { 2134 printf("%sDAssist", comma ? "," : ""); 2135 comma = 1; 2136 } 2137 printf("%sNAsids=%d", comma ? "," : "", regs[1]); 2138 return; 2139 } 2140 2141 printf("Features=0x%b", features, 2142 "\020" 2143 "\001NP" /* Nested paging */ 2144 "\002LbrVirt" /* LBR virtualization */ 2145 "\003SVML" /* SVM lock */ 2146 "\004NRIPS" /* NRIP save */ 2147 "\005TscRateMsr" /* MSR based TSC rate control */ 2148 "\006VmcbClean" /* VMCB clean bits */ 2149 "\007FlushByAsid" /* Flush by ASID */ 2150 "\010DecodeAssist" /* Decode assist */ 2151 "\011<b8>" 2152 "\012<b9>" 2153 "\013PauseFilter" /* PAUSE intercept filter */ 2154 "\014<b11>" 2155 "\015PauseFilterThreshold" /* PAUSE filter threshold */ 2156 "\016AVIC" /* virtual interrupt controller */ 2157 ); 2158 printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]); 2159} 2160 2161#ifdef __i386__ 2162static void 2163print_transmeta_info(void) 2164{ 2165 u_int regs[4], nreg = 0; 2166 2167 do_cpuid(0x80860000, regs); 2168 nreg = regs[0]; 2169 if (nreg >= 0x80860001) { 2170 do_cpuid(0x80860001, regs); 2171 printf(" Processor revision %u.%u.%u.%u\n", 2172 (regs[1] >> 24) & 0xff, 2173 (regs[1] >> 16) & 0xff, 2174 (regs[1] >> 8) & 0xff, 2175 regs[1] & 0xff); 2176 } 2177 if (nreg >= 0x80860002) { 2178 do_cpuid(0x80860002, regs); 2179 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n", 2180 (regs[1] >> 24) & 0xff, 2181 (regs[1] >> 16) & 0xff, 2182 (regs[1] >> 8) & 0xff, 2183 regs[1] & 0xff, 2184 regs[2]); 2185 } 2186 if (nreg >= 0x80860006) { 2187 char info[65]; 2188 do_cpuid(0x80860003, (u_int*) &info[0]); 2189 do_cpuid(0x80860004, (u_int*) &info[16]); 2190 do_cpuid(0x80860005, (u_int*) &info[32]); 2191 do_cpuid(0x80860006, (u_int*) &info[48]); 2192 info[64] = 0; 2193 printf(" %s\n", info); 2194 } 2195} 2196#endif 2197 2198static void 2199print_via_padlock_info(void) 2200{ 2201 u_int regs[4]; 2202 2203 do_cpuid(0xc0000001, regs); 2204 printf("\n VIA Padlock Features=0x%b", regs[3], 2205 "\020" 2206 "\003RNG" /* RNG */ 2207 "\007AES" /* ACE */ 2208 "\011AES-CTR" /* ACE2 */ 2209 "\013SHA1,SHA256" /* PHE */ 2210 "\015RSA" /* PMM */ 2211 ); 2212} 2213 2214static uint32_t 2215vmx_settable(uint64_t basic, int msr, int true_msr) 2216{ 2217 uint64_t val; 2218 2219 if (basic & (1ULL << 55)) 2220 val = rdmsr(true_msr); 2221 else 2222 val = rdmsr(msr); 2223 2224 /* Just report the controls that can be set to 1. */ 2225 return (val >> 32); 2226} 2227 2228static void 2229print_vmx_info(void) 2230{ 2231 uint64_t basic, msr; 2232 uint32_t entry, exit, mask, pin, proc, proc2; 2233 int comma; 2234 2235 printf("\n VT-x: "); 2236 msr = rdmsr(MSR_IA32_FEATURE_CONTROL); 2237 if (!(msr & IA32_FEATURE_CONTROL_VMX_EN)) 2238 printf("(disabled in BIOS) "); 2239 basic = rdmsr(MSR_VMX_BASIC); 2240 pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS, 2241 MSR_VMX_TRUE_PINBASED_CTLS); 2242 proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS, 2243 MSR_VMX_TRUE_PROCBASED_CTLS); 2244 if (proc & PROCBASED_SECONDARY_CONTROLS) 2245 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2, 2246 MSR_VMX_PROCBASED_CTLS2); 2247 else 2248 proc2 = 0; 2249 exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS); 2250 entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS); 2251 2252 if (!bootverbose) { 2253 comma = 0; 2254 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT && 2255 entry & VM_ENTRY_LOAD_PAT) { 2256 printf("%sPAT", comma ? "," : ""); 2257 comma = 1; 2258 } 2259 if (proc & PROCBASED_HLT_EXITING) { 2260 printf("%sHLT", comma ? "," : ""); 2261 comma = 1; 2262 } 2263 if (proc & PROCBASED_MTF) { 2264 printf("%sMTF", comma ? "," : ""); 2265 comma = 1; 2266 } 2267 if (proc & PROCBASED_PAUSE_EXITING) { 2268 printf("%sPAUSE", comma ? "," : ""); 2269 comma = 1; 2270 } 2271 if (proc2 & PROCBASED2_ENABLE_EPT) { 2272 printf("%sEPT", comma ? "," : ""); 2273 comma = 1; 2274 } 2275 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) { 2276 printf("%sUG", comma ? "," : ""); 2277 comma = 1; 2278 } 2279 if (proc2 & PROCBASED2_ENABLE_VPID) { 2280 printf("%sVPID", comma ? "," : ""); 2281 comma = 1; 2282 } 2283 if (proc & PROCBASED_USE_TPR_SHADOW && 2284 proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES && 2285 proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE && 2286 proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION && 2287 proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) { 2288 printf("%sVID", comma ? "," : ""); 2289 comma = 1; 2290 if (pin & PINBASED_POSTED_INTERRUPT) 2291 printf(",PostIntr"); 2292 } 2293 return; 2294 } 2295 2296 mask = basic >> 32; 2297 printf("Basic Features=0x%b", mask, 2298 "\020" 2299 "\02132PA" /* 32-bit physical addresses */ 2300 "\022SMM" /* SMM dual-monitor */ 2301 "\027INS/OUTS" /* VM-exit info for INS and OUTS */ 2302 "\030TRUE" /* TRUE_CTLS MSRs */ 2303 ); 2304 printf("\n Pin-Based Controls=0x%b", pin, 2305 "\020" 2306 "\001ExtINT" /* External-interrupt exiting */ 2307 "\004NMI" /* NMI exiting */ 2308 "\006VNMI" /* Virtual NMIs */ 2309 "\007PreTmr" /* Activate VMX-preemption timer */ 2310 "\010PostIntr" /* Process posted interrupts */ 2311 ); 2312 printf("\n Primary Processor Controls=0x%b", proc, 2313 "\020" 2314 "\003INTWIN" /* Interrupt-window exiting */ 2315 "\004TSCOff" /* Use TSC offsetting */ 2316 "\010HLT" /* HLT exiting */ 2317 "\012INVLPG" /* INVLPG exiting */ 2318 "\013MWAIT" /* MWAIT exiting */ 2319 "\014RDPMC" /* RDPMC exiting */ 2320 "\015RDTSC" /* RDTSC exiting */ 2321 "\020CR3-LD" /* CR3-load exiting */ 2322 "\021CR3-ST" /* CR3-store exiting */ 2323 "\024CR8-LD" /* CR8-load exiting */ 2324 "\025CR8-ST" /* CR8-store exiting */ 2325 "\026TPR" /* Use TPR shadow */ 2326 "\027NMIWIN" /* NMI-window exiting */ 2327 "\030MOV-DR" /* MOV-DR exiting */ 2328 "\031IO" /* Unconditional I/O exiting */ 2329 "\032IOmap" /* Use I/O bitmaps */ 2330 "\034MTF" /* Monitor trap flag */ 2331 "\035MSRmap" /* Use MSR bitmaps */ 2332 "\036MONITOR" /* MONITOR exiting */ 2333 "\037PAUSE" /* PAUSE exiting */ 2334 ); 2335 if (proc & PROCBASED_SECONDARY_CONTROLS) 2336 printf("\n Secondary Processor Controls=0x%b", proc2, 2337 "\020" 2338 "\001APIC" /* Virtualize APIC accesses */ 2339 "\002EPT" /* Enable EPT */ 2340 "\003DT" /* Descriptor-table exiting */ 2341 "\004RDTSCP" /* Enable RDTSCP */ 2342 "\005x2APIC" /* Virtualize x2APIC mode */ 2343 "\006VPID" /* Enable VPID */ 2344 "\007WBINVD" /* WBINVD exiting */ 2345 "\010UG" /* Unrestricted guest */ 2346 "\011APIC-reg" /* APIC-register virtualization */ 2347 "\012VID" /* Virtual-interrupt delivery */ 2348 "\013PAUSE-loop" /* PAUSE-loop exiting */ 2349 "\014RDRAND" /* RDRAND exiting */ 2350 "\015INVPCID" /* Enable INVPCID */ 2351 "\016VMFUNC" /* Enable VM functions */ 2352 "\017VMCS" /* VMCS shadowing */ 2353 "\020EPT#VE" /* EPT-violation #VE */ 2354 "\021XSAVES" /* Enable XSAVES/XRSTORS */ 2355 ); 2356 printf("\n Exit Controls=0x%b", mask, 2357 "\020" 2358 "\003DR" /* Save debug controls */ 2359 /* Ignore Host address-space size */ 2360 "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */ 2361 "\020AckInt" /* Acknowledge interrupt on exit */ 2362 "\023PAT-SV" /* Save MSR_PAT */ 2363 "\024PAT-LD" /* Load MSR_PAT */ 2364 "\025EFER-SV" /* Save MSR_EFER */ 2365 "\026EFER-LD" /* Load MSR_EFER */ 2366 "\027PTMR-SV" /* Save VMX-preemption timer value */ 2367 ); 2368 printf("\n Entry Controls=0x%b", mask, 2369 "\020" 2370 "\003DR" /* Save debug controls */ 2371 /* Ignore IA-32e mode guest */ 2372 /* Ignore Entry to SMM */ 2373 /* Ignore Deactivate dual-monitor treatment */ 2374 "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */ 2375 "\017PAT" /* Load MSR_PAT */ 2376 "\020EFER" /* Load MSR_EFER */ 2377 ); 2378 if (proc & PROCBASED_SECONDARY_CONTROLS && 2379 (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) { 2380 msr = rdmsr(MSR_VMX_EPT_VPID_CAP); 2381 mask = msr; 2382 printf("\n EPT Features=0x%b", mask, 2383 "\020" 2384 "\001XO" /* Execute-only translations */ 2385 "\007PW4" /* Page-walk length of 4 */ 2386 "\011UC" /* EPT paging-structure mem can be UC */ 2387 "\017WB" /* EPT paging-structure mem can be WB */ 2388 "\0212M" /* EPT PDE can map a 2-Mbyte page */ 2389 "\0221G" /* EPT PDPTE can map a 1-Gbyte page */ 2390 "\025INVEPT" /* INVEPT is supported */ 2391 "\026AD" /* Accessed and dirty flags for EPT */ 2392 "\032single" /* INVEPT single-context type */ 2393 "\033all" /* INVEPT all-context type */ 2394 ); 2395 mask = msr >> 32; 2396 printf("\n VPID Features=0x%b", mask, 2397 "\020" 2398 "\001INVVPID" /* INVVPID is supported */ 2399 "\011individual" /* INVVPID individual-address type */ 2400 "\012single" /* INVVPID single-context type */ 2401 "\013all" /* INVVPID all-context type */ 2402 /* INVVPID single-context-retaining-globals type */ 2403 "\014single-globals" 2404 ); 2405 } 2406} 2407 2408static void 2409print_hypervisor_info(void) 2410{ 2411 2412 if (*hv_vendor) 2413 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor); 2414} 2415