identcpu.c revision 304429
1/*- 2 * Copyright (c) 1992 Terrence R. Lambert. 3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 4 * Copyright (c) 1997 KATO Takenori. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp 39 */ 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: stable/11/sys/x86/x86/identcpu.c 304429 2016-08-18 14:10:36Z badger $"); 43 44#include "opt_cpu.h" 45 46#include <sys/param.h> 47#include <sys/bus.h> 48#include <sys/cpu.h> 49#include <sys/eventhandler.h> 50#include <sys/limits.h> 51#include <sys/systm.h> 52#include <sys/kernel.h> 53#include <sys/sysctl.h> 54#include <sys/power.h> 55 56#include <machine/asmacros.h> 57#include <machine/clock.h> 58#include <machine/cputypes.h> 59#include <machine/frame.h> 60#include <machine/intr_machdep.h> 61#include <machine/md_var.h> 62#include <machine/segments.h> 63#include <machine/specialreg.h> 64 65#include <amd64/vmm/intel/vmx_controls.h> 66#include <x86/isa/icu.h> 67#include <x86/vmware.h> 68 69#ifdef __i386__ 70#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 71#define CPU_ENABLE_SSE 72#endif 73 74#define IDENTBLUE_CYRIX486 0 75#define IDENTBLUE_IBMCPU 1 76#define IDENTBLUE_CYRIXM2 2 77 78static void identifycyrix(void); 79static void print_transmeta_info(void); 80#endif 81static u_int find_cpu_vendor_id(void); 82static void print_AMD_info(void); 83static void print_INTEL_info(void); 84static void print_INTEL_TLB(u_int data); 85static void print_hypervisor_info(void); 86static void print_svm_info(void); 87static void print_via_padlock_info(void); 88static void print_vmx_info(void); 89 90int cpu; /* Are we 386, 386sx, 486, etc? */ 91int cpu_class; 92u_int cpu_feature; /* Feature flags */ 93u_int cpu_feature2; /* Feature flags */ 94u_int amd_feature; /* AMD feature flags */ 95u_int amd_feature2; /* AMD feature flags */ 96u_int amd_pminfo; /* AMD advanced power management info */ 97u_int via_feature_rng; /* VIA RNG features */ 98u_int via_feature_xcrypt; /* VIA ACE features */ 99u_int cpu_high; /* Highest arg to CPUID */ 100u_int cpu_exthigh; /* Highest arg to extended CPUID */ 101u_int cpu_id; /* Stepping ID */ 102u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */ 103u_int cpu_procinfo2; /* Multicore info */ 104char cpu_vendor[20]; /* CPU Origin code */ 105u_int cpu_vendor_id; /* CPU vendor ID */ 106#if defined(__amd64__) || defined(CPU_ENABLE_SSE) 107u_int cpu_fxsr; /* SSE enabled */ 108u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */ 109#endif 110u_int cpu_clflush_line_size = 32; 111u_int cpu_stdext_feature; 112u_int cpu_stdext_feature2; 113u_int cpu_max_ext_state_size; 114u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */ 115u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */ 116u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */ 117u_int cpu_maxphyaddr; /* Max phys addr width in bits */ 118char machine[] = MACHINE; 119 120SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD, 121 &via_feature_rng, 0, 122 "VIA RNG feature available in CPU"); 123SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD, 124 &via_feature_xcrypt, 0, 125 "VIA xcrypt feature available in CPU"); 126 127#ifdef __amd64__ 128#ifdef SCTL_MASK32 129extern int adaptive_machine_arch; 130#endif 131 132static int 133sysctl_hw_machine(SYSCTL_HANDLER_ARGS) 134{ 135#ifdef SCTL_MASK32 136 static const char machine32[] = "i386"; 137#endif 138 int error; 139 140#ifdef SCTL_MASK32 141 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch) 142 error = SYSCTL_OUT(req, machine32, sizeof(machine32)); 143 else 144#endif 145 error = SYSCTL_OUT(req, machine, sizeof(machine)); 146 return (error); 147 148} 149SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD, 150 NULL, 0, sysctl_hw_machine, "A", "Machine class"); 151#else 152SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 153 machine, 0, "Machine class"); 154#endif 155 156static char cpu_model[128]; 157SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 158 cpu_model, 0, "Machine model"); 159 160static int hw_clockrate; 161SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 162 &hw_clockrate, 0, "CPU instruction clock rate"); 163 164u_int hv_high; 165char hv_vendor[16]; 166SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD, hv_vendor, 0, 167 "Hypervisor vendor"); 168 169static eventhandler_tag tsc_post_tag; 170 171static char cpu_brand[48]; 172 173#ifdef __i386__ 174#define MAX_BRAND_INDEX 8 175 176static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = { 177 NULL, /* No brand */ 178 "Intel Celeron", 179 "Intel Pentium III", 180 "Intel Pentium III Xeon", 181 NULL, 182 NULL, 183 NULL, 184 NULL, 185 "Intel Pentium 4" 186}; 187#endif 188 189static struct { 190 char *cpu_name; 191 int cpu_class; 192} cpus[] = { 193#ifdef __i386__ 194 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */ 195 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */ 196 { "i386DX", CPUCLASS_386 }, /* CPU_386 */ 197 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */ 198 { "i486DX", CPUCLASS_486 }, /* CPU_486 */ 199 { "Pentium", CPUCLASS_586 }, /* CPU_586 */ 200 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */ 201 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */ 202 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */ 203 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */ 204 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */ 205 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */ 206 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */ 207 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */ 208 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */ 209 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */ 210 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */ 211#else 212 { "Clawhammer", CPUCLASS_K8 }, /* CPU_CLAWHAMMER */ 213 { "Sledgehammer", CPUCLASS_K8 }, /* CPU_SLEDGEHAMMER */ 214#endif 215}; 216 217static struct { 218 char *vendor; 219 u_int vendor_id; 220} cpu_vendors[] = { 221 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */ 222 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */ 223 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */ 224#ifdef __i386__ 225 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */ 226 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */ 227 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */ 228 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */ 229 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */ 230 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */ 231 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */ 232#if 0 233 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */ 234 { "TransmetaCPU", CPU_VENDOR_TRANSMETA }, 235#endif 236#endif 237}; 238 239void 240printcpuinfo(void) 241{ 242 u_int regs[4], i; 243 char *brand; 244 245 cpu_class = cpus[cpu].cpu_class; 246 printf("CPU: "); 247 strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model)); 248 249 /* Check for extended CPUID information and a processor name. */ 250 if (cpu_exthigh >= 0x80000004) { 251 brand = cpu_brand; 252 for (i = 0x80000002; i < 0x80000005; i++) { 253 do_cpuid(i, regs); 254 memcpy(brand, regs, sizeof(regs)); 255 brand += sizeof(regs); 256 } 257 } 258 259 switch (cpu_vendor_id) { 260 case CPU_VENDOR_INTEL: 261#ifdef __i386__ 262 if ((cpu_id & 0xf00) > 0x300) { 263 u_int brand_index; 264 265 cpu_model[0] = '\0'; 266 267 switch (cpu_id & 0x3000) { 268 case 0x1000: 269 strcpy(cpu_model, "Overdrive "); 270 break; 271 case 0x2000: 272 strcpy(cpu_model, "Dual "); 273 break; 274 } 275 276 switch (cpu_id & 0xf00) { 277 case 0x400: 278 strcat(cpu_model, "i486 "); 279 /* Check the particular flavor of 486 */ 280 switch (cpu_id & 0xf0) { 281 case 0x00: 282 case 0x10: 283 strcat(cpu_model, "DX"); 284 break; 285 case 0x20: 286 strcat(cpu_model, "SX"); 287 break; 288 case 0x30: 289 strcat(cpu_model, "DX2"); 290 break; 291 case 0x40: 292 strcat(cpu_model, "SL"); 293 break; 294 case 0x50: 295 strcat(cpu_model, "SX2"); 296 break; 297 case 0x70: 298 strcat(cpu_model, 299 "DX2 Write-Back Enhanced"); 300 break; 301 case 0x80: 302 strcat(cpu_model, "DX4"); 303 break; 304 } 305 break; 306 case 0x500: 307 /* Check the particular flavor of 586 */ 308 strcat(cpu_model, "Pentium"); 309 switch (cpu_id & 0xf0) { 310 case 0x00: 311 strcat(cpu_model, " A-step"); 312 break; 313 case 0x10: 314 strcat(cpu_model, "/P5"); 315 break; 316 case 0x20: 317 strcat(cpu_model, "/P54C"); 318 break; 319 case 0x30: 320 strcat(cpu_model, "/P24T"); 321 break; 322 case 0x40: 323 strcat(cpu_model, "/P55C"); 324 break; 325 case 0x70: 326 strcat(cpu_model, "/P54C"); 327 break; 328 case 0x80: 329 strcat(cpu_model, "/P55C (quarter-micron)"); 330 break; 331 default: 332 /* nothing */ 333 break; 334 } 335#if defined(I586_CPU) && !defined(NO_F00F_HACK) 336 /* 337 * XXX - If/when Intel fixes the bug, this 338 * should also check the version of the 339 * CPU, not just that it's a Pentium. 340 */ 341 has_f00f_bug = 1; 342#endif 343 break; 344 case 0x600: 345 /* Check the particular flavor of 686 */ 346 switch (cpu_id & 0xf0) { 347 case 0x00: 348 strcat(cpu_model, "Pentium Pro A-step"); 349 break; 350 case 0x10: 351 strcat(cpu_model, "Pentium Pro"); 352 break; 353 case 0x30: 354 case 0x50: 355 case 0x60: 356 strcat(cpu_model, 357 "Pentium II/Pentium II Xeon/Celeron"); 358 cpu = CPU_PII; 359 break; 360 case 0x70: 361 case 0x80: 362 case 0xa0: 363 case 0xb0: 364 strcat(cpu_model, 365 "Pentium III/Pentium III Xeon/Celeron"); 366 cpu = CPU_PIII; 367 break; 368 default: 369 strcat(cpu_model, "Unknown 80686"); 370 break; 371 } 372 break; 373 case 0xf00: 374 strcat(cpu_model, "Pentium 4"); 375 cpu = CPU_P4; 376 break; 377 default: 378 strcat(cpu_model, "unknown"); 379 break; 380 } 381 382 /* 383 * If we didn't get a brand name from the extended 384 * CPUID, try to look it up in the brand table. 385 */ 386 if (cpu_high > 0 && *cpu_brand == '\0') { 387 brand_index = cpu_procinfo & CPUID_BRAND_INDEX; 388 if (brand_index <= MAX_BRAND_INDEX && 389 cpu_brandtable[brand_index] != NULL) 390 strcpy(cpu_brand, 391 cpu_brandtable[brand_index]); 392 } 393 } 394#else 395 /* Please make up your mind folks! */ 396 strcat(cpu_model, "EM64T"); 397#endif 398 break; 399 case CPU_VENDOR_AMD: 400 /* 401 * Values taken from AMD Processor Recognition 402 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf 403 * (also describes ``Features'' encodings. 404 */ 405 strcpy(cpu_model, "AMD "); 406#ifdef __i386__ 407 switch (cpu_id & 0xFF0) { 408 case 0x410: 409 strcat(cpu_model, "Standard Am486DX"); 410 break; 411 case 0x430: 412 strcat(cpu_model, "Enhanced Am486DX2 Write-Through"); 413 break; 414 case 0x470: 415 strcat(cpu_model, "Enhanced Am486DX2 Write-Back"); 416 break; 417 case 0x480: 418 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through"); 419 break; 420 case 0x490: 421 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back"); 422 break; 423 case 0x4E0: 424 strcat(cpu_model, "Am5x86 Write-Through"); 425 break; 426 case 0x4F0: 427 strcat(cpu_model, "Am5x86 Write-Back"); 428 break; 429 case 0x500: 430 strcat(cpu_model, "K5 model 0"); 431 break; 432 case 0x510: 433 strcat(cpu_model, "K5 model 1"); 434 break; 435 case 0x520: 436 strcat(cpu_model, "K5 PR166 (model 2)"); 437 break; 438 case 0x530: 439 strcat(cpu_model, "K5 PR200 (model 3)"); 440 break; 441 case 0x560: 442 strcat(cpu_model, "K6"); 443 break; 444 case 0x570: 445 strcat(cpu_model, "K6 266 (model 1)"); 446 break; 447 case 0x580: 448 strcat(cpu_model, "K6-2"); 449 break; 450 case 0x590: 451 strcat(cpu_model, "K6-III"); 452 break; 453 case 0x5a0: 454 strcat(cpu_model, "Geode LX"); 455 break; 456 default: 457 strcat(cpu_model, "Unknown"); 458 break; 459 } 460#else 461 if ((cpu_id & 0xf00) == 0xf00) 462 strcat(cpu_model, "AMD64 Processor"); 463 else 464 strcat(cpu_model, "Unknown"); 465#endif 466 break; 467#ifdef __i386__ 468 case CPU_VENDOR_CYRIX: 469 strcpy(cpu_model, "Cyrix "); 470 switch (cpu_id & 0xff0) { 471 case 0x440: 472 strcat(cpu_model, "MediaGX"); 473 break; 474 case 0x520: 475 strcat(cpu_model, "6x86"); 476 break; 477 case 0x540: 478 cpu_class = CPUCLASS_586; 479 strcat(cpu_model, "GXm"); 480 break; 481 case 0x600: 482 strcat(cpu_model, "6x86MX"); 483 break; 484 default: 485 /* 486 * Even though CPU supports the cpuid 487 * instruction, it can be disabled. 488 * Therefore, this routine supports all Cyrix 489 * CPUs. 490 */ 491 switch (cyrix_did & 0xf0) { 492 case 0x00: 493 switch (cyrix_did & 0x0f) { 494 case 0x00: 495 strcat(cpu_model, "486SLC"); 496 break; 497 case 0x01: 498 strcat(cpu_model, "486DLC"); 499 break; 500 case 0x02: 501 strcat(cpu_model, "486SLC2"); 502 break; 503 case 0x03: 504 strcat(cpu_model, "486DLC2"); 505 break; 506 case 0x04: 507 strcat(cpu_model, "486SRx"); 508 break; 509 case 0x05: 510 strcat(cpu_model, "486DRx"); 511 break; 512 case 0x06: 513 strcat(cpu_model, "486SRx2"); 514 break; 515 case 0x07: 516 strcat(cpu_model, "486DRx2"); 517 break; 518 case 0x08: 519 strcat(cpu_model, "486SRu"); 520 break; 521 case 0x09: 522 strcat(cpu_model, "486DRu"); 523 break; 524 case 0x0a: 525 strcat(cpu_model, "486SRu2"); 526 break; 527 case 0x0b: 528 strcat(cpu_model, "486DRu2"); 529 break; 530 default: 531 strcat(cpu_model, "Unknown"); 532 break; 533 } 534 break; 535 case 0x10: 536 switch (cyrix_did & 0x0f) { 537 case 0x00: 538 strcat(cpu_model, "486S"); 539 break; 540 case 0x01: 541 strcat(cpu_model, "486S2"); 542 break; 543 case 0x02: 544 strcat(cpu_model, "486Se"); 545 break; 546 case 0x03: 547 strcat(cpu_model, "486S2e"); 548 break; 549 case 0x0a: 550 strcat(cpu_model, "486DX"); 551 break; 552 case 0x0b: 553 strcat(cpu_model, "486DX2"); 554 break; 555 case 0x0f: 556 strcat(cpu_model, "486DX4"); 557 break; 558 default: 559 strcat(cpu_model, "Unknown"); 560 break; 561 } 562 break; 563 case 0x20: 564 if ((cyrix_did & 0x0f) < 8) 565 strcat(cpu_model, "6x86"); /* Where did you get it? */ 566 else 567 strcat(cpu_model, "5x86"); 568 break; 569 case 0x30: 570 strcat(cpu_model, "6x86"); 571 break; 572 case 0x40: 573 if ((cyrix_did & 0xf000) == 0x3000) { 574 cpu_class = CPUCLASS_586; 575 strcat(cpu_model, "GXm"); 576 } else 577 strcat(cpu_model, "MediaGX"); 578 break; 579 case 0x50: 580 strcat(cpu_model, "6x86MX"); 581 break; 582 case 0xf0: 583 switch (cyrix_did & 0x0f) { 584 case 0x0d: 585 strcat(cpu_model, "Overdrive CPU"); 586 break; 587 case 0x0e: 588 strcpy(cpu_model, "Texas Instruments 486SXL"); 589 break; 590 case 0x0f: 591 strcat(cpu_model, "486SLC/DLC"); 592 break; 593 default: 594 strcat(cpu_model, "Unknown"); 595 break; 596 } 597 break; 598 default: 599 strcat(cpu_model, "Unknown"); 600 break; 601 } 602 break; 603 } 604 break; 605 case CPU_VENDOR_RISE: 606 strcpy(cpu_model, "Rise "); 607 switch (cpu_id & 0xff0) { 608 case 0x500: /* 6401 and 6441 (Kirin) */ 609 case 0x520: /* 6510 (Lynx) */ 610 strcat(cpu_model, "mP6"); 611 break; 612 default: 613 strcat(cpu_model, "Unknown"); 614 } 615 break; 616#endif 617 case CPU_VENDOR_CENTAUR: 618#ifdef __i386__ 619 switch (cpu_id & 0xff0) { 620 case 0x540: 621 strcpy(cpu_model, "IDT WinChip C6"); 622 break; 623 case 0x580: 624 strcpy(cpu_model, "IDT WinChip 2"); 625 break; 626 case 0x590: 627 strcpy(cpu_model, "IDT WinChip 3"); 628 break; 629 case 0x660: 630 strcpy(cpu_model, "VIA C3 Samuel"); 631 break; 632 case 0x670: 633 if (cpu_id & 0x8) 634 strcpy(cpu_model, "VIA C3 Ezra"); 635 else 636 strcpy(cpu_model, "VIA C3 Samuel 2"); 637 break; 638 case 0x680: 639 strcpy(cpu_model, "VIA C3 Ezra-T"); 640 break; 641 case 0x690: 642 strcpy(cpu_model, "VIA C3 Nehemiah"); 643 break; 644 case 0x6a0: 645 case 0x6d0: 646 strcpy(cpu_model, "VIA C7 Esther"); 647 break; 648 case 0x6f0: 649 strcpy(cpu_model, "VIA Nano"); 650 break; 651 default: 652 strcpy(cpu_model, "VIA/IDT Unknown"); 653 } 654#else 655 strcpy(cpu_model, "VIA "); 656 if ((cpu_id & 0xff0) == 0x6f0) 657 strcat(cpu_model, "Nano Processor"); 658 else 659 strcat(cpu_model, "Unknown"); 660#endif 661 break; 662#ifdef __i386__ 663 case CPU_VENDOR_IBM: 664 strcpy(cpu_model, "Blue Lightning CPU"); 665 break; 666 case CPU_VENDOR_NSC: 667 switch (cpu_id & 0xff0) { 668 case 0x540: 669 strcpy(cpu_model, "Geode SC1100"); 670 cpu = CPU_GEODE1100; 671 break; 672 default: 673 strcpy(cpu_model, "Geode/NSC unknown"); 674 break; 675 } 676 break; 677#endif 678 default: 679 strcat(cpu_model, "Unknown"); 680 break; 681 } 682 683 /* 684 * Replace cpu_model with cpu_brand minus leading spaces if 685 * we have one. 686 */ 687 brand = cpu_brand; 688 while (*brand == ' ') 689 ++brand; 690 if (*brand != '\0') 691 strcpy(cpu_model, brand); 692 693 printf("%s (", cpu_model); 694 if (tsc_freq != 0) { 695 hw_clockrate = (tsc_freq + 5000) / 1000000; 696 printf("%jd.%02d-MHz ", 697 (intmax_t)(tsc_freq + 4999) / 1000000, 698 (u_int)((tsc_freq + 4999) / 10000) % 100); 699 } 700 switch(cpu_class) { 701#ifdef __i386__ 702 case CPUCLASS_286: 703 printf("286"); 704 break; 705 case CPUCLASS_386: 706 printf("386"); 707 break; 708#if defined(I486_CPU) 709 case CPUCLASS_486: 710 printf("486"); 711 break; 712#endif 713#if defined(I586_CPU) 714 case CPUCLASS_586: 715 printf("586"); 716 break; 717#endif 718#if defined(I686_CPU) 719 case CPUCLASS_686: 720 printf("686"); 721 break; 722#endif 723#else 724 case CPUCLASS_K8: 725 printf("K8"); 726 break; 727#endif 728 default: 729 printf("Unknown"); /* will panic below... */ 730 } 731 printf("-class CPU)\n"); 732 if (*cpu_vendor) 733 printf(" Origin=\"%s\"", cpu_vendor); 734 if (cpu_id) 735 printf(" Id=0x%x", cpu_id); 736 737 if (cpu_vendor_id == CPU_VENDOR_INTEL || 738 cpu_vendor_id == CPU_VENDOR_AMD || 739 cpu_vendor_id == CPU_VENDOR_CENTAUR || 740#ifdef __i386__ 741 cpu_vendor_id == CPU_VENDOR_TRANSMETA || 742 cpu_vendor_id == CPU_VENDOR_RISE || 743 cpu_vendor_id == CPU_VENDOR_NSC || 744 (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) || 745#endif 746 0) { 747 printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id)); 748 printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id)); 749 printf(" Stepping=%u", cpu_id & CPUID_STEPPING); 750#ifdef __i386__ 751 if (cpu_vendor_id == CPU_VENDOR_CYRIX) 752 printf("\n DIR=0x%04x", cyrix_did); 753#endif 754 755 /* 756 * AMD CPUID Specification 757 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf 758 * 759 * Intel Processor Identification and CPUID Instruction 760 * http://www.intel.com/assets/pdf/appnote/241618.pdf 761 */ 762 if (cpu_high > 0) { 763 764 /* 765 * Here we should probably set up flags indicating 766 * whether or not various features are available. 767 * The interesting ones are probably VME, PSE, PAE, 768 * and PGE. The code already assumes without bothering 769 * to check that all CPUs >= Pentium have a TSC and 770 * MSRs. 771 */ 772 printf("\n Features=0x%b", cpu_feature, 773 "\020" 774 "\001FPU" /* Integral FPU */ 775 "\002VME" /* Extended VM86 mode support */ 776 "\003DE" /* Debugging Extensions (CR4.DE) */ 777 "\004PSE" /* 4MByte page tables */ 778 "\005TSC" /* Timestamp counter */ 779 "\006MSR" /* Machine specific registers */ 780 "\007PAE" /* Physical address extension */ 781 "\010MCE" /* Machine Check support */ 782 "\011CX8" /* CMPEXCH8 instruction */ 783 "\012APIC" /* SMP local APIC */ 784 "\013oldMTRR" /* Previous implementation of MTRR */ 785 "\014SEP" /* Fast System Call */ 786 "\015MTRR" /* Memory Type Range Registers */ 787 "\016PGE" /* PG_G (global bit) support */ 788 "\017MCA" /* Machine Check Architecture */ 789 "\020CMOV" /* CMOV instruction */ 790 "\021PAT" /* Page attributes table */ 791 "\022PSE36" /* 36 bit address space support */ 792 "\023PN" /* Processor Serial number */ 793 "\024CLFLUSH" /* Has the CLFLUSH instruction */ 794 "\025<b20>" 795 "\026DTS" /* Debug Trace Store */ 796 "\027ACPI" /* ACPI support */ 797 "\030MMX" /* MMX instructions */ 798 "\031FXSR" /* FXSAVE/FXRSTOR */ 799 "\032SSE" /* Streaming SIMD Extensions */ 800 "\033SSE2" /* Streaming SIMD Extensions #2 */ 801 "\034SS" /* Self snoop */ 802 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */ 803 "\036TM" /* Thermal Monitor clock slowdown */ 804 "\037IA64" /* CPU can execute IA64 instructions */ 805 "\040PBE" /* Pending Break Enable */ 806 ); 807 808 if (cpu_feature2 != 0) { 809 printf("\n Features2=0x%b", cpu_feature2, 810 "\020" 811 "\001SSE3" /* SSE3 */ 812 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */ 813 "\003DTES64" /* 64-bit Debug Trace */ 814 "\004MON" /* MONITOR/MWAIT Instructions */ 815 "\005DS_CPL" /* CPL Qualified Debug Store */ 816 "\006VMX" /* Virtual Machine Extensions */ 817 "\007SMX" /* Safer Mode Extensions */ 818 "\010EST" /* Enhanced SpeedStep */ 819 "\011TM2" /* Thermal Monitor 2 */ 820 "\012SSSE3" /* SSSE3 */ 821 "\013CNXT-ID" /* L1 context ID available */ 822 "\014SDBG" /* IA32 silicon debug */ 823 "\015FMA" /* Fused Multiply Add */ 824 "\016CX16" /* CMPXCHG16B Instruction */ 825 "\017xTPR" /* Send Task Priority Messages*/ 826 "\020PDCM" /* Perf/Debug Capability MSR */ 827 "\021<b16>" 828 "\022PCID" /* Process-context Identifiers*/ 829 "\023DCA" /* Direct Cache Access */ 830 "\024SSE4.1" /* SSE 4.1 */ 831 "\025SSE4.2" /* SSE 4.2 */ 832 "\026x2APIC" /* xAPIC Extensions */ 833 "\027MOVBE" /* MOVBE Instruction */ 834 "\030POPCNT" /* POPCNT Instruction */ 835 "\031TSCDLT" /* TSC-Deadline Timer */ 836 "\032AESNI" /* AES Crypto */ 837 "\033XSAVE" /* XSAVE/XRSTOR States */ 838 "\034OSXSAVE" /* OS-Enabled State Management*/ 839 "\035AVX" /* Advanced Vector Extensions */ 840 "\036F16C" /* Half-precision conversions */ 841 "\037RDRAND" /* RDRAND Instruction */ 842 "\040HV" /* Hypervisor */ 843 ); 844 } 845 846 if (amd_feature != 0) { 847 printf("\n AMD Features=0x%b", amd_feature, 848 "\020" /* in hex */ 849 "\001<s0>" /* Same */ 850 "\002<s1>" /* Same */ 851 "\003<s2>" /* Same */ 852 "\004<s3>" /* Same */ 853 "\005<s4>" /* Same */ 854 "\006<s5>" /* Same */ 855 "\007<s6>" /* Same */ 856 "\010<s7>" /* Same */ 857 "\011<s8>" /* Same */ 858 "\012<s9>" /* Same */ 859 "\013<b10>" /* Undefined */ 860 "\014SYSCALL" /* Have SYSCALL/SYSRET */ 861 "\015<s12>" /* Same */ 862 "\016<s13>" /* Same */ 863 "\017<s14>" /* Same */ 864 "\020<s15>" /* Same */ 865 "\021<s16>" /* Same */ 866 "\022<s17>" /* Same */ 867 "\023<b18>" /* Reserved, unknown */ 868 "\024MP" /* Multiprocessor Capable */ 869 "\025NX" /* Has EFER.NXE, NX */ 870 "\026<b21>" /* Undefined */ 871 "\027MMX+" /* AMD MMX Extensions */ 872 "\030<s23>" /* Same */ 873 "\031<s24>" /* Same */ 874 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */ 875 "\033Page1GB" /* 1-GB large page support */ 876 "\034RDTSCP" /* RDTSCP */ 877 "\035<b28>" /* Undefined */ 878 "\036LM" /* 64 bit long mode */ 879 "\0373DNow!+" /* AMD 3DNow! Extensions */ 880 "\0403DNow!" /* AMD 3DNow! */ 881 ); 882 } 883 884 if (amd_feature2 != 0) { 885 printf("\n AMD Features2=0x%b", amd_feature2, 886 "\020" 887 "\001LAHF" /* LAHF/SAHF in long mode */ 888 "\002CMP" /* CMP legacy */ 889 "\003SVM" /* Secure Virtual Mode */ 890 "\004ExtAPIC" /* Extended APIC register */ 891 "\005CR8" /* CR8 in legacy mode */ 892 "\006ABM" /* LZCNT instruction */ 893 "\007SSE4A" /* SSE4A */ 894 "\010MAS" /* Misaligned SSE mode */ 895 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ 896 "\012OSVW" /* OS visible workaround */ 897 "\013IBS" /* Instruction based sampling */ 898 "\014XOP" /* XOP extended instructions */ 899 "\015SKINIT" /* SKINIT/STGI */ 900 "\016WDT" /* Watchdog timer */ 901 "\017<b14>" 902 "\020LWP" /* Lightweight Profiling */ 903 "\021FMA4" /* 4-operand FMA instructions */ 904 "\022TCE" /* Translation Cache Extension */ 905 "\023<b18>" 906 "\024NodeId" /* NodeId MSR support */ 907 "\025<b20>" 908 "\026TBM" /* Trailing Bit Manipulation */ 909 "\027Topology" /* Topology Extensions */ 910 "\030PCXC" /* Core perf count */ 911 "\031PNXC" /* NB perf count */ 912 "\032<b25>" 913 "\033DBE" /* Data Breakpoint extension */ 914 "\034PTSC" /* Performance TSC */ 915 "\035PL2I" /* L2I perf count */ 916 "\036<b29>" 917 "\037<b30>" 918 "\040<b31>" 919 ); 920 } 921 922 if (cpu_stdext_feature != 0) { 923 printf("\n Structured Extended Features=0x%b", 924 cpu_stdext_feature, 925 "\020" 926 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ 927 "\001FSGSBASE" 928 "\002TSCADJ" 929 "\003SGX" 930 /* Bit Manipulation Instructions */ 931 "\004BMI1" 932 /* Hardware Lock Elision */ 933 "\005HLE" 934 /* Advanced Vector Instructions 2 */ 935 "\006AVX2" 936 /* FDP_EXCPTN_ONLY */ 937 "\007FDPEXC" 938 /* Supervisor Mode Execution Prot. */ 939 "\010SMEP" 940 /* Bit Manipulation Instructions */ 941 "\011BMI2" 942 "\012ERMS" 943 /* Invalidate Processor Context ID */ 944 "\013INVPCID" 945 /* Restricted Transactional Memory */ 946 "\014RTM" 947 "\015PQM" 948 "\016NFPUSG" 949 /* Intel Memory Protection Extensions */ 950 "\017MPX" 951 "\020PQE" 952 /* AVX512 Foundation */ 953 "\021AVX512F" 954 "\022AVX512DQ" 955 /* Enhanced NRBG */ 956 "\023RDSEED" 957 /* ADCX + ADOX */ 958 "\024ADX" 959 /* Supervisor Mode Access Prevention */ 960 "\025SMAP" 961 "\026AVX512IFMA" 962 "\027PCOMMIT" 963 "\030CLFLUSHOPT" 964 "\031CLWB" 965 "\032PROCTRACE" 966 "\033AVX512PF" 967 "\034AVX512ER" 968 "\035AVX512CD" 969 "\036SHA" 970 "\037AVX512BW" 971 ); 972 } 973 974 if (cpu_stdext_feature2 != 0) { 975 printf("\n Structured Extended Features2=0x%b", 976 cpu_stdext_feature2, 977 "\020" 978 "\001PREFETCHWT1" 979 "\002AVX512VBMI" 980 "\003UMIP" 981 "\004PKU" 982 "\005OSPKE" 983 "\027RDPID" 984 "\037SGXLC" 985 ); 986 } 987 988 if ((cpu_feature2 & CPUID2_XSAVE) != 0) { 989 cpuid_count(0xd, 0x1, regs); 990 if (regs[0] != 0) { 991 printf("\n XSAVE Features=0x%b", 992 regs[0], 993 "\020" 994 "\001XSAVEOPT" 995 "\002XSAVEC" 996 "\003XINUSE" 997 "\004XSAVES"); 998 } 999 } 1000 1001 if (via_feature_rng != 0 || via_feature_xcrypt != 0) 1002 print_via_padlock_info(); 1003 1004 if (cpu_feature2 & CPUID2_VMX) 1005 print_vmx_info(); 1006 1007 if (amd_feature2 & AMDID2_SVM) 1008 print_svm_info(); 1009 1010 if ((cpu_feature & CPUID_HTT) && 1011 cpu_vendor_id == CPU_VENDOR_AMD) 1012 cpu_feature &= ~CPUID_HTT; 1013 1014 /* 1015 * If this CPU supports P-state invariant TSC then 1016 * mention the capability. 1017 */ 1018 if (tsc_is_invariant) { 1019 printf("\n TSC: P-state invariant"); 1020 if (tsc_perf_stat) 1021 printf(", performance statistics"); 1022 } 1023 } 1024#ifdef __i386__ 1025 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 1026 printf(" DIR=0x%04x", cyrix_did); 1027 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12); 1028 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8); 1029#ifndef CYRIX_CACHE_REALLY_WORKS 1030 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700) 1031 printf("\n CPU cache: write-through mode"); 1032#endif 1033#endif 1034 } 1035 1036 /* Avoid ugly blank lines: only print newline when we have to. */ 1037 if (*cpu_vendor || cpu_id) 1038 printf("\n"); 1039 1040 if (bootverbose) { 1041 if (cpu_vendor_id == CPU_VENDOR_AMD) 1042 print_AMD_info(); 1043 else if (cpu_vendor_id == CPU_VENDOR_INTEL) 1044 print_INTEL_info(); 1045#ifdef __i386__ 1046 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA) 1047 print_transmeta_info(); 1048#endif 1049 } 1050 1051 print_hypervisor_info(); 1052} 1053 1054void 1055panicifcpuunsupported(void) 1056{ 1057 1058#ifdef __i386__ 1059#if !defined(lint) 1060#if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU) 1061#error This kernel is not configured for one of the supported CPUs 1062#endif 1063#else /* lint */ 1064#endif /* lint */ 1065#else /* __amd64__ */ 1066#ifndef HAMMER 1067#error "You need to specify a cpu type" 1068#endif 1069#endif 1070 /* 1071 * Now that we have told the user what they have, 1072 * let them know if that machine type isn't configured. 1073 */ 1074 switch (cpu_class) { 1075#ifdef __i386__ 1076 case CPUCLASS_286: /* a 286 should not make it this far, anyway */ 1077 case CPUCLASS_386: 1078#if !defined(I486_CPU) 1079 case CPUCLASS_486: 1080#endif 1081#if !defined(I586_CPU) 1082 case CPUCLASS_586: 1083#endif 1084#if !defined(I686_CPU) 1085 case CPUCLASS_686: 1086#endif 1087#else /* __amd64__ */ 1088 case CPUCLASS_X86: 1089#ifndef HAMMER 1090 case CPUCLASS_K8: 1091#endif 1092#endif 1093 panic("CPU class not configured"); 1094 default: 1095 break; 1096 } 1097} 1098 1099#ifdef __i386__ 1100static volatile u_int trap_by_rdmsr; 1101 1102/* 1103 * Special exception 6 handler. 1104 * The rdmsr instruction generates invalid opcodes fault on 486-class 1105 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the 1106 * function identblue() when this handler is called. Stacked eip should 1107 * be advanced. 1108 */ 1109inthand_t bluetrap6; 1110#ifdef __GNUCLIKE_ASM 1111__asm 1112(" \n\ 1113 .text \n\ 1114 .p2align 2,0x90 \n\ 1115 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\ 1116" __XSTRING(CNAME(bluetrap6)) ": \n\ 1117 ss \n\ 1118 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 1119 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 1120 iret \n\ 1121"); 1122#endif 1123 1124/* 1125 * Special exception 13 handler. 1126 * Accessing non-existent MSR generates general protection fault. 1127 */ 1128inthand_t bluetrap13; 1129#ifdef __GNUCLIKE_ASM 1130__asm 1131(" \n\ 1132 .text \n\ 1133 .p2align 2,0x90 \n\ 1134 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\ 1135" __XSTRING(CNAME(bluetrap13)) ": \n\ 1136 ss \n\ 1137 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 1138 popl %eax /* discard error code */ \n\ 1139 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 1140 iret \n\ 1141"); 1142#endif 1143 1144/* 1145 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not 1146 * support cpuid instruction. This function should be called after 1147 * loading interrupt descriptor table register. 1148 * 1149 * I don't like this method that handles fault, but I couldn't get 1150 * information for any other methods. Does blue giant know? 1151 */ 1152static int 1153identblue(void) 1154{ 1155 1156 trap_by_rdmsr = 0; 1157 1158 /* 1159 * Cyrix 486-class CPU does not support rdmsr instruction. 1160 * The rdmsr instruction generates invalid opcode fault, and exception 1161 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The 1162 * bluetrap6() set the magic number to trap_by_rdmsr. 1163 */ 1164 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL, 1165 GSEL(GCODE_SEL, SEL_KPL)); 1166 1167 /* 1168 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU. 1169 * In this case, rdmsr generates general protection fault, and 1170 * exception will be trapped by bluetrap13(). 1171 */ 1172 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL, 1173 GSEL(GCODE_SEL, SEL_KPL)); 1174 1175 rdmsr(0x1002); /* Cyrix CPU generates fault. */ 1176 1177 if (trap_by_rdmsr == 0xa8c1d) 1178 return IDENTBLUE_CYRIX486; 1179 else if (trap_by_rdmsr == 0xa89c4) 1180 return IDENTBLUE_CYRIXM2; 1181 return IDENTBLUE_IBMCPU; 1182} 1183 1184 1185/* 1186 * identifycyrix() set lower 16 bits of cyrix_did as follows: 1187 * 1188 * F E D C B A 9 8 7 6 5 4 3 2 1 0 1189 * +-------+-------+---------------+ 1190 * | SID | RID | Device ID | 1191 * | (DIR 1) | (DIR 0) | 1192 * +-------+-------+---------------+ 1193 */ 1194static void 1195identifycyrix(void) 1196{ 1197 register_t saveintr; 1198 int ccr2_test = 0, dir_test = 0; 1199 u_char ccr2, ccr3; 1200 1201 saveintr = intr_disable(); 1202 1203 ccr2 = read_cyrix_reg(CCR2); 1204 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW); 1205 read_cyrix_reg(CCR2); 1206 if (read_cyrix_reg(CCR2) != ccr2) 1207 ccr2_test = 1; 1208 write_cyrix_reg(CCR2, ccr2); 1209 1210 ccr3 = read_cyrix_reg(CCR3); 1211 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3); 1212 read_cyrix_reg(CCR3); 1213 if (read_cyrix_reg(CCR3) != ccr3) 1214 dir_test = 1; /* CPU supports DIRs. */ 1215 write_cyrix_reg(CCR3, ccr3); 1216 1217 if (dir_test) { 1218 /* Device ID registers are available. */ 1219 cyrix_did = read_cyrix_reg(DIR1) << 8; 1220 cyrix_did += read_cyrix_reg(DIR0); 1221 } else if (ccr2_test) 1222 cyrix_did = 0x0010; /* 486S A-step */ 1223 else 1224 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */ 1225 1226 intr_restore(saveintr); 1227} 1228#endif 1229 1230/* Update TSC freq with the value indicated by the caller. */ 1231static void 1232tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status) 1233{ 1234 1235 /* If there was an error during the transition, don't do anything. */ 1236 if (status != 0) 1237 return; 1238 1239 /* Total setting for this level gives the new frequency in MHz. */ 1240 hw_clockrate = level->total_set.freq; 1241} 1242 1243static void 1244hook_tsc_freq(void *arg __unused) 1245{ 1246 1247 if (tsc_is_invariant) 1248 return; 1249 1250 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change, 1251 tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY); 1252} 1253 1254SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL); 1255 1256static const char *const vm_bnames[] = { 1257 "QEMU", /* QEMU */ 1258 "Plex86", /* Plex86 */ 1259 "Bochs", /* Bochs */ 1260 "Xen", /* Xen */ 1261 "BHYVE", /* bhyve */ 1262 "Seabios", /* KVM */ 1263 NULL 1264}; 1265 1266static const char *const vm_pnames[] = { 1267 "VMware Virtual Platform", /* VMWare VM */ 1268 "Virtual Machine", /* Microsoft VirtualPC */ 1269 "VirtualBox", /* Sun xVM VirtualBox */ 1270 "Parallels Virtual Platform", /* Parallels VM */ 1271 "KVM", /* KVM */ 1272 NULL 1273}; 1274 1275static void 1276identify_hypervisor(void) 1277{ 1278 u_int regs[4]; 1279 char *p; 1280 int i; 1281 1282 /* 1283 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1284 * http://lkml.org/lkml/2008/10/1/246 1285 * 1286 * KB1009458: Mechanisms to determine if software is running in 1287 * a VMware virtual machine 1288 * http://kb.vmware.com/kb/1009458 1289 */ 1290 if (cpu_feature2 & CPUID2_HV) { 1291 vm_guest = VM_GUEST_VM; 1292 do_cpuid(0x40000000, regs); 1293 if (regs[0] >= 0x40000000) { 1294 hv_high = regs[0]; 1295 ((u_int *)&hv_vendor)[0] = regs[1]; 1296 ((u_int *)&hv_vendor)[1] = regs[2]; 1297 ((u_int *)&hv_vendor)[2] = regs[3]; 1298 hv_vendor[12] = '\0'; 1299 if (strcmp(hv_vendor, "VMwareVMware") == 0) 1300 vm_guest = VM_GUEST_VMWARE; 1301 else if (strcmp(hv_vendor, "Microsoft Hv") == 0) 1302 vm_guest = VM_GUEST_HV; 1303 else if (strcmp(hv_vendor, "KVMKVMKVM") == 0) 1304 vm_guest = VM_GUEST_KVM; 1305 } 1306 return; 1307 } 1308 1309 /* 1310 * Examine SMBIOS strings for older hypervisors. 1311 */ 1312 p = kern_getenv("smbios.system.serial"); 1313 if (p != NULL) { 1314 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) { 1315 vmware_hvcall(VMW_HVCMD_GETVERSION, regs); 1316 if (regs[1] == VMW_HVMAGIC) { 1317 vm_guest = VM_GUEST_VMWARE; 1318 freeenv(p); 1319 return; 1320 } 1321 } 1322 freeenv(p); 1323 } 1324 1325 /* 1326 * XXX: Some of these entries may not be needed since they were 1327 * added to FreeBSD before the checks above. 1328 */ 1329 p = kern_getenv("smbios.bios.vendor"); 1330 if (p != NULL) { 1331 for (i = 0; vm_bnames[i] != NULL; i++) 1332 if (strcmp(p, vm_bnames[i]) == 0) { 1333 vm_guest = VM_GUEST_VM; 1334 freeenv(p); 1335 return; 1336 } 1337 freeenv(p); 1338 } 1339 p = kern_getenv("smbios.system.product"); 1340 if (p != NULL) { 1341 for (i = 0; vm_pnames[i] != NULL; i++) 1342 if (strcmp(p, vm_pnames[i]) == 0) { 1343 vm_guest = VM_GUEST_VM; 1344 freeenv(p); 1345 return; 1346 } 1347 freeenv(p); 1348 } 1349} 1350 1351bool 1352fix_cpuid(void) 1353{ 1354 uint64_t msr; 1355 1356 /* 1357 * Clear "Limit CPUID Maxval" bit and return true if the caller should 1358 * get the largest standard CPUID function number again if it is set 1359 * from BIOS. It is necessary for probing correct CPU topology later 1360 * and for the correct operation of the AVX-aware userspace. 1361 */ 1362 if (cpu_vendor_id == CPU_VENDOR_INTEL && 1363 ((CPUID_TO_FAMILY(cpu_id) == 0xf && 1364 CPUID_TO_MODEL(cpu_id) >= 0x3) || 1365 (CPUID_TO_FAMILY(cpu_id) == 0x6 && 1366 CPUID_TO_MODEL(cpu_id) >= 0xe))) { 1367 msr = rdmsr(MSR_IA32_MISC_ENABLE); 1368 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) { 1369 msr &= ~IA32_MISC_EN_LIMCPUID; 1370 wrmsr(MSR_IA32_MISC_ENABLE, msr); 1371 return (true); 1372 } 1373 } 1374 1375 /* 1376 * Re-enable AMD Topology Extension that could be disabled by BIOS 1377 * on some notebook processors. Without the extension it's really 1378 * hard to determine the correct CPU cache topology. 1379 * See BIOS and Kernel Developer���s Guide (BKDG) for AMD Family 15h 1380 * Models 60h-6Fh Processors, Publication # 50742. 1381 */ 1382 if (cpu_vendor_id == CPU_VENDOR_AMD && CPUID_TO_FAMILY(cpu_id) == 0x15) { 1383 msr = rdmsr(MSR_EXTFEATURES); 1384 if ((msr & ((uint64_t)1 << 54)) == 0) { 1385 msr |= (uint64_t)1 << 54; 1386 wrmsr(MSR_EXTFEATURES, msr); 1387 return (true); 1388 } 1389 } 1390 return (false); 1391} 1392 1393/* 1394 * Final stage of CPU identification. 1395 */ 1396#ifdef __i386__ 1397void 1398finishidentcpu(void) 1399#else 1400void 1401identify_cpu(void) 1402#endif 1403{ 1404 u_int regs[4], cpu_stdext_disable; 1405#ifdef __i386__ 1406 u_char ccr3; 1407#endif 1408 1409#ifdef __amd64__ 1410 do_cpuid(0, regs); 1411 cpu_high = regs[0]; 1412 ((u_int *)&cpu_vendor)[0] = regs[1]; 1413 ((u_int *)&cpu_vendor)[1] = regs[3]; 1414 ((u_int *)&cpu_vendor)[2] = regs[2]; 1415 cpu_vendor[12] = '\0'; 1416 1417 do_cpuid(1, regs); 1418 cpu_id = regs[0]; 1419 cpu_procinfo = regs[1]; 1420 cpu_feature = regs[3]; 1421 cpu_feature2 = regs[2]; 1422#endif 1423 1424 identify_hypervisor(); 1425 cpu_vendor_id = find_cpu_vendor_id(); 1426 1427 if (fix_cpuid()) { 1428 do_cpuid(0, regs); 1429 cpu_high = regs[0]; 1430 } 1431 1432 if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) { 1433 do_cpuid(5, regs); 1434 cpu_mon_mwait_flags = regs[2]; 1435 cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE; 1436 cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE; 1437 } 1438 1439 if (cpu_high >= 7) { 1440 cpuid_count(7, 0, regs); 1441 cpu_stdext_feature = regs[1]; 1442 1443 /* 1444 * Some hypervisors fail to filter out unsupported 1445 * extended features. For now, disable the 1446 * extensions, activation of which requires setting a 1447 * bit in CR4, and which VM monitors do not support. 1448 */ 1449 if (cpu_feature2 & CPUID2_HV) { 1450 cpu_stdext_disable = CPUID_STDEXT_FSGSBASE | 1451 CPUID_STDEXT_SMEP; 1452 } else 1453 cpu_stdext_disable = 0; 1454 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable); 1455 cpu_stdext_feature &= ~cpu_stdext_disable; 1456 cpu_stdext_feature2 = regs[2]; 1457 } 1458 1459#ifdef __i386__ 1460 if (cpu_high > 0 && 1461 (cpu_vendor_id == CPU_VENDOR_INTEL || 1462 cpu_vendor_id == CPU_VENDOR_AMD || 1463 cpu_vendor_id == CPU_VENDOR_TRANSMETA || 1464 cpu_vendor_id == CPU_VENDOR_CENTAUR || 1465 cpu_vendor_id == CPU_VENDOR_NSC)) { 1466 do_cpuid(0x80000000, regs); 1467 if (regs[0] >= 0x80000000) 1468 cpu_exthigh = regs[0]; 1469 } 1470#else 1471 if (cpu_vendor_id == CPU_VENDOR_INTEL || 1472 cpu_vendor_id == CPU_VENDOR_AMD || 1473 cpu_vendor_id == CPU_VENDOR_CENTAUR) { 1474 do_cpuid(0x80000000, regs); 1475 cpu_exthigh = regs[0]; 1476 } 1477#endif 1478 if (cpu_exthigh >= 0x80000001) { 1479 do_cpuid(0x80000001, regs); 1480 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); 1481 amd_feature2 = regs[2]; 1482 } 1483 if (cpu_exthigh >= 0x80000007) { 1484 do_cpuid(0x80000007, regs); 1485 amd_pminfo = regs[3]; 1486 } 1487 if (cpu_exthigh >= 0x80000008) { 1488 do_cpuid(0x80000008, regs); 1489 cpu_maxphyaddr = regs[0] & 0xff; 1490 cpu_procinfo2 = regs[2]; 1491 } else { 1492 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32; 1493 } 1494 1495#ifdef __i386__ 1496 if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 1497 if (cpu == CPU_486) { 1498 /* 1499 * These conditions are equivalent to: 1500 * - CPU does not support cpuid instruction. 1501 * - Cyrix/IBM CPU is detected. 1502 */ 1503 if (identblue() == IDENTBLUE_IBMCPU) { 1504 strcpy(cpu_vendor, "IBM"); 1505 cpu_vendor_id = CPU_VENDOR_IBM; 1506 cpu = CPU_BLUE; 1507 return; 1508 } 1509 } 1510 switch (cpu_id & 0xf00) { 1511 case 0x600: 1512 /* 1513 * Cyrix's datasheet does not describe DIRs. 1514 * Therefor, I assume it does not have them 1515 * and use the result of the cpuid instruction. 1516 * XXX they seem to have it for now at least. -Peter 1517 */ 1518 identifycyrix(); 1519 cpu = CPU_M2; 1520 break; 1521 default: 1522 identifycyrix(); 1523 /* 1524 * This routine contains a trick. 1525 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now. 1526 */ 1527 switch (cyrix_did & 0x00f0) { 1528 case 0x00: 1529 case 0xf0: 1530 cpu = CPU_486DLC; 1531 break; 1532 case 0x10: 1533 cpu = CPU_CY486DX; 1534 break; 1535 case 0x20: 1536 if ((cyrix_did & 0x000f) < 8) 1537 cpu = CPU_M1; 1538 else 1539 cpu = CPU_M1SC; 1540 break; 1541 case 0x30: 1542 cpu = CPU_M1; 1543 break; 1544 case 0x40: 1545 /* MediaGX CPU */ 1546 cpu = CPU_M1SC; 1547 break; 1548 default: 1549 /* M2 and later CPUs are treated as M2. */ 1550 cpu = CPU_M2; 1551 1552 /* 1553 * enable cpuid instruction. 1554 */ 1555 ccr3 = read_cyrix_reg(CCR3); 1556 write_cyrix_reg(CCR3, CCR3_MAPEN0); 1557 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID); 1558 write_cyrix_reg(CCR3, ccr3); 1559 1560 do_cpuid(0, regs); 1561 cpu_high = regs[0]; /* eax */ 1562 do_cpuid(1, regs); 1563 cpu_id = regs[0]; /* eax */ 1564 cpu_feature = regs[3]; /* edx */ 1565 break; 1566 } 1567 } 1568 } else if (cpu == CPU_486 && *cpu_vendor == '\0') { 1569 /* 1570 * There are BlueLightning CPUs that do not change 1571 * undefined flags by dividing 5 by 2. In this case, 1572 * the CPU identification routine in locore.s leaves 1573 * cpu_vendor null string and puts CPU_486 into the 1574 * cpu. 1575 */ 1576 if (identblue() == IDENTBLUE_IBMCPU) { 1577 strcpy(cpu_vendor, "IBM"); 1578 cpu_vendor_id = CPU_VENDOR_IBM; 1579 cpu = CPU_BLUE; 1580 return; 1581 } 1582 } 1583#else 1584 /* XXX */ 1585 cpu = CPU_CLAWHAMMER; 1586#endif 1587} 1588 1589static u_int 1590find_cpu_vendor_id(void) 1591{ 1592 int i; 1593 1594 for (i = 0; i < nitems(cpu_vendors); i++) 1595 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0) 1596 return (cpu_vendors[i].vendor_id); 1597 return (0); 1598} 1599 1600static void 1601print_AMD_assoc(int i) 1602{ 1603 if (i == 255) 1604 printf(", fully associative\n"); 1605 else 1606 printf(", %d-way associative\n", i); 1607} 1608 1609static void 1610print_AMD_l2_assoc(int i) 1611{ 1612 switch (i & 0x0f) { 1613 case 0: printf(", disabled/not present\n"); break; 1614 case 1: printf(", direct mapped\n"); break; 1615 case 2: printf(", 2-way associative\n"); break; 1616 case 4: printf(", 4-way associative\n"); break; 1617 case 6: printf(", 8-way associative\n"); break; 1618 case 8: printf(", 16-way associative\n"); break; 1619 case 15: printf(", fully associative\n"); break; 1620 default: printf(", reserved configuration\n"); break; 1621 } 1622} 1623 1624static void 1625print_AMD_info(void) 1626{ 1627#ifdef __i386__ 1628 uint64_t amd_whcr; 1629#endif 1630 u_int regs[4]; 1631 1632 if (cpu_exthigh >= 0x80000005) { 1633 do_cpuid(0x80000005, regs); 1634 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff); 1635 print_AMD_assoc(regs[0] >> 24); 1636 1637 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff); 1638 print_AMD_assoc((regs[0] >> 8) & 0xff); 1639 1640 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff); 1641 print_AMD_assoc(regs[1] >> 24); 1642 1643 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff); 1644 print_AMD_assoc((regs[1] >> 8) & 0xff); 1645 1646 printf("L1 data cache: %d kbytes", regs[2] >> 24); 1647 printf(", %d bytes/line", regs[2] & 0xff); 1648 printf(", %d lines/tag", (regs[2] >> 8) & 0xff); 1649 print_AMD_assoc((regs[2] >> 16) & 0xff); 1650 1651 printf("L1 instruction cache: %d kbytes", regs[3] >> 24); 1652 printf(", %d bytes/line", regs[3] & 0xff); 1653 printf(", %d lines/tag", (regs[3] >> 8) & 0xff); 1654 print_AMD_assoc((regs[3] >> 16) & 0xff); 1655 } 1656 1657 if (cpu_exthigh >= 0x80000006) { 1658 do_cpuid(0x80000006, regs); 1659 if ((regs[0] >> 16) != 0) { 1660 printf("L2 2MB data TLB: %d entries", 1661 (regs[0] >> 16) & 0xfff); 1662 print_AMD_l2_assoc(regs[0] >> 28); 1663 printf("L2 2MB instruction TLB: %d entries", 1664 regs[0] & 0xfff); 1665 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 1666 } else { 1667 printf("L2 2MB unified TLB: %d entries", 1668 regs[0] & 0xfff); 1669 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 1670 } 1671 if ((regs[1] >> 16) != 0) { 1672 printf("L2 4KB data TLB: %d entries", 1673 (regs[1] >> 16) & 0xfff); 1674 print_AMD_l2_assoc(regs[1] >> 28); 1675 1676 printf("L2 4KB instruction TLB: %d entries", 1677 (regs[1] >> 16) & 0xfff); 1678 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 1679 } else { 1680 printf("L2 4KB unified TLB: %d entries", 1681 (regs[1] >> 16) & 0xfff); 1682 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 1683 } 1684 printf("L2 unified cache: %d kbytes", regs[2] >> 16); 1685 printf(", %d bytes/line", regs[2] & 0xff); 1686 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); 1687 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f); 1688 } 1689 1690#ifdef __i386__ 1691 if (((cpu_id & 0xf00) == 0x500) 1692 && (((cpu_id & 0x0f0) > 0x80) 1693 || (((cpu_id & 0x0f0) == 0x80) 1694 && (cpu_id & 0x00f) > 0x07))) { 1695 /* K6-2(new core [Stepping 8-F]), K6-III or later */ 1696 amd_whcr = rdmsr(0xc0000082); 1697 if (!(amd_whcr & (0x3ff << 22))) { 1698 printf("Write Allocate Disable\n"); 1699 } else { 1700 printf("Write Allocate Enable Limit: %dM bytes\n", 1701 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4); 1702 printf("Write Allocate 15-16M bytes: %s\n", 1703 (amd_whcr & (1 << 16)) ? "Enable" : "Disable"); 1704 } 1705 } else if (((cpu_id & 0xf00) == 0x500) 1706 && ((cpu_id & 0x0f0) > 0x50)) { 1707 /* K6, K6-2(old core) */ 1708 amd_whcr = rdmsr(0xc0000082); 1709 if (!(amd_whcr & (0x7f << 1))) { 1710 printf("Write Allocate Disable\n"); 1711 } else { 1712 printf("Write Allocate Enable Limit: %dM bytes\n", 1713 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4); 1714 printf("Write Allocate 15-16M bytes: %s\n", 1715 (amd_whcr & 0x0001) ? "Enable" : "Disable"); 1716 printf("Hardware Write Allocate Control: %s\n", 1717 (amd_whcr & 0x0100) ? "Enable" : "Disable"); 1718 } 1719 } 1720#endif 1721 /* 1722 * Opteron Rev E shows a bug as in very rare occasions a read memory 1723 * barrier is not performed as expected if it is followed by a 1724 * non-atomic read-modify-write instruction. 1725 * As long as that bug pops up very rarely (intensive machine usage 1726 * on other operating systems generally generates one unexplainable 1727 * crash any 2 months) and as long as a model specific fix would be 1728 * impratical at this stage, print out a warning string if the broken 1729 * model and family are identified. 1730 */ 1731 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 && 1732 CPUID_TO_MODEL(cpu_id) <= 0x3f) 1733 printf("WARNING: This architecture revision has known SMP " 1734 "hardware bugs which may cause random instability\n"); 1735} 1736 1737static void 1738print_INTEL_info(void) 1739{ 1740 u_int regs[4]; 1741 u_int rounds, regnum; 1742 u_int nwaycode, nway; 1743 1744 if (cpu_high >= 2) { 1745 rounds = 0; 1746 do { 1747 do_cpuid(0x2, regs); 1748 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0) 1749 break; /* we have a buggy CPU */ 1750 1751 for (regnum = 0; regnum <= 3; ++regnum) { 1752 if (regs[regnum] & (1<<31)) 1753 continue; 1754 if (regnum != 0) 1755 print_INTEL_TLB(regs[regnum] & 0xff); 1756 print_INTEL_TLB((regs[regnum] >> 8) & 0xff); 1757 print_INTEL_TLB((regs[regnum] >> 16) & 0xff); 1758 print_INTEL_TLB((regs[regnum] >> 24) & 0xff); 1759 } 1760 } while (--rounds > 0); 1761 } 1762 1763 if (cpu_exthigh >= 0x80000006) { 1764 do_cpuid(0x80000006, regs); 1765 nwaycode = (regs[2] >> 12) & 0x0f; 1766 if (nwaycode >= 0x02 && nwaycode <= 0x08) 1767 nway = 1 << (nwaycode / 2); 1768 else 1769 nway = 0; 1770 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n", 1771 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff); 1772 } 1773} 1774 1775static void 1776print_INTEL_TLB(u_int data) 1777{ 1778 switch (data) { 1779 case 0x0: 1780 case 0x40: 1781 default: 1782 break; 1783 case 0x1: 1784 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n"); 1785 break; 1786 case 0x2: 1787 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n"); 1788 break; 1789 case 0x3: 1790 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n"); 1791 break; 1792 case 0x4: 1793 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n"); 1794 break; 1795 case 0x6: 1796 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n"); 1797 break; 1798 case 0x8: 1799 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n"); 1800 break; 1801 case 0x9: 1802 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n"); 1803 break; 1804 case 0xa: 1805 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n"); 1806 break; 1807 case 0xb: 1808 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n"); 1809 break; 1810 case 0xc: 1811 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n"); 1812 break; 1813 case 0xd: 1814 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size"); 1815 break; 1816 case 0xe: 1817 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n"); 1818 break; 1819 case 0x1d: 1820 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n"); 1821 break; 1822 case 0x21: 1823 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n"); 1824 break; 1825 case 0x22: 1826 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1827 break; 1828 case 0x23: 1829 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1830 break; 1831 case 0x24: 1832 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n"); 1833 break; 1834 case 0x25: 1835 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1836 break; 1837 case 0x29: 1838 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1839 break; 1840 case 0x2c: 1841 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n"); 1842 break; 1843 case 0x30: 1844 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n"); 1845 break; 1846 case 0x39: /* De-listed in SDM rev. 54 */ 1847 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1848 break; 1849 case 0x3b: /* De-listed in SDM rev. 54 */ 1850 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n"); 1851 break; 1852 case 0x3c: /* De-listed in SDM rev. 54 */ 1853 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1854 break; 1855 case 0x41: 1856 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n"); 1857 break; 1858 case 0x42: 1859 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n"); 1860 break; 1861 case 0x43: 1862 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n"); 1863 break; 1864 case 0x44: 1865 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n"); 1866 break; 1867 case 0x45: 1868 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n"); 1869 break; 1870 case 0x46: 1871 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n"); 1872 break; 1873 case 0x47: 1874 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n"); 1875 break; 1876 case 0x48: 1877 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n"); 1878 break; 1879 case 0x49: 1880 if (CPUID_TO_FAMILY(cpu_id) == 0xf && 1881 CPUID_TO_MODEL(cpu_id) == 0x6) 1882 printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n"); 1883 else 1884 printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size"); 1885 break; 1886 case 0x4a: 1887 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n"); 1888 break; 1889 case 0x4b: 1890 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n"); 1891 break; 1892 case 0x4c: 1893 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n"); 1894 break; 1895 case 0x4d: 1896 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n"); 1897 break; 1898 case 0x4e: 1899 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n"); 1900 break; 1901 case 0x4f: 1902 printf("Instruction TLB: 4 KByte pages, 32 entries\n"); 1903 break; 1904 case 0x50: 1905 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n"); 1906 break; 1907 case 0x51: 1908 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n"); 1909 break; 1910 case 0x52: 1911 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n"); 1912 break; 1913 case 0x55: 1914 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n"); 1915 break; 1916 case 0x56: 1917 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n"); 1918 break; 1919 case 0x57: 1920 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n"); 1921 break; 1922 case 0x59: 1923 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n"); 1924 break; 1925 case 0x5a: 1926 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n"); 1927 break; 1928 case 0x5b: 1929 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n"); 1930 break; 1931 case 0x5c: 1932 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n"); 1933 break; 1934 case 0x5d: 1935 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n"); 1936 break; 1937 case 0x60: 1938 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 1939 break; 1940 case 0x61: 1941 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n"); 1942 break; 1943 case 0x63: 1944 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n"); 1945 break; 1946 case 0x64: 1947 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n"); 1948 break; 1949 case 0x66: 1950 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1951 break; 1952 case 0x67: 1953 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1954 break; 1955 case 0x68: 1956 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n"); 1957 break; 1958 case 0x6a: 1959 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n"); 1960 break; 1961 case 0x6b: 1962 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n"); 1963 break; 1964 case 0x6c: 1965 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n"); 1966 break; 1967 case 0x6d: 1968 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n"); 1969 break; 1970 case 0x70: 1971 printf("Trace cache: 12K-uops, 8-way set associative\n"); 1972 break; 1973 case 0x71: 1974 printf("Trace cache: 16K-uops, 8-way set associative\n"); 1975 break; 1976 case 0x72: 1977 printf("Trace cache: 32K-uops, 8-way set associative\n"); 1978 break; 1979 case 0x76: 1980 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n"); 1981 break; 1982 case 0x78: 1983 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n"); 1984 break; 1985 case 0x79: 1986 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 1987 break; 1988 case 0x7a: 1989 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 1990 break; 1991 case 0x7b: 1992 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 1993 break; 1994 case 0x7c: 1995 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1996 break; 1997 case 0x7d: 1998 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n"); 1999 break; 2000 case 0x7f: 2001 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n"); 2002 break; 2003 case 0x80: 2004 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n"); 2005 break; 2006 case 0x82: 2007 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n"); 2008 break; 2009 case 0x83: 2010 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n"); 2011 break; 2012 case 0x84: 2013 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n"); 2014 break; 2015 case 0x85: 2016 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n"); 2017 break; 2018 case 0x86: 2019 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n"); 2020 break; 2021 case 0x87: 2022 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n"); 2023 break; 2024 case 0xa0: 2025 printf("DTLB: 4k pages, fully associative, 32 entries\n"); 2026 break; 2027 case 0xb0: 2028 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); 2029 break; 2030 case 0xb1: 2031 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n"); 2032 break; 2033 case 0xb2: 2034 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n"); 2035 break; 2036 case 0xb3: 2037 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); 2038 break; 2039 case 0xb4: 2040 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n"); 2041 break; 2042 case 0xb5: 2043 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n"); 2044 break; 2045 case 0xb6: 2046 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n"); 2047 break; 2048 case 0xba: 2049 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n"); 2050 break; 2051 case 0xc0: 2052 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n"); 2053 break; 2054 case 0xc1: 2055 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n"); 2056 break; 2057 case 0xc2: 2058 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n"); 2059 break; 2060 case 0xc3: 2061 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n"); 2062 break; 2063 case 0xc4: 2064 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n"); 2065 break; 2066 case 0xca: 2067 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n"); 2068 break; 2069 case 0xd0: 2070 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n"); 2071 break; 2072 case 0xd1: 2073 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n"); 2074 break; 2075 case 0xd2: 2076 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n"); 2077 break; 2078 case 0xd6: 2079 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n"); 2080 break; 2081 case 0xd7: 2082 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n"); 2083 break; 2084 case 0xd8: 2085 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n"); 2086 break; 2087 case 0xdc: 2088 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n"); 2089 break; 2090 case 0xdd: 2091 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n"); 2092 break; 2093 case 0xde: 2094 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n"); 2095 break; 2096 case 0xe2: 2097 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n"); 2098 break; 2099 case 0xe3: 2100 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n"); 2101 break; 2102 case 0xe4: 2103 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n"); 2104 break; 2105 case 0xea: 2106 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n"); 2107 break; 2108 case 0xeb: 2109 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n"); 2110 break; 2111 case 0xec: 2112 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n"); 2113 break; 2114 case 0xf0: 2115 printf("64-Byte prefetching\n"); 2116 break; 2117 case 0xf1: 2118 printf("128-Byte prefetching\n"); 2119 break; 2120 } 2121} 2122 2123static void 2124print_svm_info(void) 2125{ 2126 u_int features, regs[4]; 2127 uint64_t msr; 2128 int comma; 2129 2130 printf("\n SVM: "); 2131 do_cpuid(0x8000000A, regs); 2132 features = regs[3]; 2133 2134 msr = rdmsr(MSR_VM_CR); 2135 if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS) 2136 printf("(disabled in BIOS) "); 2137 2138 if (!bootverbose) { 2139 comma = 0; 2140 if (features & (1 << 0)) { 2141 printf("%sNP", comma ? "," : ""); 2142 comma = 1; 2143 } 2144 if (features & (1 << 3)) { 2145 printf("%sNRIP", comma ? "," : ""); 2146 comma = 1; 2147 } 2148 if (features & (1 << 5)) { 2149 printf("%sVClean", comma ? "," : ""); 2150 comma = 1; 2151 } 2152 if (features & (1 << 6)) { 2153 printf("%sAFlush", comma ? "," : ""); 2154 comma = 1; 2155 } 2156 if (features & (1 << 7)) { 2157 printf("%sDAssist", comma ? "," : ""); 2158 comma = 1; 2159 } 2160 printf("%sNAsids=%d", comma ? "," : "", regs[1]); 2161 return; 2162 } 2163 2164 printf("Features=0x%b", features, 2165 "\020" 2166 "\001NP" /* Nested paging */ 2167 "\002LbrVirt" /* LBR virtualization */ 2168 "\003SVML" /* SVM lock */ 2169 "\004NRIPS" /* NRIP save */ 2170 "\005TscRateMsr" /* MSR based TSC rate control */ 2171 "\006VmcbClean" /* VMCB clean bits */ 2172 "\007FlushByAsid" /* Flush by ASID */ 2173 "\010DecodeAssist" /* Decode assist */ 2174 "\011<b8>" 2175 "\012<b9>" 2176 "\013PauseFilter" /* PAUSE intercept filter */ 2177 "\014<b11>" 2178 "\015PauseFilterThreshold" /* PAUSE filter threshold */ 2179 "\016AVIC" /* virtual interrupt controller */ 2180 ); 2181 printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]); 2182} 2183 2184#ifdef __i386__ 2185static void 2186print_transmeta_info(void) 2187{ 2188 u_int regs[4], nreg = 0; 2189 2190 do_cpuid(0x80860000, regs); 2191 nreg = regs[0]; 2192 if (nreg >= 0x80860001) { 2193 do_cpuid(0x80860001, regs); 2194 printf(" Processor revision %u.%u.%u.%u\n", 2195 (regs[1] >> 24) & 0xff, 2196 (regs[1] >> 16) & 0xff, 2197 (regs[1] >> 8) & 0xff, 2198 regs[1] & 0xff); 2199 } 2200 if (nreg >= 0x80860002) { 2201 do_cpuid(0x80860002, regs); 2202 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n", 2203 (regs[1] >> 24) & 0xff, 2204 (regs[1] >> 16) & 0xff, 2205 (regs[1] >> 8) & 0xff, 2206 regs[1] & 0xff, 2207 regs[2]); 2208 } 2209 if (nreg >= 0x80860006) { 2210 char info[65]; 2211 do_cpuid(0x80860003, (u_int*) &info[0]); 2212 do_cpuid(0x80860004, (u_int*) &info[16]); 2213 do_cpuid(0x80860005, (u_int*) &info[32]); 2214 do_cpuid(0x80860006, (u_int*) &info[48]); 2215 info[64] = 0; 2216 printf(" %s\n", info); 2217 } 2218} 2219#endif 2220 2221static void 2222print_via_padlock_info(void) 2223{ 2224 u_int regs[4]; 2225 2226 do_cpuid(0xc0000001, regs); 2227 printf("\n VIA Padlock Features=0x%b", regs[3], 2228 "\020" 2229 "\003RNG" /* RNG */ 2230 "\007AES" /* ACE */ 2231 "\011AES-CTR" /* ACE2 */ 2232 "\013SHA1,SHA256" /* PHE */ 2233 "\015RSA" /* PMM */ 2234 ); 2235} 2236 2237static uint32_t 2238vmx_settable(uint64_t basic, int msr, int true_msr) 2239{ 2240 uint64_t val; 2241 2242 if (basic & (1ULL << 55)) 2243 val = rdmsr(true_msr); 2244 else 2245 val = rdmsr(msr); 2246 2247 /* Just report the controls that can be set to 1. */ 2248 return (val >> 32); 2249} 2250 2251static void 2252print_vmx_info(void) 2253{ 2254 uint64_t basic, msr; 2255 uint32_t entry, exit, mask, pin, proc, proc2; 2256 int comma; 2257 2258 printf("\n VT-x: "); 2259 msr = rdmsr(MSR_IA32_FEATURE_CONTROL); 2260 if (!(msr & IA32_FEATURE_CONTROL_VMX_EN)) 2261 printf("(disabled in BIOS) "); 2262 basic = rdmsr(MSR_VMX_BASIC); 2263 pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS, 2264 MSR_VMX_TRUE_PINBASED_CTLS); 2265 proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS, 2266 MSR_VMX_TRUE_PROCBASED_CTLS); 2267 if (proc & PROCBASED_SECONDARY_CONTROLS) 2268 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2, 2269 MSR_VMX_PROCBASED_CTLS2); 2270 else 2271 proc2 = 0; 2272 exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS); 2273 entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS); 2274 2275 if (!bootverbose) { 2276 comma = 0; 2277 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT && 2278 entry & VM_ENTRY_LOAD_PAT) { 2279 printf("%sPAT", comma ? "," : ""); 2280 comma = 1; 2281 } 2282 if (proc & PROCBASED_HLT_EXITING) { 2283 printf("%sHLT", comma ? "," : ""); 2284 comma = 1; 2285 } 2286 if (proc & PROCBASED_MTF) { 2287 printf("%sMTF", comma ? "," : ""); 2288 comma = 1; 2289 } 2290 if (proc & PROCBASED_PAUSE_EXITING) { 2291 printf("%sPAUSE", comma ? "," : ""); 2292 comma = 1; 2293 } 2294 if (proc2 & PROCBASED2_ENABLE_EPT) { 2295 printf("%sEPT", comma ? "," : ""); 2296 comma = 1; 2297 } 2298 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) { 2299 printf("%sUG", comma ? "," : ""); 2300 comma = 1; 2301 } 2302 if (proc2 & PROCBASED2_ENABLE_VPID) { 2303 printf("%sVPID", comma ? "," : ""); 2304 comma = 1; 2305 } 2306 if (proc & PROCBASED_USE_TPR_SHADOW && 2307 proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES && 2308 proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE && 2309 proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION && 2310 proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) { 2311 printf("%sVID", comma ? "," : ""); 2312 comma = 1; 2313 if (pin & PINBASED_POSTED_INTERRUPT) 2314 printf(",PostIntr"); 2315 } 2316 return; 2317 } 2318 2319 mask = basic >> 32; 2320 printf("Basic Features=0x%b", mask, 2321 "\020" 2322 "\02132PA" /* 32-bit physical addresses */ 2323 "\022SMM" /* SMM dual-monitor */ 2324 "\027INS/OUTS" /* VM-exit info for INS and OUTS */ 2325 "\030TRUE" /* TRUE_CTLS MSRs */ 2326 ); 2327 printf("\n Pin-Based Controls=0x%b", pin, 2328 "\020" 2329 "\001ExtINT" /* External-interrupt exiting */ 2330 "\004NMI" /* NMI exiting */ 2331 "\006VNMI" /* Virtual NMIs */ 2332 "\007PreTmr" /* Activate VMX-preemption timer */ 2333 "\010PostIntr" /* Process posted interrupts */ 2334 ); 2335 printf("\n Primary Processor Controls=0x%b", proc, 2336 "\020" 2337 "\003INTWIN" /* Interrupt-window exiting */ 2338 "\004TSCOff" /* Use TSC offsetting */ 2339 "\010HLT" /* HLT exiting */ 2340 "\012INVLPG" /* INVLPG exiting */ 2341 "\013MWAIT" /* MWAIT exiting */ 2342 "\014RDPMC" /* RDPMC exiting */ 2343 "\015RDTSC" /* RDTSC exiting */ 2344 "\020CR3-LD" /* CR3-load exiting */ 2345 "\021CR3-ST" /* CR3-store exiting */ 2346 "\024CR8-LD" /* CR8-load exiting */ 2347 "\025CR8-ST" /* CR8-store exiting */ 2348 "\026TPR" /* Use TPR shadow */ 2349 "\027NMIWIN" /* NMI-window exiting */ 2350 "\030MOV-DR" /* MOV-DR exiting */ 2351 "\031IO" /* Unconditional I/O exiting */ 2352 "\032IOmap" /* Use I/O bitmaps */ 2353 "\034MTF" /* Monitor trap flag */ 2354 "\035MSRmap" /* Use MSR bitmaps */ 2355 "\036MONITOR" /* MONITOR exiting */ 2356 "\037PAUSE" /* PAUSE exiting */ 2357 ); 2358 if (proc & PROCBASED_SECONDARY_CONTROLS) 2359 printf("\n Secondary Processor Controls=0x%b", proc2, 2360 "\020" 2361 "\001APIC" /* Virtualize APIC accesses */ 2362 "\002EPT" /* Enable EPT */ 2363 "\003DT" /* Descriptor-table exiting */ 2364 "\004RDTSCP" /* Enable RDTSCP */ 2365 "\005x2APIC" /* Virtualize x2APIC mode */ 2366 "\006VPID" /* Enable VPID */ 2367 "\007WBINVD" /* WBINVD exiting */ 2368 "\010UG" /* Unrestricted guest */ 2369 "\011APIC-reg" /* APIC-register virtualization */ 2370 "\012VID" /* Virtual-interrupt delivery */ 2371 "\013PAUSE-loop" /* PAUSE-loop exiting */ 2372 "\014RDRAND" /* RDRAND exiting */ 2373 "\015INVPCID" /* Enable INVPCID */ 2374 "\016VMFUNC" /* Enable VM functions */ 2375 "\017VMCS" /* VMCS shadowing */ 2376 "\020EPT#VE" /* EPT-violation #VE */ 2377 "\021XSAVES" /* Enable XSAVES/XRSTORS */ 2378 ); 2379 printf("\n Exit Controls=0x%b", mask, 2380 "\020" 2381 "\003DR" /* Save debug controls */ 2382 /* Ignore Host address-space size */ 2383 "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */ 2384 "\020AckInt" /* Acknowledge interrupt on exit */ 2385 "\023PAT-SV" /* Save MSR_PAT */ 2386 "\024PAT-LD" /* Load MSR_PAT */ 2387 "\025EFER-SV" /* Save MSR_EFER */ 2388 "\026EFER-LD" /* Load MSR_EFER */ 2389 "\027PTMR-SV" /* Save VMX-preemption timer value */ 2390 ); 2391 printf("\n Entry Controls=0x%b", mask, 2392 "\020" 2393 "\003DR" /* Save debug controls */ 2394 /* Ignore IA-32e mode guest */ 2395 /* Ignore Entry to SMM */ 2396 /* Ignore Deactivate dual-monitor treatment */ 2397 "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */ 2398 "\017PAT" /* Load MSR_PAT */ 2399 "\020EFER" /* Load MSR_EFER */ 2400 ); 2401 if (proc & PROCBASED_SECONDARY_CONTROLS && 2402 (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) { 2403 msr = rdmsr(MSR_VMX_EPT_VPID_CAP); 2404 mask = msr; 2405 printf("\n EPT Features=0x%b", mask, 2406 "\020" 2407 "\001XO" /* Execute-only translations */ 2408 "\007PW4" /* Page-walk length of 4 */ 2409 "\011UC" /* EPT paging-structure mem can be UC */ 2410 "\017WB" /* EPT paging-structure mem can be WB */ 2411 "\0212M" /* EPT PDE can map a 2-Mbyte page */ 2412 "\0221G" /* EPT PDPTE can map a 1-Gbyte page */ 2413 "\025INVEPT" /* INVEPT is supported */ 2414 "\026AD" /* Accessed and dirty flags for EPT */ 2415 "\032single" /* INVEPT single-context type */ 2416 "\033all" /* INVEPT all-context type */ 2417 ); 2418 mask = msr >> 32; 2419 printf("\n VPID Features=0x%b", mask, 2420 "\020" 2421 "\001INVVPID" /* INVVPID is supported */ 2422 "\011individual" /* INVVPID individual-address type */ 2423 "\012single" /* INVVPID single-context type */ 2424 "\013all" /* INVVPID all-context type */ 2425 /* INVVPID single-context-retaining-globals type */ 2426 "\014single-globals" 2427 ); 2428 } 2429} 2430 2431static void 2432print_hypervisor_info(void) 2433{ 2434 2435 if (*hv_vendor) 2436 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor); 2437} 2438