1142425Snectar/*- 2142425Snectar * Copyright (c) 2004 John Baldwin <jhb@FreeBSD.org> 3142425Snectar * 4142425Snectar * Redistribution and use in source and binary forms, with or without 5142425Snectar * modification, are permitted provided that the following conditions 6142425Snectar * are met: 7142425Snectar * 1. Redistributions of source code must retain the above copyright 8142425Snectar * notice, this list of conditions and the following disclaimer. 9142425Snectar * 2. Redistributions in binary form must reproduce the above copyright 10142425Snectar * notice, this list of conditions and the following disclaimer in the 11142425Snectar * documentation and/or other materials provided with the distribution. 12142425Snectar * 13142425Snectar * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14238405Sjkim * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15160814Ssimon * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16142425Snectar * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17160814Ssimon * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18160814Ssimon * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19142425Snectar * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20142425Snectar * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21142425Snectar * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22142425Snectar * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23142425Snectar * SUCH DAMAGE. 24142425Snectar */ 25142425Snectar 26162911Ssimon#include <sys/cdefs.h> 27194206Ssimon__FBSDID("$FreeBSD: stable/11/sys/x86/isa/elcr.c 367457 2020-11-07 18:10:59Z dim $"); 28194206Ssimon 29238405Sjkim/* 30142425Snectar * The ELCR is a register that controls the trigger mode and polarity of 31142425Snectar * EISA and ISA interrupts. In FreeBSD 3.x and 4.x, the ELCR was only 32142425Snectar * consulted for determining the appropriate trigger mode of EISA 33142425Snectar * interrupts when using an APIC. However, it seems that almost all 34142425Snectar * systems that include PCI also include an ELCR that manages the ISA 35142425Snectar * IRQs 0 through 15. Thus, we check for the presence of an ELCR on 36142425Snectar * every machine by checking to see if the values found at bootup are 37142425Snectar * sane. Note that the polarity of ISA and EISA IRQs are linked to the 38142425Snectar * trigger mode. All edge triggered IRQs use active-hi polarity, and 39142425Snectar * all level triggered interrupts use active-lo polarity. 40142425Snectar * 41142425Snectar * The format of the ELCR is simple: it is a 16-bit bitmap where bit 0 42142425Snectar * controls IRQ 0, bit 1 controls IRQ 1, etc. If the bit is zero, the 43142425Snectar * associated IRQ is edge triggered. If the bit is one, the IRQ is 44238405Sjkim * level triggered. 45142425Snectar */ 46142425Snectar 47142425Snectar#include <sys/param.h> 48160814Ssimon#include <sys/bus.h> 49160814Ssimon#include <sys/systm.h> 50160814Ssimon#include <machine/intr_machdep.h> 51238405Sjkim 52238405Sjkim#define ELCR_PORT 0x4d0 53238405Sjkim#define ELCR_MASK(irq) (1 << (irq)) 54238405Sjkim 55238405Sjkimstatic int elcr_status; 56238405Sjkimint elcr_found; 57160814Ssimon 58194206Ssimon/* 59238405Sjkim * Check to see if we have what looks like a valid ELCR. We do this by 60238405Sjkim * verifying that IRQs 0, 1, 2, and 13 are all edge triggered. 61238405Sjkim */ 62238405Sjkimint 63238405Sjkimelcr_probe(void) 64238405Sjkim{ 65238405Sjkim int i; 66238405Sjkim 67238405Sjkim elcr_status = inb(ELCR_PORT) | inb(ELCR_PORT + 1) << 8; 68290207Sjkim if ((elcr_status & (ELCR_MASK(0) | ELCR_MASK(1) | ELCR_MASK(2) | 69290207Sjkim ELCR_MASK(8) | ELCR_MASK(13))) != 0) 70290207Sjkim return (ENXIO); 71290207Sjkim if (bootverbose) { 72194206Ssimon printf("ELCR Found. ISA IRQs programmed as:\n"); 73238405Sjkim for (i = 0; i < 16; i++) 74238405Sjkim printf(" %2d", i); 75290207Sjkim printf("\n"); 76290207Sjkim for (i = 0; i < 16; i++) 77238405Sjkim if (elcr_status & ELCR_MASK(i)) 78238405Sjkim printf(" L"); 79238405Sjkim else 80290207Sjkim printf(" E"); 81290207Sjkim printf("\n"); 82290207Sjkim } 83290207Sjkim if (resource_disabled("elcr", 0)) 84238405Sjkim return (ENXIO); 85238405Sjkim elcr_found = 1; 86238405Sjkim return (0); 87238405Sjkim} 88238405Sjkim 89238405Sjkim/* 90238405Sjkim * Returns 1 for level trigger, 0 for edge. 91290207Sjkim */ 92290207Sjkimenum intr_trigger 93290207Sjkimelcr_read_trigger(u_int irq) 94290207Sjkim{ 95238405Sjkim 96238405Sjkim KASSERT(elcr_found, ("%s: no ELCR was found!", __func__)); 97238405Sjkim KASSERT(irq <= 15, ("%s: invalid IRQ %u", __func__, irq)); 98290207Sjkim if (elcr_status & ELCR_MASK(irq)) 99290207Sjkim return (INTR_TRIGGER_LEVEL); 100238405Sjkim else 101142425Snectar return (INTR_TRIGGER_EDGE); 102290207Sjkim} 103142425Snectar 104142425Snectar/* 105142425Snectar * Set the trigger mode for a specified IRQ. Mode of 0 means edge triggered, 106142425Snectar * and a mode of 1 means level triggered. 107142425Snectar */ 108142425Snectarvoid 109160814Ssimonelcr_write_trigger(u_int irq, enum intr_trigger trigger) 110160814Ssimon{ 111160814Ssimon int new_status; 112142425Snectar 113142425Snectar KASSERT(elcr_found, ("%s: no ELCR was found!", __func__)); 114142425Snectar KASSERT(irq <= 15, ("%s: invalid IRQ %u", __func__, irq)); 115142425Snectar if (trigger == INTR_TRIGGER_LEVEL) 116142425Snectar new_status = elcr_status | ELCR_MASK(irq); 117142425Snectar else 118142425Snectar new_status = elcr_status & ~ELCR_MASK(irq); 119142425Snectar if (new_status == elcr_status) 120142425Snectar return; 121142425Snectar elcr_status = new_status; 122142425Snectar if (irq >= 8) 123142425Snectar outb(ELCR_PORT + 1, elcr_status >> 8); 124142425Snectar else 125284283Sjkim outb(ELCR_PORT, elcr_status & 0xff); 126284283Sjkim} 127142425Snectar 128160814Ssimonvoid 129142425Snectarelcr_resume(void) 130142425Snectar{ 131142425Snectar 132142425Snectar KASSERT(elcr_found, ("%s: no ELCR was found!", __func__)); 133142425Snectar outb(ELCR_PORT, elcr_status & 0xff); 134142425Snectar outb(ELCR_PORT + 1, elcr_status >> 8); 135142425Snectar} 136325335Sjkim