intel_utils.c revision 327785
1/*- 2 * Copyright (c) 2013 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 6 * under sponsorship from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: stable/11/sys/x86/iommu/intel_utils.c 327785 2018-01-10 20:39:26Z markj $"); 32 33#include <sys/param.h> 34#include <sys/bus.h> 35#include <sys/kernel.h> 36#include <sys/lock.h> 37#include <sys/malloc.h> 38#include <sys/memdesc.h> 39#include <sys/mutex.h> 40#include <sys/proc.h> 41#include <sys/queue.h> 42#include <sys/rman.h> 43#include <sys/rwlock.h> 44#include <sys/sched.h> 45#include <sys/sf_buf.h> 46#include <sys/sysctl.h> 47#include <sys/systm.h> 48#include <sys/taskqueue.h> 49#include <sys/time.h> 50#include <sys/tree.h> 51#include <sys/vmem.h> 52#include <dev/pci/pcivar.h> 53#include <vm/vm.h> 54#include <vm/vm_extern.h> 55#include <vm/vm_kern.h> 56#include <vm/vm_object.h> 57#include <vm/vm_page.h> 58#include <vm/vm_map.h> 59#include <vm/vm_pageout.h> 60#include <machine/bus.h> 61#include <machine/cpu.h> 62#include <machine/intr_machdep.h> 63#include <x86/include/apicvar.h> 64#include <x86/include/busdma_impl.h> 65#include <x86/iommu/intel_reg.h> 66#include <x86/iommu/busdma_dmar.h> 67#include <x86/iommu/intel_dmar.h> 68 69u_int 70dmar_nd2mask(u_int nd) 71{ 72 static const u_int masks[] = { 73 0x000f, /* nd == 0 */ 74 0x002f, /* nd == 1 */ 75 0x00ff, /* nd == 2 */ 76 0x02ff, /* nd == 3 */ 77 0x0fff, /* nd == 4 */ 78 0x2fff, /* nd == 5 */ 79 0xffff, /* nd == 6 */ 80 0x0000, /* nd == 7 reserved */ 81 }; 82 83 KASSERT(nd <= 6, ("number of domains %d", nd)); 84 return (masks[nd]); 85} 86 87static const struct sagaw_bits_tag { 88 int agaw; 89 int cap; 90 int awlvl; 91 int pglvl; 92} sagaw_bits[] = { 93 {.agaw = 30, .cap = DMAR_CAP_SAGAW_2LVL, .awlvl = DMAR_CTX2_AW_2LVL, 94 .pglvl = 2}, 95 {.agaw = 39, .cap = DMAR_CAP_SAGAW_3LVL, .awlvl = DMAR_CTX2_AW_3LVL, 96 .pglvl = 3}, 97 {.agaw = 48, .cap = DMAR_CAP_SAGAW_4LVL, .awlvl = DMAR_CTX2_AW_4LVL, 98 .pglvl = 4}, 99 {.agaw = 57, .cap = DMAR_CAP_SAGAW_5LVL, .awlvl = DMAR_CTX2_AW_5LVL, 100 .pglvl = 5}, 101 {.agaw = 64, .cap = DMAR_CAP_SAGAW_6LVL, .awlvl = DMAR_CTX2_AW_6LVL, 102 .pglvl = 6} 103}; 104 105bool 106dmar_pglvl_supported(struct dmar_unit *unit, int pglvl) 107{ 108 int i; 109 110 for (i = 0; i < nitems(sagaw_bits); i++) { 111 if (sagaw_bits[i].pglvl != pglvl) 112 continue; 113 if ((DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap) != 0) 114 return (true); 115 } 116 return (false); 117} 118 119int 120domain_set_agaw(struct dmar_domain *domain, int mgaw) 121{ 122 int sagaw, i; 123 124 domain->mgaw = mgaw; 125 sagaw = DMAR_CAP_SAGAW(domain->dmar->hw_cap); 126 for (i = 0; i < nitems(sagaw_bits); i++) { 127 if (sagaw_bits[i].agaw >= mgaw) { 128 domain->agaw = sagaw_bits[i].agaw; 129 domain->pglvl = sagaw_bits[i].pglvl; 130 domain->awlvl = sagaw_bits[i].awlvl; 131 return (0); 132 } 133 } 134 device_printf(domain->dmar->dev, 135 "context request mgaw %d: no agaw found, sagaw %x\n", 136 mgaw, sagaw); 137 return (EINVAL); 138} 139 140/* 141 * Find a best fit mgaw for the given maxaddr: 142 * - if allow_less is false, must find sagaw which maps all requested 143 * addresses (used by identity mappings); 144 * - if allow_less is true, and no supported sagaw can map all requested 145 * address space, accept the biggest sagaw, whatever is it. 146 */ 147int 148dmar_maxaddr2mgaw(struct dmar_unit *unit, dmar_gaddr_t maxaddr, bool allow_less) 149{ 150 int i; 151 152 for (i = 0; i < nitems(sagaw_bits); i++) { 153 if ((1ULL << sagaw_bits[i].agaw) >= maxaddr && 154 (DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap) != 0) 155 break; 156 } 157 if (allow_less && i == nitems(sagaw_bits)) { 158 do { 159 i--; 160 } while ((DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap) 161 == 0); 162 } 163 if (i < nitems(sagaw_bits)) 164 return (sagaw_bits[i].agaw); 165 KASSERT(0, ("no mgaw for maxaddr %jx allow_less %d", 166 (uintmax_t) maxaddr, allow_less)); 167 return (-1); 168} 169 170/* 171 * Calculate the total amount of page table pages needed to map the 172 * whole bus address space on the context with the selected agaw. 173 */ 174vm_pindex_t 175pglvl_max_pages(int pglvl) 176{ 177 vm_pindex_t res; 178 int i; 179 180 for (res = 0, i = pglvl; i > 0; i--) { 181 res *= DMAR_NPTEPG; 182 res++; 183 } 184 return (res); 185} 186 187/* 188 * Return true if the page table level lvl supports the superpage for 189 * the context ctx. 190 */ 191int 192domain_is_sp_lvl(struct dmar_domain *domain, int lvl) 193{ 194 int alvl, cap_sps; 195 static const int sagaw_sp[] = { 196 DMAR_CAP_SPS_2M, 197 DMAR_CAP_SPS_1G, 198 DMAR_CAP_SPS_512G, 199 DMAR_CAP_SPS_1T 200 }; 201 202 alvl = domain->pglvl - lvl - 1; 203 cap_sps = DMAR_CAP_SPS(domain->dmar->hw_cap); 204 return (alvl < nitems(sagaw_sp) && (sagaw_sp[alvl] & cap_sps) != 0); 205} 206 207dmar_gaddr_t 208pglvl_page_size(int total_pglvl, int lvl) 209{ 210 int rlvl; 211 static const dmar_gaddr_t pg_sz[] = { 212 (dmar_gaddr_t)DMAR_PAGE_SIZE, 213 (dmar_gaddr_t)DMAR_PAGE_SIZE << DMAR_NPTEPGSHIFT, 214 (dmar_gaddr_t)DMAR_PAGE_SIZE << (2 * DMAR_NPTEPGSHIFT), 215 (dmar_gaddr_t)DMAR_PAGE_SIZE << (3 * DMAR_NPTEPGSHIFT), 216 (dmar_gaddr_t)DMAR_PAGE_SIZE << (4 * DMAR_NPTEPGSHIFT), 217 (dmar_gaddr_t)DMAR_PAGE_SIZE << (5 * DMAR_NPTEPGSHIFT) 218 }; 219 220 KASSERT(lvl >= 0 && lvl < total_pglvl, 221 ("total %d lvl %d", total_pglvl, lvl)); 222 rlvl = total_pglvl - lvl - 1; 223 KASSERT(rlvl < nitems(pg_sz), ("sizeof pg_sz lvl %d", lvl)); 224 return (pg_sz[rlvl]); 225} 226 227dmar_gaddr_t 228domain_page_size(struct dmar_domain *domain, int lvl) 229{ 230 231 return (pglvl_page_size(domain->pglvl, lvl)); 232} 233 234int 235calc_am(struct dmar_unit *unit, dmar_gaddr_t base, dmar_gaddr_t size, 236 dmar_gaddr_t *isizep) 237{ 238 dmar_gaddr_t isize; 239 int am; 240 241 for (am = DMAR_CAP_MAMV(unit->hw_cap);; am--) { 242 isize = 1ULL << (am + DMAR_PAGE_SHIFT); 243 if ((base & (isize - 1)) == 0 && size >= isize) 244 break; 245 if (am == 0) 246 break; 247 } 248 *isizep = isize; 249 return (am); 250} 251 252dmar_haddr_t dmar_high; 253int haw; 254int dmar_tbl_pagecnt; 255 256vm_page_t 257dmar_pgalloc(vm_object_t obj, vm_pindex_t idx, int flags) 258{ 259 vm_page_t m; 260 int zeroed, aflags; 261 262 zeroed = (flags & DMAR_PGF_ZERO) != 0 ? VM_ALLOC_ZERO : 0; 263 aflags = zeroed | VM_ALLOC_NOBUSY | VM_ALLOC_SYSTEM | VM_ALLOC_NODUMP | 264 ((flags & DMAR_PGF_WAITOK) != 0 ? VM_ALLOC_WAITFAIL : 265 VM_ALLOC_NOWAIT); 266 for (;;) { 267 if ((flags & DMAR_PGF_OBJL) == 0) 268 VM_OBJECT_WLOCK(obj); 269 m = vm_page_lookup(obj, idx); 270 if ((flags & DMAR_PGF_NOALLOC) != 0 || m != NULL) { 271 if ((flags & DMAR_PGF_OBJL) == 0) 272 VM_OBJECT_WUNLOCK(obj); 273 break; 274 } 275 m = vm_page_alloc_contig(obj, idx, aflags, 1, 0, 276 dmar_high, PAGE_SIZE, 0, VM_MEMATTR_DEFAULT); 277 if ((flags & DMAR_PGF_OBJL) == 0) 278 VM_OBJECT_WUNLOCK(obj); 279 if (m != NULL) { 280 if (zeroed && (m->flags & PG_ZERO) == 0) 281 pmap_zero_page(m); 282 atomic_add_int(&dmar_tbl_pagecnt, 1); 283 break; 284 } 285 if ((flags & DMAR_PGF_WAITOK) == 0) 286 break; 287 } 288 return (m); 289} 290 291void 292dmar_pgfree(vm_object_t obj, vm_pindex_t idx, int flags) 293{ 294 vm_page_t m; 295 296 if ((flags & DMAR_PGF_OBJL) == 0) 297 VM_OBJECT_WLOCK(obj); 298 m = vm_page_lookup(obj, idx); 299 if (m != NULL) { 300 vm_page_free(m); 301 atomic_subtract_int(&dmar_tbl_pagecnt, 1); 302 } 303 if ((flags & DMAR_PGF_OBJL) == 0) 304 VM_OBJECT_WUNLOCK(obj); 305} 306 307void * 308dmar_map_pgtbl(vm_object_t obj, vm_pindex_t idx, int flags, 309 struct sf_buf **sf) 310{ 311 vm_page_t m; 312 bool allocated; 313 314 if ((flags & DMAR_PGF_OBJL) == 0) 315 VM_OBJECT_WLOCK(obj); 316 m = vm_page_lookup(obj, idx); 317 if (m == NULL && (flags & DMAR_PGF_ALLOC) != 0) { 318 m = dmar_pgalloc(obj, idx, flags | DMAR_PGF_OBJL); 319 allocated = true; 320 } else 321 allocated = false; 322 if (m == NULL) { 323 if ((flags & DMAR_PGF_OBJL) == 0) 324 VM_OBJECT_WUNLOCK(obj); 325 return (NULL); 326 } 327 /* Sleepable allocations cannot fail. */ 328 if ((flags & DMAR_PGF_WAITOK) != 0) 329 VM_OBJECT_WUNLOCK(obj); 330 sched_pin(); 331 *sf = sf_buf_alloc(m, SFB_CPUPRIVATE | ((flags & DMAR_PGF_WAITOK) 332 == 0 ? SFB_NOWAIT : 0)); 333 if (*sf == NULL) { 334 sched_unpin(); 335 if (allocated) { 336 VM_OBJECT_ASSERT_WLOCKED(obj); 337 dmar_pgfree(obj, m->pindex, flags | DMAR_PGF_OBJL); 338 } 339 if ((flags & DMAR_PGF_OBJL) == 0) 340 VM_OBJECT_WUNLOCK(obj); 341 return (NULL); 342 } 343 if ((flags & (DMAR_PGF_WAITOK | DMAR_PGF_OBJL)) == 344 (DMAR_PGF_WAITOK | DMAR_PGF_OBJL)) 345 VM_OBJECT_WLOCK(obj); 346 else if ((flags & (DMAR_PGF_WAITOK | DMAR_PGF_OBJL)) == 0) 347 VM_OBJECT_WUNLOCK(obj); 348 return ((void *)sf_buf_kva(*sf)); 349} 350 351void 352dmar_unmap_pgtbl(struct sf_buf *sf) 353{ 354 355 sf_buf_free(sf); 356 sched_unpin(); 357} 358 359static void 360dmar_flush_transl_to_ram(struct dmar_unit *unit, void *dst, size_t sz) 361{ 362 363 if (DMAR_IS_COHERENT(unit)) 364 return; 365 /* 366 * If DMAR does not snoop paging structures accesses, flush 367 * CPU cache to memory. 368 */ 369 pmap_invalidate_cache_range((uintptr_t)dst, (uintptr_t)dst + sz, 370 TRUE); 371} 372 373void 374dmar_flush_pte_to_ram(struct dmar_unit *unit, dmar_pte_t *dst) 375{ 376 377 dmar_flush_transl_to_ram(unit, dst, sizeof(*dst)); 378} 379 380void 381dmar_flush_ctx_to_ram(struct dmar_unit *unit, dmar_ctx_entry_t *dst) 382{ 383 384 dmar_flush_transl_to_ram(unit, dst, sizeof(*dst)); 385} 386 387void 388dmar_flush_root_to_ram(struct dmar_unit *unit, dmar_root_entry_t *dst) 389{ 390 391 dmar_flush_transl_to_ram(unit, dst, sizeof(*dst)); 392} 393 394/* 395 * Load the root entry pointer into the hardware, busily waiting for 396 * the completion. 397 */ 398int 399dmar_load_root_entry_ptr(struct dmar_unit *unit) 400{ 401 vm_page_t root_entry; 402 int error; 403 404 /* 405 * Access to the GCMD register must be serialized while the 406 * command is submitted. 407 */ 408 DMAR_ASSERT_LOCKED(unit); 409 410 VM_OBJECT_RLOCK(unit->ctx_obj); 411 root_entry = vm_page_lookup(unit->ctx_obj, 0); 412 VM_OBJECT_RUNLOCK(unit->ctx_obj); 413 dmar_write8(unit, DMAR_RTADDR_REG, VM_PAGE_TO_PHYS(root_entry)); 414 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_SRTP); 415 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_RTPS) 416 != 0)); 417 return (error); 418} 419 420/* 421 * Globally invalidate the context entries cache, busily waiting for 422 * the completion. 423 */ 424int 425dmar_inv_ctx_glob(struct dmar_unit *unit) 426{ 427 int error; 428 429 /* 430 * Access to the CCMD register must be serialized while the 431 * command is submitted. 432 */ 433 DMAR_ASSERT_LOCKED(unit); 434 KASSERT(!unit->qi_enabled, ("QI enabled")); 435 436 /* 437 * The DMAR_CCMD_ICC bit in the upper dword should be written 438 * after the low dword write is completed. Amd64 439 * dmar_write8() does not have this issue, i386 dmar_write8() 440 * writes the upper dword last. 441 */ 442 dmar_write8(unit, DMAR_CCMD_REG, DMAR_CCMD_ICC | DMAR_CCMD_CIRG_GLOB); 443 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_CCMD_REG + 4) & DMAR_CCMD_ICC32) 444 == 0)); 445 return (error); 446} 447 448/* 449 * Globally invalidate the IOTLB, busily waiting for the completion. 450 */ 451int 452dmar_inv_iotlb_glob(struct dmar_unit *unit) 453{ 454 int error, reg; 455 456 DMAR_ASSERT_LOCKED(unit); 457 KASSERT(!unit->qi_enabled, ("QI enabled")); 458 459 reg = 16 * DMAR_ECAP_IRO(unit->hw_ecap); 460 /* See a comment about DMAR_CCMD_ICC in dmar_inv_ctx_glob. */ 461 dmar_write8(unit, reg + DMAR_IOTLB_REG_OFF, DMAR_IOTLB_IVT | 462 DMAR_IOTLB_IIRG_GLB | DMAR_IOTLB_DR | DMAR_IOTLB_DW); 463 DMAR_WAIT_UNTIL(((dmar_read4(unit, reg + DMAR_IOTLB_REG_OFF + 4) & 464 DMAR_IOTLB_IVT32) == 0)); 465 return (error); 466} 467 468/* 469 * Flush the chipset write buffers. See 11.1 "Write Buffer Flushing" 470 * in the architecture specification. 471 */ 472int 473dmar_flush_write_bufs(struct dmar_unit *unit) 474{ 475 int error; 476 477 DMAR_ASSERT_LOCKED(unit); 478 479 /* 480 * DMAR_GCMD_WBF is only valid when CAP_RWBF is reported. 481 */ 482 KASSERT((unit->hw_cap & DMAR_CAP_RWBF) != 0, 483 ("dmar%d: no RWBF", unit->unit)); 484 485 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_WBF); 486 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_WBFS) 487 != 0)); 488 return (error); 489} 490 491int 492dmar_enable_translation(struct dmar_unit *unit) 493{ 494 int error; 495 496 DMAR_ASSERT_LOCKED(unit); 497 unit->hw_gcmd |= DMAR_GCMD_TE; 498 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd); 499 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_TES) 500 != 0)); 501 return (error); 502} 503 504int 505dmar_disable_translation(struct dmar_unit *unit) 506{ 507 int error; 508 509 DMAR_ASSERT_LOCKED(unit); 510 unit->hw_gcmd &= ~DMAR_GCMD_TE; 511 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd); 512 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_TES) 513 == 0)); 514 return (error); 515} 516 517int 518dmar_load_irt_ptr(struct dmar_unit *unit) 519{ 520 uint64_t irta, s; 521 int error; 522 523 DMAR_ASSERT_LOCKED(unit); 524 irta = unit->irt_phys; 525 if (DMAR_X2APIC(unit)) 526 irta |= DMAR_IRTA_EIME; 527 s = fls(unit->irte_cnt) - 2; 528 KASSERT(unit->irte_cnt >= 2 && s <= DMAR_IRTA_S_MASK && 529 powerof2(unit->irte_cnt), 530 ("IRTA_REG_S overflow %x", unit->irte_cnt)); 531 irta |= s; 532 dmar_write8(unit, DMAR_IRTA_REG, irta); 533 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_SIRTP); 534 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRTPS) 535 != 0)); 536 return (error); 537} 538 539int 540dmar_enable_ir(struct dmar_unit *unit) 541{ 542 int error; 543 544 DMAR_ASSERT_LOCKED(unit); 545 unit->hw_gcmd |= DMAR_GCMD_IRE; 546 unit->hw_gcmd &= ~DMAR_GCMD_CFI; 547 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd); 548 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRES) 549 != 0)); 550 return (error); 551} 552 553int 554dmar_disable_ir(struct dmar_unit *unit) 555{ 556 int error; 557 558 DMAR_ASSERT_LOCKED(unit); 559 unit->hw_gcmd &= ~DMAR_GCMD_IRE; 560 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd); 561 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRES) 562 == 0)); 563 return (error); 564} 565 566#define BARRIER_F \ 567 u_int f_done, f_inproc, f_wakeup; \ 568 \ 569 f_done = 1 << (barrier_id * 3); \ 570 f_inproc = 1 << (barrier_id * 3 + 1); \ 571 f_wakeup = 1 << (barrier_id * 3 + 2) 572 573bool 574dmar_barrier_enter(struct dmar_unit *dmar, u_int barrier_id) 575{ 576 BARRIER_F; 577 578 DMAR_LOCK(dmar); 579 if ((dmar->barrier_flags & f_done) != 0) { 580 DMAR_UNLOCK(dmar); 581 return (false); 582 } 583 584 if ((dmar->barrier_flags & f_inproc) != 0) { 585 while ((dmar->barrier_flags & f_inproc) != 0) { 586 dmar->barrier_flags |= f_wakeup; 587 msleep(&dmar->barrier_flags, &dmar->lock, 0, 588 "dmarb", 0); 589 } 590 KASSERT((dmar->barrier_flags & f_done) != 0, 591 ("dmar%d barrier %d missing done", dmar->unit, barrier_id)); 592 DMAR_UNLOCK(dmar); 593 return (false); 594 } 595 596 dmar->barrier_flags |= f_inproc; 597 DMAR_UNLOCK(dmar); 598 return (true); 599} 600 601void 602dmar_barrier_exit(struct dmar_unit *dmar, u_int barrier_id) 603{ 604 BARRIER_F; 605 606 DMAR_ASSERT_LOCKED(dmar); 607 KASSERT((dmar->barrier_flags & (f_done | f_inproc)) == f_inproc, 608 ("dmar%d barrier %d missed entry", dmar->unit, barrier_id)); 609 dmar->barrier_flags |= f_done; 610 if ((dmar->barrier_flags & f_wakeup) != 0) 611 wakeup(&dmar->barrier_flags); 612 dmar->barrier_flags &= ~(f_inproc | f_wakeup); 613 DMAR_UNLOCK(dmar); 614} 615 616int dmar_match_verbose; 617int dmar_batch_coalesce = 100; 618struct timespec dmar_hw_timeout = { 619 .tv_sec = 0, 620 .tv_nsec = 1000000 621}; 622 623static const uint64_t d = 1000000000; 624 625void 626dmar_update_timeout(uint64_t newval) 627{ 628 629 /* XXXKIB not atomic */ 630 dmar_hw_timeout.tv_sec = newval / d; 631 dmar_hw_timeout.tv_nsec = newval % d; 632} 633 634uint64_t 635dmar_get_timeout(void) 636{ 637 638 return ((uint64_t)dmar_hw_timeout.tv_sec * d + 639 dmar_hw_timeout.tv_nsec); 640} 641 642static int 643dmar_timeout_sysctl(SYSCTL_HANDLER_ARGS) 644{ 645 uint64_t val; 646 int error; 647 648 val = dmar_get_timeout(); 649 error = sysctl_handle_long(oidp, &val, 0, req); 650 if (error != 0 || req->newptr == NULL) 651 return (error); 652 dmar_update_timeout(val); 653 return (error); 654} 655 656static SYSCTL_NODE(_hw, OID_AUTO, dmar, CTLFLAG_RD, NULL, ""); 657SYSCTL_INT(_hw_dmar, OID_AUTO, tbl_pagecnt, CTLFLAG_RD, 658 &dmar_tbl_pagecnt, 0, 659 "Count of pages used for DMAR pagetables"); 660SYSCTL_INT(_hw_dmar, OID_AUTO, match_verbose, CTLFLAG_RWTUN, 661 &dmar_match_verbose, 0, 662 "Verbose matching of the PCI devices to DMAR paths"); 663SYSCTL_INT(_hw_dmar, OID_AUTO, batch_coalesce, CTLFLAG_RWTUN, 664 &dmar_batch_coalesce, 0, 665 "Number of qi batches between interrupt"); 666SYSCTL_PROC(_hw_dmar, OID_AUTO, timeout, 667 CTLTYPE_U64 | CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 0, 668 dmar_timeout_sysctl, "QU", 669 "Timeout for command wait, in nanoseconds"); 670#ifdef INVARIANTS 671int dmar_check_free; 672SYSCTL_INT(_hw_dmar, OID_AUTO, check_free, CTLFLAG_RWTUN, 673 &dmar_check_free, 0, 674 "Check the GPA RBtree for free_down and free_after validity"); 675#endif 676 677