intel_dmar.h revision 316449
1/*- 2 * Copyright (c) 2013-2015 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 6 * under sponsorship from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: stable/11/sys/x86/iommu/intel_dmar.h 316449 2017-04-03 09:41:43Z kib $ 30 */ 31 32#ifndef __X86_IOMMU_INTEL_DMAR_H 33#define __X86_IOMMU_INTEL_DMAR_H 34 35/* Host or physical memory address, after translation. */ 36typedef uint64_t dmar_haddr_t; 37/* Guest or bus address, before translation. */ 38typedef uint64_t dmar_gaddr_t; 39 40struct dmar_qi_genseq { 41 u_int gen; 42 uint32_t seq; 43}; 44 45struct dmar_map_entry { 46 dmar_gaddr_t start; 47 dmar_gaddr_t end; 48 dmar_gaddr_t free_after; /* Free space after the entry */ 49 dmar_gaddr_t free_down; /* Max free space below the 50 current R/B tree node */ 51 u_int flags; 52 TAILQ_ENTRY(dmar_map_entry) dmamap_link; /* Link for dmamap entries */ 53 RB_ENTRY(dmar_map_entry) rb_entry; /* Links for domain entries */ 54 TAILQ_ENTRY(dmar_map_entry) unroll_link; /* Link for unroll after 55 dmamap_load failure */ 56 struct dmar_domain *domain; 57 struct dmar_qi_genseq gseq; 58}; 59 60RB_HEAD(dmar_gas_entries_tree, dmar_map_entry); 61RB_PROTOTYPE(dmar_gas_entries_tree, dmar_map_entry, rb_entry, 62 dmar_gas_cmp_entries); 63 64#define DMAR_MAP_ENTRY_PLACE 0x0001 /* Fake entry */ 65#define DMAR_MAP_ENTRY_RMRR 0x0002 /* Permanent, not linked by 66 dmamap_link */ 67#define DMAR_MAP_ENTRY_MAP 0x0004 /* Busdma created, linked by 68 dmamap_link */ 69#define DMAR_MAP_ENTRY_UNMAPPED 0x0010 /* No backing pages */ 70#define DMAR_MAP_ENTRY_QI_NF 0x0020 /* qi task, do not free entry */ 71#define DMAR_MAP_ENTRY_READ 0x1000 /* Read permitted */ 72#define DMAR_MAP_ENTRY_WRITE 0x2000 /* Write permitted */ 73#define DMAR_MAP_ENTRY_SNOOP 0x4000 /* Snoop */ 74#define DMAR_MAP_ENTRY_TM 0x8000 /* Transient */ 75 76/* 77 * Locking annotations: 78 * (u) - Protected by dmar unit lock 79 * (d) - Protected by domain lock 80 * (c) - Immutable after initialization 81 */ 82 83/* 84 * The domain abstraction. Most non-constant members of the domain 85 * are protected by owning dmar unit lock, not by the domain lock. 86 * Most important, the dmar lock protects the contexts list. 87 * 88 * The domain lock protects the address map for the domain, and list 89 * of unload entries delayed. 90 * 91 * Page tables pages and pages content is protected by the vm object 92 * lock pgtbl_obj, which contains the page tables pages. 93 */ 94struct dmar_domain { 95 int domain; /* (c) DID, written in context entry */ 96 int mgaw; /* (c) Real max address width */ 97 int agaw; /* (c) Adjusted guest address width */ 98 int pglvl; /* (c) The pagelevel */ 99 int awlvl; /* (c) The pagelevel as the bitmask, 100 to set in context entry */ 101 dmar_gaddr_t end; /* (c) Highest address + 1 in 102 the guest AS */ 103 u_int ctx_cnt; /* (u) Number of contexts owned */ 104 u_int refs; /* (u) Refs, including ctx */ 105 struct dmar_unit *dmar; /* (c) */ 106 struct mtx lock; /* (c) */ 107 LIST_ENTRY(dmar_domain) link; /* (u) Member in the dmar list */ 108 LIST_HEAD(, dmar_ctx) contexts; /* (u) */ 109 vm_object_t pgtbl_obj; /* (c) Page table pages */ 110 u_int flags; /* (u) */ 111 u_int entries_cnt; /* (d) */ 112 struct dmar_gas_entries_tree rb_root; /* (d) */ 113 struct dmar_map_entries_tailq unload_entries; /* (d) Entries to 114 unload */ 115 struct dmar_map_entry *first_place, *last_place; /* (d) */ 116 struct task unload_task; /* (c) */ 117 u_int batch_no; 118}; 119 120struct dmar_ctx { 121 struct bus_dma_tag_dmar ctx_tag; /* (c) Root tag */ 122 uint16_t rid; /* (c) pci RID */ 123 uint64_t last_fault_rec[2]; /* Last fault reported */ 124 struct dmar_domain *domain; /* (c) */ 125 LIST_ENTRY(dmar_ctx) link; /* (u) Member in the domain list */ 126 u_int refs; /* (u) References from tags */ 127 u_int flags; /* (u) */ 128 u_long loads; /* atomic updates, for stat only */ 129 u_long unloads; /* same */ 130}; 131 132#define DMAR_DOMAIN_GAS_INITED 0x0001 133#define DMAR_DOMAIN_PGTBL_INITED 0x0002 134#define DMAR_DOMAIN_IDMAP 0x0010 /* Domain uses identity 135 page table */ 136#define DMAR_DOMAIN_RMRR 0x0020 /* Domain contains RMRR entry, 137 cannot be turned off */ 138 139/* struct dmar_ctx flags */ 140#define DMAR_CTX_FAULTED 0x0001 /* Fault was reported, 141 last_fault_rec is valid */ 142#define DMAR_CTX_DISABLED 0x0002 /* Device is disabled, the 143 ephemeral reference is kept 144 to prevent context destruction */ 145 146#define DMAR_DOMAIN_PGLOCK(dom) VM_OBJECT_WLOCK((dom)->pgtbl_obj) 147#define DMAR_DOMAIN_PGTRYLOCK(dom) VM_OBJECT_TRYWLOCK((dom)->pgtbl_obj) 148#define DMAR_DOMAIN_PGUNLOCK(dom) VM_OBJECT_WUNLOCK((dom)->pgtbl_obj) 149#define DMAR_DOMAIN_ASSERT_PGLOCKED(dom) \ 150 VM_OBJECT_ASSERT_WLOCKED((dom)->pgtbl_obj) 151 152#define DMAR_DOMAIN_LOCK(dom) mtx_lock(&(dom)->lock) 153#define DMAR_DOMAIN_UNLOCK(dom) mtx_unlock(&(dom)->lock) 154#define DMAR_DOMAIN_ASSERT_LOCKED(dom) mtx_assert(&(dom)->lock, MA_OWNED) 155 156struct dmar_msi_data { 157 int irq; 158 int irq_rid; 159 struct resource *irq_res; 160 void *intr_handle; 161 int (*handler)(void *); 162 int msi_data_reg; 163 int msi_addr_reg; 164 int msi_uaddr_reg; 165 void (*enable_intr)(struct dmar_unit *); 166 void (*disable_intr)(struct dmar_unit *); 167 const char *name; 168}; 169 170#define DMAR_INTR_FAULT 0 171#define DMAR_INTR_QI 1 172#define DMAR_INTR_TOTAL 2 173 174struct dmar_unit { 175 device_t dev; 176 int unit; 177 uint16_t segment; 178 uint64_t base; 179 180 /* Resources */ 181 int reg_rid; 182 struct resource *regs; 183 184 struct dmar_msi_data intrs[DMAR_INTR_TOTAL]; 185 186 /* Hardware registers cache */ 187 uint32_t hw_ver; 188 uint64_t hw_cap; 189 uint64_t hw_ecap; 190 uint32_t hw_gcmd; 191 192 /* Data for being a dmar */ 193 struct mtx lock; 194 LIST_HEAD(, dmar_domain) domains; 195 struct unrhdr *domids; 196 vm_object_t ctx_obj; 197 u_int barrier_flags; 198 199 /* Fault handler data */ 200 struct mtx fault_lock; 201 uint64_t *fault_log; 202 int fault_log_head; 203 int fault_log_tail; 204 int fault_log_size; 205 struct task fault_task; 206 struct taskqueue *fault_taskqueue; 207 208 /* QI */ 209 int qi_enabled; 210 vm_offset_t inv_queue; 211 vm_size_t inv_queue_size; 212 uint32_t inv_queue_avail; 213 uint32_t inv_queue_tail; 214 volatile uint32_t inv_waitd_seq_hw; /* hw writes there on wait 215 descr completion */ 216 uint64_t inv_waitd_seq_hw_phys; 217 uint32_t inv_waitd_seq; /* next sequence number to use for wait descr */ 218 u_int inv_waitd_gen; /* seq number generation AKA seq overflows */ 219 u_int inv_seq_waiters; /* count of waiters for seq */ 220 u_int inv_queue_full; /* informational counter */ 221 222 /* IR */ 223 int ir_enabled; 224 vm_paddr_t irt_phys; 225 dmar_irte_t *irt; 226 u_int irte_cnt; 227 vmem_t *irtids; 228 229 /* Delayed freeing of map entries queue processing */ 230 struct dmar_map_entries_tailq tlb_flush_entries; 231 struct task qi_task; 232 struct taskqueue *qi_taskqueue; 233 234 /* Busdma delayed map load */ 235 struct task dmamap_load_task; 236 TAILQ_HEAD(, bus_dmamap_dmar) delayed_maps; 237 struct taskqueue *delayed_taskqueue; 238 239 int dma_enabled; 240}; 241 242#define DMAR_LOCK(dmar) mtx_lock(&(dmar)->lock) 243#define DMAR_UNLOCK(dmar) mtx_unlock(&(dmar)->lock) 244#define DMAR_ASSERT_LOCKED(dmar) mtx_assert(&(dmar)->lock, MA_OWNED) 245 246#define DMAR_FAULT_LOCK(dmar) mtx_lock_spin(&(dmar)->fault_lock) 247#define DMAR_FAULT_UNLOCK(dmar) mtx_unlock_spin(&(dmar)->fault_lock) 248#define DMAR_FAULT_ASSERT_LOCKED(dmar) mtx_assert(&(dmar)->fault_lock, MA_OWNED) 249 250#define DMAR_IS_COHERENT(dmar) (((dmar)->hw_ecap & DMAR_ECAP_C) != 0) 251#define DMAR_HAS_QI(dmar) (((dmar)->hw_ecap & DMAR_ECAP_QI) != 0) 252#define DMAR_X2APIC(dmar) \ 253 (x2apic_mode && ((dmar)->hw_ecap & DMAR_ECAP_EIM) != 0) 254 255/* Barrier ids */ 256#define DMAR_BARRIER_RMRR 0 257#define DMAR_BARRIER_USEQ 1 258 259struct dmar_unit *dmar_find(device_t dev); 260struct dmar_unit *dmar_find_hpet(device_t dev, uint16_t *rid); 261struct dmar_unit *dmar_find_ioapic(u_int apic_id, uint16_t *rid); 262 263u_int dmar_nd2mask(u_int nd); 264bool dmar_pglvl_supported(struct dmar_unit *unit, int pglvl); 265int domain_set_agaw(struct dmar_domain *domain, int mgaw); 266int dmar_maxaddr2mgaw(struct dmar_unit *unit, dmar_gaddr_t maxaddr, 267 bool allow_less); 268vm_pindex_t pglvl_max_pages(int pglvl); 269int domain_is_sp_lvl(struct dmar_domain *domain, int lvl); 270dmar_gaddr_t pglvl_page_size(int total_pglvl, int lvl); 271dmar_gaddr_t domain_page_size(struct dmar_domain *domain, int lvl); 272int calc_am(struct dmar_unit *unit, dmar_gaddr_t base, dmar_gaddr_t size, 273 dmar_gaddr_t *isizep); 274struct vm_page *dmar_pgalloc(vm_object_t obj, vm_pindex_t idx, int flags); 275void dmar_pgfree(vm_object_t obj, vm_pindex_t idx, int flags); 276void *dmar_map_pgtbl(vm_object_t obj, vm_pindex_t idx, int flags, 277 struct sf_buf **sf); 278void dmar_unmap_pgtbl(struct sf_buf *sf); 279int dmar_load_root_entry_ptr(struct dmar_unit *unit); 280int dmar_inv_ctx_glob(struct dmar_unit *unit); 281int dmar_inv_iotlb_glob(struct dmar_unit *unit); 282int dmar_flush_write_bufs(struct dmar_unit *unit); 283void dmar_flush_pte_to_ram(struct dmar_unit *unit, dmar_pte_t *dst); 284void dmar_flush_ctx_to_ram(struct dmar_unit *unit, dmar_ctx_entry_t *dst); 285void dmar_flush_root_to_ram(struct dmar_unit *unit, dmar_root_entry_t *dst); 286int dmar_enable_translation(struct dmar_unit *unit); 287int dmar_disable_translation(struct dmar_unit *unit); 288int dmar_load_irt_ptr(struct dmar_unit *unit); 289int dmar_enable_ir(struct dmar_unit *unit); 290int dmar_disable_ir(struct dmar_unit *unit); 291bool dmar_barrier_enter(struct dmar_unit *dmar, u_int barrier_id); 292void dmar_barrier_exit(struct dmar_unit *dmar, u_int barrier_id); 293uint64_t dmar_get_timeout(void); 294void dmar_update_timeout(uint64_t newval); 295 296int dmar_fault_intr(void *arg); 297void dmar_enable_fault_intr(struct dmar_unit *unit); 298void dmar_disable_fault_intr(struct dmar_unit *unit); 299int dmar_init_fault_log(struct dmar_unit *unit); 300void dmar_fini_fault_log(struct dmar_unit *unit); 301 302int dmar_qi_intr(void *arg); 303void dmar_enable_qi_intr(struct dmar_unit *unit); 304void dmar_disable_qi_intr(struct dmar_unit *unit); 305int dmar_init_qi(struct dmar_unit *unit); 306void dmar_fini_qi(struct dmar_unit *unit); 307void dmar_qi_invalidate_locked(struct dmar_domain *domain, dmar_gaddr_t start, 308 dmar_gaddr_t size, struct dmar_qi_genseq *pseq); 309void dmar_qi_invalidate_ctx_glob_locked(struct dmar_unit *unit); 310void dmar_qi_invalidate_iotlb_glob_locked(struct dmar_unit *unit); 311void dmar_qi_invalidate_iec_glob(struct dmar_unit *unit); 312void dmar_qi_invalidate_iec(struct dmar_unit *unit, u_int start, u_int cnt); 313 314vm_object_t domain_get_idmap_pgtbl(struct dmar_domain *domain, 315 dmar_gaddr_t maxaddr); 316void put_idmap_pgtbl(vm_object_t obj); 317int domain_map_buf(struct dmar_domain *domain, dmar_gaddr_t base, 318 dmar_gaddr_t size, vm_page_t *ma, uint64_t pflags, int flags); 319int domain_unmap_buf(struct dmar_domain *domain, dmar_gaddr_t base, 320 dmar_gaddr_t size, int flags); 321void domain_flush_iotlb_sync(struct dmar_domain *domain, dmar_gaddr_t base, 322 dmar_gaddr_t size); 323int domain_alloc_pgtbl(struct dmar_domain *domain); 324void domain_free_pgtbl(struct dmar_domain *domain); 325 326struct dmar_ctx *dmar_instantiate_ctx(struct dmar_unit *dmar, device_t dev, 327 bool rmrr); 328struct dmar_ctx *dmar_get_ctx_for_dev(struct dmar_unit *dmar, device_t dev, 329 uint16_t rid, bool id_mapped, bool rmrr_init); 330int dmar_move_ctx_to_domain(struct dmar_domain *domain, struct dmar_ctx *ctx); 331void dmar_free_ctx_locked(struct dmar_unit *dmar, struct dmar_ctx *ctx); 332void dmar_free_ctx(struct dmar_ctx *ctx); 333struct dmar_ctx *dmar_find_ctx_locked(struct dmar_unit *dmar, uint16_t rid); 334void dmar_domain_unload_entry(struct dmar_map_entry *entry, bool free); 335void dmar_domain_unload(struct dmar_domain *domain, 336 struct dmar_map_entries_tailq *entries, bool cansleep); 337void dmar_domain_free_entry(struct dmar_map_entry *entry, bool free); 338 339int dmar_init_busdma(struct dmar_unit *unit); 340void dmar_fini_busdma(struct dmar_unit *unit); 341device_t dmar_get_requester(device_t dev, uint16_t *rid); 342 343void dmar_gas_init_domain(struct dmar_domain *domain); 344void dmar_gas_fini_domain(struct dmar_domain *domain); 345struct dmar_map_entry *dmar_gas_alloc_entry(struct dmar_domain *domain, 346 u_int flags); 347void dmar_gas_free_entry(struct dmar_domain *domain, 348 struct dmar_map_entry *entry); 349void dmar_gas_free_space(struct dmar_domain *domain, 350 struct dmar_map_entry *entry); 351int dmar_gas_map(struct dmar_domain *domain, 352 const struct bus_dma_tag_common *common, dmar_gaddr_t size, int offset, 353 u_int eflags, u_int flags, vm_page_t *ma, struct dmar_map_entry **res); 354void dmar_gas_free_region(struct dmar_domain *domain, 355 struct dmar_map_entry *entry); 356int dmar_gas_map_region(struct dmar_domain *domain, 357 struct dmar_map_entry *entry, u_int eflags, u_int flags, vm_page_t *ma); 358int dmar_gas_reserve_region(struct dmar_domain *domain, dmar_gaddr_t start, 359 dmar_gaddr_t end); 360 361void dmar_dev_parse_rmrr(struct dmar_domain *domain, device_t dev, 362 struct dmar_map_entries_tailq *rmrr_entries); 363int dmar_instantiate_rmrr_ctxs(struct dmar_unit *dmar); 364 365void dmar_quirks_post_ident(struct dmar_unit *dmar); 366void dmar_quirks_pre_use(struct dmar_unit *dmar); 367 368int dmar_init_irt(struct dmar_unit *unit); 369void dmar_fini_irt(struct dmar_unit *unit); 370 371#define DMAR_GM_CANWAIT 0x0001 372#define DMAR_GM_CANSPLIT 0x0002 373 374#define DMAR_PGF_WAITOK 0x0001 375#define DMAR_PGF_ZERO 0x0002 376#define DMAR_PGF_ALLOC 0x0004 377#define DMAR_PGF_NOALLOC 0x0008 378#define DMAR_PGF_OBJL 0x0010 379 380extern dmar_haddr_t dmar_high; 381extern int haw; 382extern int dmar_tbl_pagecnt; 383extern int dmar_match_verbose; 384extern int dmar_batch_coalesce; 385extern int dmar_check_free; 386 387static inline uint32_t 388dmar_read4(const struct dmar_unit *unit, int reg) 389{ 390 391 return (bus_read_4(unit->regs, reg)); 392} 393 394static inline uint64_t 395dmar_read8(const struct dmar_unit *unit, int reg) 396{ 397#ifdef __i386__ 398 uint32_t high, low; 399 400 low = bus_read_4(unit->regs, reg); 401 high = bus_read_4(unit->regs, reg + 4); 402 return (low | ((uint64_t)high << 32)); 403#else 404 return (bus_read_8(unit->regs, reg)); 405#endif 406} 407 408static inline void 409dmar_write4(const struct dmar_unit *unit, int reg, uint32_t val) 410{ 411 412 KASSERT(reg != DMAR_GCMD_REG || (val & DMAR_GCMD_TE) == 413 (unit->hw_gcmd & DMAR_GCMD_TE), 414 ("dmar%d clearing TE 0x%08x 0x%08x", unit->unit, 415 unit->hw_gcmd, val)); 416 bus_write_4(unit->regs, reg, val); 417} 418 419static inline void 420dmar_write8(const struct dmar_unit *unit, int reg, uint64_t val) 421{ 422 423 KASSERT(reg != DMAR_GCMD_REG, ("8byte GCMD write")); 424#ifdef __i386__ 425 uint32_t high, low; 426 427 low = val; 428 high = val >> 32; 429 bus_write_4(unit->regs, reg, low); 430 bus_write_4(unit->regs, reg + 4, high); 431#else 432 bus_write_8(unit->regs, reg, val); 433#endif 434} 435 436/* 437 * dmar_pte_store and dmar_pte_clear ensure that on i386, 32bit writes 438 * are issued in the correct order. For store, the lower word, 439 * containing the P or R and W bits, is set only after the high word 440 * is written. For clear, the P bit is cleared first, then the high 441 * word is cleared. 442 * 443 * dmar_pte_update updates the pte. For amd64, the update is atomic. 444 * For i386, it first disables the entry by clearing the word 445 * containing the P bit, and then defer to dmar_pte_store. The locked 446 * cmpxchg8b is probably available on any machine having DMAR support, 447 * but interrupt translation table may be mapped uncached. 448 */ 449static inline void 450dmar_pte_store1(volatile uint64_t *dst, uint64_t val) 451{ 452#ifdef __i386__ 453 volatile uint32_t *p; 454 uint32_t hi, lo; 455 456 hi = val >> 32; 457 lo = val; 458 p = (volatile uint32_t *)dst; 459 *(p + 1) = hi; 460 *p = lo; 461#else 462 *dst = val; 463#endif 464} 465 466static inline void 467dmar_pte_store(volatile uint64_t *dst, uint64_t val) 468{ 469 470 KASSERT(*dst == 0, ("used pte %p oldval %jx newval %jx", 471 dst, (uintmax_t)*dst, (uintmax_t)val)); 472 dmar_pte_store1(dst, val); 473} 474 475static inline void 476dmar_pte_update(volatile uint64_t *dst, uint64_t val) 477{ 478 479#ifdef __i386__ 480 volatile uint32_t *p; 481 482 p = (volatile uint32_t *)dst; 483 *p = 0; 484#endif 485 dmar_pte_store1(dst, val); 486} 487 488static inline void 489dmar_pte_clear(volatile uint64_t *dst) 490{ 491#ifdef __i386__ 492 volatile uint32_t *p; 493 494 p = (volatile uint32_t *)dst; 495 *p = 0; 496 *(p + 1) = 0; 497#else 498 *dst = 0; 499#endif 500} 501 502static inline bool 503dmar_test_boundary(dmar_gaddr_t start, dmar_gaddr_t size, 504 dmar_gaddr_t boundary) 505{ 506 507 if (boundary == 0) 508 return (true); 509 return (start + size <= ((start + boundary) & ~(boundary - 1))); 510} 511 512extern struct timespec dmar_hw_timeout; 513 514#define DMAR_WAIT_UNTIL(cond) \ 515{ \ 516 struct timespec last, curr; \ 517 bool forever; \ 518 \ 519 if (dmar_hw_timeout.tv_sec == 0 && \ 520 dmar_hw_timeout.tv_nsec == 0) { \ 521 forever = true; \ 522 } else { \ 523 forever = false; \ 524 nanouptime(&curr); \ 525 last = curr; \ 526 timespecadd(&last, &dmar_hw_timeout); \ 527 } \ 528 for (;;) { \ 529 if (cond) { \ 530 error = 0; \ 531 break; \ 532 } \ 533 nanouptime(&curr); \ 534 if (!forever && timespeccmp(&last, &curr, <)) { \ 535 error = ETIMEDOUT; \ 536 break; \ 537 } \ 538 cpu_spinwait(); \ 539 } \ 540} 541 542#ifdef INVARIANTS 543#define TD_PREP_PINNED_ASSERT \ 544 int old_td_pinned; \ 545 old_td_pinned = curthread->td_pinned 546#define TD_PINNED_ASSERT \ 547 KASSERT(curthread->td_pinned == old_td_pinned, \ 548 ("pin count leak: %d %d %s:%d", curthread->td_pinned, \ 549 old_td_pinned, __FILE__, __LINE__)) 550#else 551#define TD_PREP_PINNED_ASSERT 552#define TD_PINNED_ASSERT 553#endif 554 555#endif 556