intel_dmar.h revision 284869
12088Ssos/*- 2270653Sse * Copyright (c) 2013-2015 The FreeBSD Foundation 32088Ssos * All rights reserved. 42088Ssos * 52088Ssos * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 62088Ssos * under sponsorship from the FreeBSD Foundation. 72088Ssos * 82088Ssos * Redistribution and use in source and binary forms, with or without 92088Ssos * modification, are permitted provided that the following conditions 102088Ssos * are met: 112088Ssos * 1. Redistributions of source code must retain the above copyright 122088Ssos * notice, this list of conditions and the following disclaimer. 132088Ssos * 2. Redistributions in binary form must reproduce the above copyright 1450479Speter * notice, this list of conditions and the following disclaimer in the 152088Ssos * documentation and/or other materials provided with the distribution. 16296926Semaste * 1748586Syokota * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1877252Sdd * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1920780Smpp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2020780Smpp * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 2177329Sdes * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2220780Smpp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2320780Smpp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2477329Sdes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25148017Semax * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26148017Semax * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2771898Sru * SUCH DAMAGE. 2871898Sru * 2971898Sru * $FreeBSD: head/sys/x86/iommu/intel_dmar.h 284869 2015-06-26 07:01:29Z kib $ 3071898Sru */ 3171898Sru 3271898Sru#ifndef __X86_IOMMU_INTEL_DMAR_H 3371898Sru#define __X86_IOMMU_INTEL_DMAR_H 3471898Sru 3548586Syokota/* Host or physical memory address, after translation. */ 3620780Smpptypedef uint64_t dmar_haddr_t; 3749881Syokota/* Guest or bus address, before translation. */ 3848586Syokotatypedef uint64_t dmar_gaddr_t; 39296926Semaste 4020780Smppstruct dmar_qi_genseq { 412088Ssos u_int gen; 4229603Scharnier uint32_t seq; 4348586Syokota}; 4448586Syokota 45270653Ssestruct dmar_map_entry { 46270653Sse dmar_gaddr_t start; 4748586Syokota dmar_gaddr_t end; 4879755Sdd dmar_gaddr_t free_after; /* Free space after the entry */ 492088Ssos dmar_gaddr_t free_down; /* Max free space below the 5020780Smpp current R/B tree node */ 5148586Syokota u_int flags; 5248586Syokota TAILQ_ENTRY(dmar_map_entry) dmamap_link; /* Link for dmamap entries */ 5348586Syokota RB_ENTRY(dmar_map_entry) rb_entry; /* Links for domain entries */ 5448586Syokota TAILQ_ENTRY(dmar_map_entry) unroll_link; /* Link for unroll after 5548586Syokota dmamap_load failure */ 5648586Syokota struct dmar_domain *domain; 5748586Syokota struct dmar_qi_genseq gseq; 5820780Smpp}; 5929603Scharnier 60148017SemaxRB_HEAD(dmar_gas_entries_tree, dmar_map_entry); 61148017SemaxRB_PROTOTYPE(dmar_gas_entries_tree, dmar_map_entry, rb_entry, 62148017Semax dmar_gas_cmp_entries); 63148017Semax 64148017Semax#define DMAR_MAP_ENTRY_PLACE 0x0001 /* Fake entry */ 65148270Smarkus#define DMAR_MAP_ENTRY_RMRR 0x0002 /* Permanent, not linked by 66148270Smarkus dmamap_link */ 67148017Semax#define DMAR_MAP_ENTRY_MAP 0x0004 /* Busdma created, linked by 68148270Smarkus dmamap_link */ 69148017Semax#define DMAR_MAP_ENTRY_UNMAPPED 0x0010 /* No backing pages */ 70148017Semax#define DMAR_MAP_ENTRY_QI_NF 0x0020 /* qi task, do not free entry */ 71148017Semax#define DMAR_MAP_ENTRY_READ 0x1000 /* Read permitted */ 72148017Semax#define DMAR_MAP_ENTRY_WRITE 0x2000 /* Write permitted */ 73148017Semax#define DMAR_MAP_ENTRY_SNOOP 0x4000 /* Snoop */ 74148017Semax#define DMAR_MAP_ENTRY_TM 0x8000 /* Transient */ 75148270Smarkus 76148270Smarkus/* 77148017Semax * Locking annotations: 78148270Smarkus * (u) - Protected by dmar unit lock 79148017Semax * (d) - Protected by domain lock 8071898Sru * (c) - Immutable after initialization 8171898Sru */ 8271898Sru 8379755Sdd/* 8479755Sdd * The domain abstraction. Most non-constant members of the domain 8520780Smpp * are locked by the owning dmar unit lock, not by the domain lock. 8679755Sdd * Most important, dmar lock protects the contexts list. 8748586Syokota * 8848982Syokota * The domain lock protects the address map for the domain, and list 8948982Syokota * of unload entries delayed. 9048982Syokota * 9148586Syokota * Page tables pages and pages content is protected by the vm object 92131500Sru * lock pgtbl_obj, which contains the page tables pages. 9379755Sdd */ 9440256Syokotastruct dmar_domain { 9541491Sbillf int domain; /* (c) DID, written in context entry */ 9648586Syokota int mgaw; /* (c) Real max address width */ 9740256Syokota int agaw; /* (c) Adjusted guest address width */ 98164334Sru int pglvl; /* (c) The pagelevel */ 99164334Sru int awlvl; /* (c) The pagelevel as the bitmask, 100164336Sru to set in context entry */ 101164334Sru dmar_gaddr_t end; /* (c) Highest address + 1 in 10271898Sru the guest AS */ 10371898Sru u_int ctx_cnt; /* (u) Number of contexts owned */ 10471898Sru u_int refs; /* (u) Refs, including ctx */ 1052088Ssos struct dmar_unit *dmar; /* (c) */ 10660258Ssheldonh struct mtx lock; /* (c) */ 10760258Ssheldonh LIST_ENTRY(dmar_domain) link; /* (u) Member in the dmar list */ 1082088Ssos LIST_HEAD(, dmar_ctx) contexts; /* (u) */ 10960258Ssheldonh vm_object_t pgtbl_obj; /* (c) Page table pages */ 11079755Sdd u_int flags; /* (u) */ 11115955Swosch u_int entries_cnt; /* (d) */ 11215955Swosch struct dmar_gas_entries_tree rb_root; /* (d) */ 11320780Smpp struct dmar_map_entries_tailq unload_entries; /* (d) Entries to 11420780Smpp unload */ 11579755Sdd struct dmar_map_entry *first_place, *last_place; /* (d) */ 11648586Syokota struct task unload_task; /* (c) */ 11720780Smpp}; 11848586Syokota 11920780Smppstruct dmar_ctx { 1202088Ssos struct bus_dma_tag_dmar ctx_tag; /* (c) Root tag */ 12148586Syokota uint16_t rid; /* (c) pci RID */ 12229603Scharnier uint64_t last_fault_rec[2]; /* Last fault reported */ 12348586Syokota struct dmar_domain *domain; /* (c) */ 1242088Ssos LIST_ENTRY(dmar_ctx) link; /* (u) Member in the domain list */ 12548586Syokota u_int refs; /* (u) References from tags */ 12679755Sdd u_int flags; /* (u) */ 12748586Syokota u_long loads; /* atomic updates, for stat only */ 128175799Strhodes u_long unloads; /* same */ 129175799Strhodes}; 130175799Strhodes 13120780Smpp#define DMAR_DOMAIN_GAS_INITED 0x0001 13229603Scharnier#define DMAR_DOMAIN_PGTBL_INITED 0x0002 13348586Syokota#define DMAR_DOMAIN_IDMAP 0x0010 /* Domain uses identity 13448586Syokota page table */ 13548586Syokota#define DMAR_DOMAIN_RMRR 0x0020 /* Domain contains RMRR entry, 13648586Syokota cannot be turned off */ 13720780Smpp 1382088Ssos/* struct dmar_ctx flags */ 13920780Smpp#define DMAR_CTX_FAULTED 0x0001 /* Fault was reported, 1402088Ssos last_fault_rec is valid */ 14129603Scharnier#define DMAR_CTX_DISABLED 0x0002 /* Device is disabled, the 14248586Syokota ephemeral reference is kept 14381251Sru to prevent context destruction */ 14481251Sru 14548586Syokota#define DMAR_DOMAIN_PGLOCK(dom) VM_OBJECT_WLOCK((dom)->pgtbl_obj) 14620780Smpp#define DMAR_DOMAIN_PGTRYLOCK(dom) VM_OBJECT_TRYWLOCK((dom)->pgtbl_obj) 1472088Ssos#define DMAR_DOMAIN_PGUNLOCK(dom) VM_OBJECT_WUNLOCK((dom)->pgtbl_obj) 14820780Smpp#define DMAR_DOMAIN_ASSERT_PGLOCKED(dom) \ 1499202Srgrimes VM_OBJECT_ASSERT_WLOCKED((dom)->pgtbl_obj) 15049881Syokota 15149881Syokota#define DMAR_DOMAIN_LOCK(dom) mtx_lock(&(dom)->lock) 15249881Syokota#define DMAR_DOMAIN_UNLOCK(dom) mtx_unlock(&(dom)->lock) 15349881Syokota#define DMAR_DOMAIN_ASSERT_LOCKED(dom) mtx_assert(&(dom)->lock, MA_OWNED) 15449881Syokota 15549881Syokotastruct dmar_msi_data { 15649881Syokota int irq; 15749881Syokota int irq_rid; 15849881Syokota struct resource *irq_res; 15963549Sben void *intr_handle; 16063549Sben int (*handler)(void *); 16163549Sben int msi_data_reg; 16263549Sben int msi_addr_reg; 16363549Sben int msi_uaddr_reg; 16463549Sben void (*enable_intr)(struct dmar_unit *); 16563549Sben void (*disable_intr)(struct dmar_unit *); 16663549Sben const char *name; 16748586Syokota}; 16819569Sjoerg 16948586Syokota#define DMAR_INTR_FAULT 0 17079755Sdd#define DMAR_INTR_QI 1 17120780Smpp#define DMAR_INTR_TOTAL 2 17220780Smpp 17348586Syokotastruct dmar_unit { 17448586Syokota device_t dev; 175296926Semaste int unit; 176296926Semaste uint16_t segment; 177296926Semaste uint64_t base; 178296926Semaste 179296926Semaste /* Resources */ 180296926Semaste int reg_rid; 18129603Scharnier struct resource *regs; 18276502Ssobomax 18376671Sru struct dmar_msi_data intrs[DMAR_INTR_TOTAL]; 18476502Ssobomax 18576502Ssobomax /* Hardware registers cache */ 18648586Syokota uint32_t hw_ver; 18748586Syokota uint64_t hw_cap; 18848586Syokota uint64_t hw_ecap; 18948586Syokota uint32_t hw_gcmd; 19048586Syokota 19148586Syokota /* Data for being a dmar */ 19248586Syokota struct mtx lock; 19348586Syokota LIST_HEAD(, dmar_domain) domains; 19448586Syokota struct unrhdr *domids; 19548586Syokota vm_object_t ctx_obj; 19648586Syokota u_int barrier_flags; 19748586Syokota 19848586Syokota /* Fault handler data */ 19948586Syokota struct mtx fault_lock; 20048586Syokota uint64_t *fault_log; 20148586Syokota int fault_log_head; 20248586Syokota int fault_log_tail; 20348586Syokota int fault_log_size; 20448586Syokota struct task fault_task; 20548586Syokota struct taskqueue *fault_taskqueue; 20648586Syokota 20748586Syokota /* QI */ 20848586Syokota int qi_enabled; 20948586Syokota vm_offset_t inv_queue; 21048586Syokota vm_size_t inv_queue_size; 21179755Sdd uint32_t inv_queue_avail; 21248586Syokota uint32_t inv_queue_tail; 21348586Syokota volatile uint32_t inv_waitd_seq_hw; /* hw writes there on wait 21448586Syokota descr completion */ 21548586Syokota uint64_t inv_waitd_seq_hw_phys; 21648586Syokota uint32_t inv_waitd_seq; /* next sequence number to use for wait descr */ 21748586Syokota u_int inv_waitd_gen; /* seq number generation AKA seq overflows */ 21881251Sru u_int inv_seq_waiters; /* count of waiters for seq */ 21981251Sru u_int inv_queue_full; /* informational counter */ 22081251Sru 22148586Syokota /* IR */ 22220780Smpp int ir_enabled; 22348586Syokota vm_paddr_t irt_phys; 22448586Syokota dmar_irte_t *irt; 225270653Sse u_int irte_cnt; 226270653Sse vmem_t *irtids; 227270653Sse 22870403Sru /* Delayed freeing of map entries queue processing */ 22968854Sru struct dmar_map_entries_tailq tlb_flush_entries; 23048586Syokota struct task qi_task; 23148586Syokota struct taskqueue *qi_taskqueue; 23248586Syokota 23348586Syokota /* Busdma delayed map load */ 23448586Syokota struct task dmamap_load_task; 23548586Syokota TAILQ_HEAD(, bus_dmamap_dmar) delayed_maps; 236270653Sse struct taskqueue *delayed_taskqueue; 237270653Sse 238270653Sse int dma_enabled; 239270653Sse}; 240276360Sjoel 241270653Sse#define DMAR_LOCK(dmar) mtx_lock(&(dmar)->lock) 24248586Syokota#define DMAR_UNLOCK(dmar) mtx_unlock(&(dmar)->lock) 24348586Syokota#define DMAR_ASSERT_LOCKED(dmar) mtx_assert(&(dmar)->lock, MA_OWNED) 244270653Sse 245270653Sse#define DMAR_FAULT_LOCK(dmar) mtx_lock_spin(&(dmar)->fault_lock) 246270653Sse#define DMAR_FAULT_UNLOCK(dmar) mtx_unlock_spin(&(dmar)->fault_lock) 247270653Sse#define DMAR_FAULT_ASSERT_LOCKED(dmar) mtx_assert(&(dmar)->fault_lock, MA_OWNED) 248270653Sse 24948586Syokota#define DMAR_IS_COHERENT(dmar) (((dmar)->hw_ecap & DMAR_ECAP_C) != 0) 25048586Syokota#define DMAR_HAS_QI(dmar) (((dmar)->hw_ecap & DMAR_ECAP_QI) != 0) 25148586Syokota#define DMAR_X2APIC(dmar) \ 25248586Syokota (x2apic_mode && ((dmar)->hw_ecap & DMAR_ECAP_EIM) != 0) 25348586Syokota 25448586Syokota/* Barrier ids */ 25548586Syokota#define DMAR_BARRIER_RMRR 0 25648586Syokota#define DMAR_BARRIER_USEQ 1 257211172Solli 25848586Syokotastruct dmar_unit *dmar_find(device_t dev); 25948586Syokotastruct dmar_unit *dmar_find_hpet(device_t dev, uint16_t *rid); 26048586Syokotastruct dmar_unit *dmar_find_ioapic(u_int apic_id, uint16_t *rid); 26148586Syokota 262211172Solliu_int dmar_nd2mask(u_int nd); 26363549Sbenbool dmar_pglvl_supported(struct dmar_unit *unit, int pglvl); 26463549Sbenint domain_set_agaw(struct dmar_domain *domain, int mgaw); 265211172Solliint dmar_maxaddr2mgaw(struct dmar_unit *unit, dmar_gaddr_t maxaddr, 26663549Sben bool allow_less); 267139898Sbrooksvm_pindex_t pglvl_max_pages(int pglvl); 26863549Sbenint domain_is_sp_lvl(struct dmar_domain *domain, int lvl); 26963549Sbendmar_gaddr_t pglvl_page_size(int total_pglvl, int lvl); 27063549Sbendmar_gaddr_t domain_page_size(struct dmar_domain *domain, int lvl); 27163549Sbenint calc_am(struct dmar_unit *unit, dmar_gaddr_t base, dmar_gaddr_t size, 272153851Ssobomax dmar_gaddr_t *isizep); 273153851Ssobomaxstruct vm_page *dmar_pgalloc(vm_object_t obj, vm_pindex_t idx, int flags); 274162806Sruvoid dmar_pgfree(vm_object_t obj, vm_pindex_t idx, int flags); 275153851Ssobomaxvoid *dmar_map_pgtbl(vm_object_t obj, vm_pindex_t idx, int flags, 276162806Sru struct sf_buf **sf); 277162806Sruvoid dmar_unmap_pgtbl(struct sf_buf *sf); 278162806Sruint dmar_load_root_entry_ptr(struct dmar_unit *unit); 279162806Sruint dmar_inv_ctx_glob(struct dmar_unit *unit); 280162806Sruint dmar_inv_iotlb_glob(struct dmar_unit *unit); 281162806Sruint dmar_flush_write_bufs(struct dmar_unit *unit); 282162806Sruvoid dmar_flush_pte_to_ram(struct dmar_unit *unit, dmar_pte_t *dst); 28348586Syokotavoid dmar_flush_ctx_to_ram(struct dmar_unit *unit, dmar_ctx_entry_t *dst); 28448586Syokotavoid dmar_flush_root_to_ram(struct dmar_unit *unit, dmar_root_entry_t *dst); 28520780Smppint dmar_enable_translation(struct dmar_unit *unit); 28648586Syokotaint dmar_disable_translation(struct dmar_unit *unit); 287153851Ssobomaxint dmar_load_irt_ptr(struct dmar_unit *unit); 28820780Smppint dmar_enable_ir(struct dmar_unit *unit); 28948586Syokotaint dmar_disable_ir(struct dmar_unit *unit); 29048586Syokotabool dmar_barrier_enter(struct dmar_unit *dmar, u_int barrier_id); 29148586Syokotavoid dmar_barrier_exit(struct dmar_unit *dmar, u_int barrier_id); 292270653Sse 29365807Sdwmaloneint dmar_fault_intr(void *arg); 29461020Scharniervoid dmar_enable_fault_intr(struct dmar_unit *unit); 29520780Smppvoid dmar_disable_fault_intr(struct dmar_unit *unit); 296267668Sbaptint dmar_init_fault_log(struct dmar_unit *unit); 297140442Sruvoid dmar_fini_fault_log(struct dmar_unit *unit); 298140442Sru 299int dmar_qi_intr(void *arg); 300void dmar_enable_qi_intr(struct dmar_unit *unit); 301void dmar_disable_qi_intr(struct dmar_unit *unit); 302int dmar_init_qi(struct dmar_unit *unit); 303void dmar_fini_qi(struct dmar_unit *unit); 304void dmar_qi_invalidate_locked(struct dmar_domain *domain, dmar_gaddr_t start, 305 dmar_gaddr_t size, struct dmar_qi_genseq *pseq); 306void dmar_qi_invalidate_ctx_glob_locked(struct dmar_unit *unit); 307void dmar_qi_invalidate_iotlb_glob_locked(struct dmar_unit *unit); 308void dmar_qi_invalidate_iec_glob(struct dmar_unit *unit); 309void dmar_qi_invalidate_iec(struct dmar_unit *unit, u_int start, u_int cnt); 310 311vm_object_t domain_get_idmap_pgtbl(struct dmar_domain *domain, 312 dmar_gaddr_t maxaddr); 313void put_idmap_pgtbl(vm_object_t obj); 314int domain_map_buf(struct dmar_domain *domain, dmar_gaddr_t base, 315 dmar_gaddr_t size, vm_page_t *ma, uint64_t pflags, int flags); 316int domain_unmap_buf(struct dmar_domain *domain, dmar_gaddr_t base, 317 dmar_gaddr_t size, int flags); 318void domain_flush_iotlb_sync(struct dmar_domain *domain, dmar_gaddr_t base, 319 dmar_gaddr_t size); 320int domain_alloc_pgtbl(struct dmar_domain *domain); 321void domain_free_pgtbl(struct dmar_domain *domain); 322 323struct dmar_ctx *dmar_instantiate_ctx(struct dmar_unit *dmar, device_t dev, 324 bool rmrr); 325struct dmar_ctx *dmar_get_ctx_for_dev(struct dmar_unit *dmar, device_t dev, 326 uint16_t rid, bool id_mapped, bool rmrr_init); 327int dmar_move_ctx_to_domain(struct dmar_domain *domain, struct dmar_ctx *ctx); 328void dmar_free_ctx_locked(struct dmar_unit *dmar, struct dmar_ctx *ctx); 329void dmar_free_ctx(struct dmar_ctx *ctx); 330struct dmar_ctx *dmar_find_ctx_locked(struct dmar_unit *dmar, uint16_t rid); 331void dmar_domain_unload_entry(struct dmar_map_entry *entry, bool free); 332void dmar_domain_unload(struct dmar_domain *domain, 333 struct dmar_map_entries_tailq *entries, bool cansleep); 334void dmar_domain_free_entry(struct dmar_map_entry *entry, bool free); 335 336int dmar_init_busdma(struct dmar_unit *unit); 337void dmar_fini_busdma(struct dmar_unit *unit); 338device_t dmar_get_requester(device_t dev, uint16_t *rid); 339 340void dmar_gas_init_domain(struct dmar_domain *domain); 341void dmar_gas_fini_domain(struct dmar_domain *domain); 342struct dmar_map_entry *dmar_gas_alloc_entry(struct dmar_domain *domain, 343 u_int flags); 344void dmar_gas_free_entry(struct dmar_domain *domain, 345 struct dmar_map_entry *entry); 346void dmar_gas_free_space(struct dmar_domain *domain, 347 struct dmar_map_entry *entry); 348int dmar_gas_map(struct dmar_domain *domain, 349 const struct bus_dma_tag_common *common, dmar_gaddr_t size, int offset, 350 u_int eflags, u_int flags, vm_page_t *ma, struct dmar_map_entry **res); 351void dmar_gas_free_region(struct dmar_domain *domain, 352 struct dmar_map_entry *entry); 353int dmar_gas_map_region(struct dmar_domain *domain, 354 struct dmar_map_entry *entry, u_int eflags, u_int flags, vm_page_t *ma); 355int dmar_gas_reserve_region(struct dmar_domain *domain, dmar_gaddr_t start, 356 dmar_gaddr_t end); 357 358void dmar_dev_parse_rmrr(struct dmar_domain *domain, device_t dev, 359 struct dmar_map_entries_tailq *rmrr_entries); 360int dmar_instantiate_rmrr_ctxs(struct dmar_unit *dmar); 361 362void dmar_quirks_post_ident(struct dmar_unit *dmar); 363void dmar_quirks_pre_use(struct dmar_unit *dmar); 364 365int dmar_init_irt(struct dmar_unit *unit); 366void dmar_fini_irt(struct dmar_unit *unit); 367 368#define DMAR_GM_CANWAIT 0x0001 369#define DMAR_GM_CANSPLIT 0x0002 370 371#define DMAR_PGF_WAITOK 0x0001 372#define DMAR_PGF_ZERO 0x0002 373#define DMAR_PGF_ALLOC 0x0004 374#define DMAR_PGF_NOALLOC 0x0008 375#define DMAR_PGF_OBJL 0x0010 376 377extern dmar_haddr_t dmar_high; 378extern int haw; 379extern int dmar_tbl_pagecnt; 380extern int dmar_match_verbose; 381extern int dmar_check_free; 382 383static inline uint32_t 384dmar_read4(const struct dmar_unit *unit, int reg) 385{ 386 387 return (bus_read_4(unit->regs, reg)); 388} 389 390static inline uint64_t 391dmar_read8(const struct dmar_unit *unit, int reg) 392{ 393#ifdef __i386__ 394 uint32_t high, low; 395 396 low = bus_read_4(unit->regs, reg); 397 high = bus_read_4(unit->regs, reg + 4); 398 return (low | ((uint64_t)high << 32)); 399#else 400 return (bus_read_8(unit->regs, reg)); 401#endif 402} 403 404static inline void 405dmar_write4(const struct dmar_unit *unit, int reg, uint32_t val) 406{ 407 408 KASSERT(reg != DMAR_GCMD_REG || (val & DMAR_GCMD_TE) == 409 (unit->hw_gcmd & DMAR_GCMD_TE), 410 ("dmar%d clearing TE 0x%08x 0x%08x", unit->unit, 411 unit->hw_gcmd, val)); 412 bus_write_4(unit->regs, reg, val); 413} 414 415static inline void 416dmar_write8(const struct dmar_unit *unit, int reg, uint64_t val) 417{ 418 419 KASSERT(reg != DMAR_GCMD_REG, ("8byte GCMD write")); 420#ifdef __i386__ 421 uint32_t high, low; 422 423 low = val; 424 high = val >> 32; 425 bus_write_4(unit->regs, reg, low); 426 bus_write_4(unit->regs, reg + 4, high); 427#else 428 bus_write_8(unit->regs, reg, val); 429#endif 430} 431 432/* 433 * dmar_pte_store and dmar_pte_clear ensure that on i386, 32bit writes 434 * are issued in the correct order. For store, the lower word, 435 * containing the P or R and W bits, is set only after the high word 436 * is written. For clear, the P bit is cleared first, then the high 437 * word is cleared. 438 * 439 * dmar_pte_update updates the pte. For amd64, the update is atomic. 440 * For i386, it first disables the entry by clearing the word 441 * containing the P bit, and then defer to dmar_pte_store. The locked 442 * cmpxchg8b is probably available on any machine having DMAR support, 443 * but interrupt translation table may be mapped uncached. 444 */ 445static inline void 446dmar_pte_store1(volatile uint64_t *dst, uint64_t val) 447{ 448#ifdef __i386__ 449 volatile uint32_t *p; 450 uint32_t hi, lo; 451 452 hi = val >> 32; 453 lo = val; 454 p = (volatile uint32_t *)dst; 455 *(p + 1) = hi; 456 *p = lo; 457#else 458 *dst = val; 459#endif 460} 461 462static inline void 463dmar_pte_store(volatile uint64_t *dst, uint64_t val) 464{ 465 466 KASSERT(*dst == 0, ("used pte %p oldval %jx newval %jx", 467 dst, (uintmax_t)*dst, (uintmax_t)val)); 468 dmar_pte_store1(dst, val); 469} 470 471static inline void 472dmar_pte_update(volatile uint64_t *dst, uint64_t val) 473{ 474 475#ifdef __i386__ 476 volatile uint32_t *p; 477 478 p = (volatile uint32_t *)dst; 479 *p = 0; 480#endif 481 dmar_pte_store1(dst, val); 482} 483 484static inline void 485dmar_pte_clear(volatile uint64_t *dst) 486{ 487#ifdef __i386__ 488 volatile uint32_t *p; 489 490 p = (volatile uint32_t *)dst; 491 *p = 0; 492 *(p + 1) = 0; 493#else 494 *dst = 0; 495#endif 496} 497 498static inline bool 499dmar_test_boundary(dmar_gaddr_t start, dmar_gaddr_t size, 500 dmar_gaddr_t boundary) 501{ 502 503 if (boundary == 0) 504 return (true); 505 return (start + size <= ((start + boundary) & ~(boundary - 1))); 506} 507 508#ifdef INVARIANTS 509#define TD_PREP_PINNED_ASSERT \ 510 int old_td_pinned; \ 511 old_td_pinned = curthread->td_pinned 512#define TD_PINNED_ASSERT \ 513 KASSERT(curthread->td_pinned == old_td_pinned, \ 514 ("pin count leak: %d %d %s:%d", curthread->td_pinned, \ 515 old_td_pinned, __FILE__, __LINE__)) 516#else 517#define TD_PREP_PINNED_ASSERT 518#define TD_PINNED_ASSERT 519#endif 520 521#endif 522