intel_dmar.h revision 280260
1/*- 2 * Copyright (c) 2013-2015 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 6 * under sponsorship from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: head/sys/x86/iommu/intel_dmar.h 280260 2015-03-19 13:57:47Z kib $ 30 */ 31 32#ifndef __X86_IOMMU_INTEL_DMAR_H 33#define __X86_IOMMU_INTEL_DMAR_H 34 35/* Host or physical memory address, after translation. */ 36typedef uint64_t dmar_haddr_t; 37/* Guest or bus address, before translation. */ 38typedef uint64_t dmar_gaddr_t; 39 40struct dmar_qi_genseq { 41 u_int gen; 42 uint32_t seq; 43}; 44 45struct dmar_map_entry { 46 dmar_gaddr_t start; 47 dmar_gaddr_t end; 48 dmar_gaddr_t free_after; /* Free space after the entry */ 49 dmar_gaddr_t free_down; /* Max free space below the 50 current R/B tree node */ 51 u_int flags; 52 TAILQ_ENTRY(dmar_map_entry) dmamap_link; /* Link for dmamap entries */ 53 RB_ENTRY(dmar_map_entry) rb_entry; /* Links for ctx entries */ 54 TAILQ_ENTRY(dmar_map_entry) unroll_link; /* Link for unroll after 55 dmamap_load failure */ 56 struct dmar_ctx *ctx; 57 struct dmar_qi_genseq gseq; 58}; 59 60RB_HEAD(dmar_gas_entries_tree, dmar_map_entry); 61RB_PROTOTYPE(dmar_gas_entries_tree, dmar_map_entry, rb_entry, 62 dmar_gas_cmp_entries); 63 64#define DMAR_MAP_ENTRY_PLACE 0x0001 /* Fake entry */ 65#define DMAR_MAP_ENTRY_RMRR 0x0002 /* Permanent, not linked by 66 dmamap_link */ 67#define DMAR_MAP_ENTRY_MAP 0x0004 /* Busdma created, linked by 68 dmamap_link */ 69#define DMAR_MAP_ENTRY_UNMAPPED 0x0010 /* No backing pages */ 70#define DMAR_MAP_ENTRY_QI_NF 0x0020 /* qi task, do not free entry */ 71#define DMAR_MAP_ENTRY_READ 0x1000 /* Read permitted */ 72#define DMAR_MAP_ENTRY_WRITE 0x2000 /* Write permitted */ 73#define DMAR_MAP_ENTRY_SNOOP 0x4000 /* Snoop */ 74#define DMAR_MAP_ENTRY_TM 0x8000 /* Transient */ 75 76struct dmar_ctx { 77 uint16_t rid; /* pci RID */ 78 int domain; /* DID */ 79 int mgaw; /* Real max address width */ 80 int agaw; /* Adjusted guest address width */ 81 int pglvl; /* The pagelevel */ 82 int awlvl; /* The pagelevel as the bitmask, to set in 83 context entry */ 84 dmar_gaddr_t end;/* Highest address + 1 in the guest AS */ 85 u_int refs; /* References to the context, from tags */ 86 struct dmar_unit *dmar; 87 struct bus_dma_tag_dmar ctx_tag; /* Root tag */ 88 struct mtx lock; 89 LIST_ENTRY(dmar_ctx) link; /* Member in the dmar list */ 90 vm_object_t pgtbl_obj; /* Page table pages */ 91 u_int flags; /* Protected by dmar lock */ 92 uint64_t last_fault_rec[2]; /* Last fault reported */ 93 u_int entries_cnt; 94 u_long loads; 95 u_long unloads; 96 struct dmar_gas_entries_tree rb_root; 97 struct dmar_map_entries_tailq unload_entries; /* Entries to unload */ 98 struct dmar_map_entry *first_place, *last_place; 99 struct task unload_task; 100}; 101 102/* struct dmar_ctx flags */ 103#define DMAR_CTX_FAULTED 0x0001 /* Fault was reported, 104 last_fault_rec is valid */ 105#define DMAR_CTX_IDMAP 0x0002 /* Context uses identity page table */ 106#define DMAR_CTX_RMRR 0x0004 /* Context contains RMRR entry, 107 cannot be turned off */ 108#define DMAR_CTX_DISABLED 0x0008 /* Device is disabled, the 109 ephemeral reference is kept 110 to prevent context destruction */ 111 112#define DMAR_CTX_PGLOCK(ctx) VM_OBJECT_WLOCK((ctx)->pgtbl_obj) 113#define DMAR_CTX_PGTRYLOCK(ctx) VM_OBJECT_TRYWLOCK((ctx)->pgtbl_obj) 114#define DMAR_CTX_PGUNLOCK(ctx) VM_OBJECT_WUNLOCK((ctx)->pgtbl_obj) 115#define DMAR_CTX_ASSERT_PGLOCKED(ctx) \ 116 VM_OBJECT_ASSERT_WLOCKED((ctx)->pgtbl_obj) 117 118#define DMAR_CTX_LOCK(ctx) mtx_lock(&(ctx)->lock) 119#define DMAR_CTX_UNLOCK(ctx) mtx_unlock(&(ctx)->lock) 120#define DMAR_CTX_ASSERT_LOCKED(ctx) mtx_assert(&(ctx)->lock, MA_OWNED) 121 122struct dmar_msi_data { 123 int irq; 124 int irq_rid; 125 struct resource *irq_res; 126 void *intr_handle; 127 int (*handler)(void *); 128 int msi_data_reg; 129 int msi_addr_reg; 130 int msi_uaddr_reg; 131 void (*enable_intr)(struct dmar_unit *); 132 void (*disable_intr)(struct dmar_unit *); 133 const char *name; 134}; 135 136#define DMAR_INTR_FAULT 0 137#define DMAR_INTR_QI 1 138#define DMAR_INTR_TOTAL 2 139 140struct dmar_unit { 141 device_t dev; 142 int unit; 143 uint16_t segment; 144 uint64_t base; 145 146 /* Resources */ 147 int reg_rid; 148 struct resource *regs; 149 150 struct dmar_msi_data intrs[DMAR_INTR_TOTAL]; 151 152 /* Hardware registers cache */ 153 uint32_t hw_ver; 154 uint64_t hw_cap; 155 uint64_t hw_ecap; 156 uint32_t hw_gcmd; 157 158 /* Data for being a dmar */ 159 struct mtx lock; 160 LIST_HEAD(, dmar_ctx) contexts; 161 struct unrhdr *domids; 162 vm_object_t ctx_obj; 163 u_int barrier_flags; 164 165 /* Fault handler data */ 166 struct mtx fault_lock; 167 uint64_t *fault_log; 168 int fault_log_head; 169 int fault_log_tail; 170 int fault_log_size; 171 struct task fault_task; 172 struct taskqueue *fault_taskqueue; 173 174 /* QI */ 175 int qi_enabled; 176 vm_offset_t inv_queue; 177 vm_size_t inv_queue_size; 178 uint32_t inv_queue_avail; 179 uint32_t inv_queue_tail; 180 volatile uint32_t inv_waitd_seq_hw; /* hw writes there on wait 181 descr completion */ 182 uint64_t inv_waitd_seq_hw_phys; 183 uint32_t inv_waitd_seq; /* next sequence number to use for wait descr */ 184 u_int inv_waitd_gen; /* seq number generation AKA seq overflows */ 185 u_int inv_seq_waiters; /* count of waiters for seq */ 186 u_int inv_queue_full; /* informational counter */ 187 188 /* IR */ 189 int ir_enabled; 190 vm_paddr_t irt_phys; 191 dmar_irte_t *irt; 192 u_int irte_cnt; 193 vmem_t *irtids; 194 195 /* Delayed freeing of map entries queue processing */ 196 struct dmar_map_entries_tailq tlb_flush_entries; 197 struct task qi_task; 198 struct taskqueue *qi_taskqueue; 199 200 /* Busdma delayed map load */ 201 struct task dmamap_load_task; 202 TAILQ_HEAD(, bus_dmamap_dmar) delayed_maps; 203 struct taskqueue *delayed_taskqueue; 204 205 int dma_enabled; 206}; 207 208#define DMAR_LOCK(dmar) mtx_lock(&(dmar)->lock) 209#define DMAR_UNLOCK(dmar) mtx_unlock(&(dmar)->lock) 210#define DMAR_ASSERT_LOCKED(dmar) mtx_assert(&(dmar)->lock, MA_OWNED) 211 212#define DMAR_FAULT_LOCK(dmar) mtx_lock_spin(&(dmar)->fault_lock) 213#define DMAR_FAULT_UNLOCK(dmar) mtx_unlock_spin(&(dmar)->fault_lock) 214#define DMAR_FAULT_ASSERT_LOCKED(dmar) mtx_assert(&(dmar)->fault_lock, MA_OWNED) 215 216#define DMAR_IS_COHERENT(dmar) (((dmar)->hw_ecap & DMAR_ECAP_C) != 0) 217#define DMAR_HAS_QI(dmar) (((dmar)->hw_ecap & DMAR_ECAP_QI) != 0) 218#define DMAR_X2APIC(dmar) \ 219 (x2apic_mode && ((dmar)->hw_ecap & DMAR_ECAP_EIM) != 0) 220 221/* Barrier ids */ 222#define DMAR_BARRIER_RMRR 0 223#define DMAR_BARRIER_USEQ 1 224 225struct dmar_unit *dmar_find(device_t dev); 226struct dmar_unit *dmar_find_hpet(device_t dev, uint16_t *rid); 227struct dmar_unit *dmar_find_ioapic(u_int apic_id, uint16_t *rid); 228 229u_int dmar_nd2mask(u_int nd); 230bool dmar_pglvl_supported(struct dmar_unit *unit, int pglvl); 231int ctx_set_agaw(struct dmar_ctx *ctx, int mgaw); 232int dmar_maxaddr2mgaw(struct dmar_unit* unit, dmar_gaddr_t maxaddr, 233 bool allow_less); 234vm_pindex_t pglvl_max_pages(int pglvl); 235int ctx_is_sp_lvl(struct dmar_ctx *ctx, int lvl); 236dmar_gaddr_t pglvl_page_size(int total_pglvl, int lvl); 237dmar_gaddr_t ctx_page_size(struct dmar_ctx *ctx, int lvl); 238int calc_am(struct dmar_unit *unit, dmar_gaddr_t base, dmar_gaddr_t size, 239 dmar_gaddr_t *isizep); 240struct vm_page *dmar_pgalloc(vm_object_t obj, vm_pindex_t idx, int flags); 241void dmar_pgfree(vm_object_t obj, vm_pindex_t idx, int flags); 242void *dmar_map_pgtbl(vm_object_t obj, vm_pindex_t idx, int flags, 243 struct sf_buf **sf); 244void dmar_unmap_pgtbl(struct sf_buf *sf); 245int dmar_load_root_entry_ptr(struct dmar_unit *unit); 246int dmar_inv_ctx_glob(struct dmar_unit *unit); 247int dmar_inv_iotlb_glob(struct dmar_unit *unit); 248int dmar_flush_write_bufs(struct dmar_unit *unit); 249void dmar_flush_pte_to_ram(struct dmar_unit *unit, dmar_pte_t *dst); 250void dmar_flush_ctx_to_ram(struct dmar_unit *unit, dmar_ctx_entry_t *dst); 251void dmar_flush_root_to_ram(struct dmar_unit *unit, dmar_root_entry_t *dst); 252int dmar_enable_translation(struct dmar_unit *unit); 253int dmar_disable_translation(struct dmar_unit *unit); 254int dmar_load_irt_ptr(struct dmar_unit *unit); 255int dmar_enable_ir(struct dmar_unit *unit); 256int dmar_disable_ir(struct dmar_unit *unit); 257bool dmar_barrier_enter(struct dmar_unit *dmar, u_int barrier_id); 258void dmar_barrier_exit(struct dmar_unit *dmar, u_int barrier_id); 259 260int dmar_fault_intr(void *arg); 261void dmar_enable_fault_intr(struct dmar_unit *unit); 262void dmar_disable_fault_intr(struct dmar_unit *unit); 263int dmar_init_fault_log(struct dmar_unit *unit); 264void dmar_fini_fault_log(struct dmar_unit *unit); 265 266int dmar_qi_intr(void *arg); 267void dmar_enable_qi_intr(struct dmar_unit *unit); 268void dmar_disable_qi_intr(struct dmar_unit *unit); 269int dmar_init_qi(struct dmar_unit *unit); 270void dmar_fini_qi(struct dmar_unit *unit); 271void dmar_qi_invalidate_locked(struct dmar_ctx *ctx, dmar_gaddr_t start, 272 dmar_gaddr_t size, struct dmar_qi_genseq *pseq); 273void dmar_qi_invalidate_ctx_glob_locked(struct dmar_unit *unit); 274void dmar_qi_invalidate_iotlb_glob_locked(struct dmar_unit *unit); 275void dmar_qi_invalidate_iec_glob(struct dmar_unit *unit); 276void dmar_qi_invalidate_iec(struct dmar_unit *unit, u_int start, u_int cnt); 277 278vm_object_t ctx_get_idmap_pgtbl(struct dmar_ctx *ctx, dmar_gaddr_t maxaddr); 279void put_idmap_pgtbl(vm_object_t obj); 280int ctx_map_buf(struct dmar_ctx *ctx, dmar_gaddr_t base, dmar_gaddr_t size, 281 vm_page_t *ma, uint64_t pflags, int flags); 282int ctx_unmap_buf(struct dmar_ctx *ctx, dmar_gaddr_t base, dmar_gaddr_t size, 283 int flags); 284void ctx_flush_iotlb_sync(struct dmar_ctx *ctx, dmar_gaddr_t base, 285 dmar_gaddr_t size); 286int ctx_alloc_pgtbl(struct dmar_ctx *ctx); 287void ctx_free_pgtbl(struct dmar_ctx *ctx); 288 289struct dmar_ctx *dmar_instantiate_ctx(struct dmar_unit *dmar, device_t dev, 290 bool rmrr); 291struct dmar_ctx *dmar_get_ctx(struct dmar_unit *dmar, device_t dev, 292 uint16_t rid, bool id_mapped, bool rmrr_init); 293void dmar_free_ctx_locked(struct dmar_unit *dmar, struct dmar_ctx *ctx); 294void dmar_free_ctx(struct dmar_ctx *ctx); 295struct dmar_ctx *dmar_find_ctx_locked(struct dmar_unit *dmar, uint16_t rid); 296void dmar_ctx_unload_entry(struct dmar_map_entry *entry, bool free); 297void dmar_ctx_unload(struct dmar_ctx *ctx, 298 struct dmar_map_entries_tailq *entries, bool cansleep); 299void dmar_ctx_free_entry(struct dmar_map_entry *entry, bool free); 300 301int dmar_init_busdma(struct dmar_unit *unit); 302void dmar_fini_busdma(struct dmar_unit *unit); 303device_t dmar_get_requester(device_t dev, uint16_t *rid); 304 305void dmar_gas_init_ctx(struct dmar_ctx *ctx); 306void dmar_gas_fini_ctx(struct dmar_ctx *ctx); 307struct dmar_map_entry *dmar_gas_alloc_entry(struct dmar_ctx *ctx, u_int flags); 308void dmar_gas_free_entry(struct dmar_ctx *ctx, struct dmar_map_entry *entry); 309void dmar_gas_free_space(struct dmar_ctx *ctx, struct dmar_map_entry *entry); 310int dmar_gas_map(struct dmar_ctx *ctx, const struct bus_dma_tag_common *common, 311 dmar_gaddr_t size, u_int eflags, u_int flags, vm_page_t *ma, 312 struct dmar_map_entry **res); 313void dmar_gas_free_region(struct dmar_ctx *ctx, struct dmar_map_entry *entry); 314int dmar_gas_map_region(struct dmar_ctx *ctx, struct dmar_map_entry *entry, 315 u_int eflags, u_int flags, vm_page_t *ma); 316int dmar_gas_reserve_region(struct dmar_ctx *ctx, dmar_gaddr_t start, 317 dmar_gaddr_t end); 318 319void dmar_ctx_parse_rmrr(struct dmar_ctx *ctx, device_t dev, 320 struct dmar_map_entries_tailq *rmrr_entries); 321int dmar_instantiate_rmrr_ctxs(struct dmar_unit *dmar); 322 323void dmar_quirks_post_ident(struct dmar_unit *dmar); 324void dmar_quirks_pre_use(struct dmar_unit *dmar); 325 326int dmar_init_irt(struct dmar_unit *unit); 327void dmar_fini_irt(struct dmar_unit *unit); 328 329#define DMAR_GM_CANWAIT 0x0001 330#define DMAR_GM_CANSPLIT 0x0002 331 332#define DMAR_PGF_WAITOK 0x0001 333#define DMAR_PGF_ZERO 0x0002 334#define DMAR_PGF_ALLOC 0x0004 335#define DMAR_PGF_NOALLOC 0x0008 336#define DMAR_PGF_OBJL 0x0010 337 338extern dmar_haddr_t dmar_high; 339extern int haw; 340extern int dmar_tbl_pagecnt; 341extern int dmar_match_verbose; 342extern int dmar_check_free; 343 344static inline uint32_t 345dmar_read4(const struct dmar_unit *unit, int reg) 346{ 347 348 return (bus_read_4(unit->regs, reg)); 349} 350 351static inline uint64_t 352dmar_read8(const struct dmar_unit *unit, int reg) 353{ 354#ifdef __i386__ 355 uint32_t high, low; 356 357 low = bus_read_4(unit->regs, reg); 358 high = bus_read_4(unit->regs, reg + 4); 359 return (low | ((uint64_t)high << 32)); 360#else 361 return (bus_read_8(unit->regs, reg)); 362#endif 363} 364 365static inline void 366dmar_write4(const struct dmar_unit *unit, int reg, uint32_t val) 367{ 368 369 KASSERT(reg != DMAR_GCMD_REG || (val & DMAR_GCMD_TE) == 370 (unit->hw_gcmd & DMAR_GCMD_TE), 371 ("dmar%d clearing TE 0x%08x 0x%08x", unit->unit, 372 unit->hw_gcmd, val)); 373 bus_write_4(unit->regs, reg, val); 374} 375 376static inline void 377dmar_write8(const struct dmar_unit *unit, int reg, uint64_t val) 378{ 379 380 KASSERT(reg != DMAR_GCMD_REG, ("8byte GCMD write")); 381#ifdef __i386__ 382 uint32_t high, low; 383 384 low = val; 385 high = val >> 32; 386 bus_write_4(unit->regs, reg, low); 387 bus_write_4(unit->regs, reg + 4, high); 388#else 389 bus_write_8(unit->regs, reg, val); 390#endif 391} 392 393/* 394 * dmar_pte_store and dmar_pte_clear ensure that on i386, 32bit writes 395 * are issued in the correct order. For store, the lower word, 396 * containing the P or R and W bits, is set only after the high word 397 * is written. For clear, the P bit is cleared first, then the high 398 * word is cleared. 399 * 400 * dmar_pte_update updates the pte. For amd64, the update is atomic. 401 * For i386, it first disables the entry by clearing the word 402 * containing the P bit, and then defer to dmar_pte_store. The locked 403 * cmpxchg8b is probably available on any machine having DMAR support, 404 * but interrupt translation table may be mapped uncached. 405 */ 406static inline void 407dmar_pte_store1(volatile uint64_t *dst, uint64_t val) 408{ 409#ifdef __i386__ 410 volatile uint32_t *p; 411 uint32_t hi, lo; 412 413 hi = val >> 32; 414 lo = val; 415 p = (volatile uint32_t *)dst; 416 *(p + 1) = hi; 417 *p = lo; 418#else 419 *dst = val; 420#endif 421} 422 423static inline void 424dmar_pte_store(volatile uint64_t *dst, uint64_t val) 425{ 426 427 KASSERT(*dst == 0, ("used pte %p oldval %jx newval %jx", 428 dst, (uintmax_t)*dst, (uintmax_t)val)); 429 dmar_pte_store1(dst, val); 430} 431 432static inline void 433dmar_pte_update(volatile uint64_t *dst, uint64_t val) 434{ 435 436#ifdef __i386__ 437 volatile uint32_t *p; 438 439 p = (volatile uint32_t *)dst; 440 *p = 0; 441#endif 442 dmar_pte_store1(dst, val); 443} 444 445static inline void 446dmar_pte_clear(volatile uint64_t *dst) 447{ 448#ifdef __i386__ 449 volatile uint32_t *p; 450 451 p = (volatile uint32_t *)dst; 452 *p = 0; 453 *(p + 1) = 0; 454#else 455 *dst = 0; 456#endif 457} 458 459static inline bool 460dmar_test_boundary(dmar_gaddr_t start, dmar_gaddr_t size, 461 dmar_gaddr_t boundary) 462{ 463 464 if (boundary == 0) 465 return (true); 466 return (start + size <= ((start + boundary) & ~(boundary - 1))); 467} 468 469#ifdef INVARIANTS 470#define TD_PREP_PINNED_ASSERT \ 471 int old_td_pinned; \ 472 old_td_pinned = curthread->td_pinned 473#define TD_PINNED_ASSERT \ 474 KASSERT(curthread->td_pinned == old_td_pinned, \ 475 ("pin count leak: %d %d %s:%d", curthread->td_pinned, \ 476 old_td_pinned, __FILE__, __LINE__)) 477#else 478#define TD_PREP_PINNED_ASSERT 479#define TD_PINNED_ASSERT 480#endif 481 482#endif 483