intel_dmar.h revision 264002
1331722Seadler/*- 2174604Sscottl * Copyright (c) 2013 The FreeBSD Foundation 3174604Sscottl * All rights reserved. 4174604Sscottl * 5174604Sscottl * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 6174604Sscottl * under sponsorship from the FreeBSD Foundation. 7174604Sscottl * 8174604Sscottl * Redistribution and use in source and binary forms, with or without 9174604Sscottl * modification, are permitted provided that the following conditions 10174604Sscottl * are met: 11174604Sscottl * 1. Redistributions of source code must retain the above copyright 12174604Sscottl * notice, this list of conditions and the following disclaimer. 13174604Sscottl * 2. Redistributions in binary form must reproduce the above copyright 14174604Sscottl * notice, this list of conditions and the following disclaimer in the 15174604Sscottl * documentation and/or other materials provided with the distribution. 16174604Sscottl * 17174604Sscottl * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18174604Sscottl * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19174604Sscottl * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20174604Sscottl * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21174604Sscottl * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22174604Sscottl * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23174604Sscottl * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24174604Sscottl * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25174604Sscottl * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26174604Sscottl * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27174604Sscottl * SUCH DAMAGE. 28174604Sscottl * 29174604Sscottl * $FreeBSD: head/sys/x86/iommu/intel_dmar.h 264002 2014-04-01 14:51:45Z rstone $ 30174604Sscottl */ 31174604Sscottl 32174604Sscottl#ifndef __X86_IOMMU_INTEL_DMAR_H 33174604Sscottl#define __X86_IOMMU_INTEL_DMAR_H 34174604Sscottl 35174604Sscottl/* Host or physical memory address, after translation. */ 36174604Sscottltypedef uint64_t dmar_haddr_t; 37174604Sscottl/* Guest or bus address, before translation. */ 38176018Sscottltypedef uint64_t dmar_gaddr_t; 39176018Sscottl 40176018Sscottlstruct dmar_qi_genseq { 41176018Sscottl u_int gen; 42174604Sscottl uint32_t seq; 43174604Sscottl}; 44174604Sscottl 45174604Sscottlstruct dmar_map_entry { 46174604Sscottl dmar_gaddr_t start; 47174604Sscottl dmar_gaddr_t end; 48174604Sscottl dmar_gaddr_t free_after; /* Free space after the entry */ 49174604Sscottl dmar_gaddr_t free_down; /* Max free space below the 50174604Sscottl current R/B tree node */ 51174604Sscottl u_int flags; 52174604Sscottl TAILQ_ENTRY(dmar_map_entry) dmamap_link; /* Link for dmamap entries */ 53174604Sscottl RB_ENTRY(dmar_map_entry) rb_entry; /* Links for ctx entries */ 54174604Sscottl TAILQ_ENTRY(dmar_map_entry) unroll_link; /* Link for unroll after 55174604Sscottl dmamap_load failure */ 56174604Sscottl struct dmar_ctx *ctx; 57174604Sscottl struct dmar_qi_genseq gseq; 58174604Sscottl}; 59174604Sscottl 60174604SscottlRB_HEAD(dmar_gas_entries_tree, dmar_map_entry); 61174604SscottlRB_PROTOTYPE(dmar_gas_entries_tree, dmar_map_entry, rb_entry, 62174604Sscottl dmar_gas_cmp_entries); 63174604Sscottl 64174604Sscottl#define DMAR_MAP_ENTRY_PLACE 0x0001 /* Fake entry */ 65174604Sscottl#define DMAR_MAP_ENTRY_RMRR 0x0002 /* Permanent, not linked by 66174604Sscottl dmamap_link */ 67174604Sscottl#define DMAR_MAP_ENTRY_MAP 0x0004 /* Busdma created, linked by 68174604Sscottl dmamap_link */ 69174604Sscottl#define DMAR_MAP_ENTRY_UNMAPPED 0x0010 /* No backing pages */ 70174604Sscottl#define DMAR_MAP_ENTRY_QI_NF 0x0020 /* qi task, do not free entry */ 71174604Sscottl#define DMAR_MAP_ENTRY_READ 0x1000 /* Read permitted */ 72174604Sscottl#define DMAR_MAP_ENTRY_WRITE 0x2000 /* Write permitted */ 73174604Sscottl#define DMAR_MAP_ENTRY_SNOOP 0x4000 /* Snoop */ 74174604Sscottl#define DMAR_MAP_ENTRY_TM 0x8000 /* Transient */ 75174604Sscottl 76174604Sscottlstruct dmar_ctx { 77174604Sscottl uint16_t rid; /* pci RID */ 78174604Sscottl int domain; /* DID */ 79174604Sscottl int mgaw; /* Real max address width */ 80174604Sscottl int agaw; /* Adjusted guest address width */ 81174604Sscottl int pglvl; /* The pagelevel */ 82174604Sscottl int awlvl; /* The pagelevel as the bitmask, to set in 83174604Sscottl context entry */ 84174604Sscottl dmar_gaddr_t end;/* Highest address + 1 in the guest AS */ 85174604Sscottl u_int refs; /* References to the context, from tags */ 86174604Sscottl struct dmar_unit *dmar; 87174604Sscottl struct bus_dma_tag_dmar ctx_tag; /* Root tag */ 88174604Sscottl struct mtx lock; 89174604Sscottl LIST_ENTRY(dmar_ctx) link; /* Member in the dmar list */ 90174604Sscottl vm_object_t pgtbl_obj; /* Page table pages */ 91174604Sscottl u_int flags; /* Protected by dmar lock */ 92174604Sscottl uint64_t last_fault_rec[2]; /* Last fault reported */ 93174604Sscottl u_int entries_cnt; 94174604Sscottl u_long loads; 95174604Sscottl u_long unloads; 96174604Sscottl struct dmar_gas_entries_tree rb_root; 97174604Sscottl struct dmar_map_entries_tailq unload_entries; /* Entries to unload */ 98174604Sscottl struct dmar_map_entry *first_place, *last_place; 99174604Sscottl struct task unload_task; 100174604Sscottl}; 101174604Sscottl 102174604Sscottl/* struct dmar_ctx flags */ 103174604Sscottl#define DMAR_CTX_FAULTED 0x0001 /* Fault was reported, 104174604Sscottl last_fault_rec is valid */ 105174604Sscottl#define DMAR_CTX_IDMAP 0x0002 /* Context uses identity page table */ 106174604Sscottl#define DMAR_CTX_RMRR 0x0004 /* Context contains RMRR entry, 107174604Sscottl cannot be turned off */ 108174604Sscottl#define DMAR_CTX_DISABLED 0x0008 /* Device is disabled, the 109174604Sscottl ephemeral reference is kept 110174604Sscottl to prevent context destruction */ 111174604Sscottl 112174604Sscottl#define DMAR_CTX_PGLOCK(ctx) VM_OBJECT_WLOCK((ctx)->pgtbl_obj) 113174604Sscottl#define DMAR_CTX_PGTRYLOCK(ctx) VM_OBJECT_TRYWLOCK((ctx)->pgtbl_obj) 114174604Sscottl#define DMAR_CTX_PGUNLOCK(ctx) VM_OBJECT_WUNLOCK((ctx)->pgtbl_obj) 115174604Sscottl#define DMAR_CTX_ASSERT_PGLOCKED(ctx) \ 116174604Sscottl VM_OBJECT_ASSERT_WLOCKED((ctx)->pgtbl_obj) 117174604Sscottl 118174604Sscottl#define DMAR_CTX_LOCK(ctx) mtx_lock(&(ctx)->lock) 119174604Sscottl#define DMAR_CTX_UNLOCK(ctx) mtx_unlock(&(ctx)->lock) 120174604Sscottl#define DMAR_CTX_ASSERT_LOCKED(ctx) mtx_assert(&(ctx)->lock, MA_OWNED) 121174604Sscottl 122174604Sscottlstruct dmar_msi_data { 123174604Sscottl int irq; 124174604Sscottl int irq_rid; 125174604Sscottl struct resource *irq_res; 126174604Sscottl void *intr_handle; 127174604Sscottl int (*handler)(void *); 128174604Sscottl int msi_data_reg; 129174604Sscottl int msi_addr_reg; 130174604Sscottl int msi_uaddr_reg; 131174604Sscottl void (*enable_intr)(struct dmar_unit *); 132174604Sscottl void (*disable_intr)(struct dmar_unit *); 133174604Sscottl const char *name; 134174604Sscottl}; 135174604Sscottl 136174604Sscottl#define DMAR_INTR_FAULT 0 137174604Sscottl#define DMAR_INTR_QI 1 138174604Sscottl#define DMAR_INTR_TOTAL 2 139174604Sscottl 140174604Sscottlstruct dmar_unit { 141174604Sscottl device_t dev; 142174604Sscottl int unit; 143174604Sscottl uint16_t segment; 144174604Sscottl uint64_t base; 145174604Sscottl 146174604Sscottl /* Resources */ 147174604Sscottl int reg_rid; 148174604Sscottl struct resource *regs; 149174604Sscottl 150174604Sscottl struct dmar_msi_data intrs[DMAR_INTR_TOTAL]; 151174604Sscottl 152174604Sscottl /* Hardware registers cache */ 153174604Sscottl uint32_t hw_ver; 154174604Sscottl uint64_t hw_cap; 155174604Sscottl uint64_t hw_ecap; 156174604Sscottl uint32_t hw_gcmd; 157174604Sscottl 158174604Sscottl /* Data for being a dmar */ 159269615Sjhb struct mtx lock; 160174604Sscottl LIST_HEAD(, dmar_ctx) contexts; 161174604Sscottl struct unrhdr *domids; 162174604Sscottl vm_object_t ctx_obj; 163174604Sscottl u_int barrier_flags; 164174604Sscottl 165174604Sscottl /* Fault handler data */ 166174604Sscottl struct mtx fault_lock; 167174604Sscottl uint64_t *fault_log; 168174604Sscottl int fault_log_head; 169174604Sscottl int fault_log_tail; 170174604Sscottl int fault_log_size; 171174604Sscottl struct task fault_task; 172174604Sscottl struct taskqueue *fault_taskqueue; 173174604Sscottl 174174604Sscottl /* QI */ 175174604Sscottl int qi_enabled; 176174604Sscottl vm_offset_t inv_queue; 177174604Sscottl vm_size_t inv_queue_size; 178174604Sscottl uint32_t inv_queue_avail; 179174604Sscottl uint32_t inv_queue_tail; 180174604Sscottl volatile uint32_t inv_waitd_seq_hw; /* hw writes there on wait 181269615Sjhb descr completion */ 182174604Sscottl uint64_t inv_waitd_seq_hw_phys; 183174604Sscottl uint32_t inv_waitd_seq; /* next sequence number to use for wait descr */ 184174604Sscottl u_int inv_waitd_gen; /* seq number generation AKA seq overflows */ 185174604Sscottl u_int inv_seq_waiters; /* count of waiters for seq */ 186174604Sscottl u_int inv_queue_full; /* informational counter */ 187174604Sscottl 188174604Sscottl /* Delayed freeing of map entries queue processing */ 189174604Sscottl struct dmar_map_entries_tailq tlb_flush_entries; 190174604Sscottl struct task qi_task; 191174604Sscottl struct taskqueue *qi_taskqueue; 192269615Sjhb 193174604Sscottl /* Busdma delayed map load */ 194174604Sscottl struct task dmamap_load_task; 195174604Sscottl TAILQ_HEAD(, bus_dmamap_dmar) delayed_maps; 196174604Sscottl struct taskqueue *delayed_taskqueue; 197174604Sscottl}; 198174604Sscottl 199174604Sscottl#define DMAR_LOCK(dmar) mtx_lock(&(dmar)->lock) 200174604Sscottl#define DMAR_UNLOCK(dmar) mtx_unlock(&(dmar)->lock) 201174604Sscottl#define DMAR_ASSERT_LOCKED(dmar) mtx_assert(&(dmar)->lock, MA_OWNED) 202174604Sscottl 203174604Sscottl#define DMAR_FAULT_LOCK(dmar) mtx_lock_spin(&(dmar)->fault_lock) 204174604Sscottl#define DMAR_FAULT_UNLOCK(dmar) mtx_unlock_spin(&(dmar)->fault_lock) 205174604Sscottl#define DMAR_FAULT_ASSERT_LOCKED(dmar) mtx_assert(&(dmar)->fault_lock, MA_OWNED) 206174604Sscottl 207#define DMAR_IS_COHERENT(dmar) (((dmar)->hw_ecap & DMAR_ECAP_C) != 0) 208#define DMAR_HAS_QI(dmar) (((dmar)->hw_ecap & DMAR_ECAP_QI) != 0) 209 210/* Barrier ids */ 211#define DMAR_BARRIER_RMRR 0 212#define DMAR_BARRIER_USEQ 1 213 214struct dmar_unit *dmar_find(device_t dev); 215 216u_int dmar_nd2mask(u_int nd); 217bool dmar_pglvl_supported(struct dmar_unit *unit, int pglvl); 218int ctx_set_agaw(struct dmar_ctx *ctx, int mgaw); 219int dmar_maxaddr2mgaw(struct dmar_unit* unit, dmar_gaddr_t maxaddr, 220 bool allow_less); 221vm_pindex_t pglvl_max_pages(int pglvl); 222int ctx_is_sp_lvl(struct dmar_ctx *ctx, int lvl); 223dmar_gaddr_t pglvl_page_size(int total_pglvl, int lvl); 224dmar_gaddr_t ctx_page_size(struct dmar_ctx *ctx, int lvl); 225int calc_am(struct dmar_unit *unit, dmar_gaddr_t base, dmar_gaddr_t size, 226 dmar_gaddr_t *isizep); 227struct vm_page *dmar_pgalloc(vm_object_t obj, vm_pindex_t idx, int flags); 228void dmar_pgfree(vm_object_t obj, vm_pindex_t idx, int flags); 229void *dmar_map_pgtbl(vm_object_t obj, vm_pindex_t idx, int flags, 230 struct sf_buf **sf); 231void dmar_unmap_pgtbl(struct sf_buf *sf, bool coherent); 232int dmar_load_root_entry_ptr(struct dmar_unit *unit); 233int dmar_inv_ctx_glob(struct dmar_unit *unit); 234int dmar_inv_iotlb_glob(struct dmar_unit *unit); 235int dmar_flush_write_bufs(struct dmar_unit *unit); 236int dmar_enable_translation(struct dmar_unit *unit); 237int dmar_disable_translation(struct dmar_unit *unit); 238bool dmar_barrier_enter(struct dmar_unit *dmar, u_int barrier_id); 239void dmar_barrier_exit(struct dmar_unit *dmar, u_int barrier_id); 240 241int dmar_fault_intr(void *arg); 242void dmar_enable_fault_intr(struct dmar_unit *unit); 243void dmar_disable_fault_intr(struct dmar_unit *unit); 244int dmar_init_fault_log(struct dmar_unit *unit); 245void dmar_fini_fault_log(struct dmar_unit *unit); 246 247int dmar_qi_intr(void *arg); 248void dmar_enable_qi_intr(struct dmar_unit *unit); 249void dmar_disable_qi_intr(struct dmar_unit *unit); 250int dmar_init_qi(struct dmar_unit *unit); 251void dmar_fini_qi(struct dmar_unit *unit); 252void dmar_qi_invalidate_locked(struct dmar_ctx *ctx, dmar_gaddr_t start, 253 dmar_gaddr_t size, struct dmar_qi_genseq *pseq); 254void dmar_qi_invalidate_ctx_glob_locked(struct dmar_unit *unit); 255void dmar_qi_invalidate_iotlb_glob_locked(struct dmar_unit *unit); 256 257vm_object_t ctx_get_idmap_pgtbl(struct dmar_ctx *ctx, dmar_gaddr_t maxaddr); 258void put_idmap_pgtbl(vm_object_t obj); 259int ctx_map_buf(struct dmar_ctx *ctx, dmar_gaddr_t base, dmar_gaddr_t size, 260 vm_page_t *ma, uint64_t pflags, int flags); 261int ctx_unmap_buf(struct dmar_ctx *ctx, dmar_gaddr_t base, dmar_gaddr_t size, 262 int flags); 263void ctx_flush_iotlb_sync(struct dmar_ctx *ctx, dmar_gaddr_t base, 264 dmar_gaddr_t size); 265int ctx_alloc_pgtbl(struct dmar_ctx *ctx); 266void ctx_free_pgtbl(struct dmar_ctx *ctx); 267 268struct dmar_ctx *dmar_instantiate_ctx(struct dmar_unit *dmar, device_t dev, 269 bool rmrr); 270struct dmar_ctx *dmar_get_ctx(struct dmar_unit *dmar, device_t dev, 271 uint16_t rid, bool id_mapped, bool rmrr_init); 272void dmar_free_ctx_locked(struct dmar_unit *dmar, struct dmar_ctx *ctx); 273void dmar_free_ctx(struct dmar_ctx *ctx); 274struct dmar_ctx *dmar_find_ctx_locked(struct dmar_unit *dmar, uint16_t rid); 275void dmar_ctx_unload_entry(struct dmar_map_entry *entry, bool free); 276void dmar_ctx_unload(struct dmar_ctx *ctx, 277 struct dmar_map_entries_tailq *entries, bool cansleep); 278void dmar_ctx_free_entry(struct dmar_map_entry *entry, bool free); 279 280int dmar_init_busdma(struct dmar_unit *unit); 281void dmar_fini_busdma(struct dmar_unit *unit); 282 283void dmar_gas_init_ctx(struct dmar_ctx *ctx); 284void dmar_gas_fini_ctx(struct dmar_ctx *ctx); 285struct dmar_map_entry *dmar_gas_alloc_entry(struct dmar_ctx *ctx, u_int flags); 286void dmar_gas_free_entry(struct dmar_ctx *ctx, struct dmar_map_entry *entry); 287void dmar_gas_free_space(struct dmar_ctx *ctx, struct dmar_map_entry *entry); 288int dmar_gas_map(struct dmar_ctx *ctx, const struct bus_dma_tag_common *common, 289 dmar_gaddr_t size, u_int eflags, u_int flags, vm_page_t *ma, 290 struct dmar_map_entry **res); 291void dmar_gas_free_region(struct dmar_ctx *ctx, struct dmar_map_entry *entry); 292int dmar_gas_map_region(struct dmar_ctx *ctx, struct dmar_map_entry *entry, 293 u_int eflags, u_int flags, vm_page_t *ma); 294int dmar_gas_reserve_region(struct dmar_ctx *ctx, dmar_gaddr_t start, 295 dmar_gaddr_t end); 296 297void dmar_ctx_parse_rmrr(struct dmar_ctx *ctx, device_t dev, 298 struct dmar_map_entries_tailq *rmrr_entries); 299int dmar_instantiate_rmrr_ctxs(struct dmar_unit *dmar); 300 301void dmar_quirks_post_ident(struct dmar_unit *dmar); 302void dmar_quirks_pre_use(struct dmar_unit *dmar); 303 304#define DMAR_GM_CANWAIT 0x0001 305#define DMAR_GM_CANSPLIT 0x0002 306 307#define DMAR_PGF_WAITOK 0x0001 308#define DMAR_PGF_ZERO 0x0002 309#define DMAR_PGF_ALLOC 0x0004 310#define DMAR_PGF_NOALLOC 0x0008 311#define DMAR_PGF_OBJL 0x0010 312 313extern dmar_haddr_t dmar_high; 314extern int haw; 315extern int dmar_tbl_pagecnt; 316extern int dmar_match_verbose; 317extern int dmar_check_free; 318 319static inline uint32_t 320dmar_read4(const struct dmar_unit *unit, int reg) 321{ 322 323 return (bus_read_4(unit->regs, reg)); 324} 325 326static inline uint64_t 327dmar_read8(const struct dmar_unit *unit, int reg) 328{ 329#ifdef __i386__ 330 uint32_t high, low; 331 332 low = bus_read_4(unit->regs, reg); 333 high = bus_read_4(unit->regs, reg + 4); 334 return (low | ((uint64_t)high << 32)); 335#else 336 return (bus_read_8(unit->regs, reg)); 337#endif 338} 339 340static inline void 341dmar_write4(const struct dmar_unit *unit, int reg, uint32_t val) 342{ 343 344 KASSERT(reg != DMAR_GCMD_REG || (val & DMAR_GCMD_TE) == 345 (unit->hw_gcmd & DMAR_GCMD_TE), 346 ("dmar%d clearing TE 0x%08x 0x%08x", unit->unit, 347 unit->hw_gcmd, val)); 348 bus_write_4(unit->regs, reg, val); 349} 350 351static inline void 352dmar_write8(const struct dmar_unit *unit, int reg, uint64_t val) 353{ 354 355 KASSERT(reg != DMAR_GCMD_REG, ("8byte GCMD write")); 356#ifdef __i386__ 357 uint32_t high, low; 358 359 low = val; 360 high = val >> 32; 361 bus_write_4(unit->regs, reg, low); 362 bus_write_4(unit->regs, reg + 4, high); 363#else 364 bus_write_8(unit->regs, reg, val); 365#endif 366} 367 368/* 369 * dmar_pte_store and dmar_pte_clear ensure that on i386, 32bit writes 370 * are issued in the correct order. For store, the lower word, 371 * containing the P or R and W bits, is set only after the high word 372 * is written. For clear, the P bit is cleared first, then the high 373 * word is cleared. 374 */ 375static inline void 376dmar_pte_store(volatile uint64_t *dst, uint64_t val) 377{ 378 379 KASSERT(*dst == 0, ("used pte %p oldval %jx newval %jx", 380 dst, (uintmax_t)*dst, (uintmax_t)val)); 381#ifdef __i386__ 382 volatile uint32_t *p; 383 uint32_t hi, lo; 384 385 hi = val >> 32; 386 lo = val; 387 p = (volatile uint32_t *)dst; 388 *(p + 1) = hi; 389 *p = lo; 390#else 391 *dst = val; 392#endif 393} 394 395static inline void 396dmar_pte_clear(volatile uint64_t *dst) 397{ 398#ifdef __i386__ 399 volatile uint32_t *p; 400 401 p = (volatile uint32_t *)dst; 402 *p = 0; 403 *(p + 1) = 0; 404#else 405 *dst = 0; 406#endif 407} 408 409static inline bool 410dmar_test_boundary(dmar_gaddr_t start, dmar_gaddr_t size, 411 dmar_gaddr_t boundary) 412{ 413 414 if (boundary == 0) 415 return (true); 416 return (start + size <= ((start + boundary) & ~(boundary - 1))); 417} 418 419#ifdef INVARIANTS 420#define TD_PREP_PINNED_ASSERT \ 421 int old_td_pinned; \ 422 old_td_pinned = curthread->td_pinned 423#define TD_PINNED_ASSERT \ 424 KASSERT(curthread->td_pinned == old_td_pinned, \ 425 ("pin count leak: %d %d %s:%d", curthread->td_pinned, \ 426 old_td_pinned, __FILE__, __LINE__)) 427#else 428#define TD_PREP_PINNED_ASSERT 429#define TD_PINNED_ASSERT 430#endif 431 432#endif 433