apicvar.h revision 340016 
1/*-
2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: stable/11/sys/x86/include/apicvar.h 340016 2018-11-01 18:34:26Z jhb $
27 */
28
29#ifndef _X86_APICVAR_H_
30#define _X86_APICVAR_H_
31
32/*
33 * Local && I/O APIC variable definitions.
34 */
35
36/*
37 * Layout of local APIC interrupt vectors:
38 *
39 *	0xff (255)  +-------------+
40 *                  |             | 15 (Spurious / IPIs / Local Interrupts)
41 *	0xf0 (240)  +-------------+
42 *                  |             | 14 (I/O Interrupts / Timer)
43 *	0xe0 (224)  +-------------+
44 *                  |             | 13 (I/O Interrupts)
45 *	0xd0 (208)  +-------------+
46 *                  |             | 12 (I/O Interrupts)
47 *	0xc0 (192)  +-------------+
48 *                  |             | 11 (I/O Interrupts)
49 *	0xb0 (176)  +-------------+
50 *                  |             | 10 (I/O Interrupts)
51 *	0xa0 (160)  +-------------+
52 *                  |             | 9 (I/O Interrupts)
53 *	0x90 (144)  +-------------+
54 *                  |             | 8 (I/O Interrupts / System Calls)
55 *	0x80 (128)  +-------------+
56 *                  |             | 7 (I/O Interrupts)
57 *	0x70 (112)  +-------------+
58 *                  |             | 6 (I/O Interrupts)
59 *	0x60 (96)   +-------------+
60 *                  |             | 5 (I/O Interrupts)
61 *	0x50 (80)   +-------------+
62 *                  |             | 4 (I/O Interrupts)
63 *	0x40 (64)   +-------------+
64 *                  |             | 3 (I/O Interrupts)
65 *	0x30 (48)   +-------------+
66 *                  |             | 2 (ATPIC Interrupts)
67 *	0x20 (32)   +-------------+
68 *                  |             | 1 (Exceptions, traps, faults, etc.)
69 *	0x10 (16)   +-------------+
70 *                  |             | 0 (Exceptions, traps, faults, etc.)
71 *	0x00 (0)    +-------------+
72 *
73 * Note: 0x80 needs to be handled specially and not allocated to an
74 * I/O device!
75 */
76
77#define	MAX_APIC_ID	0xfe
78#define	APIC_ID_ALL	0xff
79
80/* I/O Interrupts are used for external devices such as ISA, PCI, etc. */
81#define	APIC_IO_INTS	(IDT_IO_INTS + 16)
82#define	APIC_NUM_IOINTS	191
83
84/* The timer interrupt is used for clock handling and drives hardclock, etc. */
85#define	APIC_TIMER_INT	(APIC_IO_INTS + APIC_NUM_IOINTS)
86
87/*
88 ********************* !!! WARNING !!! ******************************
89 * Each local apic has an interrupt receive fifo that is two entries deep
90 * for each interrupt priority class (higher 4 bits of interrupt vector).
91 * Once the fifo is full the APIC can no longer receive interrupts for this
92 * class and sending IPIs from other CPUs will be blocked.
93 * To avoid deadlocks there should be no more than two IPI interrupts
94 * pending at the same time.
95 * Currently this is guaranteed by dividing the IPIs in two groups that have
96 * each at most one IPI interrupt pending. The first group is protected by the
97 * smp_ipi_mtx and waits for the completion of the IPI (Only one IPI user
98 * at a time) The second group uses a single interrupt and a bitmap to avoid
99 * redundant IPI interrupts.
100 */
101
102/* Interrupts for local APIC LVT entries other than the timer. */
103#define	APIC_LOCAL_INTS	240
104#define	APIC_ERROR_INT	APIC_LOCAL_INTS
105#define	APIC_THERMAL_INT (APIC_LOCAL_INTS + 1)
106#define	APIC_CMC_INT	(APIC_LOCAL_INTS + 2)
107#define	APIC_IPI_INTS	(APIC_LOCAL_INTS + 3)
108
109#define	IPI_RENDEZVOUS	(APIC_IPI_INTS)		/* Inter-CPU rendezvous. */
110#define	IPI_INVLTLB	(APIC_IPI_INTS + 1)	/* TLB Shootdown IPIs */
111#define	IPI_INVLPG	(APIC_IPI_INTS + 2)
112#define	IPI_INVLRNG	(APIC_IPI_INTS + 3)
113#define	IPI_INVLCACHE	(APIC_IPI_INTS + 4)
114/* Vector to handle bitmap based IPIs */
115#define	IPI_BITMAP_VECTOR	(APIC_IPI_INTS + 5)
116
117/* IPIs handled by IPI_BITMAP_VECTOR */
118#define	IPI_AST		0 	/* Generate software trap. */
119#define IPI_PREEMPT     1
120#define IPI_HARDCLOCK   2
121#define IPI_BITMAP_LAST IPI_HARDCLOCK
122#define IPI_IS_BITMAPED(x) ((x) <= IPI_BITMAP_LAST)
123
124#define	IPI_STOP	(APIC_IPI_INTS + 6)	/* Stop CPU until restarted. */
125#define	IPI_SUSPEND	(APIC_IPI_INTS + 7)	/* Suspend CPU until restarted. */
126#define	IPI_DYN_FIRST	(APIC_IPI_INTS + 8)
127#define	IPI_DYN_LAST	(253)			/* IPIs allocated at runtime */
128
129/*
130 * IPI_STOP_HARD does not need to occupy a slot in the IPI vector space since
131 * it is delivered using an NMI anyways.
132 */
133#define	IPI_NMI_FIRST	254
134#define	IPI_TRACE	254			/* Interrupt for tracing. */
135#define	IPI_STOP_HARD	255			/* Stop CPU with a NMI. */
136
137/*
138 * The spurious interrupt can share the priority class with the IPIs since
139 * it is not a normal interrupt. (Does not use the APIC's interrupt fifo)
140 */
141#define	APIC_SPURIOUS_INT 255
142
143#ifndef LOCORE
144
145#define	APIC_IPI_DEST_SELF	-1
146#define	APIC_IPI_DEST_ALL	-2
147#define	APIC_IPI_DEST_OTHERS	-3
148
149#define	APIC_BUS_UNKNOWN	-1
150#define	APIC_BUS_ISA		0
151#define	APIC_BUS_EISA		1
152#define	APIC_BUS_PCI		2
153#define	APIC_BUS_MAX		APIC_BUS_PCI
154
155#define	IRQ_EXTINT		-1
156#define	IRQ_NMI			-2
157#define	IRQ_SMI			-3
158#define	IRQ_DISABLED		-4
159
160/*
161 * An APIC enumerator is a psuedo bus driver that enumerates APIC's including
162 * CPU's and I/O APIC's.
163 */
164struct apic_enumerator {
165	const char *apic_name;
166	int (*apic_probe)(void);
167	int (*apic_probe_cpus)(void);
168	int (*apic_setup_local)(void);
169	int (*apic_setup_io)(void);
170	SLIST_ENTRY(apic_enumerator) apic_next;
171};
172
173inthand_t
174	IDTVEC(apic_isr1), IDTVEC(apic_isr2), IDTVEC(apic_isr3),
175	IDTVEC(apic_isr4), IDTVEC(apic_isr5), IDTVEC(apic_isr6),
176	IDTVEC(apic_isr7), IDTVEC(cmcint), IDTVEC(errorint),
177	IDTVEC(spuriousint), IDTVEC(timerint),
178	IDTVEC(apic_isr1_pti), IDTVEC(apic_isr2_pti), IDTVEC(apic_isr3_pti),
179	IDTVEC(apic_isr4_pti), IDTVEC(apic_isr5_pti), IDTVEC(apic_isr6_pti),
180	IDTVEC(apic_isr7_pti), IDTVEC(cmcint_pti), IDTVEC(errorint_pti),
181	IDTVEC(spuriousint_pti), IDTVEC(timerint_pti);
182
183extern vm_paddr_t lapic_paddr;
184extern int apic_cpuids[];
185
186void	apic_register_enumerator(struct apic_enumerator *enumerator);
187void	*ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase);
188int	ioapic_disable_pin(void *cookie, u_int pin);
189int	ioapic_get_vector(void *cookie, u_int pin);
190void	ioapic_register(void *cookie);
191int	ioapic_remap_vector(void *cookie, u_int pin, int vector);
192int	ioapic_set_bus(void *cookie, u_int pin, int bus_type);
193int	ioapic_set_extint(void *cookie, u_int pin);
194int	ioapic_set_nmi(void *cookie, u_int pin);
195int	ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol);
196int	ioapic_set_triggermode(void *cookie, u_int pin,
197	    enum intr_trigger trigger);
198int	ioapic_set_smi(void *cookie, u_int pin);
199
200/*
201 * Struct containing pointers to APIC functions whose
202 * implementation is run time selectable.
203 */
204struct apic_ops {
205	void	(*create)(u_int, int);
206	void	(*init)(vm_paddr_t);
207	void	(*xapic_mode)(void);
208	bool	(*is_x2apic)(void);
209	void	(*setup)(int);
210	void	(*dump)(const char *);
211	void	(*disable)(void);
212	void	(*eoi)(void);
213	int	(*id)(void);
214	int	(*intr_pending)(u_int);
215	void	(*set_logical_id)(u_int, u_int, u_int);
216	u_int	(*cpuid)(u_int);
217
218	/* Vectors */
219	u_int	(*alloc_vector)(u_int, u_int);
220	u_int	(*alloc_vectors)(u_int, u_int *, u_int, u_int);
221	void	(*enable_vector)(u_int, u_int);
222	void	(*disable_vector)(u_int, u_int);
223	void	(*free_vector)(u_int, u_int, u_int);
224
225
226	/* PMC */
227	int	(*enable_pmc)(void);
228	void	(*disable_pmc)(void);
229	void	(*reenable_pmc)(void);
230
231	/* CMC */
232	void	(*enable_cmc)(void);
233
234	/* AMD ELVT */
235	int	(*enable_mca_elvt)(void);
236
237	/* IPI */
238	void	(*ipi_raw)(register_t, u_int);
239	void	(*ipi_vectored)(u_int, int);
240	int	(*ipi_wait)(int);
241	int	(*ipi_alloc)(inthand_t *ipifunc);
242	void	(*ipi_free)(int vector);
243
244	/* LVT */
245	int	(*set_lvt_mask)(u_int, u_int, u_char);
246	int	(*set_lvt_mode)(u_int, u_int, u_int32_t);
247	int	(*set_lvt_polarity)(u_int, u_int, enum intr_polarity);
248	int	(*set_lvt_triggermode)(u_int, u_int, enum intr_trigger);
249};
250
251extern struct apic_ops apic_ops;
252
253static inline void
254lapic_create(u_int apic_id, int boot_cpu)
255{
256
257	apic_ops.create(apic_id, boot_cpu);
258}
259
260static inline void
261lapic_init(vm_paddr_t addr)
262{
263
264	apic_ops.init(addr);
265}
266
267static inline void
268lapic_xapic_mode(void)
269{
270
271	apic_ops.xapic_mode();
272}
273
274static inline bool
275lapic_is_x2apic(void)
276{
277
278	return (apic_ops.is_x2apic());
279}
280
281static inline void
282lapic_setup(int boot)
283{
284
285	apic_ops.setup(boot);
286}
287
288static inline void
289lapic_dump(const char *str)
290{
291
292	apic_ops.dump(str);
293}
294
295static inline void
296lapic_disable(void)
297{
298
299	apic_ops.disable();
300}
301
302static inline void
303lapic_eoi(void)
304{
305
306	apic_ops.eoi();
307}
308
309static inline int
310lapic_id(void)
311{
312
313	return (apic_ops.id());
314}
315
316static inline int
317lapic_intr_pending(u_int vector)
318{
319
320	return (apic_ops.intr_pending(vector));
321}
322
323/* XXX: UNUSED */
324static inline void
325lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id)
326{
327
328	apic_ops.set_logical_id(apic_id, cluster, cluster_id);
329}
330
331static inline u_int
332apic_cpuid(u_int apic_id)
333{
334
335	return (apic_ops.cpuid(apic_id));
336}
337
338static inline u_int
339apic_alloc_vector(u_int apic_id, u_int irq)
340{
341
342	return (apic_ops.alloc_vector(apic_id, irq));
343}
344
345static inline u_int
346apic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count, u_int align)
347{
348
349	return (apic_ops.alloc_vectors(apic_id, irqs, count, align));
350}
351
352static inline void
353apic_enable_vector(u_int apic_id, u_int vector)
354{
355
356	apic_ops.enable_vector(apic_id, vector);
357}
358
359static inline void
360apic_disable_vector(u_int apic_id, u_int vector)
361{
362
363	apic_ops.disable_vector(apic_id, vector);
364}
365
366static inline void
367apic_free_vector(u_int apic_id, u_int vector, u_int irq)
368{
369
370	apic_ops.free_vector(apic_id, vector, irq);
371}
372
373static inline int
374lapic_enable_pmc(void)
375{
376
377	return (apic_ops.enable_pmc());
378}
379
380static inline void
381lapic_disable_pmc(void)
382{
383
384	apic_ops.disable_pmc();
385}
386
387static inline void
388lapic_reenable_pmc(void)
389{
390
391	apic_ops.reenable_pmc();
392}
393
394static inline void
395lapic_enable_cmc(void)
396{
397
398	apic_ops.enable_cmc();
399}
400
401static inline int
402lapic_enable_mca_elvt(void)
403{
404
405	return (apic_ops.enable_mca_elvt());
406}
407
408static inline void
409lapic_ipi_raw(register_t icrlo, u_int dest)
410{
411
412	apic_ops.ipi_raw(icrlo, dest);
413}
414
415static inline void
416lapic_ipi_vectored(u_int vector, int dest)
417{
418
419	apic_ops.ipi_vectored(vector, dest);
420}
421
422static inline int
423lapic_ipi_wait(int delay)
424{
425
426	return (apic_ops.ipi_wait(delay));
427}
428
429static inline int
430lapic_ipi_alloc(inthand_t *ipifunc)
431{
432
433	return (apic_ops.ipi_alloc(ipifunc));
434}
435
436static inline void
437lapic_ipi_free(int vector)
438{
439
440	return (apic_ops.ipi_free(vector));
441}
442
443static inline int
444lapic_set_lvt_mask(u_int apic_id, u_int lvt, u_char masked)
445{
446
447	return (apic_ops.set_lvt_mask(apic_id, lvt, masked));
448}
449
450static inline int
451lapic_set_lvt_mode(u_int apic_id, u_int lvt, u_int32_t mode)
452{
453
454	return (apic_ops.set_lvt_mode(apic_id, lvt, mode));
455}
456
457static inline int
458lapic_set_lvt_polarity(u_int apic_id, u_int lvt, enum intr_polarity pol)
459{
460
461	return (apic_ops.set_lvt_polarity(apic_id, lvt, pol));
462}
463
464static inline int
465lapic_set_lvt_triggermode(u_int apic_id, u_int lvt, enum intr_trigger trigger)
466{
467
468	return (apic_ops.set_lvt_triggermode(apic_id, lvt, trigger));
469}
470
471void	lapic_handle_cmc(void);
472void	lapic_handle_error(void);
473void	lapic_handle_intr(int vector, struct trapframe *frame);
474void	lapic_handle_timer(struct trapframe *frame);
475
476int	ioapic_get_rid(u_int apic_id, uint16_t *ridp);
477
478extern int x2apic_mode;
479extern int lapic_eoi_suppression;
480
481#ifdef _SYS_SYSCTL_H_
482SYSCTL_DECL(_hw_apic);
483#endif
484
485#endif /* !LOCORE */
486#endif /* _X86_APICVAR_H_ */
487