est.c revision 199273
1142140Snjl/*- 2142140Snjl * Copyright (c) 2004 Colin Percival 3142140Snjl * Copyright (c) 2005 Nate Lawson 4142140Snjl * All rights reserved. 5142140Snjl * 6142140Snjl * Redistribution and use in source and binary forms, with or without 7142140Snjl * modification, are permitted providing that the following conditions 8142140Snjl * are met: 9142140Snjl * 1. Redistributions of source code must retain the above copyright 10142140Snjl * notice, this list of conditions and the following disclaimer. 11142140Snjl * 2. Redistributions in binary form must reproduce the above copyright 12142140Snjl * notice, this list of conditions and the following disclaimer in the 13142140Snjl * documentation and/or other materials provided with the distribution. 14142140Snjl * 15142140Snjl * THIS SOFTWARE IS PROVIDED BY THE AUTHOR``AS IS'' AND ANY EXPRESS OR 16142140Snjl * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17142140Snjl * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18142140Snjl * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 19142140Snjl * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20142140Snjl * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21142140Snjl * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22142140Snjl * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23142140Snjl * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 24142140Snjl * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25142140Snjl * POSSIBILITY OF SUCH DAMAGE. 26142140Snjl */ 27142140Snjl 28142140Snjl#include <sys/cdefs.h> 29142140Snjl__FBSDID("$FreeBSD: head/sys/i386/cpufreq/est.c 199273 2009-11-14 16:20:07Z mav $"); 30142140Snjl 31142140Snjl#include <sys/param.h> 32142140Snjl#include <sys/bus.h> 33142140Snjl#include <sys/cpu.h> 34142140Snjl#include <sys/kernel.h> 35143902Snjl#include <sys/malloc.h> 36142140Snjl#include <sys/module.h> 37142140Snjl#include <sys/smp.h> 38142140Snjl#include <sys/systm.h> 39142140Snjl 40142140Snjl#include "cpufreq_if.h" 41182048Sjhb#include <machine/clock.h> 42185341Sjkim#include <machine/cputypes.h> 43142140Snjl#include <machine/md_var.h> 44177040Sjhb#include <machine/specialreg.h> 45142140Snjl 46193530Sjkim#include <contrib/dev/acpica/include/acpi.h> 47193530Sjkim 48144630Snjl#include <dev/acpica/acpivar.h> 49144630Snjl#include "acpi_if.h" 50144630Snjl 51142140Snjl/* Status/control registers (from the IA-32 System Programming Guide). */ 52142140Snjl#define MSR_PERF_STATUS 0x198 53142140Snjl#define MSR_PERF_CTL 0x199 54142140Snjl 55142140Snjl/* Register and bit for enabling SpeedStep. */ 56142140Snjl#define MSR_MISC_ENABLE 0x1a0 57142140Snjl#define MSR_SS_ENABLE (1<<16) 58142140Snjl 59142140Snjl/* Frequency and MSR control values. */ 60142140Snjltypedef struct { 61142140Snjl uint16_t freq; 62142140Snjl uint16_t volts; 63142140Snjl uint16_t id16; 64143902Snjl int power; 65142140Snjl} freq_info; 66142140Snjl 67142140Snjl/* Identifying characteristics of a processor and supported frequencies. */ 68142140Snjltypedef struct { 69185341Sjkim const u_int vendor_id; 70142140Snjl uint32_t id32; 71143902Snjl freq_info *freqtab; 72142140Snjl} cpu_info; 73142140Snjl 74142140Snjlstruct est_softc { 75143902Snjl device_t dev; 76143902Snjl int acpi_settings; 77182048Sjhb int msr_settings; 78143902Snjl freq_info *freq_list; 79142140Snjl}; 80142140Snjl 81142140Snjl/* Convert MHz and mV into IDs for passing to the MSR. */ 82142140Snjl#define ID16(MHz, mV, bus_clk) \ 83142140Snjl (((MHz / bus_clk) << 8) | ((mV ? mV - 700 : 0) >> 4)) 84142140Snjl#define ID32(MHz_hi, mV_hi, MHz_lo, mV_lo, bus_clk) \ 85142140Snjl ((ID16(MHz_lo, mV_lo, bus_clk) << 16) | (ID16(MHz_hi, mV_hi, bus_clk))) 86142140Snjl 87142140Snjl/* Format for storing IDs in our table. */ 88158446Snjl#define FREQ_INFO_PWR(MHz, mV, bus_clk, mW) \ 89158446Snjl { MHz, mV, ID16(MHz, mV, bus_clk), mW } 90142140Snjl#define FREQ_INFO(MHz, mV, bus_clk) \ 91158446Snjl FREQ_INFO_PWR(MHz, mV, bus_clk, CPUFREQ_VAL_UNKNOWN) 92142140Snjl#define INTEL(tab, zhi, vhi, zlo, vlo, bus_clk) \ 93185341Sjkim { CPU_VENDOR_INTEL, ID32(zhi, vhi, zlo, vlo, bus_clk), tab } 94158446Snjl#define CENTAUR(tab, zhi, vhi, zlo, vlo, bus_clk) \ 95185341Sjkim { CPU_VENDOR_CENTAUR, ID32(zhi, vhi, zlo, vlo, bus_clk), tab } 96142140Snjl 97182201Sjhbstatic int msr_info_enabled = 0; 98182201SjhbTUNABLE_INT("hw.est.msr_info", &msr_info_enabled); 99199273Smavstatic int strict = -1; 100199273SmavTUNABLE_INT("hw.est.strict", &strict); 101142140Snjl 102142140Snjl/* Default bus clock value for Centrino processors. */ 103142140Snjl#define INTEL_BUS_CLK 100 104142140Snjl 105142140Snjl/* XXX Update this if new CPUs have more settings. */ 106142140Snjl#define EST_MAX_SETTINGS 10 107142140SnjlCTASSERT(EST_MAX_SETTINGS <= MAX_SETTINGS); 108142140Snjl 109142140Snjl/* Estimate in microseconds of latency for performing a transition. */ 110177296Sphk#define EST_TRANS_LAT 1000 111142140Snjl 112142140Snjl/* 113142140Snjl * Frequency (MHz) and voltage (mV) settings. Data from the 114142140Snjl * Intel Pentium M Processor Datasheet (Order Number 252612), Table 5. 115142140Snjl * 116143902Snjl * Dothan processors have multiple VID#s with different settings for 117143902Snjl * each VID#. Since we can't uniquely identify this info 118142140Snjl * without undisclosed methods from Intel, we can't support newer 119142140Snjl * processors with this table method. If ACPI Px states are supported, 120143902Snjl * we get info from them. 121142140Snjl */ 122143902Snjlstatic freq_info PM17_130[] = { 123142140Snjl /* 130nm 1.70GHz Pentium M */ 124142140Snjl FREQ_INFO(1700, 1484, INTEL_BUS_CLK), 125142140Snjl FREQ_INFO(1400, 1308, INTEL_BUS_CLK), 126142140Snjl FREQ_INFO(1200, 1228, INTEL_BUS_CLK), 127142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 128142140Snjl FREQ_INFO( 800, 1004, INTEL_BUS_CLK), 129142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 130142140Snjl FREQ_INFO( 0, 0, 1), 131142140Snjl}; 132143902Snjlstatic freq_info PM16_130[] = { 133142140Snjl /* 130nm 1.60GHz Pentium M */ 134142140Snjl FREQ_INFO(1600, 1484, INTEL_BUS_CLK), 135142140Snjl FREQ_INFO(1400, 1420, INTEL_BUS_CLK), 136142140Snjl FREQ_INFO(1200, 1276, INTEL_BUS_CLK), 137142140Snjl FREQ_INFO(1000, 1164, INTEL_BUS_CLK), 138142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 139142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 140142140Snjl FREQ_INFO( 0, 0, 1), 141142140Snjl}; 142143902Snjlstatic freq_info PM15_130[] = { 143142140Snjl /* 130nm 1.50GHz Pentium M */ 144142140Snjl FREQ_INFO(1500, 1484, INTEL_BUS_CLK), 145142140Snjl FREQ_INFO(1400, 1452, INTEL_BUS_CLK), 146142140Snjl FREQ_INFO(1200, 1356, INTEL_BUS_CLK), 147142140Snjl FREQ_INFO(1000, 1228, INTEL_BUS_CLK), 148142140Snjl FREQ_INFO( 800, 1116, INTEL_BUS_CLK), 149142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 150142140Snjl FREQ_INFO( 0, 0, 1), 151142140Snjl}; 152143902Snjlstatic freq_info PM14_130[] = { 153142140Snjl /* 130nm 1.40GHz Pentium M */ 154142140Snjl FREQ_INFO(1400, 1484, INTEL_BUS_CLK), 155142140Snjl FREQ_INFO(1200, 1436, INTEL_BUS_CLK), 156142140Snjl FREQ_INFO(1000, 1308, INTEL_BUS_CLK), 157142140Snjl FREQ_INFO( 800, 1180, INTEL_BUS_CLK), 158142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 159142140Snjl FREQ_INFO( 0, 0, 1), 160142140Snjl}; 161143902Snjlstatic freq_info PM13_130[] = { 162142140Snjl /* 130nm 1.30GHz Pentium M */ 163142140Snjl FREQ_INFO(1300, 1388, INTEL_BUS_CLK), 164142140Snjl FREQ_INFO(1200, 1356, INTEL_BUS_CLK), 165142140Snjl FREQ_INFO(1000, 1292, INTEL_BUS_CLK), 166142140Snjl FREQ_INFO( 800, 1260, INTEL_BUS_CLK), 167142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 168142140Snjl FREQ_INFO( 0, 0, 1), 169142140Snjl}; 170143902Snjlstatic freq_info PM13_LV_130[] = { 171142140Snjl /* 130nm 1.30GHz Low Voltage Pentium M */ 172142140Snjl FREQ_INFO(1300, 1180, INTEL_BUS_CLK), 173142140Snjl FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 174142140Snjl FREQ_INFO(1100, 1100, INTEL_BUS_CLK), 175142140Snjl FREQ_INFO(1000, 1020, INTEL_BUS_CLK), 176142140Snjl FREQ_INFO( 900, 1004, INTEL_BUS_CLK), 177142140Snjl FREQ_INFO( 800, 988, INTEL_BUS_CLK), 178142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 179142140Snjl FREQ_INFO( 0, 0, 1), 180142140Snjl}; 181143902Snjlstatic freq_info PM12_LV_130[] = { 182142140Snjl /* 130 nm 1.20GHz Low Voltage Pentium M */ 183142140Snjl FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 184142140Snjl FREQ_INFO(1100, 1164, INTEL_BUS_CLK), 185142140Snjl FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 186142140Snjl FREQ_INFO( 900, 1020, INTEL_BUS_CLK), 187142140Snjl FREQ_INFO( 800, 1004, INTEL_BUS_CLK), 188142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 189142140Snjl FREQ_INFO( 0, 0, 1), 190142140Snjl}; 191143902Snjlstatic freq_info PM11_LV_130[] = { 192142140Snjl /* 130 nm 1.10GHz Low Voltage Pentium M */ 193142140Snjl FREQ_INFO(1100, 1180, INTEL_BUS_CLK), 194142140Snjl FREQ_INFO(1000, 1164, INTEL_BUS_CLK), 195142140Snjl FREQ_INFO( 900, 1100, INTEL_BUS_CLK), 196142140Snjl FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 197142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 198142140Snjl FREQ_INFO( 0, 0, 1), 199142140Snjl}; 200143902Snjlstatic freq_info PM11_ULV_130[] = { 201142140Snjl /* 130 nm 1.10GHz Ultra Low Voltage Pentium M */ 202142140Snjl FREQ_INFO(1100, 1004, INTEL_BUS_CLK), 203142140Snjl FREQ_INFO(1000, 988, INTEL_BUS_CLK), 204142140Snjl FREQ_INFO( 900, 972, INTEL_BUS_CLK), 205142140Snjl FREQ_INFO( 800, 956, INTEL_BUS_CLK), 206142140Snjl FREQ_INFO( 600, 844, INTEL_BUS_CLK), 207142140Snjl FREQ_INFO( 0, 0, 1), 208142140Snjl}; 209143902Snjlstatic freq_info PM10_ULV_130[] = { 210142140Snjl /* 130 nm 1.00GHz Ultra Low Voltage Pentium M */ 211142140Snjl FREQ_INFO(1000, 1004, INTEL_BUS_CLK), 212142140Snjl FREQ_INFO( 900, 988, INTEL_BUS_CLK), 213142140Snjl FREQ_INFO( 800, 972, INTEL_BUS_CLK), 214142140Snjl FREQ_INFO( 600, 844, INTEL_BUS_CLK), 215142140Snjl FREQ_INFO( 0, 0, 1), 216142140Snjl}; 217142140Snjl 218142140Snjl/* 219142140Snjl * Data from "Intel Pentium M Processor on 90nm Process with 220142140Snjl * 2-MB L2 Cache Datasheet", Order Number 302189, Table 5. 221142140Snjl */ 222143902Snjlstatic freq_info PM_765A_90[] = { 223142140Snjl /* 90 nm 2.10GHz Pentium M, VID #A */ 224142140Snjl FREQ_INFO(2100, 1340, INTEL_BUS_CLK), 225142140Snjl FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 226142140Snjl FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 227142140Snjl FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 228142140Snjl FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 229142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 230142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 231142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 232142140Snjl FREQ_INFO( 0, 0, 1), 233142140Snjl}; 234143902Snjlstatic freq_info PM_765B_90[] = { 235142140Snjl /* 90 nm 2.10GHz Pentium M, VID #B */ 236142140Snjl FREQ_INFO(2100, 1324, INTEL_BUS_CLK), 237142140Snjl FREQ_INFO(1800, 1260, INTEL_BUS_CLK), 238142140Snjl FREQ_INFO(1600, 1212, INTEL_BUS_CLK), 239142140Snjl FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 240142140Snjl FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 241142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 242142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 243142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 244142140Snjl FREQ_INFO( 0, 0, 1), 245142140Snjl}; 246143902Snjlstatic freq_info PM_765C_90[] = { 247142140Snjl /* 90 nm 2.10GHz Pentium M, VID #C */ 248142140Snjl FREQ_INFO(2100, 1308, INTEL_BUS_CLK), 249142140Snjl FREQ_INFO(1800, 1244, INTEL_BUS_CLK), 250142140Snjl FREQ_INFO(1600, 1212, INTEL_BUS_CLK), 251142140Snjl FREQ_INFO(1400, 1164, INTEL_BUS_CLK), 252142140Snjl FREQ_INFO(1200, 1116, INTEL_BUS_CLK), 253142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 254142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 255142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 256142140Snjl FREQ_INFO( 0, 0, 1), 257142140Snjl}; 258143902Snjlstatic freq_info PM_765E_90[] = { 259142140Snjl /* 90 nm 2.10GHz Pentium M, VID #E */ 260142140Snjl FREQ_INFO(2100, 1356, INTEL_BUS_CLK), 261142140Snjl FREQ_INFO(1800, 1292, INTEL_BUS_CLK), 262142140Snjl FREQ_INFO(1600, 1244, INTEL_BUS_CLK), 263142140Snjl FREQ_INFO(1400, 1196, INTEL_BUS_CLK), 264142140Snjl FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 265142140Snjl FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 266142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 267142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 268142140Snjl FREQ_INFO( 0, 0, 1), 269142140Snjl}; 270143902Snjlstatic freq_info PM_755A_90[] = { 271142140Snjl /* 90 nm 2.00GHz Pentium M, VID #A */ 272142140Snjl FREQ_INFO(2000, 1340, INTEL_BUS_CLK), 273142140Snjl FREQ_INFO(1800, 1292, INTEL_BUS_CLK), 274142140Snjl FREQ_INFO(1600, 1244, INTEL_BUS_CLK), 275142140Snjl FREQ_INFO(1400, 1196, INTEL_BUS_CLK), 276142140Snjl FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 277142140Snjl FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 278142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 279142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 280142140Snjl FREQ_INFO( 0, 0, 1), 281142140Snjl}; 282143902Snjlstatic freq_info PM_755B_90[] = { 283142140Snjl /* 90 nm 2.00GHz Pentium M, VID #B */ 284142140Snjl FREQ_INFO(2000, 1324, INTEL_BUS_CLK), 285142140Snjl FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 286142140Snjl FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 287142140Snjl FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 288142140Snjl FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 289142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 290142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 291142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 292142140Snjl FREQ_INFO( 0, 0, 1), 293142140Snjl}; 294143902Snjlstatic freq_info PM_755C_90[] = { 295142140Snjl /* 90 nm 2.00GHz Pentium M, VID #C */ 296142140Snjl FREQ_INFO(2000, 1308, INTEL_BUS_CLK), 297142140Snjl FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 298142140Snjl FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 299142140Snjl FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 300142140Snjl FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 301142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 302142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 303142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 304142140Snjl FREQ_INFO( 0, 0, 1), 305142140Snjl}; 306143902Snjlstatic freq_info PM_755D_90[] = { 307142140Snjl /* 90 nm 2.00GHz Pentium M, VID #D */ 308142140Snjl FREQ_INFO(2000, 1276, INTEL_BUS_CLK), 309142140Snjl FREQ_INFO(1800, 1244, INTEL_BUS_CLK), 310142140Snjl FREQ_INFO(1600, 1196, INTEL_BUS_CLK), 311142140Snjl FREQ_INFO(1400, 1164, INTEL_BUS_CLK), 312142140Snjl FREQ_INFO(1200, 1116, INTEL_BUS_CLK), 313142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 314142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 315142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 316142140Snjl FREQ_INFO( 0, 0, 1), 317142140Snjl}; 318143902Snjlstatic freq_info PM_745A_90[] = { 319142140Snjl /* 90 nm 1.80GHz Pentium M, VID #A */ 320142140Snjl FREQ_INFO(1800, 1340, INTEL_BUS_CLK), 321142140Snjl FREQ_INFO(1600, 1292, INTEL_BUS_CLK), 322142140Snjl FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 323142140Snjl FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 324142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 325142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 326142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 327142140Snjl FREQ_INFO( 0, 0, 1), 328142140Snjl}; 329143902Snjlstatic freq_info PM_745B_90[] = { 330142140Snjl /* 90 nm 1.80GHz Pentium M, VID #B */ 331142140Snjl FREQ_INFO(1800, 1324, INTEL_BUS_CLK), 332142140Snjl FREQ_INFO(1600, 1276, INTEL_BUS_CLK), 333142140Snjl FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 334142140Snjl FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 335142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 336142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 337142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 338142140Snjl FREQ_INFO( 0, 0, 1), 339142140Snjl}; 340143902Snjlstatic freq_info PM_745C_90[] = { 341142140Snjl /* 90 nm 1.80GHz Pentium M, VID #C */ 342142140Snjl FREQ_INFO(1800, 1308, INTEL_BUS_CLK), 343142140Snjl FREQ_INFO(1600, 1260, INTEL_BUS_CLK), 344142140Snjl FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 345142140Snjl FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 346142140Snjl FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 347142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 348142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 349142140Snjl FREQ_INFO( 0, 0, 1), 350142140Snjl}; 351143902Snjlstatic freq_info PM_745D_90[] = { 352142140Snjl /* 90 nm 1.80GHz Pentium M, VID #D */ 353142140Snjl FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 354142140Snjl FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 355142140Snjl FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 356142140Snjl FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 357142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 358142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 359142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 360142140Snjl FREQ_INFO( 0, 0, 1), 361142140Snjl}; 362143902Snjlstatic freq_info PM_735A_90[] = { 363142140Snjl /* 90 nm 1.70GHz Pentium M, VID #A */ 364142140Snjl FREQ_INFO(1700, 1340, INTEL_BUS_CLK), 365142140Snjl FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 366142140Snjl FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 367142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 368142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 369142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 370142140Snjl FREQ_INFO( 0, 0, 1), 371142140Snjl}; 372143902Snjlstatic freq_info PM_735B_90[] = { 373142140Snjl /* 90 nm 1.70GHz Pentium M, VID #B */ 374142140Snjl FREQ_INFO(1700, 1324, INTEL_BUS_CLK), 375142140Snjl FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 376142140Snjl FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 377142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 378142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 379142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 380142140Snjl FREQ_INFO( 0, 0, 1), 381142140Snjl}; 382143902Snjlstatic freq_info PM_735C_90[] = { 383142140Snjl /* 90 nm 1.70GHz Pentium M, VID #C */ 384142140Snjl FREQ_INFO(1700, 1308, INTEL_BUS_CLK), 385142140Snjl FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 386142140Snjl FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 387142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 388142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 389142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 390142140Snjl FREQ_INFO( 0, 0, 1), 391142140Snjl}; 392143902Snjlstatic freq_info PM_735D_90[] = { 393142140Snjl /* 90 nm 1.70GHz Pentium M, VID #D */ 394142140Snjl FREQ_INFO(1700, 1276, INTEL_BUS_CLK), 395142140Snjl FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 396142140Snjl FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 397142140Snjl FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 398142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 399142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 400142140Snjl FREQ_INFO( 0, 0, 1), 401142140Snjl}; 402143902Snjlstatic freq_info PM_725A_90[] = { 403142140Snjl /* 90 nm 1.60GHz Pentium M, VID #A */ 404142140Snjl FREQ_INFO(1600, 1340, INTEL_BUS_CLK), 405142140Snjl FREQ_INFO(1400, 1276, INTEL_BUS_CLK), 406142140Snjl FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 407142140Snjl FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 408142140Snjl FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 409142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 410142140Snjl FREQ_INFO( 0, 0, 1), 411142140Snjl}; 412143902Snjlstatic freq_info PM_725B_90[] = { 413142140Snjl /* 90 nm 1.60GHz Pentium M, VID #B */ 414142140Snjl FREQ_INFO(1600, 1324, INTEL_BUS_CLK), 415142140Snjl FREQ_INFO(1400, 1260, INTEL_BUS_CLK), 416142140Snjl FREQ_INFO(1200, 1196, INTEL_BUS_CLK), 417142140Snjl FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 418142140Snjl FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 419142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 420142140Snjl FREQ_INFO( 0, 0, 1), 421142140Snjl}; 422143902Snjlstatic freq_info PM_725C_90[] = { 423142140Snjl /* 90 nm 1.60GHz Pentium M, VID #C */ 424142140Snjl FREQ_INFO(1600, 1308, INTEL_BUS_CLK), 425142140Snjl FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 426142140Snjl FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 427142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 428142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 429142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 430142140Snjl FREQ_INFO( 0, 0, 1), 431142140Snjl}; 432143902Snjlstatic freq_info PM_725D_90[] = { 433142140Snjl /* 90 nm 1.60GHz Pentium M, VID #D */ 434142140Snjl FREQ_INFO(1600, 1276, INTEL_BUS_CLK), 435142140Snjl FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 436142140Snjl FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 437142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 438142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 439142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 440142140Snjl FREQ_INFO( 0, 0, 1), 441142140Snjl}; 442143902Snjlstatic freq_info PM_715A_90[] = { 443142140Snjl /* 90 nm 1.50GHz Pentium M, VID #A */ 444142140Snjl FREQ_INFO(1500, 1340, INTEL_BUS_CLK), 445142140Snjl FREQ_INFO(1200, 1228, INTEL_BUS_CLK), 446142140Snjl FREQ_INFO(1000, 1148, INTEL_BUS_CLK), 447142140Snjl FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 448142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 449142140Snjl FREQ_INFO( 0, 0, 1), 450142140Snjl}; 451143902Snjlstatic freq_info PM_715B_90[] = { 452142140Snjl /* 90 nm 1.50GHz Pentium M, VID #B */ 453142140Snjl FREQ_INFO(1500, 1324, INTEL_BUS_CLK), 454142140Snjl FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 455142140Snjl FREQ_INFO(1000, 1148, INTEL_BUS_CLK), 456142140Snjl FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 457142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 458142140Snjl FREQ_INFO( 0, 0, 1), 459142140Snjl}; 460143902Snjlstatic freq_info PM_715C_90[] = { 461142140Snjl /* 90 nm 1.50GHz Pentium M, VID #C */ 462142140Snjl FREQ_INFO(1500, 1308, INTEL_BUS_CLK), 463142140Snjl FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 464142140Snjl FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 465142140Snjl FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 466142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 467142140Snjl FREQ_INFO( 0, 0, 1), 468142140Snjl}; 469143902Snjlstatic freq_info PM_715D_90[] = { 470142140Snjl /* 90 nm 1.50GHz Pentium M, VID #D */ 471142140Snjl FREQ_INFO(1500, 1276, INTEL_BUS_CLK), 472142140Snjl FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 473142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 474142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 475142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 476142140Snjl FREQ_INFO( 0, 0, 1), 477142140Snjl}; 478155996Scpercivastatic freq_info PM_778_90[] = { 479155996Scperciva /* 90 nm 1.60GHz Low Voltage Pentium M */ 480155996Scperciva FREQ_INFO(1600, 1116, INTEL_BUS_CLK), 481155996Scperciva FREQ_INFO(1500, 1116, INTEL_BUS_CLK), 482155996Scperciva FREQ_INFO(1400, 1100, INTEL_BUS_CLK), 483155996Scperciva FREQ_INFO(1300, 1084, INTEL_BUS_CLK), 484155996Scperciva FREQ_INFO(1200, 1068, INTEL_BUS_CLK), 485155996Scperciva FREQ_INFO(1100, 1052, INTEL_BUS_CLK), 486155996Scperciva FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 487155996Scperciva FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 488155996Scperciva FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 489155996Scperciva FREQ_INFO( 600, 988, INTEL_BUS_CLK), 490155996Scperciva FREQ_INFO( 0, 0, 1), 491155996Scperciva}; 492155996Scpercivastatic freq_info PM_758_90[] = { 493155996Scperciva /* 90 nm 1.50GHz Low Voltage Pentium M */ 494155996Scperciva FREQ_INFO(1500, 1116, INTEL_BUS_CLK), 495155996Scperciva FREQ_INFO(1400, 1116, INTEL_BUS_CLK), 496155996Scperciva FREQ_INFO(1300, 1100, INTEL_BUS_CLK), 497155996Scperciva FREQ_INFO(1200, 1084, INTEL_BUS_CLK), 498155996Scperciva FREQ_INFO(1100, 1068, INTEL_BUS_CLK), 499155996Scperciva FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 500155996Scperciva FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 501155996Scperciva FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 502155996Scperciva FREQ_INFO( 600, 988, INTEL_BUS_CLK), 503155996Scperciva FREQ_INFO( 0, 0, 1), 504155996Scperciva}; 505143902Snjlstatic freq_info PM_738_90[] = { 506142140Snjl /* 90 nm 1.40GHz Low Voltage Pentium M */ 507142140Snjl FREQ_INFO(1400, 1116, INTEL_BUS_CLK), 508142140Snjl FREQ_INFO(1300, 1116, INTEL_BUS_CLK), 509142140Snjl FREQ_INFO(1200, 1100, INTEL_BUS_CLK), 510142140Snjl FREQ_INFO(1100, 1068, INTEL_BUS_CLK), 511142140Snjl FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 512142140Snjl FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 513142140Snjl FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 514142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 515142140Snjl FREQ_INFO( 0, 0, 1), 516142140Snjl}; 517155996Scpercivastatic freq_info PM_773G_90[] = { 518155996Scperciva /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #G */ 519155996Scperciva FREQ_INFO(1300, 956, INTEL_BUS_CLK), 520155996Scperciva FREQ_INFO(1200, 940, INTEL_BUS_CLK), 521155996Scperciva FREQ_INFO(1100, 924, INTEL_BUS_CLK), 522155996Scperciva FREQ_INFO(1000, 908, INTEL_BUS_CLK), 523155996Scperciva FREQ_INFO( 900, 876, INTEL_BUS_CLK), 524155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 525155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 526155996Scperciva}; 527155996Scpercivastatic freq_info PM_773H_90[] = { 528155996Scperciva /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #H */ 529155996Scperciva FREQ_INFO(1300, 940, INTEL_BUS_CLK), 530155996Scperciva FREQ_INFO(1200, 924, INTEL_BUS_CLK), 531155996Scperciva FREQ_INFO(1100, 908, INTEL_BUS_CLK), 532155996Scperciva FREQ_INFO(1000, 892, INTEL_BUS_CLK), 533155996Scperciva FREQ_INFO( 900, 876, INTEL_BUS_CLK), 534155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 535155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 536155996Scperciva}; 537155996Scpercivastatic freq_info PM_773I_90[] = { 538155996Scperciva /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #I */ 539155996Scperciva FREQ_INFO(1300, 924, INTEL_BUS_CLK), 540155996Scperciva FREQ_INFO(1200, 908, INTEL_BUS_CLK), 541155996Scperciva FREQ_INFO(1100, 892, INTEL_BUS_CLK), 542155996Scperciva FREQ_INFO(1000, 876, INTEL_BUS_CLK), 543155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 544155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 545155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 546155996Scperciva}; 547155996Scpercivastatic freq_info PM_773J_90[] = { 548155996Scperciva /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #J */ 549155996Scperciva FREQ_INFO(1300, 908, INTEL_BUS_CLK), 550155996Scperciva FREQ_INFO(1200, 908, INTEL_BUS_CLK), 551155996Scperciva FREQ_INFO(1100, 892, INTEL_BUS_CLK), 552155996Scperciva FREQ_INFO(1000, 876, INTEL_BUS_CLK), 553155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 554155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 555155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 556155996Scperciva}; 557155996Scpercivastatic freq_info PM_773K_90[] = { 558155996Scperciva /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #K */ 559155996Scperciva FREQ_INFO(1300, 892, INTEL_BUS_CLK), 560155996Scperciva FREQ_INFO(1200, 892, INTEL_BUS_CLK), 561155996Scperciva FREQ_INFO(1100, 876, INTEL_BUS_CLK), 562155996Scperciva FREQ_INFO(1000, 860, INTEL_BUS_CLK), 563155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 564155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 565155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 566155996Scperciva}; 567155996Scpercivastatic freq_info PM_773L_90[] = { 568155996Scperciva /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #L */ 569155996Scperciva FREQ_INFO(1300, 876, INTEL_BUS_CLK), 570155996Scperciva FREQ_INFO(1200, 876, INTEL_BUS_CLK), 571155996Scperciva FREQ_INFO(1100, 860, INTEL_BUS_CLK), 572155996Scperciva FREQ_INFO(1000, 860, INTEL_BUS_CLK), 573155996Scperciva FREQ_INFO( 900, 844, INTEL_BUS_CLK), 574155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 575155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 576155996Scperciva}; 577155996Scpercivastatic freq_info PM_753G_90[] = { 578155996Scperciva /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #G */ 579155996Scperciva FREQ_INFO(1200, 956, INTEL_BUS_CLK), 580155996Scperciva FREQ_INFO(1100, 940, INTEL_BUS_CLK), 581155996Scperciva FREQ_INFO(1000, 908, INTEL_BUS_CLK), 582155996Scperciva FREQ_INFO( 900, 892, INTEL_BUS_CLK), 583155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 584155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 585155996Scperciva}; 586155996Scpercivastatic freq_info PM_753H_90[] = { 587155996Scperciva /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #H */ 588155996Scperciva FREQ_INFO(1200, 940, INTEL_BUS_CLK), 589155996Scperciva FREQ_INFO(1100, 924, INTEL_BUS_CLK), 590155996Scperciva FREQ_INFO(1000, 908, INTEL_BUS_CLK), 591155996Scperciva FREQ_INFO( 900, 876, INTEL_BUS_CLK), 592155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 593155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 594155996Scperciva}; 595155996Scpercivastatic freq_info PM_753I_90[] = { 596155996Scperciva /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #I */ 597155996Scperciva FREQ_INFO(1200, 924, INTEL_BUS_CLK), 598155996Scperciva FREQ_INFO(1100, 908, INTEL_BUS_CLK), 599155996Scperciva FREQ_INFO(1000, 892, INTEL_BUS_CLK), 600155996Scperciva FREQ_INFO( 900, 876, INTEL_BUS_CLK), 601155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 602155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 603155996Scperciva}; 604155996Scpercivastatic freq_info PM_753J_90[] = { 605155996Scperciva /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #J */ 606155996Scperciva FREQ_INFO(1200, 908, INTEL_BUS_CLK), 607155996Scperciva FREQ_INFO(1100, 892, INTEL_BUS_CLK), 608155996Scperciva FREQ_INFO(1000, 876, INTEL_BUS_CLK), 609155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 610155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 611155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 612155996Scperciva}; 613155996Scpercivastatic freq_info PM_753K_90[] = { 614155996Scperciva /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #K */ 615155996Scperciva FREQ_INFO(1200, 892, INTEL_BUS_CLK), 616155996Scperciva FREQ_INFO(1100, 892, INTEL_BUS_CLK), 617155996Scperciva FREQ_INFO(1000, 876, INTEL_BUS_CLK), 618155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 619155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 620155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 621155996Scperciva}; 622155996Scpercivastatic freq_info PM_753L_90[] = { 623155996Scperciva /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #L */ 624155996Scperciva FREQ_INFO(1200, 876, INTEL_BUS_CLK), 625155996Scperciva FREQ_INFO(1100, 876, INTEL_BUS_CLK), 626155996Scperciva FREQ_INFO(1000, 860, INTEL_BUS_CLK), 627155996Scperciva FREQ_INFO( 900, 844, INTEL_BUS_CLK), 628155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 629155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 630155996Scperciva}; 631155996Scperciva 632155996Scpercivastatic freq_info PM_733JG_90[] = { 633155996Scperciva /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #G */ 634155996Scperciva FREQ_INFO(1100, 956, INTEL_BUS_CLK), 635155996Scperciva FREQ_INFO(1000, 940, INTEL_BUS_CLK), 636155996Scperciva FREQ_INFO( 900, 908, INTEL_BUS_CLK), 637155996Scperciva FREQ_INFO( 800, 876, INTEL_BUS_CLK), 638155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 639155996Scperciva}; 640155996Scpercivastatic freq_info PM_733JH_90[] = { 641155996Scperciva /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #H */ 642155996Scperciva FREQ_INFO(1100, 940, INTEL_BUS_CLK), 643155996Scperciva FREQ_INFO(1000, 924, INTEL_BUS_CLK), 644155996Scperciva FREQ_INFO( 900, 892, INTEL_BUS_CLK), 645155996Scperciva FREQ_INFO( 800, 876, INTEL_BUS_CLK), 646155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 647155996Scperciva}; 648155996Scpercivastatic freq_info PM_733JI_90[] = { 649155996Scperciva /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #I */ 650155996Scperciva FREQ_INFO(1100, 924, INTEL_BUS_CLK), 651155996Scperciva FREQ_INFO(1000, 908, INTEL_BUS_CLK), 652155996Scperciva FREQ_INFO( 900, 892, INTEL_BUS_CLK), 653155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 654155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 655155996Scperciva}; 656155996Scpercivastatic freq_info PM_733JJ_90[] = { 657155996Scperciva /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #J */ 658155996Scperciva FREQ_INFO(1100, 908, INTEL_BUS_CLK), 659155996Scperciva FREQ_INFO(1000, 892, INTEL_BUS_CLK), 660155996Scperciva FREQ_INFO( 900, 876, INTEL_BUS_CLK), 661155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 662155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 663155996Scperciva}; 664155996Scpercivastatic freq_info PM_733JK_90[] = { 665155996Scperciva /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #K */ 666155996Scperciva FREQ_INFO(1100, 892, INTEL_BUS_CLK), 667155996Scperciva FREQ_INFO(1000, 876, INTEL_BUS_CLK), 668155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 669155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 670155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 671155996Scperciva}; 672155996Scpercivastatic freq_info PM_733JL_90[] = { 673155996Scperciva /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #L */ 674155996Scperciva FREQ_INFO(1100, 876, INTEL_BUS_CLK), 675155996Scperciva FREQ_INFO(1000, 876, INTEL_BUS_CLK), 676155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 677155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 678155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 679155996Scperciva}; 680143902Snjlstatic freq_info PM_733_90[] = { 681142140Snjl /* 90 nm 1.10GHz Ultra Low Voltage Pentium M */ 682142140Snjl FREQ_INFO(1100, 940, INTEL_BUS_CLK), 683142140Snjl FREQ_INFO(1000, 924, INTEL_BUS_CLK), 684142140Snjl FREQ_INFO( 900, 892, INTEL_BUS_CLK), 685142140Snjl FREQ_INFO( 800, 876, INTEL_BUS_CLK), 686142140Snjl FREQ_INFO( 600, 812, INTEL_BUS_CLK), 687142140Snjl FREQ_INFO( 0, 0, 1), 688142140Snjl}; 689143902Snjlstatic freq_info PM_723_90[] = { 690142140Snjl /* 90 nm 1.00GHz Ultra Low Voltage Pentium M */ 691142140Snjl FREQ_INFO(1000, 940, INTEL_BUS_CLK), 692142140Snjl FREQ_INFO( 900, 908, INTEL_BUS_CLK), 693142140Snjl FREQ_INFO( 800, 876, INTEL_BUS_CLK), 694142140Snjl FREQ_INFO( 600, 812, INTEL_BUS_CLK), 695142140Snjl FREQ_INFO( 0, 0, 1), 696142140Snjl}; 697142140Snjl 698158446Snjl/* 699158446Snjl * VIA C7-M 500 MHz FSB, 400 MHz FSB, and ULV variants. 700158446Snjl * Data from the "VIA C7-M Processor BIOS Writer's Guide (v2.17)" datasheet. 701158446Snjl */ 702158446Snjlstatic freq_info C7M_795[] = { 703158446Snjl /* 2.00GHz Centaur C7-M 533 Mhz FSB */ 704158446Snjl FREQ_INFO_PWR(2000, 1148, 133, 20000), 705158446Snjl FREQ_INFO_PWR(1867, 1132, 133, 18000), 706158446Snjl FREQ_INFO_PWR(1600, 1100, 133, 15000), 707158446Snjl FREQ_INFO_PWR(1467, 1052, 133, 13000), 708158446Snjl FREQ_INFO_PWR(1200, 1004, 133, 10000), 709158446Snjl FREQ_INFO_PWR( 800, 844, 133, 7000), 710158446Snjl FREQ_INFO_PWR( 667, 844, 133, 6000), 711158446Snjl FREQ_INFO_PWR( 533, 844, 133, 5000), 712158446Snjl FREQ_INFO(0, 0, 1), 713158446Snjl}; 714158446Snjlstatic freq_info C7M_785[] = { 715158446Snjl /* 1.80GHz Centaur C7-M 533 Mhz FSB */ 716158446Snjl FREQ_INFO_PWR(1867, 1148, 133, 18000), 717158446Snjl FREQ_INFO_PWR(1600, 1100, 133, 15000), 718158446Snjl FREQ_INFO_PWR(1467, 1052, 133, 13000), 719158446Snjl FREQ_INFO_PWR(1200, 1004, 133, 10000), 720158446Snjl FREQ_INFO_PWR( 800, 844, 133, 7000), 721158446Snjl FREQ_INFO_PWR( 667, 844, 133, 6000), 722158446Snjl FREQ_INFO_PWR( 533, 844, 133, 5000), 723158446Snjl FREQ_INFO(0, 0, 1), 724158446Snjl}; 725158446Snjlstatic freq_info C7M_765[] = { 726158446Snjl /* 1.60GHz Centaur C7-M 533 Mhz FSB */ 727158446Snjl FREQ_INFO_PWR(1600, 1084, 133, 15000), 728158446Snjl FREQ_INFO_PWR(1467, 1052, 133, 13000), 729158446Snjl FREQ_INFO_PWR(1200, 1004, 133, 10000), 730158446Snjl FREQ_INFO_PWR( 800, 844, 133, 7000), 731158446Snjl FREQ_INFO_PWR( 667, 844, 133, 6000), 732158446Snjl FREQ_INFO_PWR( 533, 844, 133, 5000), 733158446Snjl FREQ_INFO(0, 0, 1), 734158446Snjl}; 735158446Snjl 736158446Snjlstatic freq_info C7M_794[] = { 737158446Snjl /* 2.00GHz Centaur C7-M 400 Mhz FSB */ 738158446Snjl FREQ_INFO_PWR(2000, 1148, 100, 20000), 739158446Snjl FREQ_INFO_PWR(1800, 1132, 100, 18000), 740158446Snjl FREQ_INFO_PWR(1600, 1100, 100, 15000), 741158446Snjl FREQ_INFO_PWR(1400, 1052, 100, 13000), 742158446Snjl FREQ_INFO_PWR(1000, 1004, 100, 10000), 743158446Snjl FREQ_INFO_PWR( 800, 844, 100, 7000), 744158446Snjl FREQ_INFO_PWR( 600, 844, 100, 6000), 745158446Snjl FREQ_INFO_PWR( 400, 844, 100, 5000), 746158446Snjl FREQ_INFO(0, 0, 1), 747158446Snjl}; 748158446Snjlstatic freq_info C7M_784[] = { 749158446Snjl /* 1.80GHz Centaur C7-M 400 Mhz FSB */ 750158446Snjl FREQ_INFO_PWR(1800, 1148, 100, 18000), 751158446Snjl FREQ_INFO_PWR(1600, 1100, 100, 15000), 752158446Snjl FREQ_INFO_PWR(1400, 1052, 100, 13000), 753158446Snjl FREQ_INFO_PWR(1000, 1004, 100, 10000), 754158446Snjl FREQ_INFO_PWR( 800, 844, 100, 7000), 755158446Snjl FREQ_INFO_PWR( 600, 844, 100, 6000), 756158446Snjl FREQ_INFO_PWR( 400, 844, 100, 5000), 757158446Snjl FREQ_INFO(0, 0, 1), 758158446Snjl}; 759158446Snjlstatic freq_info C7M_764[] = { 760158446Snjl /* 1.60GHz Centaur C7-M 400 Mhz FSB */ 761158446Snjl FREQ_INFO_PWR(1600, 1084, 100, 15000), 762158446Snjl FREQ_INFO_PWR(1400, 1052, 100, 13000), 763158446Snjl FREQ_INFO_PWR(1000, 1004, 100, 10000), 764158446Snjl FREQ_INFO_PWR( 800, 844, 100, 7000), 765158446Snjl FREQ_INFO_PWR( 600, 844, 100, 6000), 766158446Snjl FREQ_INFO_PWR( 400, 844, 100, 5000), 767158446Snjl FREQ_INFO(0, 0, 1), 768158446Snjl}; 769158446Snjlstatic freq_info C7M_754[] = { 770158446Snjl /* 1.50GHz Centaur C7-M 400 Mhz FSB */ 771158446Snjl FREQ_INFO_PWR(1500, 1004, 100, 12000), 772158446Snjl FREQ_INFO_PWR(1400, 988, 100, 11000), 773158446Snjl FREQ_INFO_PWR(1000, 940, 100, 9000), 774158446Snjl FREQ_INFO_PWR( 800, 844, 100, 7000), 775158446Snjl FREQ_INFO_PWR( 600, 844, 100, 6000), 776158446Snjl FREQ_INFO_PWR( 400, 844, 100, 5000), 777158446Snjl FREQ_INFO(0, 0, 1), 778158446Snjl}; 779158446Snjlstatic freq_info C7M_771[] = { 780158446Snjl /* 1.20GHz Centaur C7-M 400 Mhz FSB */ 781158446Snjl FREQ_INFO_PWR(1200, 860, 100, 7000), 782158446Snjl FREQ_INFO_PWR(1000, 860, 100, 6000), 783158446Snjl FREQ_INFO_PWR( 800, 844, 100, 5500), 784158446Snjl FREQ_INFO_PWR( 600, 844, 100, 5000), 785158446Snjl FREQ_INFO_PWR( 400, 844, 100, 4000), 786158446Snjl FREQ_INFO(0, 0, 1), 787158446Snjl}; 788158446Snjl 789158446Snjlstatic freq_info C7M_775_ULV[] = { 790158446Snjl /* 1.50GHz Centaur C7-M ULV */ 791158446Snjl FREQ_INFO_PWR(1500, 956, 100, 7500), 792158446Snjl FREQ_INFO_PWR(1400, 940, 100, 6000), 793158446Snjl FREQ_INFO_PWR(1000, 860, 100, 5000), 794158446Snjl FREQ_INFO_PWR( 800, 828, 100, 2800), 795158446Snjl FREQ_INFO_PWR( 600, 796, 100, 2500), 796158446Snjl FREQ_INFO_PWR( 400, 796, 100, 2000), 797158446Snjl FREQ_INFO(0, 0, 1), 798158446Snjl}; 799158446Snjlstatic freq_info C7M_772_ULV[] = { 800158446Snjl /* 1.20GHz Centaur C7-M ULV */ 801158446Snjl FREQ_INFO_PWR(1200, 844, 100, 5000), 802158446Snjl FREQ_INFO_PWR(1000, 844, 100, 4000), 803158446Snjl FREQ_INFO_PWR( 800, 828, 100, 2800), 804158446Snjl FREQ_INFO_PWR( 600, 796, 100, 2500), 805158446Snjl FREQ_INFO_PWR( 400, 796, 100, 2000), 806158446Snjl FREQ_INFO(0, 0, 1), 807158446Snjl}; 808158446Snjlstatic freq_info C7M_779_ULV[] = { 809158446Snjl /* 1.00GHz Centaur C7-M ULV */ 810158446Snjl FREQ_INFO_PWR(1000, 796, 100, 3500), 811158446Snjl FREQ_INFO_PWR( 800, 796, 100, 2800), 812158446Snjl FREQ_INFO_PWR( 600, 796, 100, 2500), 813158446Snjl FREQ_INFO_PWR( 400, 796, 100, 2000), 814158446Snjl FREQ_INFO(0, 0, 1), 815158446Snjl}; 816158446Snjlstatic freq_info C7M_770_ULV[] = { 817158446Snjl /* 1.00GHz Centaur C7-M ULV */ 818158446Snjl FREQ_INFO_PWR(1000, 844, 100, 5000), 819158446Snjl FREQ_INFO_PWR( 800, 796, 100, 2800), 820158446Snjl FREQ_INFO_PWR( 600, 796, 100, 2500), 821158446Snjl FREQ_INFO_PWR( 400, 796, 100, 2000), 822158446Snjl FREQ_INFO(0, 0, 1), 823158446Snjl}; 824158446Snjl 825143902Snjlstatic cpu_info ESTprocs[] = { 826142140Snjl INTEL(PM17_130, 1700, 1484, 600, 956, INTEL_BUS_CLK), 827142140Snjl INTEL(PM16_130, 1600, 1484, 600, 956, INTEL_BUS_CLK), 828142140Snjl INTEL(PM15_130, 1500, 1484, 600, 956, INTEL_BUS_CLK), 829142140Snjl INTEL(PM14_130, 1400, 1484, 600, 956, INTEL_BUS_CLK), 830142140Snjl INTEL(PM13_130, 1300, 1388, 600, 956, INTEL_BUS_CLK), 831142140Snjl INTEL(PM13_LV_130, 1300, 1180, 600, 956, INTEL_BUS_CLK), 832142140Snjl INTEL(PM12_LV_130, 1200, 1180, 600, 956, INTEL_BUS_CLK), 833142140Snjl INTEL(PM11_LV_130, 1100, 1180, 600, 956, INTEL_BUS_CLK), 834142140Snjl INTEL(PM11_ULV_130, 1100, 1004, 600, 844, INTEL_BUS_CLK), 835142140Snjl INTEL(PM10_ULV_130, 1000, 1004, 600, 844, INTEL_BUS_CLK), 836142140Snjl INTEL(PM_765A_90, 2100, 1340, 600, 988, INTEL_BUS_CLK), 837142140Snjl INTEL(PM_765B_90, 2100, 1324, 600, 988, INTEL_BUS_CLK), 838142140Snjl INTEL(PM_765C_90, 2100, 1308, 600, 988, INTEL_BUS_CLK), 839142140Snjl INTEL(PM_765E_90, 2100, 1356, 600, 988, INTEL_BUS_CLK), 840142140Snjl INTEL(PM_755A_90, 2000, 1340, 600, 988, INTEL_BUS_CLK), 841142140Snjl INTEL(PM_755B_90, 2000, 1324, 600, 988, INTEL_BUS_CLK), 842142140Snjl INTEL(PM_755C_90, 2000, 1308, 600, 988, INTEL_BUS_CLK), 843142140Snjl INTEL(PM_755D_90, 2000, 1276, 600, 988, INTEL_BUS_CLK), 844142140Snjl INTEL(PM_745A_90, 1800, 1340, 600, 988, INTEL_BUS_CLK), 845142140Snjl INTEL(PM_745B_90, 1800, 1324, 600, 988, INTEL_BUS_CLK), 846142140Snjl INTEL(PM_745C_90, 1800, 1308, 600, 988, INTEL_BUS_CLK), 847142140Snjl INTEL(PM_745D_90, 1800, 1276, 600, 988, INTEL_BUS_CLK), 848142140Snjl INTEL(PM_735A_90, 1700, 1340, 600, 988, INTEL_BUS_CLK), 849142140Snjl INTEL(PM_735B_90, 1700, 1324, 600, 988, INTEL_BUS_CLK), 850142140Snjl INTEL(PM_735C_90, 1700, 1308, 600, 988, INTEL_BUS_CLK), 851142140Snjl INTEL(PM_735D_90, 1700, 1276, 600, 988, INTEL_BUS_CLK), 852142140Snjl INTEL(PM_725A_90, 1600, 1340, 600, 988, INTEL_BUS_CLK), 853142140Snjl INTEL(PM_725B_90, 1600, 1324, 600, 988, INTEL_BUS_CLK), 854142140Snjl INTEL(PM_725C_90, 1600, 1308, 600, 988, INTEL_BUS_CLK), 855142140Snjl INTEL(PM_725D_90, 1600, 1276, 600, 988, INTEL_BUS_CLK), 856142140Snjl INTEL(PM_715A_90, 1500, 1340, 600, 988, INTEL_BUS_CLK), 857142140Snjl INTEL(PM_715B_90, 1500, 1324, 600, 988, INTEL_BUS_CLK), 858142140Snjl INTEL(PM_715C_90, 1500, 1308, 600, 988, INTEL_BUS_CLK), 859142140Snjl INTEL(PM_715D_90, 1500, 1276, 600, 988, INTEL_BUS_CLK), 860155996Scperciva INTEL(PM_778_90, 1600, 1116, 600, 988, INTEL_BUS_CLK), 861155996Scperciva INTEL(PM_758_90, 1500, 1116, 600, 988, INTEL_BUS_CLK), 862142140Snjl INTEL(PM_738_90, 1400, 1116, 600, 988, INTEL_BUS_CLK), 863155996Scperciva INTEL(PM_773G_90, 1300, 956, 600, 812, INTEL_BUS_CLK), 864155996Scperciva INTEL(PM_773H_90, 1300, 940, 600, 812, INTEL_BUS_CLK), 865155996Scperciva INTEL(PM_773I_90, 1300, 924, 600, 812, INTEL_BUS_CLK), 866155996Scperciva INTEL(PM_773J_90, 1300, 908, 600, 812, INTEL_BUS_CLK), 867155996Scperciva INTEL(PM_773K_90, 1300, 892, 600, 812, INTEL_BUS_CLK), 868155996Scperciva INTEL(PM_773L_90, 1300, 876, 600, 812, INTEL_BUS_CLK), 869155996Scperciva INTEL(PM_753G_90, 1200, 956, 600, 812, INTEL_BUS_CLK), 870155996Scperciva INTEL(PM_753H_90, 1200, 940, 600, 812, INTEL_BUS_CLK), 871155996Scperciva INTEL(PM_753I_90, 1200, 924, 600, 812, INTEL_BUS_CLK), 872155996Scperciva INTEL(PM_753J_90, 1200, 908, 600, 812, INTEL_BUS_CLK), 873155996Scperciva INTEL(PM_753K_90, 1200, 892, 600, 812, INTEL_BUS_CLK), 874155996Scperciva INTEL(PM_753L_90, 1200, 876, 600, 812, INTEL_BUS_CLK), 875155996Scperciva INTEL(PM_733JG_90, 1100, 956, 600, 812, INTEL_BUS_CLK), 876155996Scperciva INTEL(PM_733JH_90, 1100, 940, 600, 812, INTEL_BUS_CLK), 877155996Scperciva INTEL(PM_733JI_90, 1100, 924, 600, 812, INTEL_BUS_CLK), 878155996Scperciva INTEL(PM_733JJ_90, 1100, 908, 600, 812, INTEL_BUS_CLK), 879155996Scperciva INTEL(PM_733JK_90, 1100, 892, 600, 812, INTEL_BUS_CLK), 880155996Scperciva INTEL(PM_733JL_90, 1100, 876, 600, 812, INTEL_BUS_CLK), 881142140Snjl INTEL(PM_733_90, 1100, 940, 600, 812, INTEL_BUS_CLK), 882142140Snjl INTEL(PM_723_90, 1000, 940, 600, 812, INTEL_BUS_CLK), 883158446Snjl 884158446Snjl CENTAUR(C7M_795, 2000, 1148, 533, 844, 133), 885158446Snjl CENTAUR(C7M_794, 2000, 1148, 400, 844, 100), 886158446Snjl CENTAUR(C7M_785, 1867, 1148, 533, 844, 133), 887158446Snjl CENTAUR(C7M_784, 1800, 1148, 400, 844, 100), 888158446Snjl CENTAUR(C7M_765, 1600, 1084, 533, 844, 133), 889158446Snjl CENTAUR(C7M_764, 1600, 1084, 400, 844, 100), 890158446Snjl CENTAUR(C7M_754, 1500, 1004, 400, 844, 100), 891158446Snjl CENTAUR(C7M_775_ULV, 1500, 956, 400, 796, 100), 892158446Snjl CENTAUR(C7M_771, 1200, 860, 400, 844, 100), 893158446Snjl CENTAUR(C7M_772_ULV, 1200, 844, 400, 796, 100), 894158446Snjl CENTAUR(C7M_779_ULV, 1000, 796, 400, 796, 100), 895158446Snjl CENTAUR(C7M_770_ULV, 1000, 844, 400, 796, 100), 896185341Sjkim { 0, 0, NULL }, 897142140Snjl}; 898142140Snjl 899142140Snjlstatic void est_identify(driver_t *driver, device_t parent); 900144630Snjlstatic int est_features(driver_t *driver, u_int *features); 901142140Snjlstatic int est_probe(device_t parent); 902142140Snjlstatic int est_attach(device_t parent); 903142140Snjlstatic int est_detach(device_t parent); 904143902Snjlstatic int est_get_info(device_t dev); 905143902Snjlstatic int est_acpi_info(device_t dev, freq_info **freqs); 906158446Snjlstatic int est_table_info(device_t dev, uint64_t msr, freq_info **freqs); 907182048Sjhbstatic int est_msr_info(device_t dev, uint64_t msr, freq_info **freqs); 908143902Snjlstatic freq_info *est_get_current(freq_info *freq_list); 909142140Snjlstatic int est_settings(device_t dev, struct cf_setting *sets, int *count); 910142140Snjlstatic int est_set(device_t dev, const struct cf_setting *set); 911142140Snjlstatic int est_get(device_t dev, struct cf_setting *set); 912142140Snjlstatic int est_type(device_t dev, int *type); 913176649Srpaulostatic int est_set_id16(device_t dev, uint16_t id16, int need_check); 914176649Srpaulostatic void est_get_id16(uint16_t *id16_p); 915142140Snjl 916142140Snjlstatic device_method_t est_methods[] = { 917142140Snjl /* Device interface */ 918142140Snjl DEVMETHOD(device_identify, est_identify), 919142140Snjl DEVMETHOD(device_probe, est_probe), 920142140Snjl DEVMETHOD(device_attach, est_attach), 921142140Snjl DEVMETHOD(device_detach, est_detach), 922142140Snjl 923142140Snjl /* cpufreq interface */ 924142140Snjl DEVMETHOD(cpufreq_drv_set, est_set), 925142140Snjl DEVMETHOD(cpufreq_drv_get, est_get), 926142140Snjl DEVMETHOD(cpufreq_drv_type, est_type), 927142140Snjl DEVMETHOD(cpufreq_drv_settings, est_settings), 928144630Snjl 929144630Snjl /* ACPI interface */ 930144630Snjl DEVMETHOD(acpi_get_features, est_features), 931144630Snjl 932142140Snjl {0, 0} 933142140Snjl}; 934142140Snjl 935142140Snjlstatic driver_t est_driver = { 936142140Snjl "est", 937142140Snjl est_methods, 938142140Snjl sizeof(struct est_softc), 939142140Snjl}; 940142140Snjl 941142140Snjlstatic devclass_t est_devclass; 942142140SnjlDRIVER_MODULE(est, cpu, est_driver, est_devclass, 0, 0); 943142140Snjl 944144630Snjlstatic int 945144630Snjlest_features(driver_t *driver, u_int *features) 946144630Snjl{ 947144630Snjl 948144630Snjl /* Notify the ACPI CPU that we support direct access to MSRs */ 949144630Snjl *features = ACPI_CAP_PERF_MSRS; 950144630Snjl return (0); 951144630Snjl} 952144630Snjl 953142140Snjlstatic void 954142140Snjlest_identify(driver_t *driver, device_t parent) 955142140Snjl{ 956144630Snjl device_t child; 957142140Snjl 958142140Snjl /* Make sure we're not being doubly invoked. */ 959142140Snjl if (device_find_child(parent, "est", -1) != NULL) 960142140Snjl return; 961142140Snjl 962142140Snjl /* Check that CPUID is supported and the vendor is Intel.*/ 963185341Sjkim if (cpu_high == 0 || (cpu_vendor_id != CPU_VENDOR_INTEL && 964185341Sjkim cpu_vendor_id != CPU_VENDOR_CENTAUR)) 965142140Snjl return; 966142140Snjl 967158446Snjl /* 968177040Sjhb * Check if the CPU supports EST. 969158446Snjl */ 970177040Sjhb if (!(cpu_feature2 & CPUID2_EST)) 971142140Snjl return; 972142140Snjl 973142625Snjl /* 974142625Snjl * We add a child for each CPU since settings must be performed 975142625Snjl * on each CPU in the SMP case. 976142625Snjl */ 977181691Sjhb child = BUS_ADD_CHILD(parent, 10, "est", -1); 978144630Snjl if (child == NULL) 979142140Snjl device_printf(parent, "add est child failed\n"); 980142140Snjl} 981142140Snjl 982142140Snjlstatic int 983142140Snjlest_probe(device_t dev) 984142140Snjl{ 985142140Snjl device_t perf_dev; 986142140Snjl uint64_t msr; 987142140Snjl int error, type; 988142203Snjl 989142203Snjl if (resource_disabled("est", 0)) 990142203Snjl return (ENXIO); 991142140Snjl 992142140Snjl /* 993142140Snjl * If the ACPI perf driver has attached and is not just offering 994142140Snjl * info, let it manage things. 995142140Snjl */ 996142140Snjl perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 997142140Snjl if (perf_dev && device_is_attached(perf_dev)) { 998142140Snjl error = CPUFREQ_DRV_TYPE(perf_dev, &type); 999142140Snjl if (error == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0) 1000142140Snjl return (ENXIO); 1001142140Snjl } 1002142140Snjl 1003142140Snjl /* Attempt to enable SpeedStep if not currently enabled. */ 1004142140Snjl msr = rdmsr(MSR_MISC_ENABLE); 1005142140Snjl if ((msr & MSR_SS_ENABLE) == 0) { 1006142140Snjl wrmsr(MSR_MISC_ENABLE, msr | MSR_SS_ENABLE); 1007143902Snjl if (bootverbose) 1008143902Snjl device_printf(dev, "enabling SpeedStep\n"); 1009142140Snjl 1010142140Snjl /* Check if the enable failed. */ 1011142140Snjl msr = rdmsr(MSR_MISC_ENABLE); 1012142140Snjl if ((msr & MSR_SS_ENABLE) == 0) { 1013142140Snjl device_printf(dev, "failed to enable SpeedStep\n"); 1014142140Snjl return (ENXIO); 1015142140Snjl } 1016142140Snjl } 1017142140Snjl 1018142140Snjl device_set_desc(dev, "Enhanced SpeedStep Frequency Control"); 1019142140Snjl return (0); 1020142140Snjl} 1021142140Snjl 1022142140Snjlstatic int 1023142140Snjlest_attach(device_t dev) 1024142140Snjl{ 1025142140Snjl struct est_softc *sc; 1026142140Snjl 1027142140Snjl sc = device_get_softc(dev); 1028142140Snjl sc->dev = dev; 1029143902Snjl 1030199273Smav /* On SMP system we can't guarantie independent freq setting. */ 1031199273Smav if (strict == -1 && mp_ncpus > 1) 1032199273Smav strict = 0; 1033143902Snjl /* Check CPU for supported settings. */ 1034143902Snjl if (est_get_info(dev)) 1035143902Snjl return (ENXIO); 1036143902Snjl 1037142140Snjl cpufreq_register(dev); 1038142140Snjl return (0); 1039142140Snjl} 1040142140Snjl 1041142140Snjlstatic int 1042142140Snjlest_detach(device_t dev) 1043142140Snjl{ 1044143902Snjl struct est_softc *sc; 1045182908Sjhb int error; 1046143902Snjl 1047182908Sjhb error = cpufreq_unregister(dev); 1048182908Sjhb if (error) 1049182908Sjhb return (error); 1050182908Sjhb 1051143902Snjl sc = device_get_softc(dev); 1052182048Sjhb if (sc->acpi_settings || sc->msr_settings) 1053143902Snjl free(sc->freq_list, M_DEVBUF); 1054182908Sjhb return (0); 1055142140Snjl} 1056142140Snjl 1057143902Snjl/* 1058143902Snjl * Probe for supported CPU settings. First, check our static table of 1059143902Snjl * settings. If no match, try using the ones offered by acpi_perf 1060143902Snjl * (i.e., _PSS). We use ACPI second because some systems (IBM R/T40 1061143902Snjl * series) export both legacy SMM IO-based access and direct MSR access 1062143902Snjl * but the direct access specifies invalid values for _PSS. 1063143902Snjl */ 1064142140Snjlstatic int 1065143902Snjlest_get_info(device_t dev) 1066142140Snjl{ 1067143902Snjl struct est_softc *sc; 1068143902Snjl uint64_t msr; 1069143902Snjl int error; 1070143902Snjl 1071143902Snjl sc = device_get_softc(dev); 1072143902Snjl msr = rdmsr(MSR_PERF_STATUS); 1073158446Snjl error = est_table_info(dev, msr, &sc->freq_list); 1074143902Snjl if (error) 1075143902Snjl error = est_acpi_info(dev, &sc->freq_list); 1076182048Sjhb if (error) 1077182048Sjhb error = est_msr_info(dev, msr, &sc->freq_list); 1078143902Snjl 1079143902Snjl if (error) { 1080143902Snjl printf( 1081143902Snjl "est: CPU supports Enhanced Speedstep, but is not recognized.\n" 1082148583Scperciva "est: cpu_vendor %s, msr %0jx\n", cpu_vendor, msr); 1083143902Snjl return (ENXIO); 1084143902Snjl } 1085143902Snjl 1086143902Snjl return (0); 1087143902Snjl} 1088143902Snjl 1089143902Snjlstatic int 1090143902Snjlest_acpi_info(device_t dev, freq_info **freqs) 1091143902Snjl{ 1092143902Snjl struct est_softc *sc; 1093143902Snjl struct cf_setting *sets; 1094143902Snjl freq_info *table; 1095143902Snjl device_t perf_dev; 1096199273Smav int count, error, i, j; 1097179445Sjhb uint16_t saved_id16; 1098143902Snjl 1099143902Snjl perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 1100143902Snjl if (perf_dev == NULL || !device_is_attached(perf_dev)) 1101143902Snjl return (ENXIO); 1102143902Snjl 1103143902Snjl /* Fetch settings from acpi_perf. */ 1104143902Snjl sc = device_get_softc(dev); 1105143902Snjl table = NULL; 1106143902Snjl sets = malloc(MAX_SETTINGS * sizeof(*sets), M_TEMP, M_NOWAIT); 1107143902Snjl if (sets == NULL) 1108143902Snjl return (ENOMEM); 1109176714Sgibbs count = MAX_SETTINGS; 1110143902Snjl error = CPUFREQ_DRV_SETTINGS(perf_dev, sets, &count); 1111143902Snjl if (error) 1112143902Snjl goto out; 1113143902Snjl 1114143902Snjl /* Parse settings into our local table format. */ 1115144881Snjl table = malloc((count + 1) * sizeof(freq_info), M_DEVBUF, M_NOWAIT); 1116143902Snjl if (table == NULL) { 1117143902Snjl error = ENOMEM; 1118143902Snjl goto out; 1119143902Snjl } 1120179445Sjhb est_get_id16(&saved_id16); 1121176649Srpaulo for (i = 0, j = 0; i < count; i++) { 1122143902Snjl /* 1123176649Srpaulo * Confirm id16 value is correct. 1124143902Snjl */ 1125176649Srpaulo if (sets[i].freq > 0) { 1126199273Smav error = est_set_id16(dev, sets[i].spec[0], 1); 1127199273Smav if (error != 0 && strict) { 1128176649Srpaulo if (bootverbose) 1129176649Srpaulo device_printf(dev, "Invalid freq %u, " 1130176649Srpaulo "ignored.\n", sets[i].freq); 1131199273Smav continue; 1132199273Smav } else if (error != 0 && bootverbose) { 1133199273Smav device_printf(dev, "Can't check freq %u, " 1134199273Smav "it may be invalid\n", 1135199273Smav sets[i].freq); 1136176649Srpaulo } 1137199273Smav table[j].freq = sets[i].freq; 1138199273Smav table[j].volts = sets[i].volts; 1139199273Smav table[j].id16 = sets[i].spec[0]; 1140199273Smav table[j].power = sets[i].power; 1141199273Smav ++j; 1142176649Srpaulo } 1143143902Snjl } 1144179445Sjhb /* restore saved setting */ 1145179445Sjhb est_set_id16(dev, saved_id16, 0); 1146143902Snjl 1147144881Snjl /* Mark end of table with a terminator. */ 1148176649Srpaulo bzero(&table[j], sizeof(freq_info)); 1149144881Snjl 1150143902Snjl sc->acpi_settings = TRUE; 1151143902Snjl *freqs = table; 1152143902Snjl error = 0; 1153143902Snjl 1154143902Snjlout: 1155143902Snjl if (sets) 1156143902Snjl free(sets, M_TEMP); 1157143902Snjl if (error && table) 1158143902Snjl free(table, M_DEVBUF); 1159143902Snjl return (error); 1160143902Snjl} 1161143902Snjl 1162143902Snjlstatic int 1163158446Snjlest_table_info(device_t dev, uint64_t msr, freq_info **freqs) 1164143902Snjl{ 1165143902Snjl cpu_info *p; 1166142140Snjl uint32_t id; 1167142140Snjl 1168158446Snjl /* Find a table which matches (vendor, id32). */ 1169142140Snjl id = msr >> 32; 1170142140Snjl for (p = ESTprocs; p->id32 != 0; p++) { 1171185341Sjkim if (p->vendor_id == cpu_vendor_id && p->id32 == id) 1172142140Snjl break; 1173142140Snjl } 1174142140Snjl if (p->id32 == 0) 1175142140Snjl return (EOPNOTSUPP); 1176142140Snjl 1177142140Snjl /* Make sure the current setpoint is valid. */ 1178143902Snjl if (est_get_current(p->freqtab) == NULL) { 1179143902Snjl device_printf(dev, "current setting not found in table\n"); 1180142140Snjl return (EOPNOTSUPP); 1181143902Snjl } 1182142140Snjl 1183142140Snjl *freqs = p->freqtab; 1184142140Snjl return (0); 1185142140Snjl} 1186142140Snjl 1187182048Sjhbstatic int 1188182048Sjhbbus_speed_ok(int bus) 1189182048Sjhb{ 1190182048Sjhb 1191182048Sjhb switch (bus) { 1192182048Sjhb case 100: 1193182048Sjhb case 133: 1194182048Sjhb case 333: 1195182048Sjhb return (1); 1196182048Sjhb default: 1197182048Sjhb return (0); 1198182048Sjhb } 1199182048Sjhb} 1200182048Sjhb 1201182048Sjhb/* 1202182048Sjhb * Flesh out a simple rate table containing the high and low frequencies 1203182048Sjhb * based on the current clock speed and the upper 32 bits of the MSR. 1204182048Sjhb */ 1205182048Sjhbstatic int 1206182048Sjhbest_msr_info(device_t dev, uint64_t msr, freq_info **freqs) 1207182048Sjhb{ 1208182048Sjhb struct est_softc *sc; 1209182048Sjhb freq_info *fp; 1210182048Sjhb int bus, freq, volts; 1211182048Sjhb uint16_t id; 1212182048Sjhb 1213182201Sjhb if (!msr_info_enabled) 1214182201Sjhb return (EOPNOTSUPP); 1215182201Sjhb 1216182048Sjhb /* Figure out the bus clock. */ 1217182048Sjhb freq = tsc_freq / 1000000; 1218182048Sjhb id = msr >> 32; 1219182048Sjhb bus = freq / (id >> 8); 1220182048Sjhb device_printf(dev, "Guessed bus clock (high) of %d MHz\n", bus); 1221182048Sjhb if (!bus_speed_ok(bus)) { 1222182048Sjhb /* We may be running on the low frequency. */ 1223182048Sjhb id = msr >> 48; 1224182048Sjhb bus = freq / (id >> 8); 1225182048Sjhb device_printf(dev, "Guessed bus clock (low) of %d MHz\n", bus); 1226182048Sjhb if (!bus_speed_ok(bus)) 1227182048Sjhb return (EOPNOTSUPP); 1228182048Sjhb 1229182048Sjhb /* Calculate high frequency. */ 1230182048Sjhb id = msr >> 32; 1231182048Sjhb freq = ((id >> 8) & 0xff) * bus; 1232182048Sjhb } 1233182048Sjhb 1234182048Sjhb /* Fill out a new freq table containing just the high and low freqs. */ 1235182048Sjhb sc = device_get_softc(dev); 1236182048Sjhb fp = malloc(sizeof(freq_info) * 3, M_DEVBUF, M_WAITOK | M_ZERO); 1237182048Sjhb 1238182048Sjhb /* First, the high frequency. */ 1239182048Sjhb volts = id & 0xff; 1240182048Sjhb if (volts != 0) { 1241182048Sjhb volts <<= 4; 1242182048Sjhb volts += 700; 1243182048Sjhb } 1244182048Sjhb fp[0].freq = freq; 1245182048Sjhb fp[0].volts = volts; 1246182048Sjhb fp[0].id16 = id; 1247182048Sjhb fp[0].power = CPUFREQ_VAL_UNKNOWN; 1248182048Sjhb device_printf(dev, "Guessed high setting of %d MHz @ %d Mv\n", freq, 1249182048Sjhb volts); 1250182048Sjhb 1251182048Sjhb /* Second, the low frequency. */ 1252182048Sjhb id = msr >> 48; 1253182048Sjhb freq = ((id >> 8) & 0xff) * bus; 1254182048Sjhb volts = id & 0xff; 1255182048Sjhb if (volts != 0) { 1256182048Sjhb volts <<= 4; 1257182048Sjhb volts += 700; 1258182048Sjhb } 1259182048Sjhb fp[1].freq = freq; 1260182048Sjhb fp[1].volts = volts; 1261182048Sjhb fp[1].id16 = id; 1262182048Sjhb fp[1].power = CPUFREQ_VAL_UNKNOWN; 1263182048Sjhb device_printf(dev, "Guessed low setting of %d MHz @ %d Mv\n", freq, 1264182048Sjhb volts); 1265182048Sjhb 1266182048Sjhb /* Table is already terminated due to M_ZERO. */ 1267182048Sjhb sc->msr_settings = TRUE; 1268182048Sjhb *freqs = fp; 1269182048Sjhb return (0); 1270182048Sjhb} 1271182048Sjhb 1272176649Srpaulostatic void 1273176649Srpauloest_get_id16(uint16_t *id16_p) 1274176649Srpaulo{ 1275176649Srpaulo *id16_p = rdmsr(MSR_PERF_STATUS) & 0xffff; 1276176649Srpaulo} 1277176649Srpaulo 1278176649Srpaulostatic int 1279176649Srpauloest_set_id16(device_t dev, uint16_t id16, int need_check) 1280176649Srpaulo{ 1281176649Srpaulo uint64_t msr; 1282176649Srpaulo uint16_t new_id16; 1283176649Srpaulo int ret = 0; 1284176649Srpaulo 1285176649Srpaulo /* Read the current register, mask out the old, set the new id. */ 1286176649Srpaulo msr = rdmsr(MSR_PERF_CTL); 1287176649Srpaulo msr = (msr & ~0xffff) | id16; 1288176649Srpaulo wrmsr(MSR_PERF_CTL, msr); 1289176649Srpaulo 1290176649Srpaulo /* Wait a short while for the new setting. XXX Is this necessary? */ 1291176649Srpaulo DELAY(EST_TRANS_LAT); 1292176649Srpaulo 1293176649Srpaulo if (need_check) { 1294176649Srpaulo est_get_id16(&new_id16); 1295176649Srpaulo if (new_id16 != id16) { 1296176649Srpaulo if (bootverbose) 1297176649Srpaulo device_printf(dev, "Invalid id16 (set, cur) " 1298176649Srpaulo "= (%u, %u)\n", id16, new_id16); 1299176649Srpaulo ret = ENXIO; 1300176649Srpaulo } 1301176649Srpaulo } 1302176649Srpaulo return (ret); 1303176649Srpaulo} 1304176649Srpaulo 1305143902Snjlstatic freq_info * 1306143902Snjlest_get_current(freq_info *freq_list) 1307142140Snjl{ 1308143902Snjl freq_info *f; 1309142140Snjl int i; 1310142140Snjl uint16_t id16; 1311142140Snjl 1312142140Snjl /* 1313142140Snjl * Try a few times to get a valid value. Sometimes, if the CPU 1314142140Snjl * is in the middle of an asynchronous transition (i.e., P4TCC), 1315142140Snjl * we get a temporary invalid result. 1316142140Snjl */ 1317142140Snjl for (i = 0; i < 5; i++) { 1318176649Srpaulo est_get_id16(&id16); 1319142140Snjl for (f = freq_list; f->id16 != 0; f++) { 1320142140Snjl if (f->id16 == id16) 1321142140Snjl return (f); 1322142140Snjl } 1323142140Snjl DELAY(100); 1324142140Snjl } 1325142140Snjl return (NULL); 1326142140Snjl} 1327142140Snjl 1328142140Snjlstatic int 1329142140Snjlest_settings(device_t dev, struct cf_setting *sets, int *count) 1330142140Snjl{ 1331142140Snjl struct est_softc *sc; 1332143902Snjl freq_info *f; 1333142140Snjl int i; 1334142140Snjl 1335142140Snjl sc = device_get_softc(dev); 1336142140Snjl if (*count < EST_MAX_SETTINGS) 1337142140Snjl return (E2BIG); 1338142140Snjl 1339142140Snjl i = 0; 1340142394Snjl for (f = sc->freq_list; f->freq != 0; f++, i++) { 1341142140Snjl sets[i].freq = f->freq; 1342142140Snjl sets[i].volts = f->volts; 1343143902Snjl sets[i].power = f->power; 1344142140Snjl sets[i].lat = EST_TRANS_LAT; 1345142140Snjl sets[i].dev = dev; 1346142140Snjl } 1347142394Snjl *count = i; 1348142140Snjl 1349142140Snjl return (0); 1350142140Snjl} 1351142140Snjl 1352142140Snjlstatic int 1353142140Snjlest_set(device_t dev, const struct cf_setting *set) 1354142140Snjl{ 1355142140Snjl struct est_softc *sc; 1356143902Snjl freq_info *f; 1357142140Snjl 1358142140Snjl /* Find the setting matching the requested one. */ 1359142140Snjl sc = device_get_softc(dev); 1360142140Snjl for (f = sc->freq_list; f->freq != 0; f++) { 1361142140Snjl if (f->freq == set->freq) 1362142140Snjl break; 1363142140Snjl } 1364142140Snjl if (f->freq == 0) 1365142140Snjl return (EINVAL); 1366142140Snjl 1367142140Snjl /* Read the current register, mask out the old, set the new id. */ 1368176649Srpaulo est_set_id16(dev, f->id16, 0); 1369142140Snjl 1370142140Snjl return (0); 1371142140Snjl} 1372142140Snjl 1373142140Snjlstatic int 1374142140Snjlest_get(device_t dev, struct cf_setting *set) 1375142140Snjl{ 1376142140Snjl struct est_softc *sc; 1377143902Snjl freq_info *f; 1378142140Snjl 1379142140Snjl sc = device_get_softc(dev); 1380142140Snjl f = est_get_current(sc->freq_list); 1381142140Snjl if (f == NULL) 1382142140Snjl return (ENXIO); 1383142140Snjl 1384142140Snjl set->freq = f->freq; 1385142140Snjl set->volts = f->volts; 1386143902Snjl set->power = f->power; 1387142140Snjl set->lat = EST_TRANS_LAT; 1388142140Snjl set->dev = dev; 1389142140Snjl return (0); 1390142140Snjl} 1391142140Snjl 1392142140Snjlstatic int 1393142140Snjlest_type(device_t dev, int *type) 1394142140Snjl{ 1395142140Snjl 1396142140Snjl if (type == NULL) 1397142140Snjl return (EINVAL); 1398142140Snjl 1399142140Snjl *type = CPUFREQ_TYPE_ABSOLUTE; 1400142140Snjl return (0); 1401142140Snjl} 1402