est.c revision 176649
1142140Snjl/*- 2142140Snjl * Copyright (c) 2004 Colin Percival 3142140Snjl * Copyright (c) 2005 Nate Lawson 4142140Snjl * All rights reserved. 5142140Snjl * 6142140Snjl * Redistribution and use in source and binary forms, with or without 7142140Snjl * modification, are permitted providing that the following conditions 8142140Snjl * are met: 9142140Snjl * 1. Redistributions of source code must retain the above copyright 10142140Snjl * notice, this list of conditions and the following disclaimer. 11142140Snjl * 2. Redistributions in binary form must reproduce the above copyright 12142140Snjl * notice, this list of conditions and the following disclaimer in the 13142140Snjl * documentation and/or other materials provided with the distribution. 14142140Snjl * 15142140Snjl * THIS SOFTWARE IS PROVIDED BY THE AUTHOR``AS IS'' AND ANY EXPRESS OR 16142140Snjl * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17142140Snjl * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18142140Snjl * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 19142140Snjl * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20142140Snjl * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21142140Snjl * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22142140Snjl * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23142140Snjl * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 24142140Snjl * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25142140Snjl * POSSIBILITY OF SUCH DAMAGE. 26142140Snjl */ 27142140Snjl 28142140Snjl#include <sys/cdefs.h> 29142140Snjl__FBSDID("$FreeBSD: head/sys/i386/cpufreq/est.c 176649 2008-02-28 19:10:42Z rpaulo $"); 30142140Snjl 31142140Snjl#include <sys/param.h> 32142140Snjl#include <sys/bus.h> 33142140Snjl#include <sys/cpu.h> 34142140Snjl#include <sys/kernel.h> 35143902Snjl#include <sys/malloc.h> 36142140Snjl#include <sys/module.h> 37142140Snjl#include <sys/smp.h> 38142140Snjl#include <sys/systm.h> 39142140Snjl 40142140Snjl#include "cpufreq_if.h" 41142140Snjl#include <machine/md_var.h> 42142140Snjl 43144630Snjl#include <contrib/dev/acpica/acpi.h> 44144630Snjl#include <dev/acpica/acpivar.h> 45144630Snjl#include "acpi_if.h" 46144630Snjl 47142140Snjl/* Status/control registers (from the IA-32 System Programming Guide). */ 48142140Snjl#define MSR_PERF_STATUS 0x198 49142140Snjl#define MSR_PERF_CTL 0x199 50142140Snjl 51142140Snjl/* Register and bit for enabling SpeedStep. */ 52142140Snjl#define MSR_MISC_ENABLE 0x1a0 53142140Snjl#define MSR_SS_ENABLE (1<<16) 54142140Snjl 55142140Snjl/* Frequency and MSR control values. */ 56142140Snjltypedef struct { 57142140Snjl uint16_t freq; 58142140Snjl uint16_t volts; 59142140Snjl uint16_t id16; 60143902Snjl int power; 61142140Snjl} freq_info; 62142140Snjl 63142140Snjl/* Identifying characteristics of a processor and supported frequencies. */ 64142140Snjltypedef struct { 65142140Snjl const char *vendor; 66142140Snjl uint32_t id32; 67143902Snjl freq_info *freqtab; 68142140Snjl} cpu_info; 69142140Snjl 70142140Snjlstruct est_softc { 71143902Snjl device_t dev; 72143902Snjl int acpi_settings; 73143902Snjl freq_info *freq_list; 74142140Snjl}; 75142140Snjl 76142140Snjl/* Convert MHz and mV into IDs for passing to the MSR. */ 77142140Snjl#define ID16(MHz, mV, bus_clk) \ 78142140Snjl (((MHz / bus_clk) << 8) | ((mV ? mV - 700 : 0) >> 4)) 79142140Snjl#define ID32(MHz_hi, mV_hi, MHz_lo, mV_lo, bus_clk) \ 80142140Snjl ((ID16(MHz_lo, mV_lo, bus_clk) << 16) | (ID16(MHz_hi, mV_hi, bus_clk))) 81142140Snjl 82142140Snjl/* Format for storing IDs in our table. */ 83158446Snjl#define FREQ_INFO_PWR(MHz, mV, bus_clk, mW) \ 84158446Snjl { MHz, mV, ID16(MHz, mV, bus_clk), mW } 85142140Snjl#define FREQ_INFO(MHz, mV, bus_clk) \ 86158446Snjl FREQ_INFO_PWR(MHz, mV, bus_clk, CPUFREQ_VAL_UNKNOWN) 87142140Snjl#define INTEL(tab, zhi, vhi, zlo, vlo, bus_clk) \ 88158446Snjl { intel_id, ID32(zhi, vhi, zlo, vlo, bus_clk), tab } 89158446Snjl#define CENTAUR(tab, zhi, vhi, zlo, vlo, bus_clk) \ 90158446Snjl { centaur_id, ID32(zhi, vhi, zlo, vlo, bus_clk), tab } 91142140Snjl 92158446Snjlconst char intel_id[] = "GenuineIntel"; 93158446Snjlconst char centaur_id[] = "CentaurHauls"; 94142140Snjl 95142140Snjl/* Default bus clock value for Centrino processors. */ 96142140Snjl#define INTEL_BUS_CLK 100 97142140Snjl 98142140Snjl/* XXX Update this if new CPUs have more settings. */ 99142140Snjl#define EST_MAX_SETTINGS 10 100142140SnjlCTASSERT(EST_MAX_SETTINGS <= MAX_SETTINGS); 101142140Snjl 102142140Snjl/* Estimate in microseconds of latency for performing a transition. */ 103142140Snjl#define EST_TRANS_LAT 10 104142140Snjl 105142140Snjl/* 106142140Snjl * Frequency (MHz) and voltage (mV) settings. Data from the 107142140Snjl * Intel Pentium M Processor Datasheet (Order Number 252612), Table 5. 108142140Snjl * 109143902Snjl * Dothan processors have multiple VID#s with different settings for 110143902Snjl * each VID#. Since we can't uniquely identify this info 111142140Snjl * without undisclosed methods from Intel, we can't support newer 112142140Snjl * processors with this table method. If ACPI Px states are supported, 113143902Snjl * we get info from them. 114142140Snjl */ 115143902Snjlstatic freq_info PM17_130[] = { 116142140Snjl /* 130nm 1.70GHz Pentium M */ 117142140Snjl FREQ_INFO(1700, 1484, INTEL_BUS_CLK), 118142140Snjl FREQ_INFO(1400, 1308, INTEL_BUS_CLK), 119142140Snjl FREQ_INFO(1200, 1228, INTEL_BUS_CLK), 120142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 121142140Snjl FREQ_INFO( 800, 1004, INTEL_BUS_CLK), 122142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 123142140Snjl FREQ_INFO( 0, 0, 1), 124142140Snjl}; 125143902Snjlstatic freq_info PM16_130[] = { 126142140Snjl /* 130nm 1.60GHz Pentium M */ 127142140Snjl FREQ_INFO(1600, 1484, INTEL_BUS_CLK), 128142140Snjl FREQ_INFO(1400, 1420, INTEL_BUS_CLK), 129142140Snjl FREQ_INFO(1200, 1276, INTEL_BUS_CLK), 130142140Snjl FREQ_INFO(1000, 1164, INTEL_BUS_CLK), 131142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 132142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 133142140Snjl FREQ_INFO( 0, 0, 1), 134142140Snjl}; 135143902Snjlstatic freq_info PM15_130[] = { 136142140Snjl /* 130nm 1.50GHz Pentium M */ 137142140Snjl FREQ_INFO(1500, 1484, INTEL_BUS_CLK), 138142140Snjl FREQ_INFO(1400, 1452, INTEL_BUS_CLK), 139142140Snjl FREQ_INFO(1200, 1356, INTEL_BUS_CLK), 140142140Snjl FREQ_INFO(1000, 1228, INTEL_BUS_CLK), 141142140Snjl FREQ_INFO( 800, 1116, INTEL_BUS_CLK), 142142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 143142140Snjl FREQ_INFO( 0, 0, 1), 144142140Snjl}; 145143902Snjlstatic freq_info PM14_130[] = { 146142140Snjl /* 130nm 1.40GHz Pentium M */ 147142140Snjl FREQ_INFO(1400, 1484, INTEL_BUS_CLK), 148142140Snjl FREQ_INFO(1200, 1436, INTEL_BUS_CLK), 149142140Snjl FREQ_INFO(1000, 1308, INTEL_BUS_CLK), 150142140Snjl FREQ_INFO( 800, 1180, INTEL_BUS_CLK), 151142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 152142140Snjl FREQ_INFO( 0, 0, 1), 153142140Snjl}; 154143902Snjlstatic freq_info PM13_130[] = { 155142140Snjl /* 130nm 1.30GHz Pentium M */ 156142140Snjl FREQ_INFO(1300, 1388, INTEL_BUS_CLK), 157142140Snjl FREQ_INFO(1200, 1356, INTEL_BUS_CLK), 158142140Snjl FREQ_INFO(1000, 1292, INTEL_BUS_CLK), 159142140Snjl FREQ_INFO( 800, 1260, INTEL_BUS_CLK), 160142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 161142140Snjl FREQ_INFO( 0, 0, 1), 162142140Snjl}; 163143902Snjlstatic freq_info PM13_LV_130[] = { 164142140Snjl /* 130nm 1.30GHz Low Voltage Pentium M */ 165142140Snjl FREQ_INFO(1300, 1180, INTEL_BUS_CLK), 166142140Snjl FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 167142140Snjl FREQ_INFO(1100, 1100, INTEL_BUS_CLK), 168142140Snjl FREQ_INFO(1000, 1020, INTEL_BUS_CLK), 169142140Snjl FREQ_INFO( 900, 1004, INTEL_BUS_CLK), 170142140Snjl FREQ_INFO( 800, 988, INTEL_BUS_CLK), 171142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 172142140Snjl FREQ_INFO( 0, 0, 1), 173142140Snjl}; 174143902Snjlstatic freq_info PM12_LV_130[] = { 175142140Snjl /* 130 nm 1.20GHz Low Voltage Pentium M */ 176142140Snjl FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 177142140Snjl FREQ_INFO(1100, 1164, INTEL_BUS_CLK), 178142140Snjl FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 179142140Snjl FREQ_INFO( 900, 1020, INTEL_BUS_CLK), 180142140Snjl FREQ_INFO( 800, 1004, INTEL_BUS_CLK), 181142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 182142140Snjl FREQ_INFO( 0, 0, 1), 183142140Snjl}; 184143902Snjlstatic freq_info PM11_LV_130[] = { 185142140Snjl /* 130 nm 1.10GHz Low Voltage Pentium M */ 186142140Snjl FREQ_INFO(1100, 1180, INTEL_BUS_CLK), 187142140Snjl FREQ_INFO(1000, 1164, INTEL_BUS_CLK), 188142140Snjl FREQ_INFO( 900, 1100, INTEL_BUS_CLK), 189142140Snjl FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 190142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 191142140Snjl FREQ_INFO( 0, 0, 1), 192142140Snjl}; 193143902Snjlstatic freq_info PM11_ULV_130[] = { 194142140Snjl /* 130 nm 1.10GHz Ultra Low Voltage Pentium M */ 195142140Snjl FREQ_INFO(1100, 1004, INTEL_BUS_CLK), 196142140Snjl FREQ_INFO(1000, 988, INTEL_BUS_CLK), 197142140Snjl FREQ_INFO( 900, 972, INTEL_BUS_CLK), 198142140Snjl FREQ_INFO( 800, 956, INTEL_BUS_CLK), 199142140Snjl FREQ_INFO( 600, 844, INTEL_BUS_CLK), 200142140Snjl FREQ_INFO( 0, 0, 1), 201142140Snjl}; 202143902Snjlstatic freq_info PM10_ULV_130[] = { 203142140Snjl /* 130 nm 1.00GHz Ultra Low Voltage Pentium M */ 204142140Snjl FREQ_INFO(1000, 1004, INTEL_BUS_CLK), 205142140Snjl FREQ_INFO( 900, 988, INTEL_BUS_CLK), 206142140Snjl FREQ_INFO( 800, 972, INTEL_BUS_CLK), 207142140Snjl FREQ_INFO( 600, 844, INTEL_BUS_CLK), 208142140Snjl FREQ_INFO( 0, 0, 1), 209142140Snjl}; 210142140Snjl 211142140Snjl/* 212142140Snjl * Data from "Intel Pentium M Processor on 90nm Process with 213142140Snjl * 2-MB L2 Cache Datasheet", Order Number 302189, Table 5. 214142140Snjl */ 215143902Snjlstatic freq_info PM_765A_90[] = { 216142140Snjl /* 90 nm 2.10GHz Pentium M, VID #A */ 217142140Snjl FREQ_INFO(2100, 1340, INTEL_BUS_CLK), 218142140Snjl FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 219142140Snjl FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 220142140Snjl FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 221142140Snjl FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 222142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 223142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 224142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 225142140Snjl FREQ_INFO( 0, 0, 1), 226142140Snjl}; 227143902Snjlstatic freq_info PM_765B_90[] = { 228142140Snjl /* 90 nm 2.10GHz Pentium M, VID #B */ 229142140Snjl FREQ_INFO(2100, 1324, INTEL_BUS_CLK), 230142140Snjl FREQ_INFO(1800, 1260, INTEL_BUS_CLK), 231142140Snjl FREQ_INFO(1600, 1212, INTEL_BUS_CLK), 232142140Snjl FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 233142140Snjl FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 234142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 235142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 236142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 237142140Snjl FREQ_INFO( 0, 0, 1), 238142140Snjl}; 239143902Snjlstatic freq_info PM_765C_90[] = { 240142140Snjl /* 90 nm 2.10GHz Pentium M, VID #C */ 241142140Snjl FREQ_INFO(2100, 1308, INTEL_BUS_CLK), 242142140Snjl FREQ_INFO(1800, 1244, INTEL_BUS_CLK), 243142140Snjl FREQ_INFO(1600, 1212, INTEL_BUS_CLK), 244142140Snjl FREQ_INFO(1400, 1164, INTEL_BUS_CLK), 245142140Snjl FREQ_INFO(1200, 1116, INTEL_BUS_CLK), 246142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 247142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 248142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 249142140Snjl FREQ_INFO( 0, 0, 1), 250142140Snjl}; 251143902Snjlstatic freq_info PM_765E_90[] = { 252142140Snjl /* 90 nm 2.10GHz Pentium M, VID #E */ 253142140Snjl FREQ_INFO(2100, 1356, INTEL_BUS_CLK), 254142140Snjl FREQ_INFO(1800, 1292, INTEL_BUS_CLK), 255142140Snjl FREQ_INFO(1600, 1244, INTEL_BUS_CLK), 256142140Snjl FREQ_INFO(1400, 1196, INTEL_BUS_CLK), 257142140Snjl FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 258142140Snjl FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 259142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 260142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 261142140Snjl FREQ_INFO( 0, 0, 1), 262142140Snjl}; 263143902Snjlstatic freq_info PM_755A_90[] = { 264142140Snjl /* 90 nm 2.00GHz Pentium M, VID #A */ 265142140Snjl FREQ_INFO(2000, 1340, INTEL_BUS_CLK), 266142140Snjl FREQ_INFO(1800, 1292, INTEL_BUS_CLK), 267142140Snjl FREQ_INFO(1600, 1244, INTEL_BUS_CLK), 268142140Snjl FREQ_INFO(1400, 1196, INTEL_BUS_CLK), 269142140Snjl FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 270142140Snjl FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 271142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 272142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 273142140Snjl FREQ_INFO( 0, 0, 1), 274142140Snjl}; 275143902Snjlstatic freq_info PM_755B_90[] = { 276142140Snjl /* 90 nm 2.00GHz Pentium M, VID #B */ 277142140Snjl FREQ_INFO(2000, 1324, INTEL_BUS_CLK), 278142140Snjl FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 279142140Snjl FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 280142140Snjl FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 281142140Snjl FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 282142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 283142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 284142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 285142140Snjl FREQ_INFO( 0, 0, 1), 286142140Snjl}; 287143902Snjlstatic freq_info PM_755C_90[] = { 288142140Snjl /* 90 nm 2.00GHz Pentium M, VID #C */ 289142140Snjl FREQ_INFO(2000, 1308, INTEL_BUS_CLK), 290142140Snjl FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 291142140Snjl FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 292142140Snjl FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 293142140Snjl FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 294142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 295142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 296142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 297142140Snjl FREQ_INFO( 0, 0, 1), 298142140Snjl}; 299143902Snjlstatic freq_info PM_755D_90[] = { 300142140Snjl /* 90 nm 2.00GHz Pentium M, VID #D */ 301142140Snjl FREQ_INFO(2000, 1276, INTEL_BUS_CLK), 302142140Snjl FREQ_INFO(1800, 1244, INTEL_BUS_CLK), 303142140Snjl FREQ_INFO(1600, 1196, INTEL_BUS_CLK), 304142140Snjl FREQ_INFO(1400, 1164, INTEL_BUS_CLK), 305142140Snjl FREQ_INFO(1200, 1116, INTEL_BUS_CLK), 306142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 307142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 308142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 309142140Snjl FREQ_INFO( 0, 0, 1), 310142140Snjl}; 311143902Snjlstatic freq_info PM_745A_90[] = { 312142140Snjl /* 90 nm 1.80GHz Pentium M, VID #A */ 313142140Snjl FREQ_INFO(1800, 1340, INTEL_BUS_CLK), 314142140Snjl FREQ_INFO(1600, 1292, INTEL_BUS_CLK), 315142140Snjl FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 316142140Snjl FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 317142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 318142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 319142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 320142140Snjl FREQ_INFO( 0, 0, 1), 321142140Snjl}; 322143902Snjlstatic freq_info PM_745B_90[] = { 323142140Snjl /* 90 nm 1.80GHz Pentium M, VID #B */ 324142140Snjl FREQ_INFO(1800, 1324, INTEL_BUS_CLK), 325142140Snjl FREQ_INFO(1600, 1276, INTEL_BUS_CLK), 326142140Snjl FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 327142140Snjl FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 328142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 329142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 330142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 331142140Snjl FREQ_INFO( 0, 0, 1), 332142140Snjl}; 333143902Snjlstatic freq_info PM_745C_90[] = { 334142140Snjl /* 90 nm 1.80GHz Pentium M, VID #C */ 335142140Snjl FREQ_INFO(1800, 1308, INTEL_BUS_CLK), 336142140Snjl FREQ_INFO(1600, 1260, INTEL_BUS_CLK), 337142140Snjl FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 338142140Snjl FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 339142140Snjl FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 340142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 341142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 342142140Snjl FREQ_INFO( 0, 0, 1), 343142140Snjl}; 344143902Snjlstatic freq_info PM_745D_90[] = { 345142140Snjl /* 90 nm 1.80GHz Pentium M, VID #D */ 346142140Snjl FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 347142140Snjl FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 348142140Snjl FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 349142140Snjl FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 350142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 351142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 352142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 353142140Snjl FREQ_INFO( 0, 0, 1), 354142140Snjl}; 355143902Snjlstatic freq_info PM_735A_90[] = { 356142140Snjl /* 90 nm 1.70GHz Pentium M, VID #A */ 357142140Snjl FREQ_INFO(1700, 1340, INTEL_BUS_CLK), 358142140Snjl FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 359142140Snjl FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 360142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 361142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 362142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 363142140Snjl FREQ_INFO( 0, 0, 1), 364142140Snjl}; 365143902Snjlstatic freq_info PM_735B_90[] = { 366142140Snjl /* 90 nm 1.70GHz Pentium M, VID #B */ 367142140Snjl FREQ_INFO(1700, 1324, INTEL_BUS_CLK), 368142140Snjl FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 369142140Snjl FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 370142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 371142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 372142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 373142140Snjl FREQ_INFO( 0, 0, 1), 374142140Snjl}; 375143902Snjlstatic freq_info PM_735C_90[] = { 376142140Snjl /* 90 nm 1.70GHz Pentium M, VID #C */ 377142140Snjl FREQ_INFO(1700, 1308, INTEL_BUS_CLK), 378142140Snjl FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 379142140Snjl FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 380142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 381142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 382142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 383142140Snjl FREQ_INFO( 0, 0, 1), 384142140Snjl}; 385143902Snjlstatic freq_info PM_735D_90[] = { 386142140Snjl /* 90 nm 1.70GHz Pentium M, VID #D */ 387142140Snjl FREQ_INFO(1700, 1276, INTEL_BUS_CLK), 388142140Snjl FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 389142140Snjl FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 390142140Snjl FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 391142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 392142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 393142140Snjl FREQ_INFO( 0, 0, 1), 394142140Snjl}; 395143902Snjlstatic freq_info PM_725A_90[] = { 396142140Snjl /* 90 nm 1.60GHz Pentium M, VID #A */ 397142140Snjl FREQ_INFO(1600, 1340, INTEL_BUS_CLK), 398142140Snjl FREQ_INFO(1400, 1276, INTEL_BUS_CLK), 399142140Snjl FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 400142140Snjl FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 401142140Snjl FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 402142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 403142140Snjl FREQ_INFO( 0, 0, 1), 404142140Snjl}; 405143902Snjlstatic freq_info PM_725B_90[] = { 406142140Snjl /* 90 nm 1.60GHz Pentium M, VID #B */ 407142140Snjl FREQ_INFO(1600, 1324, INTEL_BUS_CLK), 408142140Snjl FREQ_INFO(1400, 1260, INTEL_BUS_CLK), 409142140Snjl FREQ_INFO(1200, 1196, INTEL_BUS_CLK), 410142140Snjl FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 411142140Snjl FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 412142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 413142140Snjl FREQ_INFO( 0, 0, 1), 414142140Snjl}; 415143902Snjlstatic freq_info PM_725C_90[] = { 416142140Snjl /* 90 nm 1.60GHz Pentium M, VID #C */ 417142140Snjl FREQ_INFO(1600, 1308, INTEL_BUS_CLK), 418142140Snjl FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 419142140Snjl FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 420142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 421142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 422142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 423142140Snjl FREQ_INFO( 0, 0, 1), 424142140Snjl}; 425143902Snjlstatic freq_info PM_725D_90[] = { 426142140Snjl /* 90 nm 1.60GHz Pentium M, VID #D */ 427142140Snjl FREQ_INFO(1600, 1276, INTEL_BUS_CLK), 428142140Snjl FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 429142140Snjl FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 430142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 431142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 432142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 433142140Snjl FREQ_INFO( 0, 0, 1), 434142140Snjl}; 435143902Snjlstatic freq_info PM_715A_90[] = { 436142140Snjl /* 90 nm 1.50GHz Pentium M, VID #A */ 437142140Snjl FREQ_INFO(1500, 1340, INTEL_BUS_CLK), 438142140Snjl FREQ_INFO(1200, 1228, INTEL_BUS_CLK), 439142140Snjl FREQ_INFO(1000, 1148, INTEL_BUS_CLK), 440142140Snjl FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 441142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 442142140Snjl FREQ_INFO( 0, 0, 1), 443142140Snjl}; 444143902Snjlstatic freq_info PM_715B_90[] = { 445142140Snjl /* 90 nm 1.50GHz Pentium M, VID #B */ 446142140Snjl FREQ_INFO(1500, 1324, INTEL_BUS_CLK), 447142140Snjl FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 448142140Snjl FREQ_INFO(1000, 1148, INTEL_BUS_CLK), 449142140Snjl FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 450142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 451142140Snjl FREQ_INFO( 0, 0, 1), 452142140Snjl}; 453143902Snjlstatic freq_info PM_715C_90[] = { 454142140Snjl /* 90 nm 1.50GHz Pentium M, VID #C */ 455142140Snjl FREQ_INFO(1500, 1308, INTEL_BUS_CLK), 456142140Snjl FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 457142140Snjl FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 458142140Snjl FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 459142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 460142140Snjl FREQ_INFO( 0, 0, 1), 461142140Snjl}; 462143902Snjlstatic freq_info PM_715D_90[] = { 463142140Snjl /* 90 nm 1.50GHz Pentium M, VID #D */ 464142140Snjl FREQ_INFO(1500, 1276, INTEL_BUS_CLK), 465142140Snjl FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 466142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 467142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 468142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 469142140Snjl FREQ_INFO( 0, 0, 1), 470142140Snjl}; 471155996Scpercivastatic freq_info PM_778_90[] = { 472155996Scperciva /* 90 nm 1.60GHz Low Voltage Pentium M */ 473155996Scperciva FREQ_INFO(1600, 1116, INTEL_BUS_CLK), 474155996Scperciva FREQ_INFO(1500, 1116, INTEL_BUS_CLK), 475155996Scperciva FREQ_INFO(1400, 1100, INTEL_BUS_CLK), 476155996Scperciva FREQ_INFO(1300, 1084, INTEL_BUS_CLK), 477155996Scperciva FREQ_INFO(1200, 1068, INTEL_BUS_CLK), 478155996Scperciva FREQ_INFO(1100, 1052, INTEL_BUS_CLK), 479155996Scperciva FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 480155996Scperciva FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 481155996Scperciva FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 482155996Scperciva FREQ_INFO( 600, 988, INTEL_BUS_CLK), 483155996Scperciva FREQ_INFO( 0, 0, 1), 484155996Scperciva}; 485155996Scpercivastatic freq_info PM_758_90[] = { 486155996Scperciva /* 90 nm 1.50GHz Low Voltage Pentium M */ 487155996Scperciva FREQ_INFO(1500, 1116, INTEL_BUS_CLK), 488155996Scperciva FREQ_INFO(1400, 1116, INTEL_BUS_CLK), 489155996Scperciva FREQ_INFO(1300, 1100, INTEL_BUS_CLK), 490155996Scperciva FREQ_INFO(1200, 1084, INTEL_BUS_CLK), 491155996Scperciva FREQ_INFO(1100, 1068, INTEL_BUS_CLK), 492155996Scperciva FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 493155996Scperciva FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 494155996Scperciva FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 495155996Scperciva FREQ_INFO( 600, 988, INTEL_BUS_CLK), 496155996Scperciva FREQ_INFO( 0, 0, 1), 497155996Scperciva}; 498143902Snjlstatic freq_info PM_738_90[] = { 499142140Snjl /* 90 nm 1.40GHz Low Voltage Pentium M */ 500142140Snjl FREQ_INFO(1400, 1116, INTEL_BUS_CLK), 501142140Snjl FREQ_INFO(1300, 1116, INTEL_BUS_CLK), 502142140Snjl FREQ_INFO(1200, 1100, INTEL_BUS_CLK), 503142140Snjl FREQ_INFO(1100, 1068, INTEL_BUS_CLK), 504142140Snjl FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 505142140Snjl FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 506142140Snjl FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 507142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 508142140Snjl FREQ_INFO( 0, 0, 1), 509142140Snjl}; 510155996Scpercivastatic freq_info PM_773G_90[] = { 511155996Scperciva /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #G */ 512155996Scperciva FREQ_INFO(1300, 956, INTEL_BUS_CLK), 513155996Scperciva FREQ_INFO(1200, 940, INTEL_BUS_CLK), 514155996Scperciva FREQ_INFO(1100, 924, INTEL_BUS_CLK), 515155996Scperciva FREQ_INFO(1000, 908, INTEL_BUS_CLK), 516155996Scperciva FREQ_INFO( 900, 876, INTEL_BUS_CLK), 517155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 518155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 519155996Scperciva}; 520155996Scpercivastatic freq_info PM_773H_90[] = { 521155996Scperciva /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #H */ 522155996Scperciva FREQ_INFO(1300, 940, INTEL_BUS_CLK), 523155996Scperciva FREQ_INFO(1200, 924, INTEL_BUS_CLK), 524155996Scperciva FREQ_INFO(1100, 908, INTEL_BUS_CLK), 525155996Scperciva FREQ_INFO(1000, 892, INTEL_BUS_CLK), 526155996Scperciva FREQ_INFO( 900, 876, INTEL_BUS_CLK), 527155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 528155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 529155996Scperciva}; 530155996Scpercivastatic freq_info PM_773I_90[] = { 531155996Scperciva /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #I */ 532155996Scperciva FREQ_INFO(1300, 924, INTEL_BUS_CLK), 533155996Scperciva FREQ_INFO(1200, 908, INTEL_BUS_CLK), 534155996Scperciva FREQ_INFO(1100, 892, INTEL_BUS_CLK), 535155996Scperciva FREQ_INFO(1000, 876, INTEL_BUS_CLK), 536155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 537155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 538155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 539155996Scperciva}; 540155996Scpercivastatic freq_info PM_773J_90[] = { 541155996Scperciva /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #J */ 542155996Scperciva FREQ_INFO(1300, 908, INTEL_BUS_CLK), 543155996Scperciva FREQ_INFO(1200, 908, INTEL_BUS_CLK), 544155996Scperciva FREQ_INFO(1100, 892, INTEL_BUS_CLK), 545155996Scperciva FREQ_INFO(1000, 876, INTEL_BUS_CLK), 546155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 547155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 548155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 549155996Scperciva}; 550155996Scpercivastatic freq_info PM_773K_90[] = { 551155996Scperciva /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #K */ 552155996Scperciva FREQ_INFO(1300, 892, INTEL_BUS_CLK), 553155996Scperciva FREQ_INFO(1200, 892, INTEL_BUS_CLK), 554155996Scperciva FREQ_INFO(1100, 876, INTEL_BUS_CLK), 555155996Scperciva FREQ_INFO(1000, 860, INTEL_BUS_CLK), 556155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 557155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 558155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 559155996Scperciva}; 560155996Scpercivastatic freq_info PM_773L_90[] = { 561155996Scperciva /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #L */ 562155996Scperciva FREQ_INFO(1300, 876, INTEL_BUS_CLK), 563155996Scperciva FREQ_INFO(1200, 876, INTEL_BUS_CLK), 564155996Scperciva FREQ_INFO(1100, 860, INTEL_BUS_CLK), 565155996Scperciva FREQ_INFO(1000, 860, INTEL_BUS_CLK), 566155996Scperciva FREQ_INFO( 900, 844, INTEL_BUS_CLK), 567155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 568155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 569155996Scperciva}; 570155996Scpercivastatic freq_info PM_753G_90[] = { 571155996Scperciva /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #G */ 572155996Scperciva FREQ_INFO(1200, 956, INTEL_BUS_CLK), 573155996Scperciva FREQ_INFO(1100, 940, INTEL_BUS_CLK), 574155996Scperciva FREQ_INFO(1000, 908, INTEL_BUS_CLK), 575155996Scperciva FREQ_INFO( 900, 892, INTEL_BUS_CLK), 576155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 577155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 578155996Scperciva}; 579155996Scpercivastatic freq_info PM_753H_90[] = { 580155996Scperciva /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #H */ 581155996Scperciva FREQ_INFO(1200, 940, INTEL_BUS_CLK), 582155996Scperciva FREQ_INFO(1100, 924, INTEL_BUS_CLK), 583155996Scperciva FREQ_INFO(1000, 908, INTEL_BUS_CLK), 584155996Scperciva FREQ_INFO( 900, 876, INTEL_BUS_CLK), 585155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 586155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 587155996Scperciva}; 588155996Scpercivastatic freq_info PM_753I_90[] = { 589155996Scperciva /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #I */ 590155996Scperciva FREQ_INFO(1200, 924, INTEL_BUS_CLK), 591155996Scperciva FREQ_INFO(1100, 908, INTEL_BUS_CLK), 592155996Scperciva FREQ_INFO(1000, 892, INTEL_BUS_CLK), 593155996Scperciva FREQ_INFO( 900, 876, INTEL_BUS_CLK), 594155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 595155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 596155996Scperciva}; 597155996Scpercivastatic freq_info PM_753J_90[] = { 598155996Scperciva /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #J */ 599155996Scperciva FREQ_INFO(1200, 908, INTEL_BUS_CLK), 600155996Scperciva FREQ_INFO(1100, 892, INTEL_BUS_CLK), 601155996Scperciva FREQ_INFO(1000, 876, INTEL_BUS_CLK), 602155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 603155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 604155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 605155996Scperciva}; 606155996Scpercivastatic freq_info PM_753K_90[] = { 607155996Scperciva /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #K */ 608155996Scperciva FREQ_INFO(1200, 892, INTEL_BUS_CLK), 609155996Scperciva FREQ_INFO(1100, 892, INTEL_BUS_CLK), 610155996Scperciva FREQ_INFO(1000, 876, INTEL_BUS_CLK), 611155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 612155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 613155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 614155996Scperciva}; 615155996Scpercivastatic freq_info PM_753L_90[] = { 616155996Scperciva /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #L */ 617155996Scperciva FREQ_INFO(1200, 876, INTEL_BUS_CLK), 618155996Scperciva FREQ_INFO(1100, 876, INTEL_BUS_CLK), 619155996Scperciva FREQ_INFO(1000, 860, INTEL_BUS_CLK), 620155996Scperciva FREQ_INFO( 900, 844, INTEL_BUS_CLK), 621155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 622155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 623155996Scperciva}; 624155996Scperciva 625155996Scpercivastatic freq_info PM_733JG_90[] = { 626155996Scperciva /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #G */ 627155996Scperciva FREQ_INFO(1100, 956, INTEL_BUS_CLK), 628155996Scperciva FREQ_INFO(1000, 940, INTEL_BUS_CLK), 629155996Scperciva FREQ_INFO( 900, 908, INTEL_BUS_CLK), 630155996Scperciva FREQ_INFO( 800, 876, INTEL_BUS_CLK), 631155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 632155996Scperciva}; 633155996Scpercivastatic freq_info PM_733JH_90[] = { 634155996Scperciva /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #H */ 635155996Scperciva FREQ_INFO(1100, 940, INTEL_BUS_CLK), 636155996Scperciva FREQ_INFO(1000, 924, INTEL_BUS_CLK), 637155996Scperciva FREQ_INFO( 900, 892, INTEL_BUS_CLK), 638155996Scperciva FREQ_INFO( 800, 876, INTEL_BUS_CLK), 639155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 640155996Scperciva}; 641155996Scpercivastatic freq_info PM_733JI_90[] = { 642155996Scperciva /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #I */ 643155996Scperciva FREQ_INFO(1100, 924, INTEL_BUS_CLK), 644155996Scperciva FREQ_INFO(1000, 908, INTEL_BUS_CLK), 645155996Scperciva FREQ_INFO( 900, 892, INTEL_BUS_CLK), 646155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 647155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 648155996Scperciva}; 649155996Scpercivastatic freq_info PM_733JJ_90[] = { 650155996Scperciva /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #J */ 651155996Scperciva FREQ_INFO(1100, 908, INTEL_BUS_CLK), 652155996Scperciva FREQ_INFO(1000, 892, INTEL_BUS_CLK), 653155996Scperciva FREQ_INFO( 900, 876, INTEL_BUS_CLK), 654155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 655155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 656155996Scperciva}; 657155996Scpercivastatic freq_info PM_733JK_90[] = { 658155996Scperciva /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #K */ 659155996Scperciva FREQ_INFO(1100, 892, INTEL_BUS_CLK), 660155996Scperciva FREQ_INFO(1000, 876, INTEL_BUS_CLK), 661155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 662155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 663155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 664155996Scperciva}; 665155996Scpercivastatic freq_info PM_733JL_90[] = { 666155996Scperciva /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #L */ 667155996Scperciva FREQ_INFO(1100, 876, INTEL_BUS_CLK), 668155996Scperciva FREQ_INFO(1000, 876, INTEL_BUS_CLK), 669155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 670155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 671155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 672155996Scperciva}; 673143902Snjlstatic freq_info PM_733_90[] = { 674142140Snjl /* 90 nm 1.10GHz Ultra Low Voltage Pentium M */ 675142140Snjl FREQ_INFO(1100, 940, INTEL_BUS_CLK), 676142140Snjl FREQ_INFO(1000, 924, INTEL_BUS_CLK), 677142140Snjl FREQ_INFO( 900, 892, INTEL_BUS_CLK), 678142140Snjl FREQ_INFO( 800, 876, INTEL_BUS_CLK), 679142140Snjl FREQ_INFO( 600, 812, INTEL_BUS_CLK), 680142140Snjl FREQ_INFO( 0, 0, 1), 681142140Snjl}; 682143902Snjlstatic freq_info PM_723_90[] = { 683142140Snjl /* 90 nm 1.00GHz Ultra Low Voltage Pentium M */ 684142140Snjl FREQ_INFO(1000, 940, INTEL_BUS_CLK), 685142140Snjl FREQ_INFO( 900, 908, INTEL_BUS_CLK), 686142140Snjl FREQ_INFO( 800, 876, INTEL_BUS_CLK), 687142140Snjl FREQ_INFO( 600, 812, INTEL_BUS_CLK), 688142140Snjl FREQ_INFO( 0, 0, 1), 689142140Snjl}; 690142140Snjl 691158446Snjl/* 692158446Snjl * VIA C7-M 500 MHz FSB, 400 MHz FSB, and ULV variants. 693158446Snjl * Data from the "VIA C7-M Processor BIOS Writer's Guide (v2.17)" datasheet. 694158446Snjl */ 695158446Snjlstatic freq_info C7M_795[] = { 696158446Snjl /* 2.00GHz Centaur C7-M 533 Mhz FSB */ 697158446Snjl FREQ_INFO_PWR(2000, 1148, 133, 20000), 698158446Snjl FREQ_INFO_PWR(1867, 1132, 133, 18000), 699158446Snjl FREQ_INFO_PWR(1600, 1100, 133, 15000), 700158446Snjl FREQ_INFO_PWR(1467, 1052, 133, 13000), 701158446Snjl FREQ_INFO_PWR(1200, 1004, 133, 10000), 702158446Snjl FREQ_INFO_PWR( 800, 844, 133, 7000), 703158446Snjl FREQ_INFO_PWR( 667, 844, 133, 6000), 704158446Snjl FREQ_INFO_PWR( 533, 844, 133, 5000), 705158446Snjl FREQ_INFO(0, 0, 1), 706158446Snjl}; 707158446Snjlstatic freq_info C7M_785[] = { 708158446Snjl /* 1.80GHz Centaur C7-M 533 Mhz FSB */ 709158446Snjl FREQ_INFO_PWR(1867, 1148, 133, 18000), 710158446Snjl FREQ_INFO_PWR(1600, 1100, 133, 15000), 711158446Snjl FREQ_INFO_PWR(1467, 1052, 133, 13000), 712158446Snjl FREQ_INFO_PWR(1200, 1004, 133, 10000), 713158446Snjl FREQ_INFO_PWR( 800, 844, 133, 7000), 714158446Snjl FREQ_INFO_PWR( 667, 844, 133, 6000), 715158446Snjl FREQ_INFO_PWR( 533, 844, 133, 5000), 716158446Snjl FREQ_INFO(0, 0, 1), 717158446Snjl}; 718158446Snjlstatic freq_info C7M_765[] = { 719158446Snjl /* 1.60GHz Centaur C7-M 533 Mhz FSB */ 720158446Snjl FREQ_INFO_PWR(1600, 1084, 133, 15000), 721158446Snjl FREQ_INFO_PWR(1467, 1052, 133, 13000), 722158446Snjl FREQ_INFO_PWR(1200, 1004, 133, 10000), 723158446Snjl FREQ_INFO_PWR( 800, 844, 133, 7000), 724158446Snjl FREQ_INFO_PWR( 667, 844, 133, 6000), 725158446Snjl FREQ_INFO_PWR( 533, 844, 133, 5000), 726158446Snjl FREQ_INFO(0, 0, 1), 727158446Snjl}; 728158446Snjl 729158446Snjlstatic freq_info C7M_794[] = { 730158446Snjl /* 2.00GHz Centaur C7-M 400 Mhz FSB */ 731158446Snjl FREQ_INFO_PWR(2000, 1148, 100, 20000), 732158446Snjl FREQ_INFO_PWR(1800, 1132, 100, 18000), 733158446Snjl FREQ_INFO_PWR(1600, 1100, 100, 15000), 734158446Snjl FREQ_INFO_PWR(1400, 1052, 100, 13000), 735158446Snjl FREQ_INFO_PWR(1000, 1004, 100, 10000), 736158446Snjl FREQ_INFO_PWR( 800, 844, 100, 7000), 737158446Snjl FREQ_INFO_PWR( 600, 844, 100, 6000), 738158446Snjl FREQ_INFO_PWR( 400, 844, 100, 5000), 739158446Snjl FREQ_INFO(0, 0, 1), 740158446Snjl}; 741158446Snjlstatic freq_info C7M_784[] = { 742158446Snjl /* 1.80GHz Centaur C7-M 400 Mhz FSB */ 743158446Snjl FREQ_INFO_PWR(1800, 1148, 100, 18000), 744158446Snjl FREQ_INFO_PWR(1600, 1100, 100, 15000), 745158446Snjl FREQ_INFO_PWR(1400, 1052, 100, 13000), 746158446Snjl FREQ_INFO_PWR(1000, 1004, 100, 10000), 747158446Snjl FREQ_INFO_PWR( 800, 844, 100, 7000), 748158446Snjl FREQ_INFO_PWR( 600, 844, 100, 6000), 749158446Snjl FREQ_INFO_PWR( 400, 844, 100, 5000), 750158446Snjl FREQ_INFO(0, 0, 1), 751158446Snjl}; 752158446Snjlstatic freq_info C7M_764[] = { 753158446Snjl /* 1.60GHz Centaur C7-M 400 Mhz FSB */ 754158446Snjl FREQ_INFO_PWR(1600, 1084, 100, 15000), 755158446Snjl FREQ_INFO_PWR(1400, 1052, 100, 13000), 756158446Snjl FREQ_INFO_PWR(1000, 1004, 100, 10000), 757158446Snjl FREQ_INFO_PWR( 800, 844, 100, 7000), 758158446Snjl FREQ_INFO_PWR( 600, 844, 100, 6000), 759158446Snjl FREQ_INFO_PWR( 400, 844, 100, 5000), 760158446Snjl FREQ_INFO(0, 0, 1), 761158446Snjl}; 762158446Snjlstatic freq_info C7M_754[] = { 763158446Snjl /* 1.50GHz Centaur C7-M 400 Mhz FSB */ 764158446Snjl FREQ_INFO_PWR(1500, 1004, 100, 12000), 765158446Snjl FREQ_INFO_PWR(1400, 988, 100, 11000), 766158446Snjl FREQ_INFO_PWR(1000, 940, 100, 9000), 767158446Snjl FREQ_INFO_PWR( 800, 844, 100, 7000), 768158446Snjl FREQ_INFO_PWR( 600, 844, 100, 6000), 769158446Snjl FREQ_INFO_PWR( 400, 844, 100, 5000), 770158446Snjl FREQ_INFO(0, 0, 1), 771158446Snjl}; 772158446Snjlstatic freq_info C7M_771[] = { 773158446Snjl /* 1.20GHz Centaur C7-M 400 Mhz FSB */ 774158446Snjl FREQ_INFO_PWR(1200, 860, 100, 7000), 775158446Snjl FREQ_INFO_PWR(1000, 860, 100, 6000), 776158446Snjl FREQ_INFO_PWR( 800, 844, 100, 5500), 777158446Snjl FREQ_INFO_PWR( 600, 844, 100, 5000), 778158446Snjl FREQ_INFO_PWR( 400, 844, 100, 4000), 779158446Snjl FREQ_INFO(0, 0, 1), 780158446Snjl}; 781158446Snjl 782158446Snjlstatic freq_info C7M_775_ULV[] = { 783158446Snjl /* 1.50GHz Centaur C7-M ULV */ 784158446Snjl FREQ_INFO_PWR(1500, 956, 100, 7500), 785158446Snjl FREQ_INFO_PWR(1400, 940, 100, 6000), 786158446Snjl FREQ_INFO_PWR(1000, 860, 100, 5000), 787158446Snjl FREQ_INFO_PWR( 800, 828, 100, 2800), 788158446Snjl FREQ_INFO_PWR( 600, 796, 100, 2500), 789158446Snjl FREQ_INFO_PWR( 400, 796, 100, 2000), 790158446Snjl FREQ_INFO(0, 0, 1), 791158446Snjl}; 792158446Snjlstatic freq_info C7M_772_ULV[] = { 793158446Snjl /* 1.20GHz Centaur C7-M ULV */ 794158446Snjl FREQ_INFO_PWR(1200, 844, 100, 5000), 795158446Snjl FREQ_INFO_PWR(1000, 844, 100, 4000), 796158446Snjl FREQ_INFO_PWR( 800, 828, 100, 2800), 797158446Snjl FREQ_INFO_PWR( 600, 796, 100, 2500), 798158446Snjl FREQ_INFO_PWR( 400, 796, 100, 2000), 799158446Snjl FREQ_INFO(0, 0, 1), 800158446Snjl}; 801158446Snjlstatic freq_info C7M_779_ULV[] = { 802158446Snjl /* 1.00GHz Centaur C7-M ULV */ 803158446Snjl FREQ_INFO_PWR(1000, 796, 100, 3500), 804158446Snjl FREQ_INFO_PWR( 800, 796, 100, 2800), 805158446Snjl FREQ_INFO_PWR( 600, 796, 100, 2500), 806158446Snjl FREQ_INFO_PWR( 400, 796, 100, 2000), 807158446Snjl FREQ_INFO(0, 0, 1), 808158446Snjl}; 809158446Snjlstatic freq_info C7M_770_ULV[] = { 810158446Snjl /* 1.00GHz Centaur C7-M ULV */ 811158446Snjl FREQ_INFO_PWR(1000, 844, 100, 5000), 812158446Snjl FREQ_INFO_PWR( 800, 796, 100, 2800), 813158446Snjl FREQ_INFO_PWR( 600, 796, 100, 2500), 814158446Snjl FREQ_INFO_PWR( 400, 796, 100, 2000), 815158446Snjl FREQ_INFO(0, 0, 1), 816158446Snjl}; 817158446Snjl 818143902Snjlstatic cpu_info ESTprocs[] = { 819142140Snjl INTEL(PM17_130, 1700, 1484, 600, 956, INTEL_BUS_CLK), 820142140Snjl INTEL(PM16_130, 1600, 1484, 600, 956, INTEL_BUS_CLK), 821142140Snjl INTEL(PM15_130, 1500, 1484, 600, 956, INTEL_BUS_CLK), 822142140Snjl INTEL(PM14_130, 1400, 1484, 600, 956, INTEL_BUS_CLK), 823142140Snjl INTEL(PM13_130, 1300, 1388, 600, 956, INTEL_BUS_CLK), 824142140Snjl INTEL(PM13_LV_130, 1300, 1180, 600, 956, INTEL_BUS_CLK), 825142140Snjl INTEL(PM12_LV_130, 1200, 1180, 600, 956, INTEL_BUS_CLK), 826142140Snjl INTEL(PM11_LV_130, 1100, 1180, 600, 956, INTEL_BUS_CLK), 827142140Snjl INTEL(PM11_ULV_130, 1100, 1004, 600, 844, INTEL_BUS_CLK), 828142140Snjl INTEL(PM10_ULV_130, 1000, 1004, 600, 844, INTEL_BUS_CLK), 829142140Snjl INTEL(PM_765A_90, 2100, 1340, 600, 988, INTEL_BUS_CLK), 830142140Snjl INTEL(PM_765B_90, 2100, 1324, 600, 988, INTEL_BUS_CLK), 831142140Snjl INTEL(PM_765C_90, 2100, 1308, 600, 988, INTEL_BUS_CLK), 832142140Snjl INTEL(PM_765E_90, 2100, 1356, 600, 988, INTEL_BUS_CLK), 833142140Snjl INTEL(PM_755A_90, 2000, 1340, 600, 988, INTEL_BUS_CLK), 834142140Snjl INTEL(PM_755B_90, 2000, 1324, 600, 988, INTEL_BUS_CLK), 835142140Snjl INTEL(PM_755C_90, 2000, 1308, 600, 988, INTEL_BUS_CLK), 836142140Snjl INTEL(PM_755D_90, 2000, 1276, 600, 988, INTEL_BUS_CLK), 837142140Snjl INTEL(PM_745A_90, 1800, 1340, 600, 988, INTEL_BUS_CLK), 838142140Snjl INTEL(PM_745B_90, 1800, 1324, 600, 988, INTEL_BUS_CLK), 839142140Snjl INTEL(PM_745C_90, 1800, 1308, 600, 988, INTEL_BUS_CLK), 840142140Snjl INTEL(PM_745D_90, 1800, 1276, 600, 988, INTEL_BUS_CLK), 841142140Snjl INTEL(PM_735A_90, 1700, 1340, 600, 988, INTEL_BUS_CLK), 842142140Snjl INTEL(PM_735B_90, 1700, 1324, 600, 988, INTEL_BUS_CLK), 843142140Snjl INTEL(PM_735C_90, 1700, 1308, 600, 988, INTEL_BUS_CLK), 844142140Snjl INTEL(PM_735D_90, 1700, 1276, 600, 988, INTEL_BUS_CLK), 845142140Snjl INTEL(PM_725A_90, 1600, 1340, 600, 988, INTEL_BUS_CLK), 846142140Snjl INTEL(PM_725B_90, 1600, 1324, 600, 988, INTEL_BUS_CLK), 847142140Snjl INTEL(PM_725C_90, 1600, 1308, 600, 988, INTEL_BUS_CLK), 848142140Snjl INTEL(PM_725D_90, 1600, 1276, 600, 988, INTEL_BUS_CLK), 849142140Snjl INTEL(PM_715A_90, 1500, 1340, 600, 988, INTEL_BUS_CLK), 850142140Snjl INTEL(PM_715B_90, 1500, 1324, 600, 988, INTEL_BUS_CLK), 851142140Snjl INTEL(PM_715C_90, 1500, 1308, 600, 988, INTEL_BUS_CLK), 852142140Snjl INTEL(PM_715D_90, 1500, 1276, 600, 988, INTEL_BUS_CLK), 853155996Scperciva INTEL(PM_778_90, 1600, 1116, 600, 988, INTEL_BUS_CLK), 854155996Scperciva INTEL(PM_758_90, 1500, 1116, 600, 988, INTEL_BUS_CLK), 855142140Snjl INTEL(PM_738_90, 1400, 1116, 600, 988, INTEL_BUS_CLK), 856155996Scperciva INTEL(PM_773G_90, 1300, 956, 600, 812, INTEL_BUS_CLK), 857155996Scperciva INTEL(PM_773H_90, 1300, 940, 600, 812, INTEL_BUS_CLK), 858155996Scperciva INTEL(PM_773I_90, 1300, 924, 600, 812, INTEL_BUS_CLK), 859155996Scperciva INTEL(PM_773J_90, 1300, 908, 600, 812, INTEL_BUS_CLK), 860155996Scperciva INTEL(PM_773K_90, 1300, 892, 600, 812, INTEL_BUS_CLK), 861155996Scperciva INTEL(PM_773L_90, 1300, 876, 600, 812, INTEL_BUS_CLK), 862155996Scperciva INTEL(PM_753G_90, 1200, 956, 600, 812, INTEL_BUS_CLK), 863155996Scperciva INTEL(PM_753H_90, 1200, 940, 600, 812, INTEL_BUS_CLK), 864155996Scperciva INTEL(PM_753I_90, 1200, 924, 600, 812, INTEL_BUS_CLK), 865155996Scperciva INTEL(PM_753J_90, 1200, 908, 600, 812, INTEL_BUS_CLK), 866155996Scperciva INTEL(PM_753K_90, 1200, 892, 600, 812, INTEL_BUS_CLK), 867155996Scperciva INTEL(PM_753L_90, 1200, 876, 600, 812, INTEL_BUS_CLK), 868155996Scperciva INTEL(PM_733JG_90, 1100, 956, 600, 812, INTEL_BUS_CLK), 869155996Scperciva INTEL(PM_733JH_90, 1100, 940, 600, 812, INTEL_BUS_CLK), 870155996Scperciva INTEL(PM_733JI_90, 1100, 924, 600, 812, INTEL_BUS_CLK), 871155996Scperciva INTEL(PM_733JJ_90, 1100, 908, 600, 812, INTEL_BUS_CLK), 872155996Scperciva INTEL(PM_733JK_90, 1100, 892, 600, 812, INTEL_BUS_CLK), 873155996Scperciva INTEL(PM_733JL_90, 1100, 876, 600, 812, INTEL_BUS_CLK), 874142140Snjl INTEL(PM_733_90, 1100, 940, 600, 812, INTEL_BUS_CLK), 875142140Snjl INTEL(PM_723_90, 1000, 940, 600, 812, INTEL_BUS_CLK), 876158446Snjl 877158446Snjl CENTAUR(C7M_795, 2000, 1148, 533, 844, 133), 878158446Snjl CENTAUR(C7M_794, 2000, 1148, 400, 844, 100), 879158446Snjl CENTAUR(C7M_785, 1867, 1148, 533, 844, 133), 880158446Snjl CENTAUR(C7M_784, 1800, 1148, 400, 844, 100), 881158446Snjl CENTAUR(C7M_765, 1600, 1084, 533, 844, 133), 882158446Snjl CENTAUR(C7M_764, 1600, 1084, 400, 844, 100), 883158446Snjl CENTAUR(C7M_754, 1500, 1004, 400, 844, 100), 884158446Snjl CENTAUR(C7M_775_ULV, 1500, 956, 400, 796, 100), 885158446Snjl CENTAUR(C7M_771, 1200, 860, 400, 844, 100), 886158446Snjl CENTAUR(C7M_772_ULV, 1200, 844, 400, 796, 100), 887158446Snjl CENTAUR(C7M_779_ULV, 1000, 796, 400, 796, 100), 888158446Snjl CENTAUR(C7M_770_ULV, 1000, 844, 400, 796, 100), 889158446Snjl { NULL, 0, NULL }, 890142140Snjl}; 891142140Snjl 892142140Snjlstatic void est_identify(driver_t *driver, device_t parent); 893144630Snjlstatic int est_features(driver_t *driver, u_int *features); 894142140Snjlstatic int est_probe(device_t parent); 895142140Snjlstatic int est_attach(device_t parent); 896142140Snjlstatic int est_detach(device_t parent); 897143902Snjlstatic int est_get_info(device_t dev); 898143902Snjlstatic int est_acpi_info(device_t dev, freq_info **freqs); 899158446Snjlstatic int est_table_info(device_t dev, uint64_t msr, freq_info **freqs); 900143902Snjlstatic freq_info *est_get_current(freq_info *freq_list); 901142140Snjlstatic int est_settings(device_t dev, struct cf_setting *sets, int *count); 902142140Snjlstatic int est_set(device_t dev, const struct cf_setting *set); 903142140Snjlstatic int est_get(device_t dev, struct cf_setting *set); 904142140Snjlstatic int est_type(device_t dev, int *type); 905176649Srpaulostatic int est_set_id16(device_t dev, uint16_t id16, int need_check); 906176649Srpaulostatic void est_get_id16(uint16_t *id16_p); 907142140Snjl 908142140Snjlstatic device_method_t est_methods[] = { 909142140Snjl /* Device interface */ 910142140Snjl DEVMETHOD(device_identify, est_identify), 911142140Snjl DEVMETHOD(device_probe, est_probe), 912142140Snjl DEVMETHOD(device_attach, est_attach), 913142140Snjl DEVMETHOD(device_detach, est_detach), 914142140Snjl 915142140Snjl /* cpufreq interface */ 916142140Snjl DEVMETHOD(cpufreq_drv_set, est_set), 917142140Snjl DEVMETHOD(cpufreq_drv_get, est_get), 918142140Snjl DEVMETHOD(cpufreq_drv_type, est_type), 919142140Snjl DEVMETHOD(cpufreq_drv_settings, est_settings), 920144630Snjl 921144630Snjl /* ACPI interface */ 922144630Snjl DEVMETHOD(acpi_get_features, est_features), 923144630Snjl 924142140Snjl {0, 0} 925142140Snjl}; 926142140Snjl 927142140Snjlstatic driver_t est_driver = { 928142140Snjl "est", 929142140Snjl est_methods, 930142140Snjl sizeof(struct est_softc), 931142140Snjl}; 932142140Snjl 933142140Snjlstatic devclass_t est_devclass; 934142140SnjlDRIVER_MODULE(est, cpu, est_driver, est_devclass, 0, 0); 935142140Snjl 936144630Snjlstatic int 937144630Snjlest_features(driver_t *driver, u_int *features) 938144630Snjl{ 939144630Snjl 940144630Snjl /* Notify the ACPI CPU that we support direct access to MSRs */ 941144630Snjl *features = ACPI_CAP_PERF_MSRS; 942144630Snjl return (0); 943144630Snjl} 944144630Snjl 945142140Snjlstatic void 946142140Snjlest_identify(driver_t *driver, device_t parent) 947142140Snjl{ 948144630Snjl device_t child; 949142140Snjl u_int p[4]; 950142140Snjl 951142140Snjl /* Make sure we're not being doubly invoked. */ 952142140Snjl if (device_find_child(parent, "est", -1) != NULL) 953142140Snjl return; 954142140Snjl 955142140Snjl /* Check that CPUID is supported and the vendor is Intel.*/ 956158446Snjl if (cpu_high == 0 || (strcmp(cpu_vendor, intel_id) != 0 && 957158446Snjl strcmp(cpu_vendor, centaur_id) != 0)) 958142140Snjl return; 959142140Snjl 960158446Snjl /* 961158446Snjl * Read capability bits and check if the CPU supports EST. 962158446Snjl * This is indicated by bit 7 of ECX. 963158446Snjl */ 964142140Snjl do_cpuid(1, p); 965142140Snjl if ((p[2] & 0x80) == 0) 966142140Snjl return; 967142140Snjl 968142625Snjl /* 969142625Snjl * We add a child for each CPU since settings must be performed 970142625Snjl * on each CPU in the SMP case. 971142625Snjl */ 972144630Snjl child = BUS_ADD_CHILD(parent, 0, "est", -1); 973144630Snjl if (child == NULL) 974142140Snjl device_printf(parent, "add est child failed\n"); 975142140Snjl} 976142140Snjl 977142140Snjlstatic int 978142140Snjlest_probe(device_t dev) 979142140Snjl{ 980142140Snjl device_t perf_dev; 981142140Snjl uint64_t msr; 982142140Snjl int error, type; 983142203Snjl 984142203Snjl if (resource_disabled("est", 0)) 985142203Snjl return (ENXIO); 986142140Snjl 987142140Snjl /* 988142140Snjl * If the ACPI perf driver has attached and is not just offering 989142140Snjl * info, let it manage things. 990142140Snjl */ 991142140Snjl perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 992142140Snjl if (perf_dev && device_is_attached(perf_dev)) { 993142140Snjl error = CPUFREQ_DRV_TYPE(perf_dev, &type); 994142140Snjl if (error == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0) 995142140Snjl return (ENXIO); 996142140Snjl } 997142140Snjl 998142140Snjl /* Attempt to enable SpeedStep if not currently enabled. */ 999142140Snjl msr = rdmsr(MSR_MISC_ENABLE); 1000142140Snjl if ((msr & MSR_SS_ENABLE) == 0) { 1001142140Snjl wrmsr(MSR_MISC_ENABLE, msr | MSR_SS_ENABLE); 1002143902Snjl if (bootverbose) 1003143902Snjl device_printf(dev, "enabling SpeedStep\n"); 1004142140Snjl 1005142140Snjl /* Check if the enable failed. */ 1006142140Snjl msr = rdmsr(MSR_MISC_ENABLE); 1007142140Snjl if ((msr & MSR_SS_ENABLE) == 0) { 1008142140Snjl device_printf(dev, "failed to enable SpeedStep\n"); 1009142140Snjl return (ENXIO); 1010142140Snjl } 1011142140Snjl } 1012142140Snjl 1013142140Snjl device_set_desc(dev, "Enhanced SpeedStep Frequency Control"); 1014142140Snjl return (0); 1015142140Snjl} 1016142140Snjl 1017142140Snjlstatic int 1018142140Snjlest_attach(device_t dev) 1019142140Snjl{ 1020142140Snjl struct est_softc *sc; 1021142140Snjl 1022142140Snjl sc = device_get_softc(dev); 1023142140Snjl sc->dev = dev; 1024143902Snjl 1025143902Snjl /* Check CPU for supported settings. */ 1026143902Snjl if (est_get_info(dev)) 1027143902Snjl return (ENXIO); 1028143902Snjl 1029142140Snjl cpufreq_register(dev); 1030142140Snjl return (0); 1031142140Snjl} 1032142140Snjl 1033142140Snjlstatic int 1034142140Snjlest_detach(device_t dev) 1035142140Snjl{ 1036143902Snjl struct est_softc *sc; 1037143902Snjl 1038143902Snjl sc = device_get_softc(dev); 1039143902Snjl if (sc->acpi_settings) 1040143902Snjl free(sc->freq_list, M_DEVBUF); 1041142140Snjl return (ENXIO); 1042142140Snjl} 1043142140Snjl 1044143902Snjl/* 1045143902Snjl * Probe for supported CPU settings. First, check our static table of 1046143902Snjl * settings. If no match, try using the ones offered by acpi_perf 1047143902Snjl * (i.e., _PSS). We use ACPI second because some systems (IBM R/T40 1048143902Snjl * series) export both legacy SMM IO-based access and direct MSR access 1049143902Snjl * but the direct access specifies invalid values for _PSS. 1050143902Snjl */ 1051142140Snjlstatic int 1052143902Snjlest_get_info(device_t dev) 1053142140Snjl{ 1054143902Snjl struct est_softc *sc; 1055143902Snjl uint64_t msr; 1056143902Snjl int error; 1057143902Snjl 1058143902Snjl sc = device_get_softc(dev); 1059143902Snjl msr = rdmsr(MSR_PERF_STATUS); 1060158446Snjl error = est_table_info(dev, msr, &sc->freq_list); 1061143902Snjl if (error) 1062143902Snjl error = est_acpi_info(dev, &sc->freq_list); 1063143902Snjl 1064143902Snjl if (error) { 1065143902Snjl printf( 1066143902Snjl "est: CPU supports Enhanced Speedstep, but is not recognized.\n" 1067148583Scperciva "est: cpu_vendor %s, msr %0jx\n", cpu_vendor, msr); 1068143902Snjl return (ENXIO); 1069143902Snjl } 1070143902Snjl 1071143902Snjl return (0); 1072143902Snjl} 1073143902Snjl 1074143902Snjlstatic int 1075143902Snjlest_acpi_info(device_t dev, freq_info **freqs) 1076143902Snjl{ 1077143902Snjl struct est_softc *sc; 1078143902Snjl struct cf_setting *sets; 1079143902Snjl freq_info *table; 1080143902Snjl device_t perf_dev; 1081176649Srpaulo int count, error, i, j; 1082176649Srpaulo uint16_t saved_id16; 1083143902Snjl 1084143902Snjl perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 1085143902Snjl if (perf_dev == NULL || !device_is_attached(perf_dev)) 1086143902Snjl return (ENXIO); 1087143902Snjl 1088143902Snjl /* Fetch settings from acpi_perf. */ 1089143902Snjl sc = device_get_softc(dev); 1090143902Snjl table = NULL; 1091143902Snjl sets = malloc(MAX_SETTINGS * sizeof(*sets), M_TEMP, M_NOWAIT); 1092143902Snjl if (sets == NULL) 1093143902Snjl return (ENOMEM); 1094143902Snjl error = CPUFREQ_DRV_SETTINGS(perf_dev, sets, &count); 1095143902Snjl if (error) 1096143902Snjl goto out; 1097143902Snjl 1098143902Snjl /* Parse settings into our local table format. */ 1099144881Snjl table = malloc((count + 1) * sizeof(freq_info), M_DEVBUF, M_NOWAIT); 1100143902Snjl if (table == NULL) { 1101143902Snjl error = ENOMEM; 1102143902Snjl goto out; 1103143902Snjl } 1104176649Srpaulo for (i = 0, j = 0; i < count; i++) { 1105143902Snjl /* 1106176649Srpaulo * Confirm id16 value is correct. 1107143902Snjl */ 1108176649Srpaulo if (sets[i].freq > 0) { 1109176649Srpaulo est_get_id16(&saved_id16); 1110176649Srpaulo error = est_set_id16(dev, sets[i].spec[0], 1); 1111176649Srpaulo if (error != 0) { 1112176649Srpaulo if (bootverbose) 1113176649Srpaulo device_printf(dev, "Invalid freq %u, " 1114176649Srpaulo "ignored.\n", sets[i].freq); 1115176649Srpaulo } else { 1116176649Srpaulo table[j].freq = sets[i].freq; 1117176649Srpaulo table[j].volts = sets[i].volts; 1118176649Srpaulo table[j].id16 = sets[i].spec[0]; 1119176649Srpaulo table[j].power = sets[i].power; 1120176649Srpaulo ++j; 1121176649Srpaulo } 1122176649Srpaulo /* restore saved setting */ 1123176649Srpaulo est_set_id16(dev, sets[i].spec[0], 0); 1124176649Srpaulo } 1125143902Snjl } 1126143902Snjl 1127144881Snjl /* Mark end of table with a terminator. */ 1128176649Srpaulo bzero(&table[j], sizeof(freq_info)); 1129144881Snjl 1130143902Snjl sc->acpi_settings = TRUE; 1131143902Snjl *freqs = table; 1132143902Snjl error = 0; 1133143902Snjl 1134143902Snjlout: 1135143902Snjl if (sets) 1136143902Snjl free(sets, M_TEMP); 1137143902Snjl if (error && table) 1138143902Snjl free(table, M_DEVBUF); 1139143902Snjl return (error); 1140143902Snjl} 1141143902Snjl 1142143902Snjlstatic int 1143158446Snjlest_table_info(device_t dev, uint64_t msr, freq_info **freqs) 1144143902Snjl{ 1145143902Snjl cpu_info *p; 1146142140Snjl uint32_t id; 1147142140Snjl 1148158446Snjl /* Find a table which matches (vendor, id32). */ 1149142140Snjl id = msr >> 32; 1150142140Snjl for (p = ESTprocs; p->id32 != 0; p++) { 1151158446Snjl if (strcmp(p->vendor, cpu_vendor) == 0 && p->id32 == id) 1152142140Snjl break; 1153142140Snjl } 1154142140Snjl if (p->id32 == 0) 1155142140Snjl return (EOPNOTSUPP); 1156142140Snjl 1157142140Snjl /* Make sure the current setpoint is valid. */ 1158143902Snjl if (est_get_current(p->freqtab) == NULL) { 1159143902Snjl device_printf(dev, "current setting not found in table\n"); 1160142140Snjl return (EOPNOTSUPP); 1161143902Snjl } 1162142140Snjl 1163142140Snjl *freqs = p->freqtab; 1164142140Snjl return (0); 1165142140Snjl} 1166142140Snjl 1167176649Srpaulostatic void 1168176649Srpauloest_get_id16(uint16_t *id16_p) 1169176649Srpaulo{ 1170176649Srpaulo *id16_p = rdmsr(MSR_PERF_STATUS) & 0xffff; 1171176649Srpaulo} 1172176649Srpaulo 1173176649Srpaulostatic int 1174176649Srpauloest_set_id16(device_t dev, uint16_t id16, int need_check) 1175176649Srpaulo{ 1176176649Srpaulo uint64_t msr; 1177176649Srpaulo uint16_t new_id16; 1178176649Srpaulo int ret = 0; 1179176649Srpaulo 1180176649Srpaulo /* Read the current register, mask out the old, set the new id. */ 1181176649Srpaulo msr = rdmsr(MSR_PERF_CTL); 1182176649Srpaulo msr = (msr & ~0xffff) | id16; 1183176649Srpaulo wrmsr(MSR_PERF_CTL, msr); 1184176649Srpaulo 1185176649Srpaulo /* Wait a short while for the new setting. XXX Is this necessary? */ 1186176649Srpaulo DELAY(EST_TRANS_LAT); 1187176649Srpaulo 1188176649Srpaulo if (need_check) { 1189176649Srpaulo est_get_id16(&new_id16); 1190176649Srpaulo if (new_id16 != id16) { 1191176649Srpaulo if (bootverbose) 1192176649Srpaulo device_printf(dev, "Invalid id16 (set, cur) " 1193176649Srpaulo "= (%u, %u)\n", id16, new_id16); 1194176649Srpaulo ret = ENXIO; 1195176649Srpaulo } 1196176649Srpaulo } 1197176649Srpaulo return (ret); 1198176649Srpaulo} 1199176649Srpaulo 1200143902Snjlstatic freq_info * 1201143902Snjlest_get_current(freq_info *freq_list) 1202142140Snjl{ 1203143902Snjl freq_info *f; 1204142140Snjl int i; 1205142140Snjl uint16_t id16; 1206142140Snjl 1207142140Snjl /* 1208142140Snjl * Try a few times to get a valid value. Sometimes, if the CPU 1209142140Snjl * is in the middle of an asynchronous transition (i.e., P4TCC), 1210142140Snjl * we get a temporary invalid result. 1211142140Snjl */ 1212142140Snjl for (i = 0; i < 5; i++) { 1213176649Srpaulo est_get_id16(&id16); 1214142140Snjl for (f = freq_list; f->id16 != 0; f++) { 1215142140Snjl if (f->id16 == id16) 1216142140Snjl return (f); 1217142140Snjl } 1218142140Snjl DELAY(100); 1219142140Snjl } 1220142140Snjl return (NULL); 1221142140Snjl} 1222142140Snjl 1223142140Snjlstatic int 1224142140Snjlest_settings(device_t dev, struct cf_setting *sets, int *count) 1225142140Snjl{ 1226142140Snjl struct est_softc *sc; 1227143902Snjl freq_info *f; 1228142140Snjl int i; 1229142140Snjl 1230142140Snjl sc = device_get_softc(dev); 1231142140Snjl if (*count < EST_MAX_SETTINGS) 1232142140Snjl return (E2BIG); 1233142140Snjl 1234142140Snjl i = 0; 1235142394Snjl for (f = sc->freq_list; f->freq != 0; f++, i++) { 1236142140Snjl sets[i].freq = f->freq; 1237142140Snjl sets[i].volts = f->volts; 1238143902Snjl sets[i].power = f->power; 1239142140Snjl sets[i].lat = EST_TRANS_LAT; 1240142140Snjl sets[i].dev = dev; 1241142140Snjl } 1242142394Snjl *count = i; 1243142140Snjl 1244142140Snjl return (0); 1245142140Snjl} 1246142140Snjl 1247142140Snjlstatic int 1248142140Snjlest_set(device_t dev, const struct cf_setting *set) 1249142140Snjl{ 1250142140Snjl struct est_softc *sc; 1251143902Snjl freq_info *f; 1252142140Snjl 1253142140Snjl /* Find the setting matching the requested one. */ 1254142140Snjl sc = device_get_softc(dev); 1255142140Snjl for (f = sc->freq_list; f->freq != 0; f++) { 1256142140Snjl if (f->freq == set->freq) 1257142140Snjl break; 1258142140Snjl } 1259142140Snjl if (f->freq == 0) 1260142140Snjl return (EINVAL); 1261142140Snjl 1262142140Snjl /* Read the current register, mask out the old, set the new id. */ 1263176649Srpaulo est_set_id16(dev, f->id16, 0); 1264142140Snjl 1265142140Snjl return (0); 1266142140Snjl} 1267142140Snjl 1268142140Snjlstatic int 1269142140Snjlest_get(device_t dev, struct cf_setting *set) 1270142140Snjl{ 1271142140Snjl struct est_softc *sc; 1272143902Snjl freq_info *f; 1273142140Snjl 1274142140Snjl sc = device_get_softc(dev); 1275142140Snjl f = est_get_current(sc->freq_list); 1276142140Snjl if (f == NULL) 1277142140Snjl return (ENXIO); 1278142140Snjl 1279142140Snjl set->freq = f->freq; 1280142140Snjl set->volts = f->volts; 1281143902Snjl set->power = f->power; 1282142140Snjl set->lat = EST_TRANS_LAT; 1283142140Snjl set->dev = dev; 1284142140Snjl return (0); 1285142140Snjl} 1286142140Snjl 1287142140Snjlstatic int 1288142140Snjlest_type(device_t dev, int *type) 1289142140Snjl{ 1290142140Snjl 1291142140Snjl if (type == NULL) 1292142140Snjl return (EINVAL); 1293142140Snjl 1294142140Snjl *type = CPUFREQ_TYPE_ABSOLUTE; 1295142140Snjl return (0); 1296142140Snjl} 1297