174298Ssos/*- 2230132Suqs * Copyright (c) 2000 - 2008 S��ren Schmidt <sos@FreeBSD.org> 374298Ssos * All rights reserved. 474298Ssos * 574298Ssos * Redistribution and use in source and binary forms, with or without 674298Ssos * modification, are permitted provided that the following conditions 774298Ssos * are met: 874298Ssos * 1. Redistributions of source code must retain the above copyright 974298Ssos * notice, this list of conditions and the following disclaimer, 1074298Ssos * without modification, immediately at the beginning of the file. 1174298Ssos * 2. Redistributions in binary form must reproduce the above copyright 1274298Ssos * notice, this list of conditions and the following disclaimer in the 1374298Ssos * documentation and/or other materials provided with the distribution. 1474298Ssos * 1574298Ssos * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1674298Ssos * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1774298Ssos * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1874298Ssos * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 1974298Ssos * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2074298Ssos * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2174298Ssos * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2274298Ssos * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2374298Ssos * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2474298Ssos * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2574298Ssos * 2674298Ssos * $FreeBSD: stable/11/sys/sys/ata.h 351579 2019-08-28 20:20:38Z mav $ 2774298Ssos */ 2874298Ssos 2974298Ssos#ifndef _SYS_ATA_H_ 3074298Ssos#define _SYS_ATA_H_ 3174298Ssos 3274298Ssos#include <sys/ioccom.h> 3374298Ssos 34119404Ssos/* ATA/ATAPI device parameters */ 3593881Ssosstruct ata_params { 36146266Ssos/*000*/ u_int16_t config; /* configuration info */ 37146266Ssos#define ATA_PROTO_MASK 0x8003 38146266Ssos#define ATA_PROTO_ATAPI 0x8000 39146266Ssos#define ATA_PROTO_ATAPI_12 0x8000 40146266Ssos#define ATA_PROTO_ATAPI_16 0x8001 41174682Sphk#define ATA_PROTO_CFA 0x848a 42146266Ssos#define ATA_ATAPI_TYPE_MASK 0x1f00 43146266Ssos#define ATA_ATAPI_TYPE_DIRECT 0x0000 /* disk/floppy */ 44146266Ssos#define ATA_ATAPI_TYPE_TAPE 0x0100 /* streaming tape */ 45146266Ssos#define ATA_ATAPI_TYPE_CDROM 0x0500 /* CD-ROM device */ 46146266Ssos#define ATA_ATAPI_TYPE_OPTICAL 0x0700 /* optical disk */ 47146266Ssos#define ATA_DRQ_MASK 0x0060 48146266Ssos#define ATA_DRQ_SLOW 0x0000 /* cpu 3 ms delay */ 49146266Ssos#define ATA_DRQ_INTR 0x0020 /* interrupt 10 ms delay */ 50146266Ssos#define ATA_DRQ_FAST 0x0040 /* accel 50 us delay */ 51203421Smav#define ATA_RESP_INCOMPLETE 0x0004 5293881Ssos 53146266Ssos/*001*/ u_int16_t cylinders; /* # of cylinders */ 54204354Smav/*002*/ u_int16_t specconf; /* specific configuration */ 55146266Ssos/*003*/ u_int16_t heads; /* # heads */ 56146266Ssos u_int16_t obsolete4; 57146266Ssos u_int16_t obsolete5; 58146266Ssos/*006*/ u_int16_t sectors; /* # sectors/track */ 59146266Ssos/*007*/ u_int16_t vendor7[3]; 60146266Ssos/*010*/ u_int8_t serial[20]; /* serial number */ 61146266Ssos/*020*/ u_int16_t retired20; 62146266Ssos u_int16_t retired21; 63146266Ssos u_int16_t obsolete22; 64146266Ssos/*023*/ u_int8_t revision[8]; /* firmware revision */ 65146266Ssos/*027*/ u_int8_t model[40]; /* model name */ 66146266Ssos/*047*/ u_int16_t sectors_intr; /* sectors per interrupt */ 67350800Smav/*048*/ u_int16_t tcg; /* Trusted Computing Group */ 68350800Smav#define ATA_SUPPORT_TCG 0x0001 69146266Ssos/*049*/ u_int16_t capabilities1; 70146266Ssos#define ATA_SUPPORT_DMA 0x0100 71146266Ssos#define ATA_SUPPORT_LBA 0x0200 72322080Smav#define ATA_SUPPORT_IORDYDIS 0x0400 73322080Smav#define ATA_SUPPORT_IORDY 0x0800 74146266Ssos#define ATA_SUPPORT_OVERLAP 0x4000 7593881Ssos 76146266Ssos/*050*/ u_int16_t capabilities2; 77146266Ssos/*051*/ u_int16_t retired_piomode; /* PIO modes 0-2 */ 78146266Ssos#define ATA_RETIRED_PIO_MASK 0x0300 7974298Ssos 80146266Ssos/*052*/ u_int16_t retired_dmamode; /* DMA modes */ 81146266Ssos#define ATA_RETIRED_DMA_MASK 0x0003 8274298Ssos 83146266Ssos/*053*/ u_int16_t atavalid; /* fields valid */ 84146266Ssos#define ATA_FLAG_54_58 0x0001 /* words 54-58 valid */ 85146266Ssos#define ATA_FLAG_64_70 0x0002 /* words 64-70 valid */ 86146266Ssos#define ATA_FLAG_88 0x0004 /* word 88 valid */ 8774298Ssos 88146266Ssos/*054*/ u_int16_t current_cylinders; 89146266Ssos/*055*/ u_int16_t current_heads; 90146266Ssos/*056*/ u_int16_t current_sectors; 91146266Ssos/*057*/ u_int16_t current_size_1; 92146266Ssos/*058*/ u_int16_t current_size_2; 93146266Ssos/*059*/ u_int16_t multi; 94350800Smav#define ATA_SUPPORT_BLOCK_ERASE_EXT 0x8000 95350800Smav#define ATA_SUPPORT_OVERWRITE_EXT 0x4000 96350800Smav#define ATA_SUPPORT_CRYPTO_SCRAMBLE_EXT 0x2000 97350800Smav#define ATA_SUPPORT_SANITIZE 0x1000 98350807Smav#define ATA_SUPPORT_SANITIZE_ALLOWED 0x0800 99350807Smav#define ATA_SUPPORT_ANTIFREEZE_LOCK_EXT 0x0400 100146266Ssos#define ATA_MULTI_VALID 0x0100 10193881Ssos 102146266Ssos/*060*/ u_int16_t lba_size_1; 103146266Ssos u_int16_t lba_size_2; 104146266Ssos u_int16_t obsolete62; 105146266Ssos/*063*/ u_int16_t mwdmamodes; /* multiword DMA modes */ 106146266Ssos/*064*/ u_int16_t apiomodes; /* advanced PIO modes */ 10774298Ssos 108146266Ssos/*065*/ u_int16_t mwdmamin; /* min. M/W DMA time/word ns */ 109146266Ssos/*066*/ u_int16_t mwdmarec; /* rec. M/W DMA time ns */ 110146266Ssos/*067*/ u_int16_t pioblind; /* min. PIO cycle w/o flow */ 111146266Ssos/*068*/ u_int16_t pioiordy; /* min. PIO cycle IORDY flow */ 112201139Smav/*069*/ u_int16_t support3; 113201139Smav#define ATA_SUPPORT_RZAT 0x0020 114201139Smav#define ATA_SUPPORT_DRAT 0x4000 115350800Smav#define ATA_ENCRYPTS_ALL_USER_DATA 0x0010 /* Self-encrypting drive */ 116300207Sken#define ATA_SUPPORT_ZONE_MASK 0x0003 117300207Sken#define ATA_SUPPORT_ZONE_NR 0x0000 118300207Sken#define ATA_SUPPORT_ZONE_HOST_AWARE 0x0001 119300207Sken#define ATA_SUPPORT_ZONE_DEV_MANAGED 0x0002 120146266Ssos u_int16_t reserved70; 121146266Ssos/*071*/ u_int16_t rlsovlap; /* rel time (us) for overlap */ 122146266Ssos/*072*/ u_int16_t rlsservice; /* rel time (us) for service */ 123146266Ssos u_int16_t reserved73; 124146266Ssos u_int16_t reserved74; 125146266Ssos/*075*/ u_int16_t queue; 126146266Ssos#define ATA_QUEUE_LEN(x) ((x) & 0x001f) 12774298Ssos 128197540Smav/*76*/ u_int16_t satacapabilities; 129146266Ssos#define ATA_SATA_GEN1 0x0002 130146266Ssos#define ATA_SATA_GEN2 0x0004 131197540Smav#define ATA_SATA_GEN3 0x0008 132146266Ssos#define ATA_SUPPORT_NCQ 0x0100 133146266Ssos#define ATA_SUPPORT_IFPWRMNGTRCV 0x0200 134194902Smav#define ATA_SUPPORT_PHYEVENTCNT 0x0400 135194902Smav#define ATA_SUPPORT_NCQ_UNLOAD 0x0800 136194902Smav#define ATA_SUPPORT_NCQ_PRIO 0x1000 137197540Smav#define ATA_SUPPORT_HAPST 0x2000 138197540Smav#define ATA_SUPPORT_DAPST 0x4000 139197540Smav#define ATA_SUPPORT_READLOGDMAEXT 0x8000 140127021Ssos 141197540Smav/*77*/ u_int16_t satacapabilities2; 142197540Smav#define ATA_SATA_CURR_GEN_MASK 0x0006 143197540Smav#define ATA_SUPPORT_NCQ_STREAM 0x0010 144351579Smav#define ATA_SUPPORT_NCQ_NON_DATA 0x0020 145351579Smav#define ATA_SUPPORT_NCQ_QMANAGEMENT ATA_SUPPORT_NCQ_NON_DATA 146264853Ssmh#define ATA_SUPPORT_RCVSND_FPDMA_QUEUED 0x0040 147197540Smav/*78*/ u_int16_t satasupport; 148146266Ssos#define ATA_SUPPORT_NONZERO 0x0002 149146266Ssos#define ATA_SUPPORT_AUTOACTIVATE 0x0004 150146266Ssos#define ATA_SUPPORT_IFPWRMNGT 0x0008 151146266Ssos#define ATA_SUPPORT_INORDERDATA 0x0010 152220602Smav#define ATA_SUPPORT_ASYNCNOTIF 0x0020 153197540Smav#define ATA_SUPPORT_SOFTSETPRESERVE 0x0040 154351579Smav#define ATA_SUPPORT_NCQ_AUTOSENSE 0x0080 155197540Smav/*79*/ u_int16_t sataenabled; 156197540Smav#define ATA_ENABLED_DAPST 0x0080 157127021Ssos 158146266Ssos/*080*/ u_int16_t version_major; 159146266Ssos/*081*/ u_int16_t version_minor; 160119404Ssos 16184584Ssos struct { 162146266Ssos/*082/085*/ u_int16_t command1; 163146266Ssos#define ATA_SUPPORT_SMART 0x0001 164146266Ssos#define ATA_SUPPORT_SECURITY 0x0002 165146266Ssos#define ATA_SUPPORT_REMOVABLE 0x0004 166146266Ssos#define ATA_SUPPORT_POWERMGT 0x0008 167146266Ssos#define ATA_SUPPORT_PACKET 0x0010 168146266Ssos#define ATA_SUPPORT_WRITECACHE 0x0020 169146266Ssos#define ATA_SUPPORT_LOOKAHEAD 0x0040 170146266Ssos#define ATA_SUPPORT_RELEASEIRQ 0x0080 171146266Ssos#define ATA_SUPPORT_SERVICEIRQ 0x0100 172146266Ssos#define ATA_SUPPORT_RESET 0x0200 173146266Ssos#define ATA_SUPPORT_PROTECTED 0x0400 174146266Ssos#define ATA_SUPPORT_WRITEBUFFER 0x1000 175146266Ssos#define ATA_SUPPORT_READBUFFER 0x2000 176146266Ssos#define ATA_SUPPORT_NOP 0x4000 17784584Ssos 178146266Ssos/*083/086*/ u_int16_t command2; 179146266Ssos#define ATA_SUPPORT_MICROCODE 0x0001 180146266Ssos#define ATA_SUPPORT_QUEUED 0x0002 181146266Ssos#define ATA_SUPPORT_CFA 0x0004 182146266Ssos#define ATA_SUPPORT_APM 0x0008 183146266Ssos#define ATA_SUPPORT_NOTIFY 0x0010 184146266Ssos#define ATA_SUPPORT_STANDBY 0x0020 185146266Ssos#define ATA_SUPPORT_SPINUP 0x0040 186146266Ssos#define ATA_SUPPORT_MAXSECURITY 0x0100 187146266Ssos#define ATA_SUPPORT_AUTOACOUSTIC 0x0200 188146266Ssos#define ATA_SUPPORT_ADDRESS48 0x0400 189146266Ssos#define ATA_SUPPORT_OVERLAY 0x0800 190146266Ssos#define ATA_SUPPORT_FLUSHCACHE 0x1000 191146266Ssos#define ATA_SUPPORT_FLUSHCACHE48 0x2000 19284584Ssos 193146266Ssos/*084/087*/ u_int16_t extension; 194197540Smav#define ATA_SUPPORT_SMARTLOG 0x0001 195197540Smav#define ATA_SUPPORT_SMARTTEST 0x0002 196172606Sscottl#define ATA_SUPPORT_MEDIASN 0x0004 197172606Sscottl#define ATA_SUPPORT_MEDIAPASS 0x0008 198172606Sscottl#define ATA_SUPPORT_STREAMING 0x0010 199172606Sscottl#define ATA_SUPPORT_GENLOG 0x0020 200172606Sscottl#define ATA_SUPPORT_WRITEDMAFUAEXT 0x0040 201172606Sscottl#define ATA_SUPPORT_WRITEDMAQFUAEXT 0x0080 202172606Sscottl#define ATA_SUPPORT_64BITWWN 0x0100 203197540Smav#define ATA_SUPPORT_UNLOAD 0x2000 204144330Ssos } __packed support, enabled; 20584584Ssos 206146266Ssos/*088*/ u_int16_t udmamodes; /* UltraDMA modes */ 207249115Ssmh/*089*/ u_int16_t erase_time; /* time req'd in 2min units */ 208249115Ssmh/*090*/ u_int16_t enhanced_erase_time; /* time req'd in 2min units */ 209146266Ssos/*091*/ u_int16_t apm_value; 210249115Ssmh/*092*/ u_int16_t master_passwd_revision; /* password revision code */ 211146266Ssos/*093*/ u_int16_t hwres; 212146266Ssos#define ATA_CABLE_ID 0x2000 21384584Ssos 214146266Ssos/*094*/ u_int16_t acoustic; 215146266Ssos#define ATA_ACOUSTIC_CURRENT(x) ((x) & 0x00ff) 216146266Ssos#define ATA_ACOUSTIC_VENDOR(x) (((x) & 0xff00) >> 8) 21784584Ssos 218146266Ssos/*095*/ u_int16_t stream_min_req_size; 219146266Ssos/*096*/ u_int16_t stream_transfer_time; 220146266Ssos/*097*/ u_int16_t stream_access_latency; 221146266Ssos/*098*/ u_int32_t stream_granularity; 222146266Ssos/*100*/ u_int16_t lba_size48_1; 223146266Ssos u_int16_t lba_size48_2; 224146266Ssos u_int16_t lba_size48_3; 225146266Ssos u_int16_t lba_size48_4; 226201139Smav u_int16_t reserved104; 227201139Smav/*105*/ u_int16_t max_dsm_blocks; 228197540Smav/*106*/ u_int16_t pss; 229197540Smav#define ATA_PSS_LSPPS 0x000F 230198865Smav#define ATA_PSS_LSSABOVE512 0x1000 231198865Smav#define ATA_PSS_MULTLS 0x2000 232262886Smav#define ATA_PSS_VALID_MASK 0xC000 233262886Smav#define ATA_PSS_VALID_VALUE 0x4000 234197540Smav/*107*/ u_int16_t isd; 235197540Smav/*108*/ u_int16_t wwn[4]; 236197540Smav u_int16_t reserved112[5]; 237197540Smav/*117*/ u_int16_t lss_1; 238197540Smav/*118*/ u_int16_t lss_2; 239197540Smav/*119*/ u_int16_t support2; 240197540Smav#define ATA_SUPPORT_WRITEREADVERIFY 0x0002 241197540Smav#define ATA_SUPPORT_WRITEUNCORREXT 0x0004 242197540Smav#define ATA_SUPPORT_RWLOGDMAEXT 0x0008 243197540Smav#define ATA_SUPPORT_MICROCODE3 0x0010 244197540Smav#define ATA_SUPPORT_FREEFALL 0x0020 245300207Sken#define ATA_SUPPORT_SENSE_REPORT 0x0040 246300207Sken#define ATA_SUPPORT_EPC 0x0080 247350801Smav#define ATA_SUPPORT_AMAX_ADDR 0x0100 248350801Smav#define ATA_SUPPORT_DSN 0x0200 249197540Smav/*120*/ u_int16_t enabled2; 250300207Sken#define ATA_ENABLED_WRITEREADVERIFY 0x0002 251300207Sken#define ATA_ENABLED_WRITEUNCORREXT 0x0004 252300207Sken#define ATA_ENABLED_FREEFALL 0x0020 253300207Sken#define ATA_ENABLED_SENSE_REPORT 0x0040 254300207Sken#define ATA_ENABLED_EPC 0x0080 255350801Smav#define ATA_ENABLED_DSN 0x0200 256197540Smav u_int16_t reserved121[6]; 257146266Ssos/*127*/ u_int16_t removable_status; 258146266Ssos/*128*/ u_int16_t security_status; 259249115Ssmh#define ATA_SECURITY_LEVEL 0x0100 /* 0: high, 1: maximum */ 260249115Ssmh#define ATA_SECURITY_ENH_SUPP 0x0020 /* enhanced erase supported */ 261249115Ssmh#define ATA_SECURITY_COUNT_EXP 0x0010 /* count expired */ 262249115Ssmh#define ATA_SECURITY_FROZEN 0x0008 /* security config is frozen */ 263249115Ssmh#define ATA_SECURITY_LOCKED 0x0004 /* drive is locked */ 264249115Ssmh#define ATA_SECURITY_ENABLED 0x0002 /* ATA Security is enabled */ 265249115Ssmh#define ATA_SECURITY_SUPPORTED 0x0001 /* ATA Security is supported */ 266249115Ssmh 267146266Ssos u_int16_t reserved129[31]; 268146266Ssos/*160*/ u_int16_t cfa_powermode1; 269198587Smav u_int16_t reserved161; 270198587Smav/*162*/ u_int16_t cfa_kms_support; 271198587Smav/*163*/ u_int16_t cfa_trueide_modes; 272198587Smav/*164*/ u_int16_t cfa_memory_modes; 273350800Smav u_int16_t reserved165[3]; 274350800Smav/*168*/ u_int16_t form_factor; 275350800Smav#define ATA_FORM_FACTOR_MASK 0x000f 276350800Smav#define ATA_FORM_FACTOR_NOT_REPORTED 0x0000 277350800Smav#define ATA_FORM_FACTOR_5_25 0x0001 278350800Smav#define ATA_FORM_FACTOR_3_5 0x0002 279350800Smav#define ATA_FORM_FACTOR_2_5 0x0003 280350800Smav#define ATA_FORM_FACTOR_1_8 0x0004 281350800Smav#define ATA_FORM_FACTOR_SUB_1_8 0x0005 282350800Smav#define ATA_FORM_FACTOR_MSATA 0x0006 283350800Smav#define ATA_FORM_FACTOR_M_2 0x0007 284350800Smav#define ATA_FORM_FACTOR_MICRO_SSD 0x0008 285350800Smav#define ATA_FORM_FACTOR_C_FAST 0x0009 286201139Smav/*169*/ u_int16_t support_dsm; 287201139Smav#define ATA_SUPPORT_DSM_TRIM 0x0001 288351579Smav/*170*/ u_int8_t product_id[8]; /* Additional Product Identifier */ 289351579Smav u_int16_t reserved174[2]; 290197540Smav/*176*/ u_int8_t media_serial[60]; 291197540Smav/*206*/ u_int16_t sct; 292319089Srpokala u_int16_t reserved207[2]; 293198897Smav/*209*/ u_int16_t lsalign; 294197540Smav/*210*/ u_int16_t wrv_sectors_m3_1; 295197540Smav u_int16_t wrv_sectors_m3_2; 296197540Smav/*212*/ u_int16_t wrv_sectors_m2_1; 297197540Smav u_int16_t wrv_sectors_m2_2; 298197540Smav/*214*/ u_int16_t nv_cache_caps; 299197540Smav/*215*/ u_int16_t nv_cache_size_1; 300197540Smav u_int16_t nv_cache_size_2; 301197540Smav/*217*/ u_int16_t media_rotation_rate; 302256956Ssmh#define ATA_RATE_NOT_REPORTED 0x0000 303256956Ssmh#define ATA_RATE_NON_ROTATING 0x0001 304197540Smav u_int16_t reserved218; 305197540Smav/*219*/ u_int16_t nv_cache_opt; 306197540Smav/*220*/ u_int16_t wrv_mode; 307197540Smav u_int16_t reserved221; 308197540Smav/*222*/ u_int16_t transport_major; 309197540Smav/*223*/ u_int16_t transport_minor; 310197540Smav u_int16_t reserved224[31]; 311146266Ssos/*255*/ u_int16_t integrity; 312144330Ssos} __packed; 31374298Ssos 314249931Ssmh/* ATA Dataset Management */ 315249931Ssmh#define ATA_DSM_BLK_SIZE 512 316249931Ssmh#define ATA_DSM_BLK_RANGES 64 317249931Ssmh#define ATA_DSM_RANGE_SIZE 8 318249931Ssmh#define ATA_DSM_RANGE_MAX 65535 319249931Ssmh 320238393Sbrueffer/* 321238393Sbrueffer * ATA Device Register 322238393Sbrueffer * 323238393Sbrueffer * bit 7 Obsolete (was 1 in early ATA specs) 324238393Sbrueffer * bit 6 Sets LBA/CHS mode. 1=LBA, 0=CHS 325238393Sbrueffer * bit 5 Obsolete (was 1 in early ATA specs) 326238393Sbrueffer * bit 4 1 = Slave Drive, 0 = Master Drive 327238393Sbrueffer * bit 3-0 In LBA mode, 27-24 of address. In CHS mode, head number 328238393Sbrueffer*/ 329146266Ssos 330238393Sbrueffer#define ATA_DEV_MASTER 0x00 331238393Sbrueffer#define ATA_DEV_SLAVE 0x10 332238393Sbrueffer#define ATA_DEV_LBA 0x40 333238393Sbrueffer 334249895Ssmh/* ATA limits */ 335249895Ssmh#define ATA_MAX_28BIT_LBA 268435455UL 336238393Sbrueffer 337249895Ssmh/* ATA Status Register */ 338300207Sken#define ATA_STATUS_ERROR 0x01 339300207Sken#define ATA_STATUS_SENSE_AVAIL 0x02 340300207Sken#define ATA_STATUS_ALIGN_ERR 0x04 341300207Sken#define ATA_STATUS_DATA_REQ 0x08 342300207Sken#define ATA_STATUS_DEF_WRITE_ERR 0x10 343300207Sken#define ATA_STATUS_DEVICE_FAULT 0x20 344300207Sken#define ATA_STATUS_DEVICE_READY 0x40 345300207Sken#define ATA_STATUS_BUSY 0x80 346249895Ssmh 347249895Ssmh/* ATA Error Register */ 348249895Ssmh#define ATA_ERROR_ABORT 0x04 349249895Ssmh#define ATA_ERROR_ID_NOT_FOUND 0x10 350249895Ssmh 351249895Ssmh/* ATA HPA Features */ 352249895Ssmh#define ATA_HPA_FEAT_MAX_ADDR 0x00 353249895Ssmh#define ATA_HPA_FEAT_SET_PWD 0x01 354249895Ssmh#define ATA_HPA_FEAT_LOCK 0x02 355249895Ssmh#define ATA_HPA_FEAT_UNLOCK 0x03 356249895Ssmh#define ATA_HPA_FEAT_FREEZE 0x04 357249895Ssmh 358119404Ssos/* ATA transfer modes */ 359146266Ssos#define ATA_MODE_MASK 0x0f 360146266Ssos#define ATA_DMA_MASK 0xf0 361146266Ssos#define ATA_PIO 0x00 362146266Ssos#define ATA_PIO0 0x08 363146266Ssos#define ATA_PIO1 0x09 364146266Ssos#define ATA_PIO2 0x0a 365146266Ssos#define ATA_PIO3 0x0b 366146266Ssos#define ATA_PIO4 0x0c 367146266Ssos#define ATA_PIO_MAX 0x0f 368146266Ssos#define ATA_DMA 0x10 369146266Ssos#define ATA_WDMA0 0x20 370146266Ssos#define ATA_WDMA1 0x21 371146266Ssos#define ATA_WDMA2 0x22 372146266Ssos#define ATA_UDMA0 0x40 373146266Ssos#define ATA_UDMA1 0x41 374146266Ssos#define ATA_UDMA2 0x42 375146266Ssos#define ATA_UDMA3 0x43 376146266Ssos#define ATA_UDMA4 0x44 377146266Ssos#define ATA_UDMA5 0x45 378146266Ssos#define ATA_UDMA6 0x46 379146266Ssos#define ATA_SA150 0x47 380148991Ssos#define ATA_SA300 0x48 381286448Smav#define ATA_SA600 0x49 382146266Ssos#define ATA_DMA_MAX 0x4f 38374298Ssos 384146266Ssos 385119404Ssos/* ATA commands */ 386146266Ssos#define ATA_NOP 0x00 /* NOP */ 387146266Ssos#define ATA_NF_FLUSHQUEUE 0x00 /* flush queued cmd's */ 388146266Ssos#define ATA_NF_AUTOPOLL 0x01 /* start autopoll function */ 389201139Smav#define ATA_DATA_SET_MANAGEMENT 0x06 390201139Smav#define ATA_DSM_TRIM 0x01 391146266Ssos#define ATA_DEVICE_RESET 0x08 /* reset device */ 392146266Ssos#define ATA_READ 0x20 /* read */ 393146266Ssos#define ATA_READ48 0x24 /* read 48bit LBA */ 394146266Ssos#define ATA_READ_DMA48 0x25 /* read DMA 48bit LBA */ 395146266Ssos#define ATA_READ_DMA_QUEUED48 0x26 /* read DMA QUEUED 48bit LBA */ 396178067Ssos#define ATA_READ_NATIVE_MAX_ADDRESS48 0x27 /* read native max addr 48bit */ 397146266Ssos#define ATA_READ_MUL48 0x29 /* read multi 48bit LBA */ 398200008Smav#define ATA_READ_STREAM_DMA48 0x2a /* read DMA stream 48bit LBA */ 399264853Ssmh#define ATA_READ_LOG_EXT 0x2f /* read log ext - PIO Data-In */ 400200008Smav#define ATA_READ_STREAM48 0x2b /* read stream 48bit LBA */ 401146266Ssos#define ATA_WRITE 0x30 /* write */ 402146266Ssos#define ATA_WRITE48 0x34 /* write 48bit LBA */ 403146266Ssos#define ATA_WRITE_DMA48 0x35 /* write DMA 48bit LBA */ 404146266Ssos#define ATA_WRITE_DMA_QUEUED48 0x36 /* write DMA QUEUED 48bit LBA*/ 405152270Ssos#define ATA_SET_MAX_ADDRESS48 0x37 /* set max address 48bit */ 406146266Ssos#define ATA_WRITE_MUL48 0x39 /* write multi 48bit LBA */ 407200008Smav#define ATA_WRITE_STREAM_DMA48 0x3a 408200008Smav#define ATA_WRITE_STREAM48 0x3b 409200008Smav#define ATA_WRITE_DMA_FUA48 0x3d 410200008Smav#define ATA_WRITE_DMA_QUEUED_FUA48 0x3e 411200008Smav#define ATA_WRITE_LOG_EXT 0x3f 412200008Smav#define ATA_READ_VERIFY 0x40 413200008Smav#define ATA_READ_VERIFY48 0x42 414295276Srpokala#define ATA_WRITE_UNCORRECTABLE48 0x45 /* write uncorrectable 48bit LBA */ 415295276Srpokala#define ATA_WU_PSEUDO 0x55 /* pseudo-uncorrectable error */ 416295276Srpokala#define ATA_WU_FLAGGED 0xaa /* flagged-uncorrectable error */ 417264853Ssmh#define ATA_READ_LOG_DMA_EXT 0x47 /* read log DMA ext - PIO Data-In */ 418300207Sken#define ATA_ZAC_MANAGEMENT_IN 0x4a /* ZAC management in */ 419300207Sken#define ATA_ZM_REPORT_ZONES 0x00 /* report zones */ 420346123Smav#define ATA_WRITE_LOG_DMA_EXT 0x57 /* WRITE LOG DMA EXT */ 421346123Smav#define ATA_TRUSTED_NON_DATA 0x5b /* TRUSTED NON-DATA */ 422346123Smav#define ATA_TRUSTED_RECEIVE 0x5c /* TRUSTED RECEIVE */ 423346123Smav#define ATA_TRUSTED_RECEIVE_DMA 0x5d /* TRUSTED RECEIVE DMA */ 424346125Smav#define ATA_TRUSTED_SEND 0x5e /* TRUSTED SEND */ 425346125Smav#define ATA_TRUSTED_SEND_DMA 0x5f /* TRUSTED SEND DMA */ 426146266Ssos#define ATA_READ_FPDMA_QUEUED 0x60 /* read DMA NCQ */ 427146266Ssos#define ATA_WRITE_FPDMA_QUEUED 0x61 /* write DMA NCQ */ 428270832Simp#define ATA_NCQ_NON_DATA 0x63 /* NCQ non-data command */ 429300207Sken#define ATA_ABORT_NCQ_QUEUE 0x00 /* abort NCQ queue */ 430300207Sken#define ATA_DEADLINE_HANDLING 0x01 /* deadline handling */ 431300207Sken#define ATA_SET_FEATURES 0x05 /* set features */ 432300207Sken#define ATA_ZERO_EXT 0x06 /* zero ext */ 433300207Sken#define ATA_NCQ_ZAC_MGMT_OUT 0x07 /* NCQ ZAC mgmt out no data */ 434264853Ssmh#define ATA_SEND_FPDMA_QUEUED 0x64 /* send DMA NCQ */ 435273445Simp#define ATA_SFPDMA_DSM 0x00 /* Data set management */ 436298981Spfg#define ATA_SFPDMA_DSM_TRIM 0x01 /* Set trim bit in auxiliary */ 437273445Simp#define ATA_SFPDMA_HYBRID_EVICT 0x01 /* Hybrid Evict */ 438273445Simp#define ATA_SFPDMA_WLDMA 0x02 /* Write Log DMA EXT */ 439300207Sken#define ATA_SFPDMA_ZAC_MGMT_OUT 0x03 /* NCQ ZAC mgmt out w/data */ 440300207Sken#define ATA_RECV_FPDMA_QUEUED 0x65 /* receive DMA NCQ */ 441300207Sken#define ATA_RFPDMA_RL_DMA_EXT 0x00 /* Read Log DMA EXT */ 442300207Sken#define ATA_RFPDMA_ZAC_MGMT_IN 0x02 /* NCQ ZAC mgmt in w/data */ 443235897Smav#define ATA_SEP_ATTN 0x67 /* SEP request */ 444146266Ssos#define ATA_SEEK 0x70 /* seek */ 445350801Smav#define ATA_AMAX_ADDR 0x78 /* Accessible Max Address */ 446350801Smav#define ATA_AMAX_ADDR_GET 0x00 /* GET NATIVE MAX ADDRESS EXT */ 447350801Smav#define ATA_AMAX_ADDR_SET 0x01 /* SET ACCESSIBLE MAX ADDRESS EXT */ 448350801Smav#define ATA_AMAX_ADDR_FREEZE 0x02 /* FREEZE ACCESSIBLE MAX ADDRESS EXT */ 449300207Sken#define ATA_ZAC_MANAGEMENT_OUT 0x9f /* ZAC management out */ 450300207Sken#define ATA_ZM_CLOSE_ZONE 0x01 /* close zone */ 451300207Sken#define ATA_ZM_FINISH_ZONE 0x02 /* finish zone */ 452300207Sken#define ATA_ZM_OPEN_ZONE 0x03 /* open zone */ 453300207Sken#define ATA_ZM_RWP 0x04 /* reset write pointer */ 454346123Smav#define ATA_DOWNLOAD_MICROCODE 0x92 /* DOWNLOAD MICROCODE */ 455346123Smav#define ATA_DOWNLOAD_MICROCODE_DMA 0x93 /* DOWNLOAD MICROCODE DMA */ 456146266Ssos#define ATA_PACKET_CMD 0xa0 /* packet command */ 457146266Ssos#define ATA_ATAPI_IDENTIFY 0xa1 /* get ATAPI params*/ 458146266Ssos#define ATA_SERVICE 0xa2 /* service command */ 459166287Sremko#define ATA_SMART_CMD 0xb0 /* SMART command */ 460350807Smav#define ATA_SANITIZE 0xb4 /* sanitize device */ 461146266Ssos#define ATA_CFA_ERASE 0xc0 /* CFA erase */ 462146266Ssos#define ATA_READ_MUL 0xc4 /* read multi */ 463146266Ssos#define ATA_WRITE_MUL 0xc5 /* write multi */ 464146266Ssos#define ATA_SET_MULTI 0xc6 /* set multi size */ 465146266Ssos#define ATA_READ_DMA_QUEUED 0xc7 /* read DMA QUEUED */ 466146266Ssos#define ATA_READ_DMA 0xc8 /* read DMA */ 467146266Ssos#define ATA_WRITE_DMA 0xca /* write DMA */ 468146266Ssos#define ATA_WRITE_DMA_QUEUED 0xcc /* write DMA QUEUED */ 469200008Smav#define ATA_WRITE_MUL_FUA48 0xce 470146266Ssos#define ATA_STANDBY_IMMEDIATE 0xe0 /* standby immediate */ 471146266Ssos#define ATA_IDLE_IMMEDIATE 0xe1 /* idle immediate */ 472146266Ssos#define ATA_STANDBY_CMD 0xe2 /* standby */ 473146266Ssos#define ATA_IDLE_CMD 0xe3 /* idle */ 474146266Ssos#define ATA_READ_BUFFER 0xe4 /* read buffer */ 475178067Ssos#define ATA_READ_PM 0xe4 /* read portmultiplier */ 476286837Sgrehan#define ATA_CHECK_POWER_MODE 0xe5 /* device power mode */ 477146266Ssos#define ATA_SLEEP 0xe6 /* sleep */ 478146266Ssos#define ATA_FLUSHCACHE 0xe7 /* flush cache to disk */ 479346123Smav#define ATA_WRITE_BUFFER 0xe8 /* write buffer */ 480178067Ssos#define ATA_WRITE_PM 0xe8 /* write portmultiplier */ 481346123Smav#define ATA_READ_BUFFER_DMA 0xe9 /* read buffer DMA */ 482146266Ssos#define ATA_FLUSHCACHE48 0xea /* flush cache to disk */ 483346123Smav#define ATA_WRITE_BUFFER_DMA 0xeb /* write buffer DMA */ 484146266Ssos#define ATA_ATA_IDENTIFY 0xec /* get ATA params */ 485146266Ssos#define ATA_SETFEATURES 0xef /* features command */ 486146266Ssos#define ATA_SF_ENAB_WCACHE 0x02 /* enable write cache */ 487146266Ssos#define ATA_SF_DIS_WCACHE 0x82 /* disable write cache */ 488300207Sken#define ATA_SF_SETXFER 0x03 /* set transfer mode */ 489300207Sken#define ATA_SF_APM 0x05 /* Enable APM feature set */ 490203421Smav#define ATA_SF_ENAB_PUIS 0x06 /* enable PUIS */ 491203421Smav#define ATA_SF_DIS_PUIS 0x86 /* disable PUIS */ 492203421Smav#define ATA_SF_PUIS_SPINUP 0x07 /* PUIS spin-up */ 493300207Sken#define ATA_SF_WRV 0x0b /* Enable Write-Read-Verify */ 494300207Sken#define ATA_SF_DLC 0x0c /* Enable device life control */ 495300207Sken#define ATA_SF_SATA 0x10 /* Enable use of SATA feature */ 496300207Sken#define ATA_SF_FFC 0x41 /* Free-fall Control */ 497300207Sken#define ATA_SF_MHIST 0x43 /* Set Max Host Sect. Times */ 498300207Sken#define ATA_SF_RATE 0x45 /* Set Rate Basis */ 499300207Sken#define ATA_SF_EPC 0x4A /* Extended Power Conditions */ 500146266Ssos#define ATA_SF_ENAB_RCACHE 0xaa /* enable readahead cache */ 501146266Ssos#define ATA_SF_DIS_RCACHE 0x55 /* disable readahead cache */ 502146266Ssos#define ATA_SF_ENAB_RELIRQ 0x5d /* enable release interrupt */ 503146266Ssos#define ATA_SF_DIS_RELIRQ 0xdd /* disable release interrupt */ 504146266Ssos#define ATA_SF_ENAB_SRVIRQ 0x5e /* enable service interrupt */ 505146266Ssos#define ATA_SF_DIS_SRVIRQ 0xde /* disable service interrupt */ 506300207Sken#define ATA_SF_LPSAERC 0x62 /* Long Phys Sect Align ErrRep*/ 507300207Sken#define ATA_SF_DSN 0x63 /* Device Stats Notification */ 508300207Sken#define ATA_CHECK_POWER_MODE 0xe5 /* Check Power Mode */ 509249115Ssmh#define ATA_SECURITY_SET_PASSWORD 0xf1 /* set drive password */ 510249115Ssmh#define ATA_SECURITY_UNLOCK 0xf2 /* unlock drive using passwd */ 511249115Ssmh#define ATA_SECURITY_ERASE_PREPARE 0xf3 /* prepare to erase drive */ 512249115Ssmh#define ATA_SECURITY_ERASE_UNIT 0xf4 /* erase all blocks on drive */ 513249115Ssmh#define ATA_SECURITY_FREEZE_LOCK 0xf5 /* freeze security config */ 514249115Ssmh#define ATA_SECURITY_DISABLE_PASSWORD 0xf6 /* disable drive password */ 515178067Ssos#define ATA_READ_NATIVE_MAX_ADDRESS 0xf8 /* read native max address */ 516146266Ssos#define ATA_SET_MAX_ADDRESS 0xf9 /* set max address */ 517119404Ssos 518146266Ssos 519119404Ssos/* ATAPI commands */ 520146266Ssos#define ATAPI_TEST_UNIT_READY 0x00 /* check if device is ready */ 521146266Ssos#define ATAPI_REZERO 0x01 /* rewind */ 522146266Ssos#define ATAPI_REQUEST_SENSE 0x03 /* get sense data */ 523146266Ssos#define ATAPI_FORMAT 0x04 /* format unit */ 524146266Ssos#define ATAPI_READ 0x08 /* read data */ 525146266Ssos#define ATAPI_WRITE 0x0a /* write data */ 526146266Ssos#define ATAPI_WEOF 0x10 /* write filemark */ 527146266Ssos#define ATAPI_WF_WRITE 0x01 528146266Ssos#define ATAPI_SPACE 0x11 /* space command */ 529146266Ssos#define ATAPI_SP_FM 0x01 530146266Ssos#define ATAPI_SP_EOD 0x03 531156317Ssos#define ATAPI_INQUIRY 0x12 /* get inquiry data */ 532146266Ssos#define ATAPI_MODE_SELECT 0x15 /* mode select */ 533146266Ssos#define ATAPI_ERASE 0x19 /* erase */ 534146266Ssos#define ATAPI_MODE_SENSE 0x1a /* mode sense */ 535146266Ssos#define ATAPI_START_STOP 0x1b /* start/stop unit */ 536146266Ssos#define ATAPI_SS_LOAD 0x01 537146266Ssos#define ATAPI_SS_RETENSION 0x02 538146266Ssos#define ATAPI_SS_EJECT 0x04 539146266Ssos#define ATAPI_PREVENT_ALLOW 0x1e /* media removal */ 540146266Ssos#define ATAPI_READ_FORMAT_CAPACITIES 0x23 /* get format capacities */ 541146266Ssos#define ATAPI_READ_CAPACITY 0x25 /* get volume capacity */ 542146266Ssos#define ATAPI_READ_BIG 0x28 /* read data */ 543146266Ssos#define ATAPI_WRITE_BIG 0x2a /* write data */ 544146266Ssos#define ATAPI_LOCATE 0x2b /* locate to position */ 545146266Ssos#define ATAPI_READ_POSITION 0x34 /* read position */ 546146266Ssos#define ATAPI_SYNCHRONIZE_CACHE 0x35 /* flush buf, close channel */ 547146266Ssos#define ATAPI_WRITE_BUFFER 0x3b /* write device buffer */ 548146266Ssos#define ATAPI_READ_BUFFER 0x3c /* read device buffer */ 549146266Ssos#define ATAPI_READ_SUBCHANNEL 0x42 /* get subchannel info */ 550146266Ssos#define ATAPI_READ_TOC 0x43 /* get table of contents */ 551146266Ssos#define ATAPI_PLAY_10 0x45 /* play by lba */ 552146266Ssos#define ATAPI_PLAY_MSF 0x47 /* play by MSF address */ 553146266Ssos#define ATAPI_PLAY_TRACK 0x48 /* play by track number */ 554146266Ssos#define ATAPI_PAUSE 0x4b /* pause audio operation */ 555146266Ssos#define ATAPI_READ_DISK_INFO 0x51 /* get disk info structure */ 556146266Ssos#define ATAPI_READ_TRACK_INFO 0x52 /* get track info structure */ 557146266Ssos#define ATAPI_RESERVE_TRACK 0x53 /* reserve track */ 558146266Ssos#define ATAPI_SEND_OPC_INFO 0x54 /* send OPC structurek */ 559146266Ssos#define ATAPI_MODE_SELECT_BIG 0x55 /* set device parameters */ 560146266Ssos#define ATAPI_REPAIR_TRACK 0x58 /* repair track */ 561146266Ssos#define ATAPI_READ_MASTER_CUE 0x59 /* read master CUE info */ 562146266Ssos#define ATAPI_MODE_SENSE_BIG 0x5a /* get device parameters */ 563146266Ssos#define ATAPI_CLOSE_TRACK 0x5b /* close track/session */ 564146266Ssos#define ATAPI_READ_BUFFER_CAPACITY 0x5c /* get buffer capicity */ 565146266Ssos#define ATAPI_SEND_CUE_SHEET 0x5d /* send CUE sheet */ 566156317Ssos#define ATAPI_SERVICE_ACTION_IN 0x96 /* get service data */ 567146266Ssos#define ATAPI_BLANK 0xa1 /* blank the media */ 568146266Ssos#define ATAPI_SEND_KEY 0xa3 /* send DVD key structure */ 569146266Ssos#define ATAPI_REPORT_KEY 0xa4 /* get DVD key structure */ 570146266Ssos#define ATAPI_PLAY_12 0xa5 /* play by lba */ 571146266Ssos#define ATAPI_LOAD_UNLOAD 0xa6 /* changer control command */ 572146266Ssos#define ATAPI_READ_STRUCTURE 0xad /* get DVD structure */ 573146266Ssos#define ATAPI_PLAY_CD 0xb4 /* universal play command */ 574146266Ssos#define ATAPI_SET_SPEED 0xbb /* set drive speed */ 575146266Ssos#define ATAPI_MECH_STATUS 0xbd /* get changer status */ 576146266Ssos#define ATAPI_READ_CD 0xbe /* read data */ 577146266Ssos#define ATAPI_POLL_DSC 0xff /* poll DSC status bit */ 578119404Ssos 57974298Ssos 580146266Ssosstruct ata_ioc_devices { 581146266Ssos int channel; 582146266Ssos char name[2][32]; 583146266Ssos struct ata_params params[2]; 584146266Ssos}; 585119404Ssos 586146266Ssos/* pr channel ATA ioctl calls */ 587146266Ssos#define IOCATAGMAXCHANNEL _IOR('a', 1, int) 588146266Ssos#define IOCATAREINIT _IOW('a', 2, int) 589146266Ssos#define IOCATAATTACH _IOW('a', 3, int) 590146266Ssos#define IOCATADETACH _IOW('a', 4, int) 591146266Ssos#define IOCATADEVICES _IOWR('a', 5, struct ata_ioc_devices) 592119404Ssos 593157329Ssos/* ATAPI request sense structure */ 594157329Ssosstruct atapi_sense { 595157329Ssos u_int8_t error; /* current or deferred errors */ 596157329Ssos#define ATA_SENSE_VALID 0x80 597157329Ssos 598157329Ssos u_int8_t segment; /* segment number */ 599157329Ssos u_int8_t key; /* sense key */ 600157329Ssos#define ATA_SENSE_KEY_MASK 0x0f /* sense key mask */ 601157329Ssos#define ATA_SENSE_NO_SENSE 0x00 /* no specific sense key info */ 602157329Ssos#define ATA_SENSE_RECOVERED_ERROR 0x01 /* command OK, data recovered */ 603157329Ssos#define ATA_SENSE_NOT_READY 0x02 /* no access to drive */ 604157329Ssos#define ATA_SENSE_MEDIUM_ERROR 0x03 /* non-recovered data error */ 605157329Ssos#define ATA_SENSE_HARDWARE_ERROR 0x04 /* non-recoverable HW failure */ 606157329Ssos#define ATA_SENSE_ILLEGAL_REQUEST 0x05 /* invalid command param(s) */ 607157329Ssos#define ATA_SENSE_UNIT_ATTENTION 0x06 /* media changed */ 608157329Ssos#define ATA_SENSE_DATA_PROTECT 0x07 /* write protect */ 609157329Ssos#define ATA_SENSE_BLANK_CHECK 0x08 /* blank check */ 610157329Ssos#define ATA_SENSE_VENDOR_SPECIFIC 0x09 /* vendor specific skey */ 611157329Ssos#define ATA_SENSE_COPY_ABORTED 0x0a /* copy aborted */ 612157329Ssos#define ATA_SENSE_ABORTED_COMMAND 0x0b /* command aborted, try again */ 613157329Ssos#define ATA_SENSE_EQUAL 0x0c /* equal */ 614157329Ssos#define ATA_SENSE_VOLUME_OVERFLOW 0x0d /* volume overflow */ 615157329Ssos#define ATA_SENSE_MISCOMPARE 0x0e /* data dont match the medium */ 616157329Ssos#define ATA_SENSE_RESERVED 0x0f 617157329Ssos#define ATA_SENSE_ILI 0x20; 618157329Ssos#define ATA_SENSE_EOM 0x40; 619157329Ssos#define ATA_SENSE_FILEMARK 0x80; 620157329Ssos 621157329Ssos u_int32_t cmd_info; /* cmd information */ 622157329Ssos u_int8_t sense_length; /* additional sense len (n-7) */ 623157329Ssos u_int32_t cmd_specific_info; /* additional cmd spec info */ 624157329Ssos u_int8_t asc; /* additional sense code */ 625157329Ssos u_int8_t ascq; /* additional sense code qual */ 626157329Ssos u_int8_t replaceable_unit_code; /* replaceable unit code */ 627157329Ssos u_int8_t specific; /* sense key specific */ 628157329Ssos#define ATA_SENSE_SPEC_VALID 0x80 629157329Ssos#define ATA_SENSE_SPEC_MASK 0x7f 630157329Ssos 631157329Ssos u_int8_t specific1; /* sense key specific */ 632157329Ssos u_int8_t specific2; /* sense key specific */ 633157329Ssos} __packed; 634157329Ssos 635300207Sken/* 636300207Sken * SET FEATURES subcommands 637300207Sken */ 638300207Sken 639300207Sken/* 640300207Sken * SET FEATURES command 641300207Sken * Extended Power Conditions subcommand -- ATA_SF_EPC (0x4A) 642300207Sken * These values go in the LBA 3:0. 643300207Sken */ 644300207Sken#define ATA_SF_EPC_RESTORE 0x00 /* Restore Power Condition Settings */ 645300207Sken#define ATA_SF_EPC_GOTO 0x01 /* Go To Power Condition */ 646300207Sken#define ATA_SF_EPC_SET_TIMER 0x02 /* Set Power Condition Timer */ 647300207Sken#define ATA_SF_EPC_SET_STATE 0x03 /* Set Power Condition State */ 648300207Sken#define ATA_SF_EPC_ENABLE 0x04 /* Enable the EPC feature set */ 649300207Sken#define ATA_SF_EPC_DISABLE 0x05 /* Disable the EPC feature set */ 650300207Sken#define ATA_SF_EPC_SET_SOURCE 0x06 /* Set EPC Power Source */ 651300207Sken 652300207Sken/* 653300207Sken * SET FEATURES command 654300207Sken * Extended Power Conditions subcommand -- ATA_SF_EPC (0x4A) 655300207Sken * Power Condition ID field 656300207Sken * These values go in the count register. 657300207Sken */ 658300207Sken#define ATA_EPC_STANDBY_Z 0x00 /* Substate of PM2:Standby */ 659300207Sken#define ATA_EPC_STANDBY_Y 0x01 /* Substate of PM2:Standby */ 660300207Sken#define ATA_EPC_IDLE_A 0x81 /* Substate of PM1:Idle */ 661300207Sken#define ATA_EPC_IDLE_B 0x82 /* Substate of PM1:Idle */ 662300207Sken#define ATA_EPC_IDLE_C 0x83 /* Substate of PM1:Idle */ 663300207Sken#define ATA_EPC_ALL 0xff /* All supported power conditions */ 664300207Sken 665300207Sken/* 666300207Sken * SET FEATURES command 667300207Sken * Extended Power Conditions subcommand -- ATA_SF_EPC (0x4A) 668300207Sken * Restore Power Conditions Settings subcommand 669300207Sken * These values go in the LBA register. 670300207Sken */ 671300207Sken#define ATA_SF_EPC_RST_DFLT 0x40 /* 1=Rst from Default, 0= from Saved */ 672300207Sken#define ATA_SF_EPC_RST_SAVE 0x10 /* 1=Save on completion */ 673300207Sken 674300207Sken/* 675300207Sken * SET FEATURES command 676300207Sken * Extended Power Conditions subcommand -- ATA_SF_EPC (0x4A) 677300207Sken * Got To Power Condition subcommand 678300207Sken * These values go in the LBA register. 679300207Sken */ 680300207Sken#define ATA_SF_EPC_GOTO_DELAY 0x02000000 /* Delayed entry bit */ 681300207Sken#define ATA_SF_EPC_GOTO_HOLD 0x01000000 /* Hold Power Cond bit */ 682300207Sken 683300207Sken/* 684300207Sken * SET FEATURES command 685300207Sken * Extended Power Conditions subcommand -- ATA_SF_EPC (0x4A) 686300207Sken * Set Power Condition Timer subcommand 687300207Sken * These values go in the LBA register. 688300207Sken */ 689300207Sken#define ATA_SF_EPC_TIMER_MASK 0x00ffff00 /* Timer field */ 690300207Sken#define ATA_SF_EPC_TIMER_SHIFT 8 691300207Sken#define ATA_SF_EPC_TIMER_SEC 0x00000080 /* Timer units, 1=sec, 0=.1s */ 692300207Sken#define ATA_SF_EPC_TIMER_EN 0x00000020 /* Enable/disable cond. */ 693300207Sken#define ATA_SF_EPC_TIMER_SAVE 0x00000010 /* Save settings on comp. */ 694300207Sken 695300207Sken/* 696300207Sken * SET FEATURES command 697300207Sken * Extended Power Conditions subcommand -- ATA_SF_EPC (0x4A) 698300207Sken * Set Power Condition State subcommand 699300207Sken * These values go in the LBA register. 700300207Sken */ 701300207Sken#define ATA_SF_EPC_SETCON_EN 0x00000020 /* Enable power cond. */ 702300207Sken#define ATA_SF_EPC_SETCON_SAVE 0x00000010 /* Save settings on comp */ 703300207Sken 704300207Sken/* 705300207Sken * SET FEATURES command 706300207Sken * Extended Power Conditions subcommand -- ATA_SF_EPC (0x4A) 707300207Sken * Set EPC Power Source subcommand 708300207Sken * These values go in the count register. 709300207Sken */ 710300207Sken#define ATA_SF_EPC_SRC_UNKNOWN 0x0000 /* Unknown source */ 711300207Sken#define ATA_SF_EPC_SRC_BAT 0x0001 /* battery source */ 712300207Sken#define ATA_SF_EPC_SRC_NOT_BAT 0x0002 /* not battery source */ 713300207Sken 714300207Sken#define ATA_LOG_DIRECTORY 0x00 /* Directory of all logs */ 715300207Sken#define ATA_POWER_COND_LOG 0x08 /* Power Conditions Log */ 716300207Sken#define ATA_PCL_IDLE 0x00 /* Idle Power Conditions Page */ 717300207Sken#define ATA_PCL_STANDBY 0x01 /* Standby Power Conditions Page */ 718300207Sken#define ATA_IDENTIFY_DATA_LOG 0x30 /* Identify Device Data Log */ 719300207Sken#define ATA_IDL_PAGE_LIST 0x00 /* List of supported pages */ 720300207Sken#define ATA_IDL_IDENTIFY_DATA 0x01 /* Copy of Identify Device data */ 721300207Sken#define ATA_IDL_CAPACITY 0x02 /* Capacity */ 722300207Sken#define ATA_IDL_SUP_CAP 0x03 /* Supported Capabilities */ 723300207Sken#define ATA_IDL_CUR_SETTINGS 0x04 /* Current Settings */ 724300207Sken#define ATA_IDL_ATA_STRINGS 0x05 /* ATA Strings */ 725300207Sken#define ATA_IDL_SECURITY 0x06 /* Security */ 726300207Sken#define ATA_IDL_PARALLEL_ATA 0x07 /* Parallel ATA */ 727350799Smav#define ATA_IDL_SERIAL_ATA 0x08 /* Serial ATA */ 728300207Sken#define ATA_IDL_ZDI 0x09 /* Zoned Device Information */ 729300207Sken 730300207Skenstruct ata_gp_log_dir { 731300207Sken uint8_t header[2]; 732300207Sken#define ATA_GP_LOG_DIR_VERSION 0x0001 733300207Sken uint8_t num_pages[255*2]; /* Number of log pages at address */ 734300207Sken}; 735300207Sken 736300207Sken/* 737300207Sken * ATA Power Conditions log descriptor 738300207Sken */ 739300207Skenstruct ata_power_cond_log_desc { 740300207Sken uint8_t reserved1; 741300207Sken uint8_t flags; 742300207Sken#define ATA_PCL_COND_SUPPORTED 0x80 743300207Sken#define ATA_PCL_COND_SAVEABLE 0x40 744300207Sken#define ATA_PCL_COND_CHANGEABLE 0x20 745300207Sken#define ATA_PCL_DEFAULT_TIMER_EN 0x10 746300207Sken#define ATA_PCL_SAVED_TIMER_EN 0x08 747300207Sken#define ATA_PCL_CURRENT_TIMER_EN 0x04 748300207Sken#define ATA_PCL_HOLD_PC_NOT_SUP 0x02 749300207Sken uint8_t reserved2[2]; 750300207Sken uint8_t default_timer[4]; 751300207Sken uint8_t saved_timer[4]; 752300207Sken uint8_t current_timer[4]; 753300207Sken uint8_t nom_time_to_active[4]; 754300207Sken uint8_t min_timer[4]; 755300207Sken uint8_t max_timer[4]; 756300207Sken uint8_t num_transitions_to_pc[4]; 757300207Sken uint8_t hours_in_pc[4]; 758300207Sken uint8_t reserved3[28]; 759300207Sken}; 760300207Sken 761300207Sken/* 762300207Sken * ATA Power Conditions Log (0x08), Idle power conditions page (0x00) 763300207Sken */ 764300207Skenstruct ata_power_cond_log_idle { 765300207Sken struct ata_power_cond_log_desc idle_a_desc; 766300207Sken struct ata_power_cond_log_desc idle_b_desc; 767300207Sken struct ata_power_cond_log_desc idle_c_desc; 768300207Sken uint8_t reserved[320]; 769300207Sken}; 770300207Sken 771300207Sken/* 772300207Sken * ATA Power Conditions Log (0x08), Standby power conditions page (0x01) 773300207Sken */ 774300207Skenstruct ata_power_cond_log_standby { 775300207Sken uint8_t reserved[384]; 776300207Sken struct ata_power_cond_log_desc standby_y_desc; 777300207Sken struct ata_power_cond_log_desc standby_z_desc; 778300207Sken}; 779300207Sken 780300207Sken/* 781300207Sken * ATA IDENTIFY DEVICE data log (0x30) page 0x00 782300207Sken * List of Supported IDENTIFY DEVICE data pages. 783300207Sken */ 784300207Skenstruct ata_identify_log_pages { 785300207Sken uint8_t header[8]; 786300207Sken#define ATA_IDLOG_REVISION 0x0000000000000001 787300207Sken uint8_t entry_count; 788300207Sken uint8_t entries[503]; 789300207Sken}; 790300207Sken 791300207Sken/* 792300207Sken * ATA IDENTIFY DEVICE data log (0x30) 793300207Sken * Capacity (Page 0x02). 794300207Sken */ 795300207Skenstruct ata_identify_log_capacity { 796300207Sken uint8_t header[8]; 797300207Sken#define ATA_CAP_HEADER_VALID 0x8000000000000000 798300207Sken#define ATA_CAP_PAGE_NUM_MASK 0x0000000000ff0000 799300207Sken#define ATA_CAP_PAGE_NUM_SHIFT 16 800300207Sken#define ATA_CAP_REV_MASK 0x00000000000000ff 801300207Sken uint8_t capacity[8]; 802300207Sken#define ATA_CAP_CAPACITY_VALID 0x8000000000000000 803300207Sken#define ATA_CAP_ACCESSIBLE_CAP 0x0000ffffffffffff 804300207Sken uint8_t phys_logical_sect_size[8]; 805300207Sken#define ATA_CAP_PL_VALID 0x8000000000000000 806300207Sken#define ATA_CAP_LTOP_REL_SUP 0x4000000000000000 807300207Sken#define ATA_CAP_LOG_SECT_SUP 0x2000000000000000 808300207Sken#define ATA_CAP_ALIGN_ERR_MASK 0x0000000000300000 809300207Sken#define ATA_CAP_LTOP_MASK 0x00000000000f0000 810300207Sken#define ATA_CAP_LOG_SECT_OFF 0x000000000000ffff 811300207Sken uint8_t logical_sect_size[8]; 812300207Sken#define ATA_CAP_LOG_SECT_VALID 0x8000000000000000 813300207Sken#define ATA_CAP_LOG_SECT_SIZE 0x00000000ffffffff 814300207Sken uint8_t nominal_buffer_size[8]; 815300207Sken#define ATA_CAP_NOM_BUF_VALID 0x8000000000000000 816300207Sken#define ATA_CAP_NOM_BUF_SIZE 0x7fffffffffffffff 817300207Sken uint8_t reserved[472]; 818300207Sken}; 819300207Sken 820300207Sken/* 821300207Sken * ATA IDENTIFY DEVICE data log (0x30) 822300207Sken * Supported Capabilities (Page 0x03). 823300207Sken */ 824300207Sken 825300207Skenstruct ata_identify_log_sup_cap { 826300207Sken uint8_t header[8]; 827300207Sken#define ATA_SUP_CAP_HEADER_VALID 0x8000000000000000 828300207Sken#define ATA_SUP_CAP_PAGE_NUM_MASK 0x0000000000ff0000 829300207Sken#define ATA_SUP_CAP_PAGE_NUM_SHIFT 16 830300207Sken#define ATA_SUP_CAP_REV_MASK 0x00000000000000ff 831300207Sken uint8_t sup_cap[8]; 832300207Sken#define ATA_SUP_CAP_VALID 0x8000000000000000 833300207Sken#define ATA_SC_SET_SECT_CONFIG_SUP 0x0002000000000000 /* Set Sect Conf*/ 834300207Sken#define ATA_SC_ZERO_EXT_SUP 0x0001000000000000 /* Zero EXT */ 835300207Sken#define ATA_SC_SUCC_NCQ_SENSE_SUP 0x0000800000000000 /* Succ. NCQ Sns */ 836300207Sken#define ATA_SC_DLC_SUP 0x0000400000000000 /* DLC */ 837300207Sken#define ATA_SC_RQSN_DEV_FAULT_SUP 0x0000200000000000 /* Req Sns Dev Flt*/ 838300207Sken#define ATA_SC_DSN_SUP 0x0000100000000000 /* DSN */ 839300207Sken#define ATA_SC_LP_STANDBY_SUP 0x0000080000000000 /* LP Standby */ 840300207Sken#define ATA_SC_SET_EPC_PS_SUP 0x0000040000000000 /* Set EPC PS */ 841300207Sken#define ATA_SC_AMAX_ADDR_SUP 0x0000020000000000 /* AMAX Addr */ 842300207Sken#define ATA_SC_DRAT_SUP 0x0000008000000000 /* DRAT */ 843300207Sken#define ATA_SC_LPS_MISALGN_SUP 0x0000004000000000 /* LPS Misalign */ 844300207Sken#define ATA_SC_RB_DMA_SUP 0x0000001000000000 /* Read Buf DMA */ 845300207Sken#define ATA_SC_WB_DMA_SUP 0x0000000800000000 /* Write Buf DMA */ 846300207Sken#define ATA_SC_DNLD_MC_DMA_SUP 0x0000000200000000 /* DL MCode DMA */ 847300207Sken#define ATA_SC_28BIT_SUP 0x0000000100000000 /* 28-bit */ 848300207Sken#define ATA_SC_RZAT_SUP 0x0000000080000000 /* RZAT */ 849300207Sken#define ATA_SC_NOP_SUP 0x0000000020000000 /* NOP */ 850300207Sken#define ATA_SC_READ_BUFFER_SUP 0x0000000010000000 /* Read Buffer */ 851300207Sken#define ATA_SC_WRITE_BUFFER_SUP 0x0000000008000000 /* Write Buffer */ 852300207Sken#define ATA_SC_READ_LOOK_AHEAD_SUP 0x0000000002000000 /* Read Look-Ahead*/ 853300207Sken#define ATA_SC_VOLATILE_WC_SUP 0x0000000001000000 /* Volatile WC */ 854300207Sken#define ATA_SC_SMART_SUP 0x0000000000800000 /* SMART */ 855300207Sken#define ATA_SC_FLUSH_CACHE_EXT_SUP 0x0000000000400000 /* Flush Cache Ext */ 856300207Sken#define ATA_SC_48BIT_SUP 0x0000000000100000 /* 48-Bit */ 857300207Sken#define ATA_SC_SPINUP_SUP 0x0000000000040000 /* Spin-Up */ 858300207Sken#define ATA_SC_PUIS_SUP 0x0000000000020000 /* PUIS */ 859300207Sken#define ATA_SC_APM_SUP 0x0000000000010000 /* APM */ 860300207Sken#define ATA_SC_DL_MICROCODE_SUP 0x0000000000004000 /* DL Microcode */ 861300207Sken#define ATA_SC_UNLOAD_SUP 0x0000000000002000 /* Unload */ 862300207Sken#define ATA_SC_WRITE_FUA_EXT_SUP 0x0000000000001000 /* Write FUA EXT */ 863300207Sken#define ATA_SC_GPL_SUP 0x0000000000000800 /* GPL */ 864300207Sken#define ATA_SC_STREAMING_SUP 0x0000000000000400 /* Streaming */ 865300207Sken#define ATA_SC_SMART_SELFTEST_SUP 0x0000000000000100 /* SMART self-test */ 866300207Sken#define ATA_SC_SMART_ERR_LOG_SUP 0x0000000000000080 /* SMART Err Log */ 867300207Sken#define ATA_SC_EPC_SUP 0x0000000000000040 /* EPC */ 868300207Sken#define ATA_SC_SENSE_SUP 0x0000000000000020 /* Sense data */ 869300207Sken#define ATA_SC_FREEFALL_SUP 0x0000000000000010 /* Free-Fall */ 870300207Sken#define ATA_SC_DM_MODE3_SUP 0x0000000000000008 /* DM Mode 3 */ 871300207Sken#define ATA_SC_GPL_DMA_SUP 0x0000000000000004 /* GPL DMA */ 872300207Sken#define ATA_SC_WRITE_UNCOR_SUP 0x0000000000000002 /* Write uncorr. */ 873300207Sken#define ATA_SC_WRV_SUP 0x0000000000000001 /* WRV */ 874300207Sken uint8_t download_code_cap[8]; 875300207Sken#define ATA_DL_CODE_VALID 0x8000000000000000 876300207Sken#define ATA_DLC_DM_OFFSETS_DEFER_SUP 0x0000000400000000 877300207Sken#define ATA_DLC_DM_IMMED_SUP 0x0000000200000000 878300207Sken#define ATA_DLC_DM_OFF_IMMED_SUP 0x0000000100000000 879300207Sken#define ATA_DLC_DM_MAX_XFER_SIZE_MASK 0x00000000ffff0000 880300207Sken#define ATA_DLC_DM_MAX_XFER_SIZE_SHIFT 16 881300207Sken#define ATA_DLC_DM_MIN_XFER_SIZE_MASK 0x000000000000ffff 882300207Sken uint8_t nom_media_rotation_rate[8]; 883300207Sken#define ATA_NOM_MEDIA_ROTATION_VALID 0x8000000000000000 884300207Sken#define ATA_ROTATION_MASK 0x000000000000ffff 885300207Sken uint8_t form_factor[8]; 886300207Sken#define ATA_FORM_FACTOR_VALID 0x8000000000000000 887300207Sken#define ATA_FF_MASK 0x000000000000000f 888300207Sken#define ATA_FF_NOT_REPORTED 0x0000000000000000 /* Not reported */ 889300207Sken#define ATA_FF_525_IN 0x0000000000000001 /* 5.25 inch */ 890300207Sken#define ATA_FF_35_IN 0x0000000000000002 /* 3.5 inch */ 891300207Sken#define ATA_FF_25_IN 0x0000000000000003 /* 2.5 inch */ 892300207Sken#define ATA_FF_18_IN 0x0000000000000004 /* 1.8 inch */ 893300207Sken#define ATA_FF_LT_18_IN 0x0000000000000005 /* < 1.8 inch */ 894300207Sken#define ATA_FF_MSATA 0x0000000000000006 /* mSATA */ 895300207Sken#define ATA_FF_M2 0x0000000000000007 /* M.2 */ 896300207Sken#define ATA_FF_MICROSSD 0x0000000000000008 /* MicroSSD */ 897300207Sken#define ATA_FF_CFAST 0x0000000000000009 /* CFast */ 898300207Sken uint8_t wrv_sec_cnt_mode3[8]; 899300207Sken#define ATA_WRV_MODE3_VALID 0x8000000000000000 900300207Sken#define ATA_WRV_MODE3_COUNT 0x00000000ffffffff 901300207Sken uint8_t wrv_sec_cnt_mode2[8]; 902300207Sken#define ATA_WRV_MODE2_VALID 0x8000000000000000 903300207Sken#define ATA_WRV_MODE2_COUNT 0x00000000ffffffff 904300207Sken uint8_t wwn[16]; 905300207Sken /* XXX KDM need to figure out how to handle 128-bit fields */ 906300207Sken uint8_t dsm[8]; 907300207Sken#define ATA_DSM_VALID 0x8000000000000000 908300207Sken#define ATA_LB_MARKUP_SUP 0x000000000000ff00 909300207Sken#define ATA_TRIM_SUP 0x0000000000000001 910300207Sken uint8_t util_per_unit_time[16]; 911300207Sken /* XXX KDM need to figure out how to handle 128-bit fields */ 912300207Sken uint8_t util_usage_rate_sup[8]; 913300207Sken#define ATA_UTIL_USAGE_RATE_VALID 0x8000000000000000 914300207Sken#define ATA_SETTING_RATE_SUP 0x0000000000800000 915300207Sken#define ATA_SINCE_POWERON_SUP 0x0000000000000100 916300207Sken#define ATA_POH_RATE_SUP 0x0000000000000010 917300207Sken#define ATA_DATE_TIME_RATE_SUP 0x0000000000000001 918300207Sken uint8_t zoned_cap[8]; 919300207Sken#define ATA_ZONED_VALID 0x8000000000000000 920300207Sken#define ATA_ZONED_MASK 0x0000000000000003 921300207Sken uint8_t sup_zac_cap[8]; 922300207Sken#define ATA_SUP_ZAC_CAP_VALID 0x8000000000000000 923300207Sken#define ATA_ND_RWP_SUP 0x0000000000000010 /* Reset Write Ptr*/ 924300207Sken#define ATA_ND_FINISH_ZONE_SUP 0x0000000000000008 /* Finish Zone */ 925300207Sken#define ATA_ND_CLOSE_ZONE_SUP 0x0000000000000004 /* Close Zone */ 926300207Sken#define ATA_ND_OPEN_ZONE_SUP 0x0000000000000002 /* Open Zone */ 927300207Sken#define ATA_REPORT_ZONES_SUP 0x0000000000000001 /* Report Zones */ 928300207Sken uint8_t reserved[392]; 929300207Sken}; 930300207Sken 931300207Sken/* 932300207Sken * ATA Identify Device Data Log Zoned Device Information Page (0x09). 933300207Sken * Current as of ZAC r04a, August 25, 2015. 934300207Sken */ 935300207Skenstruct ata_zoned_info_log { 936300207Sken uint8_t header[8]; 937300207Sken#define ATA_ZDI_HEADER_VALID 0x8000000000000000 938300207Sken#define ATA_ZDI_PAGE_NUM_MASK 0x0000000000ff0000 939300207Sken#define ATA_ZDI_PAGE_NUM_SHIFT 16 940300207Sken#define ATA_ZDI_REV_MASK 0x00000000000000ff 941300207Sken uint8_t zoned_cap[8]; 942300207Sken#define ATA_ZDI_CAP_VALID 0x8000000000000000 943300207Sken#define ATA_ZDI_CAP_URSWRZ 0x0000000000000001 944300207Sken uint8_t zoned_settings[8]; 945300207Sken#define ATA_ZDI_SETTINGS_VALID 0x8000000000000000 946300207Sken uint8_t optimal_seq_zones[8]; 947300207Sken#define ATA_ZDI_OPT_SEQ_VALID 0x8000000000000000 948300207Sken#define ATA_ZDI_OPT_SEQ_MASK 0x00000000ffffffff 949300207Sken uint8_t optimal_nonseq_zones[8]; 950300207Sken#define ATA_ZDI_OPT_NS_VALID 0x8000000000000000 951300207Sken#define ATA_ZDI_OPT_NS_MASK 0x00000000ffffffff 952300207Sken uint8_t max_seq_req_zones[8]; 953300207Sken#define ATA_ZDI_MAX_SEQ_VALID 0x8000000000000000 954300207Sken#define ATA_ZDI_MAX_SEQ_MASK 0x00000000ffffffff 955300207Sken uint8_t version_info[8]; 956300207Sken#define ATA_ZDI_VER_VALID 0x8000000000000000 957300207Sken#define ATA_ZDI_VER_ZAC_SUP 0x0100000000000000 958300207Sken#define ATA_ZDI_VER_ZAC_MASK 0x00000000000000ff 959300207Sken uint8_t reserved[456]; 960300207Sken}; 961300207Sken 962146266Ssosstruct ata_ioc_request { 963146266Ssos union { 964119404Ssos struct { 965146266Ssos u_int8_t command; 966146266Ssos u_int8_t feature; 967146266Ssos u_int64_t lba; 968146266Ssos u_int16_t count; 969146266Ssos } ata; 970119404Ssos struct { 971146266Ssos char ccb[16]; 972157329Ssos struct atapi_sense sense; 973146266Ssos } atapi; 974146266Ssos } u; 975146266Ssos caddr_t data; 976146266Ssos int count; 977146266Ssos int flags; 978146266Ssos#define ATA_CMD_CONTROL 0x01 979146266Ssos#define ATA_CMD_READ 0x02 980146266Ssos#define ATA_CMD_WRITE 0x04 981146266Ssos#define ATA_CMD_ATAPI 0x08 982119404Ssos 983146266Ssos int timeout; 984146266Ssos int error; 985146266Ssos}; 986119404Ssos 987249115Ssmhstruct ata_security_password { 988249115Ssmh u_int16_t ctrl; 989249115Ssmh#define ATA_SECURITY_PASSWORD_USER 0x0000 990249115Ssmh#define ATA_SECURITY_PASSWORD_MASTER 0x0001 991249115Ssmh#define ATA_SECURITY_ERASE_NORMAL 0x0000 992249115Ssmh#define ATA_SECURITY_ERASE_ENHANCED 0x0002 993249115Ssmh#define ATA_SECURITY_LEVEL_HIGH 0x0000 994249115Ssmh#define ATA_SECURITY_LEVEL_MAXIMUM 0x0100 995249115Ssmh 996249115Ssmh u_int8_t password[32]; 997249115Ssmh u_int16_t revision; 998249115Ssmh u_int16_t reserved[238]; 999249115Ssmh}; 1000249115Ssmh 1001146266Ssos/* pr device ATA ioctl calls */ 1002146266Ssos#define IOCATAREQUEST _IOWR('a', 100, struct ata_ioc_request) 1003146266Ssos#define IOCATAGPARM _IOR('a', 101, struct ata_params) 1004146266Ssos#define IOCATAGMODE _IOR('a', 102, int) 1005146266Ssos#define IOCATASMODE _IOW('a', 103, int) 100693662Ssos 1007177298Sphk#define IOCATAGSPINDOWN _IOR('a', 104, int) 1008177298Sphk#define IOCATASSPINDOWN _IOW('a', 105, int) 1009119404Ssos 1010177298Sphk 1011146266Ssosstruct ata_ioc_raid_config { 1012146266Ssos int lun; 1013146266Ssos int type; 1014146266Ssos#define AR_JBOD 0x0001 1015146266Ssos#define AR_SPAN 0x0002 1016146266Ssos#define AR_RAID0 0x0004 1017146266Ssos#define AR_RAID1 0x0008 1018146266Ssos#define AR_RAID01 0x0010 1019146266Ssos#define AR_RAID3 0x0020 1020146266Ssos#define AR_RAID4 0x0040 1021146266Ssos#define AR_RAID5 0x0080 102293662Ssos 1023146266Ssos int interleave; 1024146266Ssos int status; 1025146266Ssos#define AR_READY 1 1026146266Ssos#define AR_DEGRADED 2 1027146266Ssos#define AR_REBUILDING 4 1028119404Ssos 1029146266Ssos int progress; 1030146266Ssos int total_disks; 1031146266Ssos int disks[16]; 103274298Ssos}; 103374298Ssos 1034171819Sjhbstruct ata_ioc_raid_status { 1035171819Sjhb int lun; 1036171819Sjhb int type; 1037171819Sjhb int interleave; 1038171819Sjhb int status; 1039171819Sjhb int progress; 1040171819Sjhb int total_disks; 1041171819Sjhb struct { 1042171819Sjhb int state; 1043171819Sjhb#define AR_DISK_ONLINE 0x01 1044171819Sjhb#define AR_DISK_PRESENT 0x02 1045171819Sjhb#define AR_DISK_SPARE 0x04 1046171819Sjhb int lun; 1047171819Sjhb } disks[16]; 1048171819Sjhb}; 1049171819Sjhb 1050146266Ssos/* ATA RAID ioctl calls */ 1051148737Ssos#define IOCATARAIDCREATE _IOWR('a', 200, struct ata_ioc_raid_config) 1052146266Ssos#define IOCATARAIDDELETE _IOW('a', 201, int) 1053171819Sjhb#define IOCATARAIDSTATUS _IOWR('a', 202, struct ata_ioc_raid_status) 1054146266Ssos#define IOCATARAIDADDSPARE _IOW('a', 203, struct ata_ioc_raid_config) 1055146266Ssos#define IOCATARAIDREBUILD _IOW('a', 204, int) 105674298Ssos 105774298Ssos#endif /* _SYS_ATA_H_ */ 1058