mp_locore.S revision 182730
189051Sjake/*- 289051Sjake * Copyright (c) 2002 Jake Burkholder. 389051Sjake * All rights reserved. 489051Sjake * 589051Sjake * Redistribution and use in source and binary forms, with or without 689051Sjake * modification, are permitted provided that the following conditions 789051Sjake * are met: 889051Sjake * 1. Redistributions of source code must retain the above copyright 989051Sjake * notice, this list of conditions and the following disclaimer. 1089051Sjake * 2. Redistributions in binary form must reproduce the above copyright 1189051Sjake * notice, this list of conditions and the following disclaimer in the 1289051Sjake * documentation and/or other materials provided with the distribution. 1389051Sjake * 1489051Sjake * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1589051Sjake * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1689051Sjake * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1789051Sjake * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1889051Sjake * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1989051Sjake * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2089051Sjake * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2189051Sjake * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2289051Sjake * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2389051Sjake * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2489051Sjake * SUCH DAMAGE. 2589051Sjake */ 2689051Sjake 27114188Sjake#include <machine/asm.h> 28114188Sjake__FBSDID("$FreeBSD: head/sys/sparc64/sparc64/mp_locore.S 182730 2008-09-03 17:39:19Z marius $"); 29114188Sjake 3089051Sjake#include <machine/asi.h> 3189051Sjake#include <machine/asmacros.h> 3289051Sjake#include <machine/ktr.h> 3389051Sjake#include <machine/pstate.h> 34166105Smarius#include <machine/smp.h> 3591617Sjake#include <machine/upa.h> 36182730Smarius#include <machine/ver.h> 3789051Sjake 3889051Sjake#include "assym.s" 3989051Sjake 4089051Sjake .register %g2, #ignore 4189051Sjake .register %g3, #ignore 4289051Sjake 4391617Sjake .text 44100899Sjake _ALIGN_TEXT 4591617Sjake1: rd %pc, %l0 4691617Sjake ldx [%l0 + (4f-1b)], %l1 4791617Sjake add %l0, (6f-1b), %l2 4891617Sjake clr %l3 4991617Sjake2: cmp %l3, %l1 5091617Sjake be %xcc, 3f 5191617Sjake nop 5291617Sjake ldx [%l2 + TTE_VPN], %l4 5391617Sjake ldx [%l2 + TTE_DATA], %l5 54102040Sjake srlx %l4, TV_SIZE_BITS, %l4 55102040Sjake sllx %l4, PAGE_SHIFT_4M, %l4 5691617Sjake wr %g0, ASI_DMMU, %asi 5791617Sjake stxa %l4, [%g0 + AA_DMMU_TAR] %asi 5891617Sjake stxa %l5, [%g0] ASI_DTLB_DATA_IN_REG 5991617Sjake wr %g0, ASI_IMMU, %asi 6091617Sjake stxa %l4, [%g0 + AA_IMMU_TAR] %asi 6191617Sjake stxa %l5, [%g0] ASI_ITLB_DATA_IN_REG 6291617Sjake membar #Sync 6391617Sjake flush %l4 6491617Sjake add %l2, 1 << TTE_SHIFT, %l2 6591617Sjake add %l3, 1, %l3 6691617Sjake ba %xcc, 2b 6791617Sjake nop 6891617Sjake3: ldx [%l0 + (5f-1b)], %l1 6991617Sjake jmpl %l1, %g0 7091617Sjake nop 71100899Sjake _ALIGN_DATA 7291617Sjake4: .xword 0x0 7391617Sjake5: .xword 0x0 7491617Sjake6: 7591617Sjake 7691617SjakeDATA(mp_tramp_code) 7791617Sjake .xword 1b 7891617SjakeDATA(mp_tramp_code_len) 7991617Sjake .xword 6b-1b 8091617SjakeDATA(mp_tramp_tlb_slots) 8191617Sjake .xword 4b-1b 8291617SjakeDATA(mp_tramp_func) 8391617Sjake .xword 5b-1b 8491617Sjake 8589051Sjake/* 8691617Sjake * void mp_startup(void) 8789051Sjake */ 8891617SjakeENTRY(mp_startup) 8991617Sjake wrpr %g0, PSTATE_NORMAL, %pstate 9091617Sjake wrpr %g0, 0, %cleanwin 9191617Sjake wrpr %g0, 0, %pil 9291617Sjake wr %g0, 0, %fprs 9389051Sjake 9491617Sjake SET(cpu_start_args, %l1, %l0) 9591617Sjake 96182730Smarius mov CPU_TICKSYNC, %l1 9789051Sjake membar #StoreLoad 9891617Sjake stw %l1, [%l0 + CSA_STATE] 9989051Sjake 10091617Sjake1: ldx [%l0 + CSA_TICK], %l1 10191617Sjake brz %l1, 1b 10291617Sjake nop 10391617Sjake wrpr %l1, 0, %tick 10491617Sjake 105182730Smarius rdpr %ver, %l1 106182730Smarius stx %l1, [%l0 + CSA_VER] 10791617Sjake 108182730Smarius srlx %l1, VER_IMPL_SHIFT, %l1 109182730Smarius sll %l1, VER_IMPL_SIZE, %l1 110182730Smarius srl %l1, VER_IMPL_SIZE, %l1 111182730Smarius cmp %l1, CPU_IMPL_ULTRASPARCIII 112182730Smarius bl %icc, 3f 113182730Smarius nop 114182730Smarius mov CPU_STICKSYNC, %l1 115182730Smarius membar #StoreLoad 116182730Smarius stw %l1, [%l0 + CSA_STATE] 117182730Smarius 118182730Smarius2: ldx [%l0 + CSA_STICK], %l1 119182730Smarius brz %l1, 2b 120182730Smarius nop 121182730Smarius wr %l1, 0, %asr24 122182730Smarius 123182730Smarius3: UPA_GET_MID(%o0) 124182730Smarius 12589051Sjake#if KTR_COMPILE & KTR_SMP 126181701Smarius CATR(KTR_SMP, "mp_start: CPU %d entered kernel" 12789051Sjake , %g1, %g2, %g3, 7, 8, 9) 12891617Sjake stx %o0, [%g1 + KTR_PARM1] 12989051Sjake9: 13089051Sjake#endif 13189051Sjake 13289051Sjake /* 13391617Sjake * Inform the boot processor we have inited. 13489051Sjake */ 13591617Sjake mov CPU_INIT, %l1 13691617Sjake membar #LoadStore 13791617Sjake stw %l1, [%l0 + CSA_STATE] 13891617Sjake 13991617Sjake /* 14091617Sjake * Wait till its our turn to bootstrap. 14191617Sjake */ 142182730Smarius4: lduw [%l0 + CSA_MID], %l1 14391617Sjake cmp %l1, %o0 144182730Smarius bne %xcc, 4b 14589051Sjake nop 14689051Sjake 14789051Sjake#if KTR_COMPILE & KTR_SMP 148181701Smarius CATR(KTR_SMP, "_mp_start: CPU %d got start signal" 14989051Sjake , %g1, %g2, %g3, 7, 8, 9) 15091617Sjake stx %o0, [%g1 + KTR_PARM1] 15189051Sjake9: 15289051Sjake#endif 15389051Sjake 15491783Sjake add %l0, CSA_TTES, %l1 15591783Sjake clr %l2 15691783Sjake 15789051Sjake /* 158181701Smarius * Map the per-CPU pages. 15989051Sjake */ 160182730Smarius5: sllx %l2, TTE_SHIFT, %l3 16191783Sjake add %l1, %l3, %l3 16289051Sjake 16391783Sjake ldx [%l3 + TTE_VPN], %l4 16491783Sjake ldx [%l3 + TTE_DATA], %l5 16591783Sjake 16689051Sjake wr %g0, ASI_DMMU, %asi 167102040Sjake srlx %l4, TV_SIZE_BITS, %l4 168102040Sjake sllx %l4, PAGE_SHIFT_8K, %l4 16991783Sjake stxa %l4, [%g0 + AA_DMMU_TAR] %asi 17091783Sjake stxa %l5, [%g0] ASI_DTLB_DATA_IN_REG 17189051Sjake membar #Sync 17289051Sjake 17391783Sjake add %l2, 1, %l2 17491783Sjake cmp %l2, PCPU_PAGES 175182730Smarius bne %xcc, 5b 17691783Sjake nop 17791783Sjake 17889051Sjake /* 179181701Smarius * Get onto our per-CPU panic stack, which precedes the struct pcpu 180181701Smarius * in the per-CPU page. 18189051Sjake */ 18291783Sjake ldx [%l0 + CSA_PCPU], %l1 18391617Sjake set PCPU_PAGES * PAGE_SIZE - PC_SIZEOF, %l2 18491617Sjake add %l1, %l2, %l1 18591617Sjake sub %l1, SPOFF + CCFSZ, %sp 18689051Sjake 18789051Sjake /* 18889051Sjake * Enable interrupts. 18989051Sjake */ 19089051Sjake wrpr %g0, PSTATE_KERNEL, %pstate 19189051Sjake 19289051Sjake#if KTR_COMPILE & KTR_SMP 19389051Sjake CATR(KTR_SMP, 19489051Sjake "_mp_start: bootstrap cpuid=%d mid=%d pcpu=%#lx data=%#lx sp=%#lx" 19589051Sjake , %g1, %g2, %g3, 7, 8, 9) 19691783Sjake lduw [%l1 + PC_CPUID], %g2 19789051Sjake stx %g2, [%g1 + KTR_PARM1] 19891783Sjake lduw [%l1 + PC_MID], %g2 19989051Sjake stx %g2, [%g1 + KTR_PARM2] 20091783Sjake stx %l1, [%g1 + KTR_PARM3] 20189051Sjake stx %sp, [%g1 + KTR_PARM5] 20289051Sjake9: 20389051Sjake#endif 20489051Sjake 20589051Sjake /* 20689051Sjake * And away we go. This doesn't return. 20789051Sjake */ 20889051Sjake call cpu_mp_bootstrap 20991617Sjake mov %l1, %o0 21089051Sjake sir 21189051Sjake ! NOTREACHED 21291617SjakeEND(mp_startup) 213