mp_exception.S revision 89051 
1/*-
2 * Copyright (c) 2002 Jake Burkholder.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/sparc64/sparc64/mp_exception.S 89051 2002-01-08 05:50:26Z jake $
27 */
28
29#include <machine/asi.h>
30#include <machine/ktr.h>
31#include <machine/asmacros.h>
32#include <machine/pstate.h>
33
34#include "assym.s"
35
36	.register	%g2, #ignore
37	.register	%g3, #ignore
38
39#define	IPI_WAIT(r1, r2, r3) \
40	ATOMIC_DEC_INT(r1, r2, r3) ; \
419:	membar	#StoreLoad ; \
42	lduw	[r1], r2 ; \
43	brnz,a,pn r2, 9b ; \
44	 nop
45
46/*
47 * Trigger a softint at the desired level.
48 */
49ENTRY(tl_ipi_level)
50	lduw	[%g5 + ILA_LEVEL], %g2
51
52	mov	1, %g1
53	sllx	%g1, %g2, %g1
54	wr	%g1, 0, %asr20
55
56	IPI_WAIT(%g5, %g1, %g2)
57	retry
58END(tl_ipi_level)
59
60ENTRY(tl_ipi_test)
61#if KTR_COMPILE & KTR_SMP
62	CATR(KTR_SMP, "ipi_test: cpuid=%d mid=%d d1=%#lx d2=%#lx"
63	    , %g1, %g2, %g3, 7, 8, 9)
64	lduw	[PCPU(CPUID)], %g2
65	stx	%g2, [%g1 + KTR_PARM1]
66	lduw	[PCPU(MID)], %g2
67	stx	%g2, [%g1 + KTR_PARM2]
68	stx	%g4, [%g1 + KTR_PARM3]
69	stx	%g5, [%g1 + KTR_PARM4]
709:
71#endif
72	retry
73END(tl_ipi_test)
74
75/*
76 * Demap a page from the dtlb and/or itlb.
77 */
78ENTRY(tl_ipi_tlb_page_demap)
79	ldx	[%g5 + ITA_TLB], %g1
80	ldx	[%g5 + ITA_CTX], %g2
81	ldx	[%g5 + ITA_VA], %g3
82
83	wr	%g0, ASI_DMMU, %asi
84
85	brz,a,pt %g2, 1f
86	 or	%g3, TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE, %g3
87
88	stxa	%g2, [%g0 + AA_DMMU_SCXR] %asi
89	membar	#Sync
90	or	%g3, TLB_DEMAP_SECONDARY | TLB_DEMAP_PAGE, %g3
91
921:	andcc	%g1, TLB_DTLB, %g0
93	bz,a,pn %xcc, 2f
94	 nop
95	stxa	%g0, [%g3] ASI_DMMU_DEMAP
96
972:	andcc	%g1, TLB_ITLB, %g0
98	bz,a,pn %xcc, 3f
99	 nop
100	stxa	%g0, [%g3] ASI_IMMU_DEMAP
101
1023:	brz,a,pt %g2, 4f
103	 nop
104	stxa	%g0, [%g0 + AA_DMMU_SCXR] %asi
105
1064:	membar	#Sync
107
108	IPI_WAIT(%g5, %g1, %g2)
109	retry
110END(tl_ipi_tlb_page_demap)
111
112/*
113 * Demap a range of pages from the dtlb and itlb.
114 */
115ENTRY(tl_ipi_tlb_range_demap)
116	ldx	[%g5 + ITA_CTX], %g1
117	ldx	[%g5 + ITA_START], %g2
118	ldx	[%g5 + ITA_END], %g3
119
120	wr	%g0, ASI_DMMU, %asi
121
122	brz,a,pt %g1, 1f
123	 mov	TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE, %g4
124
125	stxa	%g1, [%g0 + AA_DMMU_SCXR] %asi
126	membar	#Sync
127	mov	TLB_DEMAP_SECONDARY | TLB_DEMAP_PAGE, %g4
128
1291:	set	PAGE_SIZE, %g5
130
1312:	or	%g4, %g2, %g4
132	stxa	%g0, [%g4] ASI_DMMU_DEMAP
133	stxa	%g0, [%g4] ASI_IMMU_DEMAP
134
135	add	%g2, %g5, %g2
136	cmp	%g2, %g3
137	bne,a,pt %xcc, 2b
138	 nop
139
140	brz,a,pt %g1, 3f
141	 nop
142	stxa	%g0, [%g0 + AA_DMMU_SCXR] %asi
143
1443:	membar	#Sync
145
146	IPI_WAIT(%g5, %g1, %g2)
147	retry
148END(tl_ipi_tlb_range_demap)
149
150/*
151 * Demap an entire context from the dtlb and itlb.
152 */
153ENTRY(tl_ipi_tlb_context_demap)
154	ldx	[%g5 + ITA_CTX], %g1
155
156	mov	AA_DMMU_SCXR, %g2
157	stxa	%g1, [%g2] ASI_DMMU
158	membar	#Sync
159
160	mov	TLB_DEMAP_SECONDARY | TLB_DEMAP_CONTEXT, %g3
161	stxa	%g0, [%g3] ASI_DMMU_DEMAP
162	stxa	%g0, [%g3] ASI_IMMU_DEMAP
163
164	stxa	%g0, [%g2] ASI_DMMU
165	membar	#Sync
166
167	IPI_WAIT(%g5, %g1, %g2)
168	retry
169END(tl_ipi_tlb_context_demap)
170