interrupt.S revision 245017
1/*- 2 * Copyright (c) 2002 Jake Burkholder. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <machine/asm.h> 28__FBSDID("$FreeBSD: head/sys/sparc64/sparc64/interrupt.S 245017 2013-01-03 23:12:08Z marius $"); 29 30#include <machine/asi.h> 31#include <machine/asmacros.h> 32#include <machine/intr_machdep.h> 33#include <machine/pstate.h> 34#include <machine/ver.h> 35 36#include "assym.s" 37 38/* 39 * Handle a vectored interrupt. 40 * 41 * This is either a data bearing mondo vector interrupt, or a cross trap 42 * request from another cpu. In either case the hardware supplies an 43 * interrupt packet, in the form of 3 data words which are read from internal 44 * registers. A data bearing mondo vector packet consists of an interrupt 45 * number in the first data word, and zero in 2nd and 3rd. We use the 46 * interrupt number to find the function, argument and priority from the 47 * intr_vector table, allocate and fill in an intr_request from the per-cpu 48 * free list, link it onto the per-cpu active list and finally post a softint 49 * at the desired priority. Cross trap requests come in 2 forms, direct 50 * and queued. Direct requests are distinguished by the first data word 51 * being zero. The 2nd data word carries a function to call and the 3rd 52 * an argument to pass. The function is jumped to directly. It executes 53 * in nucleus context on interrupt globals and with all interrupts disabled, 54 * therefore it must be fast, and the things that it can do are limited. 55 * Queued cross trap requests are handled much like mondo vectors, except 56 * that the function, argument and priority are contained in the interrupt 57 * packet itself. They are distinguished by the upper 4 bits of the data 58 * word being non-zero, which specifies the priority of the softint to 59 * deliver. 60 * 61 * Register usage: 62 * %g1 - pointer to intr_request 63 * %g2 - pointer to intr_vector, temp once required data is loaded 64 * %g3 - interrupt number for mondo vectors, unused otherwise 65 * %g4 - function, from the interrupt packet for cross traps, or 66 * loaded from the interrupt registers for mondo vecors 67 * %g5 - argument, as above for %g4 68 * %g6 - softint priority 69 */ 70ENTRY(intr_vector) 71 /* 72 * Load the interrupt packet from the hardware. 73 */ 74 wr %g0, ASI_SDB_INTR_R, %asi 75 ldxa [%g0 + AA_SDB_INTR_D0] %asi, %g3 76 ldxa [%g0 + AA_SDB_INTR_D1] %asi, %g4 77 ldxa [%g0 + AA_SDB_INTR_D2] %asi, %g5 78 stxa %g0, [%g0] ASI_INTR_RECEIVE 79 membar #Sync 80 81 /* 82 * If the first data word is zero this is a direct cross trap request. 83 * The 2nd word points to code to execute and the 3rd is an argument 84 * to pass. Jump to it. 85 */ 86 brnz,pt %g3, 1f 87 /* 88 * NB: Zeus CPUs set some undocumented bits in the first data word. 89 */ 90 and %g3, IV_MAX - 1, %g3 91 jmpl %g4, %g0 92 nop 93 /* NOTREACHED */ 94 95 /* 96 * If the high 4 bits of the 1st data word are non-zero, this is a 97 * queued cross trap request to be delivered as a softint. The high 98 * 4 bits of the 1st data word specify a priority, and the 2nd and 99 * 3rd a function and argument. 100 */ 1011: srlx %g3, 60, %g6 102 brnz,a,pn %g6, 2f 103 clr %g3 104 105 /* 106 * Find the function, argument and desired priority from the 107 * intr_vector table. 108 */ 109 SET(intr_vectors, %g4, %g2) 110 sllx %g3, IV_SHIFT, %g4 111 add %g2, %g4, %g2 112 113 ldx [%g2 + IV_FUNC], %g4 114 ldx [%g2 + IV_ARG], %g5 115 lduw [%g2 + IV_PRI], %g6 116 117 /* 118 * Get an intr_request from the free list. There should always be one 119 * unless we are getting an interrupt storm from stray interrupts, in 120 * which case the we will deference a NULL pointer and panic. 121 */ 1222: ldx [PCPU(IRFREE)], %g1 123 ldx [%g1 + IR_NEXT], %g2 124 stx %g2, [PCPU(IRFREE)] 125 126 /* 127 * Store the vector number, function, argument and priority. 128 */ 129 stw %g3, [%g1 + IR_VEC] 130 stx %g4, [%g1 + IR_FUNC] 131 stx %g5, [%g1 + IR_ARG] 132 stw %g6, [%g1 + IR_PRI] 133 134 /* 135 * Link it onto the end of the active list. 136 */ 137 stx %g0, [%g1 + IR_NEXT] 138 ldx [PCPU(IRTAIL)], %g4 139 stx %g1, [%g4] 140 add %g1, IR_NEXT, %g1 141 stx %g1, [PCPU(IRTAIL)] 142 143 /* 144 * Trigger a softint at the level indicated by the priority. 145 */ 146 mov 1, %g1 147 sllx %g1, %g6, %g1 148 wr %g1, 0, %set_softint 149 150 /* 151 * Done, retry the instruction. 152 */ 153 retry 154END(intr_vector) 155 156ENTRY(intr_vector_stray) 157 /* 158 * SPARC64-VI trigger stray vector interrupts in order to indicate 159 * uncorrectable errors in interrupt packets, which still need to be 160 * acknowledged though. 161 * US-IV occasionally trigger stray vector interrupts for reasons 162 * unknown accompanied by a state in which they even fault on locked 163 * TLB entries so we can't even log these here. Just retrying the 164 * instruction in that case gets the CPU back on track. 165 */ 166 rdpr %ver, %g1 167 srlx %g1, VER_IMPL_SHIFT, %g1 168 sll %g1, VER_IMPL_SIZE, %g1 169 srl %g1, VER_IMPL_SIZE, %g1 170 cmp %g1, CPU_IMPL_SPARC64VI 171 bne,a,pn %icc, 1f 172 nop 173 stxa %g0, [%g0] ASI_INTR_RECEIVE 174 membar #Sync 175 1761: retry 177END(intr_vector_stray) 178 179ENTRY(intr_fast) 180 save %sp, -CCFSZ, %sp 181 182 /* 183 * Disable interrupts while we fiddle with the interrupt request lists 184 * as interrupts at levels higher than what got us here aren't blocked. 185 */ 1861: wrpr %g0, PSTATE_NORMAL, %pstate 187 188 ldx [PCPU(IRHEAD)], %l0 189 brnz,a,pt %l0, 2f 190 nop 191 192 wrpr %g0, PSTATE_KERNEL, %pstate 193 194 ret 195 restore 196 1972: ldx [%l0 + IR_NEXT], %l1 198 brnz,pt %l1, 3f 199 stx %l1, [PCPU(IRHEAD)] 200 PCPU_ADDR(IRHEAD, %l1) 201 stx %l1, [PCPU(IRTAIL)] 202 2033: ldx [%l0 + IR_FUNC], %o0 204 ldx [%l0 + IR_ARG], %o1 205 lduw [%l0 + IR_VEC], %l2 206 207 ldx [PCPU(IRFREE)], %l1 208 stx %l1, [%l0 + IR_NEXT] 209 stx %l0, [PCPU(IRFREE)] 210 211 wrpr %g0, PSTATE_KERNEL, %pstate 212 213 KASSERT(%o0, "intr_fast: ir_func null") 214 call %o0 215 mov %o1, %o0 216 217 /* intrcnt[intr_countp[%l2]]++ */ 218 SET(intrcnt, %l7, %l3) /* %l3 = intrcnt */ 219 prefetcha [%l3] ASI_N, 1 220 SET(intr_countp, %l7, %l4) /* %l4 = intr_countp */ 221 sllx %l2, 1, %l2 /* %l2 = vec << 1 */ 222 lduh [%l4 + %l2], %l4 /* %l4 = intr_countp[%l2] */ 223 sllx %l4, 3, %l4 /* %l4 = intr_countp[%l2] << 3 */ 224 add %l4, %l3, %l4 /* %l4 = intrcnt[intr_countp[%l2]] */ 225 ldx [%l4], %l2 226 inc %l2 227 stx %l2, [%l4] 228 229 ba,a %xcc, 1b 230 nop 231END(intr_fast) 232