interrupt.S revision 223721
1/*- 2 * Copyright (c) 2002 Jake Burkholder. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <machine/asm.h> 28__FBSDID("$FreeBSD: head/sys/sparc64/sparc64/interrupt.S 223721 2011-07-02 12:56:03Z marius $"); 29 30#include <machine/asi.h> 31#include <machine/asmacros.h> 32#include <machine/intr_machdep.h> 33#include <machine/ktr.h> 34#include <machine/pstate.h> 35#include <machine/ver.h> 36 37#include "assym.s" 38 39/* 40 * Handle a vectored interrupt. 41 * 42 * This is either a data bearing mondo vector interrupt, or a cross trap 43 * request from another cpu. In either case the hardware supplies an 44 * interrupt packet, in the form of 3 data words which are read from internal 45 * registers. A data bearing mondo vector packet consists of an interrupt 46 * number in the first data word, and zero in 2nd and 3rd. We use the 47 * interrupt number to find the function, argument and priority from the 48 * intr_vector table, allocate and fill in an intr_request from the per-cpu 49 * free list, link it onto the per-cpu active list and finally post a softint 50 * at the desired priority. Cross trap requests come in 2 forms, direct 51 * and queued. Direct requests are distinguished by the first data word 52 * being zero. The 2nd data word carries a function to call and the 3rd 53 * an argument to pass. The function is jumped to directly. It executes 54 * in nucleus context on interrupt globals and with all interrupts disabled, 55 * therefore it must be fast, and the things that it can do are limited. 56 * Queued cross trap requests are handled much like mondo vectors, except 57 * that the function, argument and priority are contained in the interrupt 58 * packet itself. They are distinguished by the upper 4 bits of the data 59 * word being non-zero, which specifies the priority of the softint to 60 * deliver. 61 * 62 * Register usage: 63 * %g1 - pointer to intr_request 64 * %g2 - pointer to intr_vector, temp once required data is loaded 65 * %g3 - interrupt number for mondo vectors, unused otherwise 66 * %g4 - function, from the interrupt packet for cross traps, or 67 * loaded from the interrupt registers for mondo vecors 68 * %g5 - argument, as above for %g4 69 * %g6 - softint priority 70 */ 71ENTRY(intr_vector) 72 /* 73 * Load the interrupt packet from the hardware. 74 */ 75 wr %g0, ASI_SDB_INTR_R, %asi 76 ldxa [%g0 + AA_SDB_INTR_D0] %asi, %g3 77 ldxa [%g0 + AA_SDB_INTR_D1] %asi, %g4 78 ldxa [%g0 + AA_SDB_INTR_D2] %asi, %g5 79 stxa %g0, [%g0] ASI_INTR_RECEIVE 80 membar #Sync 81 82 /* 83 * If the first data word is zero this is a direct cross trap request. 84 * The 2nd word points to code to execute and the 3rd is an argument 85 * to pass. Jump to it. 86 */ 87 brnz,pt %g3, 1f 88 /* 89 * NB: Zeus CPUs set some undocumented bits in the first data word. 90 */ 91 and %g3, IV_MAX - 1, %g3 92 jmpl %g4, %g0 93 nop 94 /* NOTREACHED */ 95 96 /* 97 * If the high 4 bits of the 1st data word are non-zero, this is a 98 * queued cross trap request to be delivered as a softint. The high 99 * 4 bits of the 1st data word specify a priority, and the 2nd and 100 * 3rd a function and argument. 101 */ 1021: srlx %g3, 60, %g6 103 brnz,a,pn %g6, 2f 104 clr %g3 105 106 /* 107 * Find the function, argument and desired priority from the 108 * intr_vector table. 109 */ 110 SET(intr_vectors, %g4, %g2) 111 sllx %g3, IV_SHIFT, %g4 112 add %g2, %g4, %g2 113 114 ldx [%g2 + IV_FUNC], %g4 115 ldx [%g2 + IV_ARG], %g5 116 lduw [%g2 + IV_PRI], %g6 117 118 /* 119 * Get an intr_request from the free list. There should always be one 120 * unless we are getting an interrupt storm from stray interrupts, in 121 * which case the we will deference a NULL pointer and panic. 122 */ 1232: ldx [PCPU(IRFREE)], %g1 124 ldx [%g1 + IR_NEXT], %g2 125 stx %g2, [PCPU(IRFREE)] 126 127 /* 128 * Store the vector number, function, argument and priority. 129 */ 130 stw %g3, [%g1 + IR_VEC] 131 stx %g4, [%g1 + IR_FUNC] 132 stx %g5, [%g1 + IR_ARG] 133 stw %g6, [%g1 + IR_PRI] 134 135 /* 136 * Link it onto the end of the active list. 137 */ 138 stx %g0, [%g1 + IR_NEXT] 139 ldx [PCPU(IRTAIL)], %g4 140 stx %g1, [%g4] 141 add %g1, IR_NEXT, %g1 142 stx %g1, [PCPU(IRTAIL)] 143 144 /* 145 * Trigger a softint at the level indicated by the priority. 146 */ 147 mov 1, %g1 148 sllx %g1, %g6, %g1 149 wr %g1, 0, %set_softint 150 151 /* 152 * Done, retry the instruction. 153 */ 154 retry 155END(intr_vector) 156 157ENTRY(intr_vector_stray) 158 /* 159 * SPARC64-VI trigger stray vector interrupts in order to indicate 160 * uncorrectable errors in interrupt packets, which still need to be 161 * acknowledged though. 162 * US-IV occasionally trigger stray vector interrupts for reasons 163 * unknown accompanied by a state in which they even fault on locked 164 * TLB entries so we can't even log these here. Just retrying the 165 * instruction in that case gets the CPU back on track. 166 */ 167 rdpr %ver, %g1 168 srlx %g1, VER_IMPL_SHIFT, %g1 169 sll %g1, VER_IMPL_SIZE, %g1 170 srl %g1, VER_IMPL_SIZE, %g1 171 cmp %g1, CPU_IMPL_SPARC64VI 172 bne,a,pn %icc, 1f 173 nop 174 stxa %g0, [%g0] ASI_INTR_RECEIVE 175 membar #Sync 176 1771: retry 178END(intr_vector_stray) 179 180ENTRY(intr_fast) 181 save %sp, -CCFSZ, %sp 182 183 /* 184 * Disable interrupts while we fiddle with the interrupt request lists 185 * as interrupts at levels higher than what got us here aren't blocked. 186 */ 1871: wrpr %g0, PSTATE_NORMAL, %pstate 188 189 ldx [PCPU(IRHEAD)], %l0 190 brnz,a,pt %l0, 2f 191 nop 192 193 wrpr %g0, PSTATE_KERNEL, %pstate 194 195 ret 196 restore 197 1982: ldx [%l0 + IR_NEXT], %l1 199 brnz,pt %l1, 3f 200 stx %l1, [PCPU(IRHEAD)] 201 PCPU_ADDR(IRHEAD, %l1) 202 stx %l1, [PCPU(IRTAIL)] 203 2043: ldx [%l0 + IR_FUNC], %o0 205 ldx [%l0 + IR_ARG], %o1 206 lduw [%l0 + IR_VEC], %l2 207 208 ldx [PCPU(IRFREE)], %l1 209 stx %l1, [%l0 + IR_NEXT] 210 stx %l0, [PCPU(IRFREE)] 211 212 wrpr %g0, PSTATE_KERNEL, %pstate 213 214 KASSERT(%o0, "intr_fast: ir_func null") 215 call %o0 216 mov %o1, %o0 217 218 /* intrcnt[intr_countp[%l2]]++ */ 219 SET(intrcnt, %l7, %l3) /* %l3 = intrcnt */ 220 prefetcha [%l3] ASI_N, 1 221 SET(intr_countp, %l7, %l4) /* %l4 = intr_countp */ 222 sllx %l2, 1, %l2 /* %l2 = vec << 1 */ 223 lduh [%l4 + %l2], %l4 /* %l4 = intr_countp[%l2] */ 224 sllx %l4, 3, %l4 /* %l4 = intr_countp[%l2] << 3 */ 225 add %l4, %l3, %l4 /* %l4 = intrcnt[intr_countp[%l2]] */ 226 ldx [%l4], %l2 227 inc %l2 228 stx %l2, [%l4] 229 230 ba,a %xcc, 1b 231 nop 232END(intr_fast) 233