bus_machdep.c revision 112436
1/*- 2 * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 7 * NASA Ames Research Center. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. Neither the name of The NetBSD Foundation nor the names of its 22 * contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37/* 38 * Copyright (c) 1992, 1993 39 * The Regents of the University of California. All rights reserved. 40 * 41 * This software was developed by the Computer Systems Engineering group 42 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 43 * contributed to Berkeley. 44 * 45 * All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by the University of 48 * California, Lawrence Berkeley Laboratory. 49 * 50 * Redistribution and use in source and binary forms, with or without 51 * modification, are permitted provided that the following conditions 52 * are met: 53 * 1. Redistributions of source code must retain the above copyright 54 * notice, this list of conditions and the following disclaimer. 55 * 2. Redistributions in binary form must reproduce the above copyright 56 * notice, this list of conditions and the following disclaimer in the 57 * documentation and/or other materials provided with the distribution. 58 * 3. All advertising materials mentioning features or use of this software 59 * must display the following acknowledgement: 60 * This product includes software developed by the University of 61 * California, Berkeley and its contributors. 62 * 4. Neither the name of the University nor the names of its contributors 63 * may be used to endorse or promote products derived from this software 64 * without specific prior written permission. 65 * 66 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 67 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 68 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 69 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 70 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 71 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 72 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 73 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 74 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 75 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 76 * SUCH DAMAGE. 77 */ 78/* 79 * Copyright (c) 1997, 1998 Justin T. Gibbs. 80 * All rights reserved. 81 * Copyright 2001 by Thomas Moestl <tmm@FreeBSD.org>. All rights reserved. 82 * 83 * Redistribution and use in source and binary forms, with or without 84 * modification, are permitted provided that the following conditions 85 * are met: 86 * 1. Redistributions of source code must retain the above copyright 87 * notice, this list of conditions, and the following disclaimer, 88 * without modification, immediately at the beginning of the file. 89 * 2. The name of the author may not be used to endorse or promote products 90 * derived from this software without specific prior written permission. 91 * 92 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 93 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 94 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 95 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 96 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 97 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 98 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 99 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 100 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 101 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 102 * SUCH DAMAGE. 103 * 104 * from: @(#)machdep.c 8.6 (Berkeley) 1/14/94 105 * from: NetBSD: machdep.c,v 1.111 2001/09/15 07:13:40 eeh Exp 106 * and 107 * from: FreeBSD: src/sys/i386/i386/busdma_machdep.c,v 1.24 2001/08/15 108 * 109 * $FreeBSD: head/sys/sparc64/sparc64/bus_machdep.c 112436 2003-03-20 19:45:26Z mux $ 110 */ 111 112#include <sys/param.h> 113#include <sys/bus.h> 114#include <sys/lock.h> 115#include <sys/malloc.h> 116#include <sys/mbuf.h> 117#include <sys/mutex.h> 118#include <sys/proc.h> 119#include <sys/smp.h> 120#include <sys/systm.h> 121#include <sys/uio.h> 122 123#include <vm/vm.h> 124#include <vm/vm_extern.h> 125#include <vm/vm_kern.h> 126#include <vm/vm_page.h> 127#include <vm/vm_param.h> 128#include <vm/vm_map.h> 129 130#include <machine/asi.h> 131#include <machine/atomic.h> 132#include <machine/bus.h> 133#include <machine/bus_private.h> 134#include <machine/cache.h> 135#include <machine/smp.h> 136#include <machine/tlb.h> 137 138/* ASI's for bus access. */ 139int bus_type_asi[] = { 140 ASI_PHYS_BYPASS_EC_WITH_EBIT, /* UPA */ 141 ASI_PHYS_BYPASS_EC_WITH_EBIT, /* SBUS */ 142 ASI_PHYS_BYPASS_EC_WITH_EBIT_L, /* PCI configuration space */ 143 ASI_PHYS_BYPASS_EC_WITH_EBIT_L, /* PCI memory space */ 144 ASI_PHYS_BYPASS_EC_WITH_EBIT_L, /* PCI I/O space */ 145 0 146}; 147 148int bus_stream_asi[] = { 149 ASI_PHYS_BYPASS_EC_WITH_EBIT, /* UPA */ 150 ASI_PHYS_BYPASS_EC_WITH_EBIT, /* SBUS */ 151 ASI_PHYS_BYPASS_EC_WITH_EBIT, /* PCI configuration space */ 152 ASI_PHYS_BYPASS_EC_WITH_EBIT, /* PCI memory space */ 153 ASI_PHYS_BYPASS_EC_WITH_EBIT, /* PCI I/O space */ 154 0 155}; 156 157/* 158 * busdma support code. 159 * Note: there is no support for bounce buffers yet. 160 */ 161 162static int nexus_dmamap_create(bus_dma_tag_t, bus_dma_tag_t, int, 163 bus_dmamap_t *); 164static int nexus_dmamap_destroy(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 165static int nexus_dmamap_load(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 166 void *, bus_size_t, bus_dmamap_callback_t *, void *, int); 167static int nexus_dmamap_load_mbuf(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 168 struct mbuf *, bus_dmamap_callback2_t *, void *, int); 169static int nexus_dmamap_load_uio(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 170 struct uio *, bus_dmamap_callback2_t *, void *, int); 171static void nexus_dmamap_unload(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 172static void nexus_dmamap_sync(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 173 bus_dmasync_op_t); 174static int nexus_dmamem_alloc_size(bus_dma_tag_t, bus_dma_tag_t, void **, int, 175 bus_dmamap_t *, u_long size); 176static int nexus_dmamem_alloc(bus_dma_tag_t, bus_dma_tag_t, void **, int, 177 bus_dmamap_t *); 178static void nexus_dmamem_free_size(bus_dma_tag_t, bus_dma_tag_t, void *, 179 bus_dmamap_t, u_long size); 180static void nexus_dmamem_free(bus_dma_tag_t, bus_dma_tag_t, void *, 181 bus_dmamap_t); 182 183/* 184 * Since there is now way for a device to obtain a dma tag from its parent 185 * we use this kluge to handle different the different supported bus systems. 186 * The sparc64_root_dma_tag is used as parent for tags that have none, so that 187 * the correct methods will be used. 188 */ 189bus_dma_tag_t sparc64_root_dma_tag; 190 191/* 192 * Allocate a device specific dma_tag. 193 */ 194int 195bus_dma_tag_create(bus_dma_tag_t parent, bus_size_t alignment, 196 bus_size_t boundary, bus_addr_t lowaddr, bus_addr_t highaddr, 197 bus_dma_filter_t *filter, void *filterarg, bus_size_t maxsize, 198 int nsegments, bus_size_t maxsegsz, int flags, bus_dma_tag_t *dmat) 199{ 200 201 bus_dma_tag_t newtag; 202 203 /* Return a NULL tag on failure */ 204 *dmat = NULL; 205 206 newtag = (bus_dma_tag_t)malloc(sizeof(*newtag), M_DEVBUF, M_NOWAIT); 207 if (newtag == NULL) 208 return (ENOMEM); 209 210 newtag->dt_parent = parent != NULL ? parent : sparc64_root_dma_tag; 211 newtag->dt_alignment = alignment; 212 newtag->dt_boundary = boundary; 213 newtag->dt_lowaddr = trunc_page((vm_offset_t)lowaddr) + (PAGE_SIZE - 1); 214 newtag->dt_highaddr = trunc_page((vm_offset_t)highaddr) + 215 (PAGE_SIZE - 1); 216 newtag->dt_filter = filter; 217 newtag->dt_filterarg = filterarg; 218 newtag->dt_maxsize = maxsize; 219 newtag->dt_nsegments = nsegments; 220 newtag->dt_maxsegsz = maxsegsz; 221 newtag->dt_flags = flags; 222 newtag->dt_ref_count = 1; /* Count ourselves */ 223 newtag->dt_map_count = 0; 224 225 newtag->dt_dmamap_create = NULL; 226 newtag->dt_dmamap_destroy = NULL; 227 newtag->dt_dmamap_load = NULL; 228 newtag->dt_dmamap_load_mbuf = NULL; 229 newtag->dt_dmamap_load_uio = NULL; 230 newtag->dt_dmamap_unload = NULL; 231 newtag->dt_dmamap_sync = NULL; 232 newtag->dt_dmamem_alloc_size = NULL; 233 newtag->dt_dmamem_alloc = NULL; 234 newtag->dt_dmamem_free_size = NULL; 235 newtag->dt_dmamem_free = NULL; 236 237 /* Take into account any restrictions imposed by our parent tag */ 238 if (parent != NULL) { 239 newtag->dt_lowaddr = ulmin(parent->dt_lowaddr, 240 newtag->dt_lowaddr); 241 newtag->dt_highaddr = ulmax(parent->dt_highaddr, 242 newtag->dt_highaddr); 243 /* 244 * XXX Not really correct??? Probably need to honor boundary 245 * all the way up the inheritence chain. 246 */ 247 newtag->dt_boundary = ulmin(parent->dt_boundary, 248 newtag->dt_boundary); 249 } 250 atomic_add_int(&newtag->dt_parent->dt_ref_count, 1); 251 252 *dmat = newtag; 253 return (0); 254} 255 256int 257bus_dma_tag_destroy(bus_dma_tag_t dmat) 258{ 259 bus_dma_tag_t parent; 260 261 if (dmat != NULL) { 262 if (dmat->dt_map_count != 0) 263 return (EBUSY); 264 while (dmat != NULL) { 265 parent = dmat->dt_parent; 266 atomic_subtract_int(&dmat->dt_ref_count, 1); 267 if (dmat->dt_ref_count == 0) { 268 free(dmat, M_DEVBUF); 269 /* 270 * Last reference count, so 271 * release our reference 272 * count on our parent. 273 */ 274 dmat = parent; 275 } else 276 dmat = NULL; 277 } 278 } 279 return (0); 280} 281 282/* 283 * Common function for DMA map creation. May be called by bus-specific 284 * DMA map creation functions. 285 */ 286static int 287nexus_dmamap_create(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, int flags, 288 bus_dmamap_t *mapp) 289{ 290 291 *mapp = malloc(sizeof(**mapp), M_DEVBUF, M_NOWAIT | M_ZERO); 292 if (*mapp != NULL) { 293 ddmat->dt_map_count++; 294 sparc64_dmamap_init(*mapp); 295 return (0); 296 } else 297 return (ENOMEM); 298} 299 300/* 301 * Common function for DMA map destruction. May be called by bus-specific 302 * DMA map destruction functions. 303 */ 304static int 305nexus_dmamap_destroy(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map) 306{ 307 308 free(map, M_DEVBUF); 309 ddmat->dt_map_count--; 310 return (0); 311} 312 313/* 314 * Utility function to load a linear buffer. lastaddrp holds state 315 * between invocations (for multiple-buffer loads). segp contains 316 * the starting segment on entrace, and the ending segment on exit. 317 * first indicates if this is the first invocation of this function. 318 */ 319static int 320_nexus_dmamap_load_buffer(bus_dma_tag_t ddmat, bus_dma_segment_t segs[], 321 void *buf, bus_size_t buflen, struct thread *td, int flags, 322 vm_offset_t *lastaddrp, int *segp, int first) 323{ 324 bus_size_t sgsize; 325 bus_addr_t curaddr, lastaddr, baddr, bmask; 326 vm_offset_t vaddr = (vm_offset_t)buf; 327 int seg; 328 pmap_t pmap; 329 330 if (td != NULL) 331 pmap = vmspace_pmap(td->td_proc->p_vmspace); 332 else 333 pmap = NULL; 334 335 lastaddr = *lastaddrp; 336 bmask = ~(ddmat->dt_boundary - 1); 337 338 for (seg = *segp; buflen > 0 ; ) { 339 /* 340 * Get the physical address for this segment. 341 */ 342 if (pmap) 343 curaddr = pmap_extract(pmap, vaddr); 344 else 345 curaddr = pmap_kextract(vaddr); 346 347 /* 348 * Compute the segment size, and adjust counts. 349 */ 350 sgsize = PAGE_SIZE - ((u_long)curaddr & PAGE_MASK); 351 if (buflen < sgsize) 352 sgsize = buflen; 353 354 /* 355 * Make sure we don't cross any boundaries. 356 */ 357 if (ddmat->dt_boundary > 0) { 358 baddr = (curaddr + ddmat->dt_boundary) & bmask; 359 if (sgsize > (baddr - curaddr)) 360 sgsize = (baddr - curaddr); 361 } 362 363 /* 364 * Insert chunk into a segment, coalescing with 365 * previous segment if possible. 366 */ 367 if (first) { 368 segs[seg].ds_addr = curaddr; 369 segs[seg].ds_len = sgsize; 370 first = 0; 371 } else { 372 if (curaddr == lastaddr && 373 (segs[seg].ds_len + sgsize) <= ddmat->dt_maxsegsz && 374 (ddmat->dt_boundary == 0 || 375 (segs[seg].ds_addr & bmask) == (curaddr & bmask))) 376 segs[seg].ds_len += sgsize; 377 else { 378 if (++seg >= ddmat->dt_nsegments) 379 break; 380 segs[seg].ds_addr = curaddr; 381 segs[seg].ds_len = sgsize; 382 } 383 } 384 385 lastaddr = curaddr + sgsize; 386 vaddr += sgsize; 387 buflen -= sgsize; 388 } 389 390 *segp = seg; 391 *lastaddrp = lastaddr; 392 393 /* 394 * Did we fit? 395 */ 396 return (buflen != 0 ? EFBIG : 0); /* XXX better return value here? */ 397} 398 399/* 400 * Common function for loading a DMA map with a linear buffer. May 401 * be called by bus-specific DMA map load functions. 402 * 403 * Most SPARCs have IOMMUs in the bus controllers. In those cases 404 * they only need one segment and will use virtual addresses for DVMA. 405 * Those bus controllers should intercept these vectors and should 406 * *NEVER* call nexus_dmamap_load() which is used only by devices that 407 * bypass DVMA. 408 */ 409static int 410nexus_dmamap_load(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map, 411 void *buf, bus_size_t buflen, bus_dmamap_callback_t *callback, 412 void *callback_arg, int flags) 413{ 414#ifdef __GNUC__ 415 bus_dma_segment_t dm_segments[ddmat->dt_nsegments]; 416#else 417 bus_dma_segment_t dm_segments[BUS_DMAMAP_NSEGS]; 418#endif 419 vm_offset_t lastaddr; 420 int error, nsegs; 421 422 error = _nexus_dmamap_load_buffer(ddmat, dm_segments, buf, buflen, 423 NULL, flags, &lastaddr, &nsegs, 1); 424 425 if (error == 0) { 426 (*callback)(callback_arg, dm_segments, nsegs + 1, 0); 427 map->dm_loaded = 1; 428 } else 429 (*callback)(callback_arg, NULL, 0, error); 430 431 return (0); 432} 433 434/* 435 * Like nexus_dmamap_load(), but for mbufs. 436 */ 437static int 438nexus_dmamap_load_mbuf(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, 439 bus_dmamap_t map, struct mbuf *m0, bus_dmamap_callback2_t *callback, 440 void *callback_arg, int flags) 441{ 442#ifdef __GNUC__ 443 bus_dma_segment_t dm_segments[ddmat->dt_nsegments]; 444#else 445 bus_dma_segment_t dm_segments[BUS_DMAMAP_NSEGS]; 446#endif 447 int nsegs, error; 448 449 KASSERT(m0->m_flags & M_PKTHDR, 450 ("nexus_dmamap_load_mbuf: no packet header")); 451 452 nsegs = 0; 453 error = 0; 454 if (m0->m_pkthdr.len <= ddmat->dt_maxsize) { 455 int first = 1; 456 vm_offset_t lastaddr = 0; 457 struct mbuf *m; 458 459 for (m = m0; m != NULL && error == 0; m = m->m_next) { 460 if (m->m_len > 0) { 461 error = _nexus_dmamap_load_buffer(ddmat, 462 dm_segments, m->m_data, m->m_len, NULL, 463 flags, &lastaddr, &nsegs, first); 464 first = 0; 465 } 466 } 467 } else { 468 error = EINVAL; 469 } 470 471 if (error) { 472 /* force "no valid mappings" in callback */ 473 (*callback)(callback_arg, dm_segments, 0, 0, error); 474 } else { 475 map->dm_loaded = 1; 476 (*callback)(callback_arg, dm_segments, nsegs + 1, 477 m0->m_pkthdr.len, error); 478 } 479 return (error); 480} 481 482/* 483 * Like nexus_dmamap_load(), but for uios. 484 */ 485static int 486nexus_dmamap_load_uio(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, 487 bus_dmamap_t map, struct uio *uio, bus_dmamap_callback2_t *callback, 488 void *callback_arg, int flags) 489{ 490 vm_offset_t lastaddr; 491#ifdef __GNUC__ 492 bus_dma_segment_t dm_segments[ddmat->dt_nsegments]; 493#else 494 bus_dma_segment_t dm_segments[BUS_DMAMAP_NSEGS]; 495#endif 496 int nsegs, error, first, i; 497 bus_size_t resid; 498 struct iovec *iov; 499 struct thread *td = NULL; 500 501 resid = uio->uio_resid; 502 iov = uio->uio_iov; 503 504 if (uio->uio_segflg == UIO_USERSPACE) { 505 td = uio->uio_td; 506 KASSERT(td != NULL, 507 ("nexus_dmamap_load_uio: USERSPACE but no proc")); 508 } 509 510 nsegs = 0; 511 error = 0; 512 first = 1; 513 for (i = 0; i < uio->uio_iovcnt && resid != 0 && !error; i++) { 514 /* 515 * Now at the first iovec to load. Load each iovec 516 * until we have exhausted the residual count. 517 */ 518 bus_size_t minlen = 519 resid < iov[i].iov_len ? resid : iov[i].iov_len; 520 caddr_t addr = (caddr_t) iov[i].iov_base; 521 522 if (minlen > 0) { 523 error = _nexus_dmamap_load_buffer(ddmat, dm_segments, 524 addr, minlen, td, flags, &lastaddr, &nsegs, first); 525 first = 0; 526 527 resid -= minlen; 528 } 529 } 530 531 if (error) { 532 /* force "no valid mappings" in callback */ 533 (*callback)(callback_arg, dm_segments, 0, 0, error); 534 } else { 535 map->dm_loaded = 1; 536 (*callback)(callback_arg, dm_segments, nsegs + 1, 537 uio->uio_resid, error); 538 } 539 return (error); 540} 541 542/* 543 * Common function for unloading a DMA map. May be called by 544 * bus-specific DMA map unload functions. 545 */ 546static void 547nexus_dmamap_unload(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map) 548{ 549 550 map->dm_loaded = 0; 551} 552 553/* 554 * Common function for DMA map synchronization. May be called 555 * by bus-specific DMA map synchronization functions. 556 */ 557static void 558nexus_dmamap_sync(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map, 559 bus_dmasync_op_t op) 560{ 561 562 /* 563 * We sync out our caches, but the bus must do the same. 564 * 565 * Actually a #Sync is expensive. We should optimize. 566 */ 567 if ((op == BUS_DMASYNC_PREREAD) || (op == BUS_DMASYNC_PREWRITE)) { 568 /* 569 * Don't really need to do anything, but flush any pending 570 * writes anyway. 571 */ 572 membar(Sync); 573 } 574#if 0 575 /* Should not be needed. */ 576 if (op == BUS_DMASYNC_POSTREAD) { 577 ecache_flush((vm_offset_t)map->buf, 578 (vm_offset_t)map->buf + map->buflen - 1); 579 } 580#endif 581 if (op == BUS_DMASYNC_POSTWRITE) { 582 /* Nothing to do. Handled by the bus controller. */ 583 } 584} 585 586/* 587 * Helper functions for buses that use their private dmamem_alloc/dmamem_free 588 * versions. 589 * These differ from the dmamap_alloc() functions in that they create a tag 590 * that is specifically for use with dmamem_alloc'ed memory. 591 * These are primitive now, but I expect that some fields of the map will need 592 * to be filled soon. 593 */ 594int 595sparc64_dmamem_alloc_map(bus_dma_tag_t dmat, bus_dmamap_t *mapp) 596{ 597 598 *mapp = malloc(sizeof(**mapp), M_DEVBUF, M_NOWAIT | M_ZERO); 599 if (*mapp == NULL) 600 return (ENOMEM); 601 602 dmat->dt_map_count++; 603 sparc64_dmamap_init(*mapp); 604 return (0); 605} 606 607void 608sparc64_dmamem_free_map(bus_dma_tag_t dmat, bus_dmamap_t map) 609{ 610 611 free(map, M_DEVBUF); 612 dmat->dt_map_count--; 613} 614 615/* 616 * Common function for DMA-safe memory allocation. May be called 617 * by bus-specific DMA memory allocation functions. 618 */ 619static int 620nexus_dmamem_alloc_size(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, void **vaddr, 621 int flags, bus_dmamap_t *mapp, bus_size_t size) 622{ 623 624 if (size > ddmat->dt_maxsize) 625 return (ENOMEM); 626 627 if ((size <= PAGE_SIZE)) { 628 *vaddr = malloc(size, M_DEVBUF, 629 (flags & BUS_DMA_NOWAIT) ? M_NOWAIT : M_WAITOK); 630 } else { 631 /* 632 * XXX: Use contigmalloc until it is merged into this facility 633 * and handles multi-seg allocations. Nobody is doing multi-seg 634 * allocations yet though. 635 */ 636 mtx_lock(&Giant); 637 *vaddr = contigmalloc(size, M_DEVBUF, 638 (flags & BUS_DMA_NOWAIT) ? M_NOWAIT : M_WAITOK, 639 0ul, ddmat->dt_lowaddr, 640 ddmat->dt_alignment ? ddmat->dt_alignment : 1UL, 641 ddmat->dt_boundary); 642 mtx_unlock(&Giant); 643 } 644 if (*vaddr == NULL) { 645 free(*mapp, M_DEVBUF); 646 return (ENOMEM); 647 } 648 return (0); 649} 650 651static int 652nexus_dmamem_alloc(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, void **vaddr, 653 int flags, bus_dmamap_t *mapp) 654{ 655 return (sparc64_dmamem_alloc_size(pdmat, ddmat, vaddr, flags, mapp, 656 ddmat->dt_maxsize)); 657} 658 659/* 660 * Common function for freeing DMA-safe memory. May be called by 661 * bus-specific DMA memory free functions. 662 */ 663static void 664nexus_dmamem_free_size(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, void *vaddr, 665 bus_dmamap_t map, bus_size_t size) 666{ 667 668 sparc64_dmamem_free_map(ddmat, map); 669 if ((size <= PAGE_SIZE)) 670 free(vaddr, M_DEVBUF); 671 else { 672 mtx_lock(&Giant); 673 contigfree(vaddr, size, M_DEVBUF); 674 mtx_unlock(&Giant); 675 } 676} 677 678static void 679nexus_dmamem_free(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, void *vaddr, 680 bus_dmamap_t map) 681{ 682 sparc64_dmamem_free_size(pdmat, ddmat, vaddr, map, ddmat->dt_maxsize); 683} 684 685struct bus_dma_tag nexus_dmatag = { 686 NULL, 687 NULL, 688 8, 689 0, 690 0, 691 0x3ffffffff, 692 NULL, /* XXX */ 693 NULL, 694 0x3ffffffff, /* XXX */ 695 0xff, /* XXX */ 696 0xffffffff, /* XXX */ 697 0, 698 0, 699 0, 700 nexus_dmamap_create, 701 nexus_dmamap_destroy, 702 nexus_dmamap_load, 703 nexus_dmamap_load_mbuf, 704 nexus_dmamap_load_uio, 705 nexus_dmamap_unload, 706 nexus_dmamap_sync, 707 708 nexus_dmamem_alloc_size, 709 nexus_dmamem_alloc, 710 nexus_dmamem_free_size, 711 nexus_dmamem_free, 712}; 713 714/* 715 * Helpers to map/unmap bus memory 716 */ 717int 718sparc64_bus_mem_map(bus_space_tag_t tag, bus_space_handle_t handle, 719 bus_size_t size, int flags, vm_offset_t vaddr, void **hp) 720{ 721 vm_offset_t addr; 722 vm_offset_t sva; 723 vm_offset_t va; 724 vm_offset_t pa; 725 vm_size_t vsz; 726 u_long pm_flags; 727 728 addr = (vm_offset_t)handle; 729 size = round_page(size); 730 if (size == 0) { 731 printf("sparc64_bus_map: zero size\n"); 732 return (EINVAL); 733 } 734 switch (tag->bst_type) { 735 case PCI_CONFIG_BUS_SPACE: 736 case PCI_IO_BUS_SPACE: 737 case PCI_MEMORY_BUS_SPACE: 738 pm_flags = TD_IE; 739 break; 740 default: 741 pm_flags = 0; 742 break; 743 } 744 745 if (!(flags & BUS_SPACE_MAP_CACHEABLE)) 746 pm_flags |= TD_E; 747 748 if (vaddr != NULL) 749 sva = trunc_page(vaddr); 750 else { 751 if ((sva = kmem_alloc_nofault(kernel_map, size)) == NULL) 752 panic("sparc64_bus_map: cannot allocate virtual " 753 "memory"); 754 } 755 756 /* Preserve page offset. */ 757 *hp = (void *)(sva | ((u_long)addr & PAGE_MASK)); 758 759 pa = trunc_page(addr); 760 if ((flags & BUS_SPACE_MAP_READONLY) == 0) 761 pm_flags |= TD_W; 762 763 va = sva; 764 vsz = size; 765 do { 766 pmap_kenter_flags(va, pa, pm_flags); 767 va += PAGE_SIZE; 768 pa += PAGE_SIZE; 769 } while ((vsz -= PAGE_SIZE) > 0); 770 tlb_range_demap(kernel_pmap, sva, sva + size - 1); 771 return (0); 772} 773 774int 775sparc64_bus_mem_unmap(void *bh, bus_size_t size) 776{ 777 vm_offset_t sva; 778 vm_offset_t va; 779 vm_offset_t endva; 780 781 sva = trunc_page((vm_offset_t)bh); 782 endva = sva + round_page(size); 783 for (va = sva; va < endva; va += PAGE_SIZE) 784 pmap_kremove_flags(va); 785 tlb_range_demap(kernel_pmap, sva, sva + size - 1); 786 kmem_free(kernel_map, sva, size); 787 return (0); 788} 789 790/* 791 * Fake up a bus tag, for use by console drivers in early boot when the regular 792 * means to allocate resources are not yet available. 793 * Note that these tags are not eligible for bus_space_barrier operations. 794 * Addr is the physical address of the desired start of the handle. 795 */ 796bus_space_handle_t 797sparc64_fake_bustag(int space, bus_addr_t addr, struct bus_space_tag *ptag) 798{ 799 800 ptag->bst_cookie = NULL; 801 ptag->bst_parent = NULL; 802 ptag->bst_type = space; 803 ptag->bst_bus_barrier = NULL; 804 return (addr); 805} 806 807/* 808 * Base bus space handlers. 809 */ 810static void nexus_bus_barrier(bus_space_tag_t, bus_space_handle_t, 811 bus_size_t, bus_size_t, int); 812 813static void 814nexus_bus_barrier(bus_space_tag_t t, bus_space_handle_t h, bus_size_t offset, 815 bus_size_t size, int flags) 816{ 817 818 /* 819 * We have lots of alternatives depending on whether we're 820 * synchronizing loads with loads, loads with stores, stores 821 * with loads, or stores with stores. The only ones that seem 822 * generic are #Sync and #MemIssue. I'll use #Sync for safety. 823 */ 824 switch(flags) { 825 case BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE: 826 case BUS_SPACE_BARRIER_READ: 827 case BUS_SPACE_BARRIER_WRITE: 828 membar(Sync); 829 break; 830 default: 831 panic("sparc64_bus_barrier: unknown flags"); 832 } 833 return; 834} 835 836struct bus_space_tag nexus_bustag = { 837 NULL, /* cookie */ 838 NULL, /* parent bus tag */ 839 UPA_BUS_SPACE, /* type */ 840 nexus_bus_barrier, /* bus_space_barrier */ 841}; 842