bus_machdep.c revision 112215
1/*- 2 * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 7 * NASA Ames Research Center. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. Neither the name of The NetBSD Foundation nor the names of its 22 * contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37/* 38 * Copyright (c) 1992, 1993 39 * The Regents of the University of California. All rights reserved. 40 * 41 * This software was developed by the Computer Systems Engineering group 42 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 43 * contributed to Berkeley. 44 * 45 * All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by the University of 48 * California, Lawrence Berkeley Laboratory. 49 * 50 * Redistribution and use in source and binary forms, with or without 51 * modification, are permitted provided that the following conditions 52 * are met: 53 * 1. Redistributions of source code must retain the above copyright 54 * notice, this list of conditions and the following disclaimer. 55 * 2. Redistributions in binary form must reproduce the above copyright 56 * notice, this list of conditions and the following disclaimer in the 57 * documentation and/or other materials provided with the distribution. 58 * 3. All advertising materials mentioning features or use of this software 59 * must display the following acknowledgement: 60 * This product includes software developed by the University of 61 * California, Berkeley and its contributors. 62 * 4. Neither the name of the University nor the names of its contributors 63 * may be used to endorse or promote products derived from this software 64 * without specific prior written permission. 65 * 66 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 67 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 68 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 69 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 70 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 71 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 72 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 73 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 74 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 75 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 76 * SUCH DAMAGE. 77 */ 78/* 79 * Copyright (c) 1997, 1998 Justin T. Gibbs. 80 * All rights reserved. 81 * Copyright 2001 by Thomas Moestl <tmm@FreeBSD.org>. All rights reserved. 82 * 83 * Redistribution and use in source and binary forms, with or without 84 * modification, are permitted provided that the following conditions 85 * are met: 86 * 1. Redistributions of source code must retain the above copyright 87 * notice, this list of conditions, and the following disclaimer, 88 * without modification, immediately at the beginning of the file. 89 * 2. The name of the author may not be used to endorse or promote products 90 * derived from this software without specific prior written permission. 91 * 92 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 93 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 94 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 95 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 96 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 97 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 98 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 99 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 100 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 101 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 102 * SUCH DAMAGE. 103 * 104 * from: @(#)machdep.c 8.6 (Berkeley) 1/14/94 105 * from: NetBSD: machdep.c,v 1.111 2001/09/15 07:13:40 eeh Exp 106 * and 107 * from: FreeBSD: src/sys/i386/i386/busdma_machdep.c,v 1.24 2001/08/15 108 * 109 * $FreeBSD: head/sys/sparc64/sparc64/bus_machdep.c 112215 2003-03-14 00:04:37Z mux $ 110 */ 111 112#include <sys/param.h> 113#include <sys/bus.h> 114#include <sys/malloc.h> 115#include <sys/mbuf.h> 116#include <sys/mutex.h> 117#include <sys/proc.h> 118#include <sys/smp.h> 119#include <sys/systm.h> 120#include <sys/uio.h> 121 122#include <vm/vm.h> 123#include <vm/vm_extern.h> 124#include <vm/vm_kern.h> 125#include <vm/vm_page.h> 126#include <vm/vm_param.h> 127#include <vm/vm_map.h> 128 129#include <machine/asi.h> 130#include <machine/bus.h> 131#include <machine/bus_private.h> 132#include <machine/cache.h> 133#include <machine/smp.h> 134#include <machine/tlb.h> 135 136/* ASI's for bus access. */ 137int bus_type_asi[] = { 138 ASI_PHYS_BYPASS_EC_WITH_EBIT, /* UPA */ 139 ASI_PHYS_BYPASS_EC_WITH_EBIT, /* SBUS */ 140 ASI_PHYS_BYPASS_EC_WITH_EBIT_L, /* PCI configuration space */ 141 ASI_PHYS_BYPASS_EC_WITH_EBIT_L, /* PCI memory space */ 142 ASI_PHYS_BYPASS_EC_WITH_EBIT_L, /* PCI I/O space */ 143 0 144}; 145 146int bus_stream_asi[] = { 147 ASI_PHYS_BYPASS_EC_WITH_EBIT, /* UPA */ 148 ASI_PHYS_BYPASS_EC_WITH_EBIT, /* SBUS */ 149 ASI_PHYS_BYPASS_EC_WITH_EBIT, /* PCI configuration space */ 150 ASI_PHYS_BYPASS_EC_WITH_EBIT, /* PCI memory space */ 151 ASI_PHYS_BYPASS_EC_WITH_EBIT, /* PCI I/O space */ 152 0 153}; 154 155/* 156 * busdma support code. 157 * Note: there is no support for bounce buffers yet. 158 */ 159 160static int nexus_dmamap_create(bus_dma_tag_t, bus_dma_tag_t, int, 161 bus_dmamap_t *); 162static int nexus_dmamap_destroy(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 163static int nexus_dmamap_load(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 164 void *, bus_size_t, bus_dmamap_callback_t *, void *, int); 165static int nexus_dmamap_load_mbuf(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 166 struct mbuf *, bus_dmamap_callback2_t *, void *, int); 167static int nexus_dmamap_load_uio(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 168 struct uio *, bus_dmamap_callback2_t *, void *, int); 169static void nexus_dmamap_unload(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 170static void nexus_dmamap_sync(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 171 bus_dmasync_op_t); 172static int nexus_dmamem_alloc_size(bus_dma_tag_t, bus_dma_tag_t, void **, int, 173 bus_dmamap_t *, u_long size); 174static int nexus_dmamem_alloc(bus_dma_tag_t, bus_dma_tag_t, void **, int, 175 bus_dmamap_t *); 176static void nexus_dmamem_free_size(bus_dma_tag_t, bus_dma_tag_t, void *, 177 bus_dmamap_t, u_long size); 178static void nexus_dmamem_free(bus_dma_tag_t, bus_dma_tag_t, void *, 179 bus_dmamap_t); 180 181/* 182 * Since there is now way for a device to obtain a dma tag from its parent 183 * we use this kluge to handle different the different supported bus systems. 184 * The sparc64_root_dma_tag is used as parent for tags that have none, so that 185 * the correct methods will be used. 186 */ 187bus_dma_tag_t sparc64_root_dma_tag; 188 189/* 190 * Allocate a device specific dma_tag. 191 */ 192int 193bus_dma_tag_create(bus_dma_tag_t parent, bus_size_t alignment, 194 bus_size_t boundary, bus_addr_t lowaddr, bus_addr_t highaddr, 195 bus_dma_filter_t *filter, void *filterarg, bus_size_t maxsize, 196 int nsegments, bus_size_t maxsegsz, int flags, bus_dma_tag_t *dmat) 197{ 198 199 bus_dma_tag_t newtag; 200 201 /* Return a NULL tag on failure */ 202 *dmat = NULL; 203 204 newtag = (bus_dma_tag_t)malloc(sizeof(*newtag), M_DEVBUF, M_NOWAIT); 205 if (newtag == NULL) 206 return (ENOMEM); 207 208 newtag->dt_parent = parent != NULL ? parent : sparc64_root_dma_tag; 209 newtag->dt_alignment = alignment; 210 newtag->dt_boundary = boundary; 211 newtag->dt_lowaddr = trunc_page((vm_offset_t)lowaddr) + (PAGE_SIZE - 1); 212 newtag->dt_highaddr = trunc_page((vm_offset_t)highaddr) + 213 (PAGE_SIZE - 1); 214 newtag->dt_filter = filter; 215 newtag->dt_filterarg = filterarg; 216 newtag->dt_maxsize = maxsize; 217 newtag->dt_nsegments = nsegments; 218 newtag->dt_maxsegsz = maxsegsz; 219 newtag->dt_flags = flags; 220 newtag->dt_ref_count = 1; /* Count ourselves */ 221 newtag->dt_map_count = 0; 222 223 newtag->dt_dmamap_create = NULL; 224 newtag->dt_dmamap_destroy = NULL; 225 newtag->dt_dmamap_load = NULL; 226 newtag->dt_dmamap_load_mbuf = NULL; 227 newtag->dt_dmamap_load_uio = NULL; 228 newtag->dt_dmamap_unload = NULL; 229 newtag->dt_dmamap_sync = NULL; 230 newtag->dt_dmamem_alloc_size = NULL; 231 newtag->dt_dmamem_alloc = NULL; 232 newtag->dt_dmamem_free_size = NULL; 233 newtag->dt_dmamem_free = NULL; 234 235 /* Take into account any restrictions imposed by our parent tag */ 236 if (parent != NULL) { 237 newtag->dt_lowaddr = ulmin(parent->dt_lowaddr, 238 newtag->dt_lowaddr); 239 newtag->dt_highaddr = ulmax(parent->dt_highaddr, 240 newtag->dt_highaddr); 241 /* 242 * XXX Not really correct??? Probably need to honor boundary 243 * all the way up the inheritence chain. 244 */ 245 newtag->dt_boundary = ulmin(parent->dt_boundary, 246 newtag->dt_boundary); 247 } 248 newtag->dt_parent->dt_ref_count++; 249 250 *dmat = newtag; 251 return (0); 252} 253 254int 255bus_dma_tag_destroy(bus_dma_tag_t dmat) 256{ 257 bus_dma_tag_t parent; 258 259 if (dmat != NULL) { 260 if (dmat->dt_map_count != 0) 261 return (EBUSY); 262 while (dmat != NULL) { 263 parent = dmat->dt_parent; 264 dmat->dt_ref_count--; 265 if (dmat->dt_ref_count == 0) { 266 free(dmat, M_DEVBUF); 267 /* 268 * Last reference count, so 269 * release our reference 270 * count on our parent. 271 */ 272 dmat = parent; 273 } else 274 dmat = NULL; 275 } 276 } 277 return (0); 278} 279 280/* 281 * Common function for DMA map creation. May be called by bus-specific 282 * DMA map creation functions. 283 */ 284static int 285nexus_dmamap_create(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, int flags, 286 bus_dmamap_t *mapp) 287{ 288 289 *mapp = malloc(sizeof(**mapp), M_DEVBUF, M_NOWAIT | M_ZERO); 290 if (*mapp != NULL) { 291 ddmat->dt_map_count++; 292 sparc64_dmamap_init(*mapp); 293 return (0); 294 } else 295 return (ENOMEM); 296} 297 298/* 299 * Common function for DMA map destruction. May be called by bus-specific 300 * DMA map destruction functions. 301 */ 302static int 303nexus_dmamap_destroy(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map) 304{ 305 306 free(map, M_DEVBUF); 307 ddmat->dt_map_count--; 308 return (0); 309} 310 311/* 312 * Utility function to load a linear buffer. lastaddrp holds state 313 * between invocations (for multiple-buffer loads). segp contains 314 * the starting segment on entrace, and the ending segment on exit. 315 * first indicates if this is the first invocation of this function. 316 */ 317static int 318_nexus_dmamap_load_buffer(bus_dma_tag_t ddmat, bus_dma_segment_t segs[], 319 void *buf, bus_size_t buflen, struct thread *td, int flags, 320 vm_offset_t *lastaddrp, int *segp, int first) 321{ 322 bus_size_t sgsize; 323 bus_addr_t curaddr, lastaddr, baddr, bmask; 324 vm_offset_t vaddr = (vm_offset_t)buf; 325 int seg; 326 pmap_t pmap; 327 328 if (td != NULL) 329 pmap = vmspace_pmap(td->td_proc->p_vmspace); 330 else 331 pmap = NULL; 332 333 lastaddr = *lastaddrp; 334 bmask = ~(ddmat->dt_boundary - 1); 335 336 for (seg = *segp; buflen > 0 ; ) { 337 /* 338 * Get the physical address for this segment. 339 */ 340 if (pmap) 341 curaddr = pmap_extract(pmap, vaddr); 342 else 343 curaddr = pmap_kextract(vaddr); 344 345 /* 346 * Compute the segment size, and adjust counts. 347 */ 348 sgsize = PAGE_SIZE - ((u_long)curaddr & PAGE_MASK); 349 if (buflen < sgsize) 350 sgsize = buflen; 351 352 /* 353 * Make sure we don't cross any boundaries. 354 */ 355 if (ddmat->dt_boundary > 0) { 356 baddr = (curaddr + ddmat->dt_boundary) & bmask; 357 if (sgsize > (baddr - curaddr)) 358 sgsize = (baddr - curaddr); 359 } 360 361 /* 362 * Insert chunk into a segment, coalescing with 363 * previous segment if possible. 364 */ 365 if (first) { 366 segs[seg].ds_addr = curaddr; 367 segs[seg].ds_len = sgsize; 368 first = 0; 369 } else { 370 if (curaddr == lastaddr && 371 (segs[seg].ds_len + sgsize) <= ddmat->dt_maxsegsz && 372 (ddmat->dt_boundary == 0 || 373 (segs[seg].ds_addr & bmask) == (curaddr & bmask))) 374 segs[seg].ds_len += sgsize; 375 else { 376 if (++seg >= ddmat->dt_nsegments) 377 break; 378 segs[seg].ds_addr = curaddr; 379 segs[seg].ds_len = sgsize; 380 } 381 } 382 383 lastaddr = curaddr + sgsize; 384 vaddr += sgsize; 385 buflen -= sgsize; 386 } 387 388 *segp = seg; 389 *lastaddrp = lastaddr; 390 391 /* 392 * Did we fit? 393 */ 394 return (buflen != 0 ? EFBIG : 0); /* XXX better return value here? */ 395} 396 397/* 398 * Common function for loading a DMA map with a linear buffer. May 399 * be called by bus-specific DMA map load functions. 400 * 401 * Most SPARCs have IOMMUs in the bus controllers. In those cases 402 * they only need one segment and will use virtual addresses for DVMA. 403 * Those bus controllers should intercept these vectors and should 404 * *NEVER* call nexus_dmamap_load() which is used only by devices that 405 * bypass DVMA. 406 */ 407static int 408nexus_dmamap_load(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map, 409 void *buf, bus_size_t buflen, bus_dmamap_callback_t *callback, 410 void *callback_arg, int flags) 411{ 412#ifdef __GNUC__ 413 bus_dma_segment_t dm_segments[ddmat->dt_nsegments]; 414#else 415 bus_dma_segment_t dm_segments[BUS_DMAMAP_NSEGS]; 416#endif 417 vm_offset_t lastaddr; 418 int error, nsegs; 419 420 error = _nexus_dmamap_load_buffer(ddmat, dm_segments, buf, buflen, 421 NULL, flags, &lastaddr, &nsegs, 1); 422 423 if (error == 0) { 424 (*callback)(callback_arg, dm_segments, nsegs + 1, 0); 425 map->dm_loaded = 1; 426 } else 427 (*callback)(callback_arg, NULL, 0, error); 428 429 return (0); 430} 431 432/* 433 * Like nexus_dmamap_load(), but for mbufs. 434 */ 435static int 436nexus_dmamap_load_mbuf(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, 437 bus_dmamap_t map, struct mbuf *m0, bus_dmamap_callback2_t *callback, 438 void *callback_arg, int flags) 439{ 440#ifdef __GNUC__ 441 bus_dma_segment_t dm_segments[ddmat->dt_nsegments]; 442#else 443 bus_dma_segment_t dm_segments[BUS_DMAMAP_NSEGS]; 444#endif 445 int nsegs, error; 446 447 KASSERT(m0->m_flags & M_PKTHDR, 448 ("nexus_dmamap_load_mbuf: no packet header")); 449 450 nsegs = 0; 451 error = 0; 452 if (m0->m_pkthdr.len <= ddmat->dt_maxsize) { 453 int first = 1; 454 vm_offset_t lastaddr = 0; 455 struct mbuf *m; 456 457 for (m = m0; m != NULL && error == 0; m = m->m_next) { 458 if (m->m_len > 0) { 459 error = _nexus_dmamap_load_buffer(ddmat, 460 dm_segments, m->m_data, m->m_len, NULL, 461 flags, &lastaddr, &nsegs, first); 462 first = 0; 463 } 464 } 465 } else { 466 error = EINVAL; 467 } 468 469 if (error) { 470 /* force "no valid mappings" in callback */ 471 (*callback)(callback_arg, dm_segments, 0, 0, error); 472 } else { 473 map->dm_loaded = 1; 474 (*callback)(callback_arg, dm_segments, nsegs + 1, 475 m0->m_pkthdr.len, error); 476 } 477 return (error); 478} 479 480/* 481 * Like nexus_dmamap_load(), but for uios. 482 */ 483static int 484nexus_dmamap_load_uio(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, 485 bus_dmamap_t map, struct uio *uio, bus_dmamap_callback2_t *callback, 486 void *callback_arg, int flags) 487{ 488 vm_offset_t lastaddr; 489#ifdef __GNUC__ 490 bus_dma_segment_t dm_segments[ddmat->dt_nsegments]; 491#else 492 bus_dma_segment_t dm_segments[BUS_DMAMAP_NSEGS]; 493#endif 494 int nsegs, error, first, i; 495 bus_size_t resid; 496 struct iovec *iov; 497 struct thread *td = NULL; 498 499 resid = uio->uio_resid; 500 iov = uio->uio_iov; 501 502 if (uio->uio_segflg == UIO_USERSPACE) { 503 td = uio->uio_td; 504 KASSERT(td != NULL, 505 ("nexus_dmamap_load_uio: USERSPACE but no proc")); 506 } 507 508 nsegs = 0; 509 error = 0; 510 first = 1; 511 for (i = 0; i < uio->uio_iovcnt && resid != 0 && !error; i++) { 512 /* 513 * Now at the first iovec to load. Load each iovec 514 * until we have exhausted the residual count. 515 */ 516 bus_size_t minlen = 517 resid < iov[i].iov_len ? resid : iov[i].iov_len; 518 caddr_t addr = (caddr_t) iov[i].iov_base; 519 520 if (minlen > 0) { 521 error = _nexus_dmamap_load_buffer(ddmat, dm_segments, 522 addr, minlen, td, flags, &lastaddr, &nsegs, first); 523 first = 0; 524 525 resid -= minlen; 526 } 527 } 528 529 if (error) { 530 /* force "no valid mappings" in callback */ 531 (*callback)(callback_arg, dm_segments, 0, 0, error); 532 } else { 533 map->dm_loaded = 1; 534 (*callback)(callback_arg, dm_segments, nsegs + 1, 535 uio->uio_resid, error); 536 } 537 return (error); 538} 539 540/* 541 * Common function for unloading a DMA map. May be called by 542 * bus-specific DMA map unload functions. 543 */ 544static void 545nexus_dmamap_unload(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map) 546{ 547 548 map->dm_loaded = 0; 549} 550 551/* 552 * Common function for DMA map synchronization. May be called 553 * by bus-specific DMA map synchronization functions. 554 */ 555static void 556nexus_dmamap_sync(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map, 557 bus_dmasync_op_t op) 558{ 559 560 /* 561 * We sync out our caches, but the bus must do the same. 562 * 563 * Actually a #Sync is expensive. We should optimize. 564 */ 565 if ((op == BUS_DMASYNC_PREREAD) || (op == BUS_DMASYNC_PREWRITE)) { 566 /* 567 * Don't really need to do anything, but flush any pending 568 * writes anyway. 569 */ 570 membar(Sync); 571 } 572#if 0 573 /* Should not be needed. */ 574 if (op == BUS_DMASYNC_POSTREAD) { 575 ecache_flush((vm_offset_t)map->buf, 576 (vm_offset_t)map->buf + map->buflen - 1); 577 } 578#endif 579 if (op == BUS_DMASYNC_POSTWRITE) { 580 /* Nothing to do. Handled by the bus controller. */ 581 } 582} 583 584/* 585 * Helper functions for buses that use their private dmamem_alloc/dmamem_free 586 * versions. 587 * These differ from the dmamap_alloc() functions in that they create a tag 588 * that is specifically for use with dmamem_alloc'ed memory. 589 * These are primitive now, but I expect that some fields of the map will need 590 * to be filled soon. 591 */ 592int 593sparc64_dmamem_alloc_map(bus_dma_tag_t dmat, bus_dmamap_t *mapp) 594{ 595 596 *mapp = malloc(sizeof(**mapp), M_DEVBUF, M_NOWAIT | M_ZERO); 597 if (*mapp == NULL) 598 return (ENOMEM); 599 600 dmat->dt_map_count++; 601 sparc64_dmamap_init(*mapp); 602 return (0); 603} 604 605void 606sparc64_dmamem_free_map(bus_dma_tag_t dmat, bus_dmamap_t map) 607{ 608 609 free(map, M_DEVBUF); 610 dmat->dt_map_count--; 611} 612 613/* 614 * Common function for DMA-safe memory allocation. May be called 615 * by bus-specific DMA memory allocation functions. 616 */ 617static int 618nexus_dmamem_alloc_size(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, void **vaddr, 619 int flags, bus_dmamap_t *mapp, bus_size_t size) 620{ 621 622 if (size > ddmat->dt_maxsize) 623 return (ENOMEM); 624 625 if ((size <= PAGE_SIZE)) { 626 *vaddr = malloc(size, M_DEVBUF, 627 (flags & BUS_DMA_NOWAIT) ? M_NOWAIT : M_WAITOK); 628 } else { 629 /* 630 * XXX: Use contigmalloc until it is merged into this facility 631 * and handles multi-seg allocations. Nobody is doing multi-seg 632 * allocations yet though. 633 */ 634 mtx_lock(&Giant); 635 *vaddr = contigmalloc(size, M_DEVBUF, 636 (flags & BUS_DMA_NOWAIT) ? M_NOWAIT : M_WAITOK, 637 0ul, ddmat->dt_lowaddr, 638 ddmat->dt_alignment ? ddmat->dt_alignment : 1UL, 639 ddmat->dt_boundary); 640 mtx_unlock(&Giant); 641 } 642 if (*vaddr == NULL) { 643 free(*mapp, M_DEVBUF); 644 return (ENOMEM); 645 } 646 return (0); 647} 648 649static int 650nexus_dmamem_alloc(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, void **vaddr, 651 int flags, bus_dmamap_t *mapp) 652{ 653 return (sparc64_dmamem_alloc_size(pdmat, ddmat, vaddr, flags, mapp, 654 ddmat->dt_maxsize)); 655} 656 657/* 658 * Common function for freeing DMA-safe memory. May be called by 659 * bus-specific DMA memory free functions. 660 */ 661static void 662nexus_dmamem_free_size(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, void *vaddr, 663 bus_dmamap_t map, bus_size_t size) 664{ 665 666 sparc64_dmamem_free_map(ddmat, map); 667 if ((size <= PAGE_SIZE)) 668 free(vaddr, M_DEVBUF); 669 else { 670 mtx_lock(&Giant); 671 contigfree(vaddr, size, M_DEVBUF); 672 mtx_unlock(&Giant); 673 } 674} 675 676static void 677nexus_dmamem_free(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, void *vaddr, 678 bus_dmamap_t map) 679{ 680 sparc64_dmamem_free_size(pdmat, ddmat, vaddr, map, ddmat->dt_maxsize); 681} 682 683struct bus_dma_tag nexus_dmatag = { 684 NULL, 685 NULL, 686 8, 687 0, 688 0, 689 0x3ffffffff, 690 NULL, /* XXX */ 691 NULL, 692 0x3ffffffff, /* XXX */ 693 0xff, /* XXX */ 694 0xffffffff, /* XXX */ 695 0, 696 0, 697 0, 698 nexus_dmamap_create, 699 nexus_dmamap_destroy, 700 nexus_dmamap_load, 701 nexus_dmamap_load_mbuf, 702 nexus_dmamap_load_uio, 703 nexus_dmamap_unload, 704 nexus_dmamap_sync, 705 706 nexus_dmamem_alloc_size, 707 nexus_dmamem_alloc, 708 nexus_dmamem_free_size, 709 nexus_dmamem_free, 710}; 711 712/* 713 * Helpers to map/unmap bus memory 714 */ 715int 716sparc64_bus_mem_map(bus_space_tag_t tag, bus_space_handle_t handle, 717 bus_size_t size, int flags, vm_offset_t vaddr, void **hp) 718{ 719 vm_offset_t addr; 720 vm_offset_t sva; 721 vm_offset_t va; 722 vm_offset_t pa; 723 vm_size_t vsz; 724 u_long pm_flags; 725 726 addr = (vm_offset_t)handle; 727 size = round_page(size); 728 if (size == 0) { 729 printf("sparc64_bus_map: zero size\n"); 730 return (EINVAL); 731 } 732 switch (tag->bst_type) { 733 case PCI_CONFIG_BUS_SPACE: 734 case PCI_IO_BUS_SPACE: 735 case PCI_MEMORY_BUS_SPACE: 736 pm_flags = TD_IE; 737 break; 738 default: 739 pm_flags = 0; 740 break; 741 } 742 743 if (!(flags & BUS_SPACE_MAP_CACHEABLE)) 744 pm_flags |= TD_E; 745 746 if (vaddr != NULL) 747 sva = trunc_page(vaddr); 748 else { 749 if ((sva = kmem_alloc_nofault(kernel_map, size)) == NULL) 750 panic("sparc64_bus_map: cannot allocate virtual " 751 "memory"); 752 } 753 754 /* Preserve page offset. */ 755 *hp = (void *)(sva | ((u_long)addr & PAGE_MASK)); 756 757 pa = trunc_page(addr); 758 if ((flags & BUS_SPACE_MAP_READONLY) == 0) 759 pm_flags |= TD_W; 760 761 va = sva; 762 vsz = size; 763 do { 764 pmap_kenter_flags(va, pa, pm_flags); 765 va += PAGE_SIZE; 766 pa += PAGE_SIZE; 767 } while ((vsz -= PAGE_SIZE) > 0); 768 tlb_range_demap(kernel_pmap, sva, sva + size - 1); 769 return (0); 770} 771 772int 773sparc64_bus_mem_unmap(void *bh, bus_size_t size) 774{ 775 vm_offset_t sva; 776 vm_offset_t va; 777 vm_offset_t endva; 778 779 sva = trunc_page((vm_offset_t)bh); 780 endva = sva + round_page(size); 781 for (va = sva; va < endva; va += PAGE_SIZE) 782 pmap_kremove_flags(va); 783 tlb_range_demap(kernel_pmap, sva, sva + size - 1); 784 kmem_free(kernel_map, sva, size); 785 return (0); 786} 787 788/* 789 * Fake up a bus tag, for use by console drivers in early boot when the regular 790 * means to allocate resources are not yet available. 791 * Note that these tags are not eligible for bus_space_barrier operations. 792 * Addr is the physical address of the desired start of the handle. 793 */ 794bus_space_handle_t 795sparc64_fake_bustag(int space, bus_addr_t addr, struct bus_space_tag *ptag) 796{ 797 798 ptag->bst_cookie = NULL; 799 ptag->bst_parent = NULL; 800 ptag->bst_type = space; 801 ptag->bst_bus_barrier = NULL; 802 return (addr); 803} 804 805/* 806 * Base bus space handlers. 807 */ 808static void nexus_bus_barrier(bus_space_tag_t, bus_space_handle_t, 809 bus_size_t, bus_size_t, int); 810 811static void 812nexus_bus_barrier(bus_space_tag_t t, bus_space_handle_t h, bus_size_t offset, 813 bus_size_t size, int flags) 814{ 815 816 /* 817 * We have lots of alternatives depending on whether we're 818 * synchronizing loads with loads, loads with stores, stores 819 * with loads, or stores with stores. The only ones that seem 820 * generic are #Sync and #MemIssue. I'll use #Sync for safety. 821 */ 822 switch(flags) { 823 case BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE: 824 case BUS_SPACE_BARRIER_READ: 825 case BUS_SPACE_BARRIER_WRITE: 826 membar(Sync); 827 break; 828 default: 829 panic("sparc64_bus_barrier: unknown flags"); 830 } 831 return; 832} 833 834struct bus_space_tag nexus_bustag = { 835 NULL, /* cookie */ 836 NULL, /* parent bus tag */ 837 UPA_BUS_SPACE, /* type */ 838 nexus_bus_barrier, /* bus_space_barrier */ 839}; 840